CX23885-15Z - CONEXANT SYSTEMS - Datasheet.Directory

CX23885

PCI Express Video and Broadcast

Audio Decoder

Data Sheet

DSH-201010p2

February 2009

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2Conexant DSH-201010p2

Preliminary Information/Conexant Proprietary and Confidential 2/4/09

Ordering Information

Revision History

Model Number Description Package

CX23885* PCI Express Video and Broadcast Audio

Decoder

128-pin ETQFP (lead-free)

*Lead-free (Pb Free) and RoHS compliant

Revision Date Description

p1 June 27, 2008 Preliminary release.

p2 February 4, 2009 P2 release

*Added Section 1.14, Crystal Oscillator.

DSH-201010p2 Conexant 3

2/4/09 Preliminary Information/Conexant Proprietary and Confidential

CX23885

PCI Express Video and Broadcast Audio

Decoder

The CX23885 brings Conexant Systems’ long heritage of audio and video

capture solutions to systems that enable PCI ExpressTM bus architectures. The

family of devices integrates all the functions required to perform television and

external A/V capture on personal computers or consumer electronic devices.

The integrated worldwide video decoder and audio decoder can be used for a

high performance, cost effective, basic analog television capture, or can be used

as the base for more complex multiple tuner configurations. The devices can

support capture of two simultaneous digital television transport streams, two

simultaneous analog streams, or a combination of analog and digital capture.

This latest generation of devices further integrates components found on a

typical video capture card such as video ADC anti-alias filter components, and

analog to digital converters for stereo audio capture.

Quality video is accomplished by using 10-bit video ADCs and a full 10-bit video

data path. For high-quality audio, a minimum of 16-bit audio resolution through

the entire audio data path ensures high fidelity audio, whether it comes from the

integrated broadcast audio decoder, the sigma-delta ADCs, or from an external

serial audio source.

The device are packaged in a 14x14 mm, lead-free 128-pin ETQFP.

Preliminary Information

This document contains information on a new product. The parametric information,

although not fully characterized, is the result of testing initial devices.

Distinguishing Features

PCI Express 1.0a compliant

Worldwide audio and video

decoding

Automatic video and broadcast

audio standard detection and

configuration

Flexible video input mux supporting

composite, S-Video, and

component inputs with integrated

anti-alias filtering

Integrated sigma-delta stereo audio

ADCs with 4:2 mux

Audio sample rate converters on all

inputs and outputs

Two MPEG transport stream

ports—parallel and serial

Two I2C master ports

Macrovision 1.0 detection

compliant

Programmable VBI data slicer for

data services such as closed

caption, WSS, and program guides

Infrared transmitter and receiver

logic

Auxiliary/Audio Phase Locked Loop

(PLL) clock for general use

Support for MPEG-2 encoding

when used with the CX23417

4Conexant DSH-201010p2

Preliminary Information/Conexant Proprietary and Confidential 2/4/09

Functional Block Diagram

3 CVBS

Luma

Inputs

Analog

Front End

CH 1

10-Bit

Video

ADC

Video

Decoder

NTSC/PAL/

SECAM

Parallel TS/PS Input

Port or BT.656/VIP1.1

Input or Output

Clock, Data[7:0],

Start, Valid

Clock, Data,

Start, Valid

Serial TS/PS

Input Port

Color Space

Converter

and

Formatter

RISC Engine

and

DMA Controller

SRAM Butters

Color Space

Converter and

Formatter

Baseband

Audio

Vol/Tone/

Balance/Mute

Audio

Decoder

BTSC/EIAJ/

A2/NICAM/

Analog

Front End

CH 2

10-Bit

Video/SIF

ADC

Analog

Front End

CH 3

3 CVBS,

Luma,

Chroma,

SIF, or

Pb Inputs

2 CVBS,

Luma,

Chroma,

SIF, or

Pr Inputs

L/R 1

Audio In

L/R 2

Audio In

18-Bit

Audio

ADCs GPIO

GPIO x24

UART

RS232

Serial Audio

In/Out

16 to 24-Bit

32, 44.1, 48,

96 kHz

I2C Master 1 SCL{1}

SDA{1}

I2C Master 2 SCL{2}

SDA{2}

PCI

Express

DLL

MAC

PCI

Express

PHY

I/F

PCI

Express

Audio

Master

Clock

System

PLL

Aux/Audio

PLL

Crystal

Amplifier

Video

PLL

Single Crystal

Frequency

Serial TS/PS Input

Port or BT.656/VIP1.1

Input or Output

Clock, Data,

Start, Valid

DSH-201010p2 Conexant 5

2/4/09 Preliminary Information/Conexant Proprietary and Confidential

Contents

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

1 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.1 Analog Video Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.2 Integrated Clamping and Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1.3 Flexible Decoder Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.4 High Performance Luma and Chroma Separation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.5 Video Processing Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

1.6 High Quality Scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.7 Pixel Formatting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.8 Vertical Blanking Interval Slicing and Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.9 Stereo Broadcast Audio Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.10 Audio Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

1.11 Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.12 PCI Express Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.13 Communication and General Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

1.14 Crystal Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

2 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.2 Memory Mapped Registers: Application Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.2.1 Device Control #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.2.2 PCI Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.2.3 PCI Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.2.4 PCI Interrupt Masked Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

3.2.5 Video A Interrupt Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.2.6 Video A Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

3.2.7 Video A Interrupt Masked Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.2.8 Video A Interrupt Set Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.2.9 Video B Interrupt Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

3.2.10 Video B Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.2.11 Video B Interrupt Masked Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2.12 Video B Interrupt Set Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2.13 Video C Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2.14 Video C Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

CX23885 Data Sheet

6Conexant DSH-201010p2

Preliminary Information/Conexant Proprietary and Confidential 2/4/09

3.2.15 Video C Interrupt Masked Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.2.16 Video C Interrupt Set Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.2.17 Audio Internal Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.2.18 Audio Internal Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.2.19 Audio Internal Interrupt Masked Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.2.20 Audio Internal Interrupt Set Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.2.21 Audio External Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.2.22 Audio External Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.2.23 Audio External Interrupt Masked Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.2.24 Audio External Interrupt Set Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

3.3 Memory Mapped Registers: DMAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.3.1 APB DMAC Current Buffer Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.3.2 APB DMAC Current Table Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.3.3 APB DMAC Buffer Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.3.4 APB DMAC Table Size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.4 Memory Mapped Registers: Miscellaneous Utilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.4.1 Timer Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.4.2 Timer Limit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.4.3 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.4.4 GPIO Interrupts Sensitivity Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.4.5 Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

3.4.6 GPIO (417 Microcontroller Interface) RW Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.4.7 GPIO (417 Microcontroller) Output Enable, Low Active. . . . . . . . . . . . . . . . . . . . . . . 61

3.4.8 GPIO (417 Microcontroller) Output Enable, Low Active. . . . . . . . . . . . . . . . . . . . . . . 62

3.4.9 Clock Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

3.4.10 Pad Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.5 Memory Mapped Registers: Video A Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.5.1 Video A General Purpose Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.5.2 Video A General Purpose Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.5.3 Video A DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3.5.4 Video A VIP Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.5.5 Video A Pixel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.5.6 Video A VBI Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.6 Memory Mapped Registers: Video B Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.6.1 Video B General Purpose Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.6.2 Video B General Purpose Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.6.3 Video B DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.6.4 Video B Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.6.5 Video B TS Line Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.6.6 Video B TS HW SOP Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

3.6.7 Video B TS General Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

3.6.8 Video B TS Bad Packet Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.6.9 Video B TS SOP Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

3.6.10 Video B TS Fifo Overflow Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.6.11 Video B TS Valid Miscellaneous. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

3.6.12 Video B TS Clock Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

3.6.13 Video B VIP Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

DSH-201010p2 Conexant 7

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CX23885 Data Sheet

3.6.14 Video B Pixel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

3.7 Memory Mapped Registers: Video C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.7.1 Video C General Purpose Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.7.2 Video C General Purpose Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.7.3 Video C DMA Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

3.7.4 Video C TS Line Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.7.5 Video C TS HW SOP Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

3.7.6 Video C TS General Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

3.7.7 Video C TS Bad Packet Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.7.8 Video C TS SOP Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.7.9 Video C TS Fifo Overflow Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.7.10 Video C TS Valid Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

3.7.11 Video C TS Clock Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

3.8 Memory Mapped Registers: Internal Audio Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.8.1 Audio Internal General Purpose Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.8.2 Audio Internal General Purpose Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.8.3 Audio Internal DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

3.8.4 Audio Internal Line Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.8.5 Audio Internal Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

3.9 Memory Mapped Registers: External Audio Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.9.1 Audio External DMA Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.9.2 Audio External General Purpose Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.9.3 Audio External General Purpose Counter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

3.9.4 Audio External DMA Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.9.5 Audio External Line Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.9.6 Audio External Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

3.10 Memory Mapped Registers: I2C Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

3.10.1 I2C Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

3.10.2 I2C Write Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.10.3 I2C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

3.10.4 I2C Read Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.10.5 I2C Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

3.11 Memory Mapped Registers: UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.11.1 UART TxD/RxD Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.11.2 UART Baud Rate Divisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

3.11.3 UART Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

3.11.4 UART FIFO Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

3.12 Rider Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.12.1 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

3.12.2 Accessing PCI Express Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

3.12.3 Accessing Rider Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

3.12.4 Register Access Exception - Vital Product Data (VPD) . . . . . . . . . . . . . . . . . . . . . . 98

3.12.5 Register Type Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

3.12.6 Read-Only Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

3.12.7 Read-Write Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

3.12.8 Read-Only; Write-1-to-Clear Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

3.12.9 Sticky Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

3.12.10 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

CX23885 Data Sheet

8Conexant DSH-201010p2

Preliminary Information/Conexant Proprietary and Confidential 2/4/09

3.12.11 Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

3.12.12 PCI Express Registers - PCI Compatible Header . . . . . . . . . . . . . . . . . . . . . . . . . 99

3.12.13 PCI Device and Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

3.12.14 PCI Status and Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

3.12.15 PCI Class Code and Revision ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

3.12.16 PCI Base Address Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

3.12.17 PCI Base Address Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

3.12.18 PCI Subsystem and Subsystem Vendor ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

3.12.19 PCI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.12.20 PCI Express Registers: Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

3.12.21 PCI Express Device Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

3.12.22 PCI Express Device Status and Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

3.12.23 PCI Express Link Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

3.12.24 PCI Express Link Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

3.12.25 Power Management Interface Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

3.12.26 Power Management Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

3.12.27 Vital Product Data Capabilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

3.12.28 VPD Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

3.12.29 Message Signaled Interrupt Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

3.12.30 MSI Address Lower 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

3.12.31 MSI Address Upper 32 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

3.12.32 MSI Data Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

3.12.33 PCI Express Registers: Extended Capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . 111

3.12.34 AER Uncorrectable Error Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

3.12.35 AER Uncorrectable Error Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

3.12.36 AER Uncorrectable Error Severity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

3.12.37 AER Correctable Error Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

3.12.38 AER Correctable Error Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

3.12.39 AER Capability and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

3.12.40 AER Header Log 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

3.12.41 AER Header Log 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

3.12.42 AER Header Log 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

3.12.43 AER Header Log 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

3.12.44 Port VC Capability Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

3.12.45 Port VC Status and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

3.12.46 VC Resource 0 Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

3.12.47 VC Resource 0 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

3.12.48 VC Resource 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

3.12.49 VC Resource 1 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

3.12.50 VC Resource 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

3.12.51 VC Resource 2 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

3.12.52 VC Resource 3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

3.12.53 VC Resource 3 Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

3.12.54 VC Arbitration Table Entries 0–7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

3.12.55 VC Arbitration Table Entries 8–15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

3.12.56 VC Arbitration Table Entries 16–23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

DSH-201010p2 Conexant 9

2/4/09 Preliminary Information/Conexant Proprietary and Confidential

CX23885 Data Sheet

3.12.57 VC Arbitration Table Entries 24–31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

3.12.58 VC Arbitration Table Entries 32–39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

3.12.59 VC Arbitration Table Entries 40–47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

3.12.60 VC Arbitration Table Entries 48–55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

3.12.61 VC Arbitration Table Entries 56–63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

3.13 Rider Registers – Global. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

3.13.1 Rider Status 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

3.13.2 Rider Control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

3.13.3 Rider Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

3.14 Rider Registers: Transaction Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

3.14.1 Transaction Layer Status 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

3.14.2 TL Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

3.14.3 Transmit Queue Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

3.14.4 AL Request Root Complex Lower Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

3.14.5 AL Request Root Complex Upper Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

3.14.6 AL Request Endpoint Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

3.14.7 AL Request Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

3.14.8 AL Request Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

3.14.9 Transaction Layer Test Control (Flow Control). . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

3.14.10 Receive Buffer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

3.14.11 Virtual Channel Resources 0 and 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

3.14.12 Virtual Channel Resources 2 and 3 Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

3.14.13 Virtual Channel Resource 0 Initial Flow Control Credits . . . . . . . . . . . . . . . . . . . 133

3.14.14 Virtual Channel Resource 2 Initial Flow Control Credits . . . . . . . . . . . . . . . . . . . 134

3.14.15 Virtual Channel Resource 3 Initial Flow Control Credits . . . . . . . . . . . . . . . . . . . 134

3.15 Rider Registers: Data Link Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135

3.15.1 Data Link Layer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

3.15.2 Replay Timeout Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

3.15.3 ACK Latency Timeout Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

3.16 Rider Registers: MAC Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

3.16.1 MAC Layer Status 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

3.16.2 MAC Layer Control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

3.16.3 MAC Layer Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

3.16.4 MAC Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

3.16.5 MAC Loopback Master Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

3.16.6 MAC L0s Exit Latencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

3.17 Audio and Video Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

3.17.1 Serial Slave Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

3.17.1.1 Host Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

3.17.1.2 Host Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

3.17.1.3 Host Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

3.18 Chip Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

3.18.1 Baseband Analog Front End and General Chip Configuration Registers . . . . . . . 143

3.18.1.1 Chip Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

3.18.1.2 Baseband AFE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

3.18.1.3 Video PLL Integer/Post Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

3.18.1.4 Video PLL Fractional. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

CX23885 Data Sheet

10 Conexant DSH-201010p2

Preliminary Information/Conexant Proprietary and Confidential 2/4/09

3.18.1.5 Auxiliary PLL Integer/Post Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

3.18.1.6 Auxiliary PLL Fractional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149

3.18.1.7 System PLL Integer/Post Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

3.18.1.8 System PLL Fractional . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

3.18.1.9 Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

3.18.1.10 Audio I/O Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

3.18.1.11 Audio Lock Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

3.18.1.12 Audio Lock Control 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

3.18.1.13 Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

3.18.1.14 AFE Diagnostic Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

3.18.1.15 AFE Diagnostics Control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

3.18.1.16 PLL Diagnostic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

3.18.1.17 AFE Clock Out Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

3.18.1.18 DLL1 Diagnostic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

3.18.1.19 GPIO[23:19] Output Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

3.18.1.20 GPIO [23:19] Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

3.18.1.21 IFADC Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

3.19 IR Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

3.19.1 Infrared Remote registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

3.19.1.1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163

3.19.1.2 Transmit Clock Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

3.19.1.3 Receive Clock Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

3.19.1.4 Transmit Carrier Duty Cycle Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

3.19.1.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

3.19.1.6 Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

3.19.1.7 Low Pass Filter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

3.19.1.8 FIFO Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169

3.20 Video Decoder Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

3.20.1 Basic Video Decoder Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

3.20.1.1 Output Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

3.20.1.2 Output Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

3.20.1.3 General Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

3.20.1.4 Interrupt Status and Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

3.20.1.5 Luma Data Path Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

3.20.1.6 Horizontal Scaling Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

3.20.1.7 Vertical Scaling Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180

3.20.1.8 Chroma Data Path Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

3.20.1.9 VBI Line Data Type Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182

3.20.1.10 VBI Line Data Type Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

3.20.1.11 VBI Line Data Type Control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

3.20.1.12 VBI Line Data Type Control 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

3.20.1.13 VBI Line Data Type Control 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

3.20.1.14 VBI Frame Code Config . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

3.20.1.15 VBI Miscellaneous Config1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

3.20.1.16 VBI Miscellaneous Config2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

3.20.1.17 VBI Payload 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

3.20.1.18 VBI Payload 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

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CX23885 Data Sheet

3.20.1.19 VBI Custom Mode 1, Config1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

3.20.1.20 VBI Custom Mode 1, Config2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

3.20.1.21 VBI Custom Mode 1, Config3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

3.20.1.22 VBI Custom Mode 2, Config1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

3.20.1.23 VBI Custom Mode 2, Config2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

3.20.1.24 VBI Custom Mode 2, Config3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192

3.20.1.25 VBI Custom Mode 3, Config1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

3.20.1.26 VBI Custom Mode 3, Config2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193

3.20.1.27 VBI Custom Mode 3, Config3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

3.20.1.28 Horizontal Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194

3.20.1.29 Vertical Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

3.20.1.30 Sample Rate Convert and Comb Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

3.20.1.31 Chroma Config and VBI Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

3.20.1.32 Field Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

3.20.1.33 Miscellaneous Timing Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

3.20.1.34 DFE Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

3.20.1.35 DFE Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199

3.20.1.36 DFE Control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

3.20.1.37 PLL Loop Filter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200

3.20.1.38 Horizontal Timing Loop Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

3.20.1.39 White Crush Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

3.20.1.40 Soft Reset Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203

3.20.1.41 Version ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204

3.20.1.42 VBI Passthrough Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

3.21 Audio Decoder Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

3.21.1 8051 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207

3.21.2 Format Detection and Subcarrier Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208

3.21.3 User Preference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

3.21.4 8051 Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212

3.21.5 General Control/Interrupt Control/Rev Number/Soft Reset . . . . . . . . . . . . . . . . . . 214

3.21.6 Audio Analog AGC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

3.21.7 Phase Fix/Dematrix/Analog Demod Source Select/Prescaler . . . . . . . . . . . . . . . . 216

3.21.8 Path 1 Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

3.21.9 Path 1 Volume/Balance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

3.21.10 Path 1 Equalizer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219

3.21.11 Path 1 Soft Clip Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

3.21.12 Path 2 Source Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221

3.21.13 Path 2 Volume/Balance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

3.21.14 Path 2 Equalizer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

3.21.15 Path 2 Soft Clip Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224

3.21.16 Sample Rate Converter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

3.21.17 Sample Rate Converter Loop Filter Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . 226

3.21.18 SRC1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226

3.21.19 SRC2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

3.21.20 SRC3 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

3.21.21 SRC4 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

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3.21.22 SRC5 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

3.21.23 SRC6 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228

3.21.24 Output Selects/Bypass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

3.21.25 I2S Input Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

3.21.26 I2S Output Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

3.21.27 Autoconfiguration Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

3.22 Audio ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

3.22.1 Delta-Sigma ADC Miscellaneous Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

3.22.2 Delta-Sigma ADC Miscellaneous Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234

3.22.3 Chopper Clocks Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

3.22.4 Chopper Clock Reference and Bandgap Divide Settings . . . . . . . . . . . . . . . . . . . 235

3.22.5 Chopper Clock S2D Divide Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

3.22.6 Bandgap Testing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

3.22.7 SD2 MUX Control for Right Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

3.22.8 SD2 MUX Control for Left Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

3.22.9 S2D Bias and Startup Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237

3.22.10 Delta-Sigma ADC Amplifier Bias Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

3.22.11 Miscellaneous Testing Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

3.22.12 Power Down Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

3.22.13 DS and S2D Stability Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

3.22.14 Dynamic Dither Amplitude Read Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

3.22.15 Digital Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

3.22.16 Digital Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241

3.22.17 I2S_TX_CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242

4 Thermal/Mechanical

Information. 243

4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

4.2 Center Pad Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

4.3 Mechanical Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

5 Electrical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

5.1 DC Electrical Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

5.2 AC Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

6 Connecting the CX23885 to the CX23417. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

6.1 CX23885 and CX23417 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

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Figures

Figure 1. Fundamental Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 2. Overtone Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 3. External Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 4. Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 5. CFG Block, Device Core, and Transaction Layer Interfaces . . . . . . . . . . . . . . . . . . . . . 96

Figure 6. Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 7. 128-Pin ETQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

Figure 8. Exposed Pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

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Tables

Table 1. External Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 2. External Component Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 3. Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

Table 6. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Table 7. Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Table 8. Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247

Table 9. Control Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Table 10. Power Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248

Table 11. CX23885 and CX23417 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249

CX23885 Data Sheet

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1Functional Overview

The CX23885 brings Conexant Systems’ fifth generation of video decoding technology

to PCI Express-enabled personal computers. Third generation broadcast audio

decoding is integrated on chip to provide high fidelity TV stereo. The product is ideally

suited for products that need to capture audio and video from analog or digital sources

and deliver that data over PCI Express.

1.1 Analog Video Inputs

The CX23885 integrates two high-performance 10-bit ADCs and provides a full 10-bit

data path through the video decoder to maintain optimum end-to-end video quality.

Eight analog inputs are provided with flexible analog muxing that can be configured for

one or a combination of the following audio and video inputs:

Eight composite inputs

Four Y/C inputs

Two composite with one Y/C, one YPbPr, and one sound IF

Four composite with four sound IF

One composite with two YPbPr and one sound IF

Time multiplexing the various inputs to the chroma and sound ADC allows for the

simultaneous digitalization of Pb and Pr inputs in component mode, or chroma with

sound-IF for supporting Y/C sources with broadcast audio. All video inputs have

integrated anti-alias filters, eliminating the need for external filter components.

1.2 Integrated Clamping and Automatic Gain

Control

DC restoration and Automatic Gain Control (AGC) are provided to compensate for

sources with differing average picture levels. Manual gain control is also supported.

Gain values can be read from and written to the device, allowing for the calibration of

each input and facilitating fast switching from one source to another.

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Functional Overview CX23885 Data Sheet

1.3 Flexible Decoder Rates

The video data path includes a sample rate converter to enable multiple pixel rates

and to track any timing fluctuations that may be present within the video source. With

the sample rate converter, the user can program the device to decode video at output

pixel rates of either 13.5 MHz for an ITU-R BT.656 compliant output stream or at 12.27

MHz and 14.75 MHz for NTSC and PAL/SECAM square pixel rates, respectively. The

sample rate converter with internal FIFO monitors the horizontal timing of the input

source to create a fixed number of samples per line. It controls a PLL to slowly adjust

the FIFO level such that short-term jitter in the input source is filtered out of the

digitized video stream. This provides stable video data and output clocks, even with

sources like VCRs that can have inherently unstable timing.

1.4 High Performance Luma and Chroma Separation

Luma/chroma separation of composite video sources is accomplished through a 5-line

adaptive chroma comb filter for NTSC and PAL standards. The adaptive comb filter

looks across five lines of incoming video and determines which of the five lines are

appropriately correlated enough to average together. Depending on the amount of

correlation among the lines, two or three lines are averaged together to form the

resulting combed filtered line. In the case where no correlation exists between lines,

the decoder automatically falls back to chroma band-pass and luma notch filtering.

The output of the chroma comb filter is also remodulated and fed back into the luma

channel. The result is a high- quality image with reduced cross-chrominance and

cross-luminance artifacts—such as dot crawl, hanging dots, rainbow effects—that

restore full bandwidth to luminance data from composite sources. Additionally, we

have a SECAM “Bell” filter to improve SECAM luminance and chroma separation. This

is because SECAM uses an FM modulated signal carrier that is always present,

regardless of whether or not there is color information being broadcast. This results in

a visible artifact in the luminance at the carrier frequency. To eliminate this effect, an

“Inverse Bell” filter is applied at the encoder to attenuate color frequencies near the Dr

and Db carriers. Thus, if little or no color information is present in the signal, the

carriers will be reduced in amplitude.

1.5 Video Processing Functions

Back-end video processing functions include contrast, brightness, hue, saturation, and

scaling. In addition, the luma data path provides white crush compensation for sources

that exceed sync tip to white level ratios. The decoder also provides four sets of

selectable peaking filters for sharpening the image. The luma data output range is

selectable so that luma codes can be limited to the nominal ITU-R BT.656 code range,

or can support values below black level, or can use the entire 10-bit range of values

where 0 is black level, and 1023 is nominal white. Additional chroma functions include

AGC to compensate for attenuated color subcarriers, a color killer for true black and

white sources, and coring for limiting low-level chroma noise.

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CX23885 Data Sheet Functional Overview

1.6 High Quality Scaling

Arbitrary horizontal and vertical scaling is available, from full resolution down to an 8:1

ratio (icon size).To maintain a high-quality scaled image, multi-tap polyphase

interpolation is used. The horizontal luma scaler uses 6-tap, 63-phase FIR

interpolation between horizontal source samples, while the horizontal chroma scaler

uses 4-tap, 63-phase interpolation. Line store memory is integrated into the decoder

so that the vertical scaler—depending on the horizontal scaling ratio—can use from 2-

tap to 5-tap, seven-phase interpolation between lines.

1.7 Pixel Formatting

Two pixel formatting engines are available for converting video samples into the

following formats:

YUY2

RGB24

RGB32

RGB555

1.8 Vertical Blanking Interval Slicing and Decoding

An integrated VBI data slicer supports a variety of data standards: WST, Closed

Caption, WSS, VITC, as well as programming guide information like Gemstar 1x,

Gemstar 2x, and VPS. Decoded data for closed caption, WSS, and Gemstar services

is available through either a register read or can be inserted as ancillary data within

the ITU-R BT.656 data stream. For high-bit rate services such as WST, NABTS, VPS,

and VITC, data is provided on the pixel output port and can be inserted as ancillary

data as well. There is independent control of what data service is to be sliced/decoded

for every line of each field in the vertical interval. Programmability is also provided

such that custom data slicing can be accomplished for data services that do not

comply with one of the standards already supported.

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Functional Overview CX23885 Data Sheet

1.9 Stereo Broadcast Audio Decoding

The CX23885 integrates a stereo broadcast audio decoder capable of demodulating

all of the worldwide audio standards: BTSC, EIAJ, A2, NICAM, FM (standard and high-

deviation modes), and AM. The sound IF output from the tuner interfaces directly with

the CX23885, eliminating the need for external sound demodulation chips. Dual

language, subchannel, and Secondary Audio Formats (SAP) are also supported for

broadcasts that transmit multilingual capability. Simultaneous dual language can be

supported with different languages on each channel of the stereo left/right pair. The

audio decoder has automatic standard detection and configuration through an on-

board microprocessor so that no user intervention is necessary to set up the decoder

for the various standards. This is especially useful in geographic regions where

different audio standards may be received on a channel-by-channel basis.

1.10 Audio Interfaces

Demodulated broadcast audio is available through two interfaces, serial audio output

or embedded in the ITU-R BT.656/VIP pixel port as ancillary data. The serial audio

output port can supply audio samples from the broadcast decoder or from the serial

audio input port. An internal sample rate converter allows for selection of 32 kHz, 44.1

kHz, 48 kHz, or 96 kHz sample rate for easy system integration. This sample rate

conversion is available for both the serial audio (input and output) and BT.656/VIP

interfaces, independent of one another. In the BT.656/VIP mode, audio samples are

embedded into the video stream and are tagged as ancillary data during the horizontal

blanking interval. This allows for the capture of audio samples on systems that do not

provide serial audio interfaces. The serial audio interfaces support programmable

master/slave modes and 16- to 32-bit sample widths.

The CX23885 features baseband analog audio input integrating a stereo 16-bit delta-

sigma analog to digital converter including multi-stage decimation filter. It supports up

to 192 kHz internal sample rate, minimum 88 dB SNR, 17.6 kHz bandwidth, and 0.1

dB passband ripple. One of two stereo 2.0 Vrms full-scale inputs can be selected via

I2S or DMA’d over PCI Express.

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CX23885 Data Sheet Functional Overview

1.11 Audio Processing

In addition to the demodulation of broadcast audio in the CX23885, premium functions

such as three-band equalization, volume, balance, mute, and automatic volume

control are independently available on both the broadcast audio and serial audio data

streams. The audio samples can also be locked to the incoming video stream to

ensure that the audio samples are rate-matched to the video, eliminating the need for

MPEG encoders to drop or repeat frames in order to keep the video and audio in sync.

The entire audio data path is a minimum of 16 bits wide to maintain CD quality

performance levels throughout the audio signal chain.

1.12 PCI Express Bus

The CX23885 features a PCI Express single lane (x1) link compliant to base

Specification 1.0a. This PCI Express single-function endpoint offers a dual simplex 2.5

Gbps upstream port supporting 8 upstream channels on VC0/TC0–TC7. The

bidirectional, point-to-point, packet-based high throughput is implemented through a

layered architecture. The physical layer is composed of an internally PIPE compliant,

logical subblock consisting of the Media Access Layer (MAC) and the Physical Coding

Sublayer (PCS), and the electrical subblock consisting of the Physical Media

Attachment Layer (PMA). Physical Layer Packets (PLPs) originate at the transmitter

(Tx) and terminate at the receiver (Rx). Above the Physical Layer is the Data Link

Layer (DLL) processing DLLPs which facilitate link initialization and training, link power

management, TLP flow control, and the acknowledgement of successful TLP delivery

across the link. Above the DLL is the Transaction Layer (TL) processing split-

transaction protocol based link traffic consisting of up to 128 byte TLPs. Above the TL

is the Application Layer (AL) supporting the DMA streaming infrastructure, Tx/Rx

buffering, decode, and execution of RISC instructions, register and memory access,

interrupts, and overall QoS management balancing traffic priorities, latencies, and

bandwidth.

1.13 Communication and General Features

A hardware interrupt pin is available along with a maskable interrupt status register so

that the device can notify the system when internal events occur without the need to

implement polling schemes.

Other convenient features consist of the following:

Programmable infrared transmitter/receiver logic, able to modulate or demodulate

low data rate consumer remote control protocols

General purpose I/O pins

Power-down pin or register-controlled power-down levels

1.2 V, 1.8 V, 3.3 V power supply configuration available with an external pass

transistor

PLL output for either supplying a video locked 256x/384x oversample audio clock

or a general purpose user programmable clock for minimizing PCB component

count

Small package size: a 128-pin, 14x14 mm ETQFP

Lead-free package

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Functional Overview CX23885 Data Sheet

1.14 Crystal Oscillator

The AFE contains a crystal oscillator circuit to produce a low-jitter clock reference for

the audio/video decoder. Three crystal frequencies are supported: 28.636MHz for

operation without IF sampling feature, and 49.920MHz and 56.010MHz for IF

sampling.

The clock reference is used for the ADC sample clocks and the reference clock for the

PLLs. This clock reference is also used by the front-end digital logic that directly

interfaces to the ADC modules.

The crystal oscillator has a dedicated power supply pin, VAA_XTAL, which should be

carefully decoupled to the VSS_XTAL pin in order to minimize board noise from

coupling into the reference clock.

Either a passive crystal circuit can be connected to XTI and XTO or a square wave

clock signal can be fed into XTI through an AC coupling capacitor of 10nF, XTO being

grounded through another similar capacitor.

Figures 1 through 3 illustrate the crystal configuration connections: third overtone,

fundamental crystals, and single-ended inputs. Table 1 lists the crystal specifications,

and Table 2 lists the external component specifications for operation at different

frequencies.

Table 1. External Crystal Specifications

Frequency 28.636 MHz 49.920 MHz 56.010 MHz

Tolerance ± 25 ppm (CL = 27 and

33 pF)

± 25 ppm ± 25 ppm

Temperature stability ± 25 ppm (0 °C to 70 °C) ± 25 ppm (0 °C to 70 °C) ± 25 ppm (0 °C to 70 °C)

Aging stability ± 15 ppm / 4 yrs ± 15 ppm / 4 yrs ± 15 ppm / 4 yrs

Oscillator Mode Fundamental Third overtone Third overtone

Calibration Mode Parallel resonant Parallel resonant Parallel resonant

Load Capacitance 20 pF, nom 18 pF, max 18 pF, max

Shunt Capacitance 7 pF, max 7 pF, max 7 pF, max

Series Resistance 80 Ω max @ 500 μW

drive level

80 Ω max @ 500 μW drive

level

80 Ω max @ 500 μW drive

level

Operating Temperature 0 °C to 70 °C0 °C to 70 °C0 °C to 70 °C

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CX23885 Data Sheet Functional Overview

Figure 1. Fundamental Mode

Figure 2. Overtone Mode

Figure 3. External Drive

C1 C2

XTI XTO

R1C4

C1 C2

XTI XTO

R1C4

XTI XTO

10 nF10 nF

Sig

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Functional Overview CX23885 Data Sheet

Table 2. External Component Specifications

Frequency 28.636 MHz 49.920 MHz 56.010 MHz

C1 27 pF 15 pF 12 pF

C2 33 pF 15 pF 12 pF

C3 Not populated 10 nF 10 nF

C4 120 pF 120 pF 120 pF

L1 Not populated 0.82 μH0.68 μH

R1 50 50 50

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2Pin Descriptions

Table 3 lists the pins and their functions. Figure 4 provides a pinout diagram.

Table 3. Pin List (1 of 10)

Pin Name Pin Number Dir Type Description

VIN3 1 I As Composite or Luma signal input to ADC1. The signal

passes through on-chip analog multiplexers before

passing through a gain stage, an anti-alias filter stage,

and into ADC1. Unused inputs should not be

connected.

VAA_CH1 2 Ap Analog channel 1 (clamp, single-to-diff, VGA, filter)

power. VAA_CH1 = 3.3 V nominal.

VIN4 3 I As Chroma, Sound IF, or Pb signal input to ADC2 or

Luma, Composite signal input to ADC1. This signal

passes through on-chip analog multiplexers before

passing through a gain stage, an anti-alias filter stage,

and into either ADC1 or ADC2. In color component

(Pb, Pr) input mode, the Pb component should be

connected to one of these pins, and the Pr component

should be connected to the Pr pins (VIN7, VIN8).

Unused inputs should not be connected.

VSS_CH1 4 Ap Analog channel 1 (clamp, single-to-diff, VGA, filter)

ground

VIN5 5 I As Chroma, Sound IF, or Pb signal input to ADC2 or

Luma, Composite signal input to ADC1. This signal

passes through on-chip analog multiplexers before

passing through a gain stage, an anti-alias filter stage,

and into either ADC1 or ADC2. In color component

(Pb, Pr) input mode, the Pb component should be

connected to one of these pins, and the Pr component

should be connected to the Pr pins (VIN7, VIN8).

Unused inputs should not be connected.

IREF 6 O Ar Current reference pin. Connect 30 kΩ, 1% precision

resistor to ground.

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Pin Descriptions CX23885 Data Sheet

VIN6 7 I As Chroma, Sound IF, or Pb signal input to ADC2 or

Luma, Composite signal input to ADC1. This signal

passes through on-chip analog multiplexers before

passing through a gain stage, an anti-alias filter stage,

and into either ADC1 or ADC2. In color component

(Pb, Pr) input mode, the Pb component should be

connected to one of these pins, and the Pr component

should be connected to the Pr pins (VIN7, VIN8).

Unused inputs should not be connected.

SD2_NEG2 8 Ar Negative input of single-to-differential converter. Tie to

analog ground through AC coupling capacitor for

common mode noise rejection. The capacitor should

match the value used on the analog inputs.

VIN7 9 I As Chroma, Sound IF or Pr signal input to ADC2 or Luma,

Composite signal input to ADC1. This signal passes

through on-chip analog multiplexers before passing

through a gain stage, an anti-alias filter stage, and into

either ADC1 or ADC2. In color component (Pb, Pr)

input mode, the Pr component should be connected to

this pin, and the Pb should be connected to a Pb pin

(VIN4, VIN5, VIN6).

Unused inputs should not be connected.

VAA_CH2 10 Ap Analog channel 2 (clamp, single-to-diff, VGA, filter)

power. VAA_CH2 = 3.3 V nominal.

VIN8 11 I As Chroma, Sound IF, or Pr signal input to ADC2 or

Luma, Composite signal input to ADC1. This signal

passes through on-chip analog multiplexers before

passing

through a gain stage, an anti-alias filter stage, and into

either ADC1 or ADC2. In color component (Pb, Pr)

input mode, the Pr component should be connected to

this pin, and the Pb should be connected to a Pb pin

(VIN4, VIN5, VIN6). Unused inputs should not be

connected.

VSS_CH2 12 Ap Analog channel 2 (clamp, single-to-diff, VGA, filter)

ground

VSS_XTAL 13 Ap Crystal oscillator ground. Connect to analog ground.

XTI 14 I As 28.63636 or MHz crystal oscillator input, or single-

ended clock oscillator input. Used for PLL clock

reference and ADC sample clock. IC master clock for

whole chip.

XTO 15 I/O As Crystal buffer return, or DC reference input for single-

ended clock oscillator mode.

VAA_XTAL 16 Ap Crystal oscillator power. VAA_XTAL = 3.3 V nominal.

Connect to VAA.

Table 3. Pin List (2 of 10)

Pin Name Pin Number Dir Type Description

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CX23885 Data Sheet Pin Descriptions

VAA_DS1 17 Ap Delta-sigma audio ADC power.

VSS_DS1 18 Ap Delta-sigma audio ADC ground

VREFP_DS 19 O Ar Delta-sigma audio ADC positive reference voltage

VREFM_DS 20 O Ar Delta-sigma audio ADC negative reference voltage

ASUB_DS 21 Ap Delta-sigma audio ADC substrate tie

VR1 22 I As Right channel audio input 1

VR_NEG 23 I As Right channel negative input

VR2 24 I As Right channel audio input 2

VL1 25 I As Left channel audio input 1

VL_NEG 26 I As Left channel negative input

VL2 27 I As Left channel audio input 2

VSS_DS2 28 Ap Delta-sigma audio ADC ground

VAA_DS2 29 Ap Delta-sigma audio ADC power

VOUT_REG 30 O Ar Internal regulator output signal. Connect to base of

NPN transistor (q2n4401).

VIN_REG 31 I Ar Internal regulator input signal. Connect to emitter of

NPN transistor (q2n4401).

VAA_REG 32 Ap Power for PCI Express internal voltage regulator

VDDA 33 Ap PCI Express receiver power supply. Connect to analog

1.2 V.

RXP 34 I D PCI Express receiver differential pair. Connect to

PERp0.

VSSA 35 Ap PCI Express receiver ground.

RXM 36 I D PCI Express receiver differential pair. Connect to

PERn0.

VDDA 37 Ap PCI Express receiver power supply. Connect to analog

1.2 V.

REF_RES 38 O Ar Reference resistor for internal bias voltage generation.

Connect to 3.0 kΩ ±1% resistor to ground.

ATEST 39 O D Reserved

VDDRO 40 Ap PCI Express power. Connect to 1.8 V.

VSSRO 41 Ap PCI Express ground. Connect to ground.

Table 3. Pin List (3 of 10)

Pin Name Pin Number Dir Type Description

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Pin Descriptions CX23885 Data Sheet

VDDTO 42 Ap PCI Express transmitter oscillator power supply.

Connect to analog 1.8 V.

VSSTO 43 Ap PCI Express transmitter oscillator ground. Connect to

ground.

VDDT 44 Ap PCI Express transmitter driver power supply. Connect

to 1.8 V.

TXP 45 O D PCI Express transmitter differential pair. Connect to

PETp0.

VSST 46 Ap PCI Express transmitter driver ground. Connect to

ground.

TXM 47 O D PCI Express receiver differential pair. Connect to

PETn0.

VDDT 48 Ap PCI Express transmitter driver power supply. Connect

to 1.8 V.

VSSTA 49 Ap PCI Express transmitter driver ground. Connect to

ground.

VDDTA 50 Ap PCI Express analog PLL power. Connect to 1.2 V.

REFCLKP 51 I D PCI Express differential pair reference clock. Connect

to REFCLK+.

REFCLKM 52 I D PCI Express differential pair reference clock. Connect

to REFCLK–.

GPIO[15] 53 I/O D General Purpose I/O

Configurable multifunction status/control pin

VDD 54 Dp Digital core logic power

TEST 55 I D Puts chip in test mode for ATE/Debug testing. Active-

high.

PERST_N 56 I D PCI Express reset input, active low

RESET_OUT_N 57 O D Buffered output PERST_N combined with internal

POR, soft reset, and hot PCI reset

VDD 58 Dp Digital core logic power

GPIO[14] 59 I/O D General Purpose I/O

Configurable multifunction status/control pin

Table 3. Pin List (4 of 10)

Pin Name Pin Number Dir Type Description

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CX23885 Data Sheet Pin Descriptions

IRQ_N (GPIO[16]) 60 I/O D When UART_GPIO_EN bit is cleared in the

MC417_GPIO_CTL register:

This is an Interrupt input, active-low (external A/V

decoder), or output from AV_CORE.

When UART_GPIO_EN bit is set in the

MC417_GPIO_CTL register:

This is a General Purpose I/O Configurable

multifunction status/control pin.

URX(GPIO[17]) 61 I/O D When UART_GPIO_EN bit is cleared in the

MC417_GPIO_CTL register:

UART receive input

When UART_GPIO_EN bit is set in the

MC417_GPIO_CTL register:

This is a General Purpose I/O Configurable

multifunction status/control pin.

UTX(GPIO[18] 62 I/O D When UART_GPIO_EN bit is cleared in the

MC417_GPIO_CTL register:

UART transmit output

When UART_GPIO_EN bit is set in the

MC417_GPIO_CTL register:

This is a General Purpose I/O Configurable

multifunction status/control pin.

VDDIO 63 Dp Digital I/O pad power

GPIO[13] 64 I/O D General Purpose I/O

Configurable multifunction status/control pin

GPIO[12] 65 I/0 D General Purpose I/O

Configurable multifunction status/control pin

VDD 66 Dp Digital core logic power

GPIO[11] 67 I/O General Purpose I/O

Configurable multifunction status/control pin

TS2_SOP 68 I/O D Start of packet indicator input or Data Request output

TS2_VAL 69 I D Valid indicator for TS2.

TS2_CLK 70 I D Transport stream input clock. All other TS2 signals

sampled at rising edge of TS2_CLK

TS2_DAT 71 I D Transport stream input serial data

TS1_SOP 72 I/O D TS input mode: Start of packet indicator input or Data

Request Output

TS1_VAL 73 I D Valid indicator for TS1.

Table 3. Pin List (5 of 10)

Pin Name Pin Number Dir Type Description

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Pin Descriptions CX23885 Data Sheet

TS1_CLK 74 I/O D Transport stream input clock. All other TS1 signals

sampled at rising edge of TS1_CLK

VDD 75 Dp Digital core logic power

GPIO[10] 76 I/O D General Purpose I/O

Configurable multifunction status/control pin

TS1_DAT[0] 77 I/O D Multiplexed pin function.

1. TS input mode: This can be a serial transport/

program stream data bit or a parallel transport/

program stream data bit[0].

2. Video input mode: Data bit[0] of ITU-656 or VIP

source

3. Video output mode: Data bit[0] of internally

decoded video

TS1_DAT[1] 78 I/O D Multiplexed pin function.

1. TS input mode: Parallel transport or program

stream data bit[1]

2. Video input mode: Data bit[1] of ITU-656 or VIP

source

3. Video output mode: Data bit[1] of internally

decoded video

TS1_DAT[2] 79 I/O D Multiplexed pin function.

1. TS input mode: Parallel transport or program

stream data bit[2]

2. Video input mode: Data bit[2] of ITU-656 or VIP

source

3. Video output mode: Data bit[2] of internally

decoded video

TS1_DAT[3] 80 I/O D Multiplexed pin function.

1. TS input mode: Parallel transport or program

stream data bit[3]

2. Video input mode: Data bit[3] of ITU-656 or VIP

source

3. Video output mode: Data bit[3] of internally

decoded video

TS1_DAT[4] 81 I/O D Multiplexed pin function.

1. TS input mode: Parallel transport or program

stream data bit[4]

2. Video input mode: Data bit[4] of ITU-656 or VIP

source

3. Video output mode: Data bit[4] of internally

decoded video

Table 3. Pin List (6 of 10)

Pin Name Pin Number Dir Type Description

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CX23885 Data Sheet Pin Descriptions

TS1_DAT[5] 82 I/O D Multiplexed pin function.

1. TS input mode: Parallel transport or program

stream data bit[5]

2. Video input mode: Data bit[5] of ITU-656 or VIP

source

3. Video output mode: Data bit[5] of internally

decoded video

TS1_DAT[6] 83 I/O D Multiplexed pin function.

1. TS input mode: Parallel transport or program

stream data bit[6]

2. Video input mode: Data bit[6] of ITU-656 or VIP

source

3. Video output mode: Data bit[6] of internally

decoded video

TS1_DAT[7] 84 I/O D Multiplexed pin function.

1. TS input mode: Parallel transport or program

stream data bit[7]

2. Video input mode: Data bit[7] of ITU-656 or VIP

source

3. Video output mode: Data bit[7] of internally

decoded video

VDDIO 85 Dp Digital I/O pad power

GPIO[9] 86 I/O D General Purpose I/O

Configurable multifunction status/control pin

GPIO[8] 87 I/O D General Purpose I/O

Configurable multifunction status/control pin

VDD 88 Dp Digital core logic power

GPIO[0] 89 I/O D General Purpose I/O

Configurable multi-function status/control pin

GPIO[1] 90 I/O D General Purpose I/O

Configurable multi-function status/control pin

GPIO[2] 91 I/O D General Purpose I/O

Configurable multi-function status/control pin

GPIO[3] 92 I/O D General Purpose I/O

Configurable multi-function status/control pin

SDA1 93 O D I2C-compatible serial data

SCL1 94 I/O D I2C-compatible serial clock output

GPIO[4] 95 I/O D General Purpose I/O

Configurable multifunction status/control pin

Table 3. Pin List (7 of 10)

Pin Name Pin Number Dir Type Description

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Pin Descriptions CX23885 Data Sheet

VDD 96 Dp Digital core logic power

SDA2 97 O D I2C-compatible serial data

SCL2 98 I/O D I2C-compatible serial clock output

VDDIO 99 Dp Digital I/O pad power

GPIO[5] 100 I/O D General Purpose I/O

Configurable multifunction status/control pin

GPIO[6] 101 I/O D General Purpose I/O

Configurable multifunction status/control pin

VDD 102 Dp Digital core logic power

I2S_BCLK(GPIO[23]) 103 I/O D When GPIO2_OUT_ENABLE_N bit is set in the

GPIO2_OUT_EN_REG register:

I2S bit clock for sampling serial data

When GPIO2_OUT_ENABLE_N bit is cleared in the

GPIO2_OUT_EN_REG register:

This is a General Purpose I/O

Configurable multifunction status/control pin.

I2S_WCLK

(GPIO[22])

104 I/O D When GPIO2_OUT_ENABLE_N bit is set in the

GPIO2_OUT_EN_REG register:

I2S word clock to frame data word boundaries

When GPIO2_OUT_ENABLE_N bit is cleared in the

GPIO2_OUT_EN_REG register:

This is a General Purpose I/O

Configurable multifunction status/control pin.

I2S_SDAT(GPIO[21]) 105 I/O D When GPIO2_OUT_ENABLE_N bit is set in the

GPIO2_OUT_EN_REG register:

I2S serial data

When GPIO2_OUT_ENABLE_N bit is cleared in the

GPIO2_OUT_EN_REG register:

This is a General Purpose I/O

Configurable multifunction status/control pin.

IR_RX (GPIO[19]) 106 I/O D When GPIO2_OUT_ENABLE_N bit is set in the

GPIO2_OUT_EN_REG register:

Infrared remote control receiver input

When GPIO2_OUT_ENABLE_N bit is cleared in the

GPIO2_OUT_EN_REG register:

This is a General Purpose I/O

Configurable multifunction status/control pin.

Table 3. Pin List (8 of 10)

Pin Name Pin Number Dir Type Description

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CX23885 Data Sheet Pin Descriptions

IR_TX (GPIO[20]) 107 I/O D When GPIO2_OUT_ENABLE_N bit is set in the

GPIO2_OUT_EN_REG register:

Infrared transmitter output

When GPIO2_OUT_ENABLE_N bit is cleared in the

GPIO2_OUT_EN_REG register:

This is a General Purpose I/O

Configurable multifunction status/control pin.

Reserved 108 Reserved pin. Not connected.

Reserved 109 Reserved pin. Not connected.

VDD 110 Dp Digital I/O pad power

GPIO[7] 111 I/O D General Purpose I/O

Configurable multifunction status/control pin

VDDO_PLL 112 Ap Isolated Aux PLL output pad power

AUX_PLL_CLK 113 O D Aux PLL output

VSSO_PLL 114 Ap Isolated Aux PLL output pad ground

VSS_PLL 115 Ap Analog PLL ground

VAA_PLL 116 Ap Analog PLL power

Reserved 117 Reserved pin. Should not be connected.

Reserved 118 Reserved pin. Should not be connected.

Reserved 119 Reserved pin. Should not be connected.

Reserved 120 Reserved pin. Should not be connected.

VAA_ADC2 121 Ap ADC core power. VAA_ADC = 3.3 V nominal.

VSS_ADC2 122 Ap ADC core ground

VSS_ADC1 123 Ap ADC core ground

VAA_ADC1 124 Ap ADC core power. VAA_ADC = 3.3 V nominal.

ASUB 125 Ap ADC core substrate ground

VIN1 126 I As Composite or Luma signal input to ADC1. The signal

passes through on-chip analog multiplexers before

passing through a gain stage, an anti-alias filter stage,

and into ADC1. Unused inputs should not be

connected.

S2D_NEG1 127 I Ar Negative input of single-to-differential converter. Tie to

analog ground through AC coupling capacitor for

common mode noise rejection. The capacitor should

match the value used on the analog inputs.

Table 3. Pin List (9 of 10)

Pin Name Pin Number Dir Type Description

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Pin Descriptions CX23885 Data Sheet

VIN2 128 I As Composite or Luma signal input to ADC1. The signal

passes through on-chip analog multiplexers before

passing through a gain stage, an anti-alias filter stage,

and into ADC1. Unused inputs should not be

connected.

Exposed Pad — — — Tie to digital ground (must be connected).

Legend for Pin Type

Active resistive pullup

Open-drain pads with glitch filters

Analog signal

Analog power or ground

Digital power or ground

Analog reference, for connection to external component

Digital signal

Table 3. Pin List (10 of 10)

Pin Name Pin Number Dir Type Description

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CX23885 Data Sheet Pin Descriptions

Figure 4. Pinout Diagram

102740_002

CX23885

128-pin ETQFP

11 7

11 6

11 5

114

11 3

11 2

111

110

109

108

107

106

105

104

103

102

101

100

TXM

VSSTA

REFCLKP

REFCLKM

GPIO[15]

TXP

VSSTO

GPIO[13]

RXP

VSSA

VDDA

RXM

VDDA

REF_RES

Reserved

VDDRO

VSSRO

VDDTO

VDDT

VSST

VDD

127

126

125

124

123

122

121

120

119

11 8

128

VIN5

IREF

VSS_CH1

SD2_NEG2

VIN7

VIN6

VIN8

VSS_CH2

VAA_CH2

VAA_CH1

VIN4

VAA_DS1

VAA_XTAL

ASUB_DS

VR1

VR_NEG

VR2

VL1

VL_NEG

VL2

VSS_DS2

VAA_DS2

VOUT_REG

VIN_REG

TEST

PERST_N

RESET_OUT_N

VDD

GPIO[14]

VDD

VDDIO

TS2_VAL

TS2_SOP

TS1_VAL

GPIO[1]

GPIO[0]

VDD

TS1_DAT[5]

TS1_DAT[4]

TS1_DAT[3]

VDDIO

TS1_DAT[7]

TS1_DAT[6]

TS1_DAT[2]

TS1_DAT[1]

TS1_DAT[0]

UTX(GPIO[18])

URX(GPIO[17])

TS1_SOP

TS2_CLK

TS2_DAT

VDD

TS1_CLK

GPIO[2]

GPIO[3]

SDA_1

SCL_1

VDD

VAA_ADC1

VSS_ADC1

ASUB

SDA_2

VIN1

S2D_NEG1

VIN2

VSS_ADC2

VAA_ADC2

IR_TX(GPIO[20])

VAA_PLL

I2S_WCLK(GPIO[22])

VSS_PLL

VSSO_PLL

AUX_PLL_CLK

VDDO_PLL

VDD

Reserved

I2S_SDAT(GPIO[21])

Reserved

IR_RX(GPIO[19])

I2S_BCLK(GPIO[23])

VDDIO

VDD

IRQ_N(GPIO[16])

SCL_2

VDDT

VDDTA

VIN3

VSS_XTAL

XTI

XTO

VSS_DS1

VREFP_DS

VREFM_DS

VAA_REG GPIO[12]

GPIO[11]

GPIO[10]

GPIO[9]

GPIO[8]

GPIO[4]

GPIO[5]

GPIO[6]

GPIO[7]

RESERVED

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3Registers

3.1 Register Map

Table 4. Register Map

RO Read-only

WO Write-only

RW Read/Write

RW* Read/Write, but data may not be same as written at a later time.

RR Same as RW, but writing a 1 resets corresponding bit location, writing 0 has no effect.

RWp Read-only, Write-only shared port, data written cannot be read. Only accessible by DMAC.

Rp Read-only port. Only accessible by DMAC.

Wd Write-only, operates on other data entering register.

GENERAL NOTE:

1. Unused register bits will read back 0.

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Registers CX23885 Data Sheet

3.2 Memory Mapped Registers: Application Layer

3.2.1 Device Control #2

3.2.2 PCI Interrupt Mask

Bits Type Default Name Description

[31:6] RO 26’b0 Reserved

[5] WO 1’b0 RUN_RISC A value of 1 enables the RISC controller. A

value of 0 holds the RISC controller in a reset

state.

[4:0] RO 5’b0 Reserved

Bits Type Default Name Description

[31:28] RO 4’b0 Reserved

[27] RW 1’b0 AV_CORE_MSK Set when AV_CORE interrupt condition occurs.

Cleared by clearing interrupt bits in AV_CORE

interrupt status register.

A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[26] RW 1’b0 UART_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[25] RW 1’b0 IRQN_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

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[24] RW 1’b0 GPIO1_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[23] RW 1’b0 GPIO0_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks

the pending request.

[22] RW 1’b0 TM_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[21] RW 1’b0 I2C_3_RACK_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[20] RW 1’b0 I2C_3_MSK Set when an I2C #3 read or write operation has

completed.

[19] RW 1’b0 I2C_2_RACK_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[18] RW 1’b0 I2C_2_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[17] RW 1’b0 I2C_1_RACK_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

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[16] RW 1’b0 I2C_1_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[15:3] RW 3’b0 Reserved

[12] RW 1’b0 APB_DMA_BERR_M

A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[11] RW 1’b0 AL_WR_BERR_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[10] RW 1’b0 AL_RD_BERR_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[9] RW 1’b0 RISC_WR_BERR_MS

A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[8] RW 1’b0 RISC_RD_BERR_MS

A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[7] RW 1’b0 RESERVED

[6] RW 1’b0 RESERVED

[5] RW 1’b0 RESERVED

[4] RW 1’b0 AUD_EXT_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

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[3] RW 1’b0 AUD_INT_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[2] RW 1’b0 VID_C_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[1] RW 1’b0 VID_B_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

[0] RW 1’b0 VID_A_MSK A value of 1 enables the corresponding interrupt

bit location in the PCI_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

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Registers CX23885 Data Sheet

3.2.3 PCI Interrupt Status

Bits Type Default Name Description

[31:28] RO 4’h0 Reserved

[27] RO 1’b0 AV_CORE_INT Set when AV_CORE interrupt condition occurs.

Cleared by clearing interrupt bits in AV_CORE

interrupt status register.

[26] RO 1’b0 UART_INT Set when UART interrupt condition occurs.

Cleared by clearing interrupt bits in UART_ISR.

[25] RR 1’b0 IRQN_INT Set when GPIO interrupt condition occurs on pin

IRQN pin, also called GPIO[4].

[24] RR 1’b0 GPIO1_INT Set when GPIO interrupt condition occurs on pin

GPIO[23].

[23] RR 1’b0 GPIO0_INT Set when GPIO interrupt condition occurs on pin

GPIO[22].

[22] RR 1’b0 TM_INT Set when timer TM_CNT reaches its limit

TM_LMT.

[21] RR 1’b0 I2C_3_RACK Set when an I2C #3 read or write operation has

completed successfully. Latched on rising edge of

I2C_2_INT. Intended for status only. Typically

masked off.

[20] RR 1’b0 I2C_3_INT Set when an I2C #3 read or write operation has

completed.

[19] RR 1’b0 I2C_2_RACK Set when an I2C #2 read or write operation has

completed successfully. Latched on rising edge of

I2C_3_INT. Intended for status only. Typically

masked off.

[18] RR 1’b0 I2C_2_INT Set when an I2C #2 read or write operation has

completed.

[17] RR 1’b0 I2C_1_RACK Set when an I2C #1 read or write operation has

completed successfully. Latched on rising edge of

I2C_1_INT. Intended for status only. Typically

masked off.

[16] RR 1’b0 I2C_1_INT Set when an I2C #1 read or write operation has

completed.

[15:13] RO 3’b0 Reserved

[12] RR 1’b0 APB_DMA_BERR_INT Set when the BERR signal is asserted to the ASB

master during an APB DMA.

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[11] RR 1’b0 AL_WR_BERR_INT Set when the BERR signal is asserted to the AL

ASB master during a write transfer.

[10] RR 1’b0 AL_RD_BERR_INT Set when the BERR signal is asserted to the AL

ASB master during a read transfer.

[9] RR 1’b0 RISC_WR_BERR_INT Set when the BERR signal is asserted to the RISC

controller during a write transfer.

[8] RR 1’b0 RISC_RD_BERR_INT Set when the BERR signal is asserted to the RISC

controller during a read transfer.

[7] RO 1’b0 Reserved

[6] RO 1’b0 Reserved

[5] RO 1’b0 Reserved

[4] RO 1’b0 AUD_EXT_INT Set when an external audio interrupt condition

occurs. Cleared by clearing the bits of the Audio

EXT Interrupt Status register.

[3] RO 1’b0 AUD_INT_INT Set when an internal audio interrupt condition

occurs. Cleared by clearing the bits of the Audio

INT Interrupt Status register.

[2] RO 1’b0 VID_C_INT Set when a Video C interrupt condition occurs.

Cleared by clearing the bits of the Video C

Interrupt Status register.

[1] RO 1’b0 VID_B_INT Set when a Video B interrupt condition occurs.

Cleared by clearing the bits of the Video B

Interrupt Status register.

[0] RO 1’b0 VID_A_INT Set when a Video A interrupt condition occurs.

Cleared by clearing the bits of the Video A

Interrupt Status register.

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3.2.4 PCI Interrupt Masked Status

Bits Type Default Name Description

[31:28] RO 4’b0 Reserved

[27] RO 1’b0 AV_CORE_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[26] RO 1’b0 UART_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[25] RO 1’b0 IRQN_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[24] RO 1’b0 GPIO1_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[23] RO 1’b0 GPIO0_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[22] RO 1’b0 TM_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[21] RO 1’b0 I2C_3_RACK_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[20] RO 1’b0 I2C_3_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[19] RO 1’b0 I2C_2_RACK_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[18] RO 1’b0 I2C_2_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[17] RO 1’b0 I2C_1_RACK_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[16] RO 1’b0 I2C_1_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[15:13] RO 3’b0 RESERVED

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[12] RO 1’b0 APB_DMA_BERR_MST

These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[11] RO 1’b0 AL_WR_BERR_MSTA

These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[10] RO 1’b0 AL_RD_BERR_MSTA

These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[9] RO 1’b0 RISC_WR_BERR_MS

TAT

These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[8] RO 1’b0 RISC_RD_BERR_MS

TAT

These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[7] RO 1’b0 RESERVED

[6] RO 1’b0 RESERVED

[5] RO 1’b0 RESERVED

[4] RO 1’b0 AUD_EXT_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[3] RO 1’b0 AUD_INT_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[2] RO 1’b0 VID_C_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[1] RO 1’b0 VID_B_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

[0] RO 1’b0 VID_A_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

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Registers CX23885 Data Sheet

3.2.5 Video A Interrupt Mask

3.2.6 Video A Interrupt Status

Bits Type Default Name Description

[31:18] RO 14’b0 Reserved

[17:0] RW 18’b0 VID_A_INT_MSK A value of 1 enables the corresponding interrupt

bit location in the VID_A_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until the

device driver clears or masks the pending request.

Bits Type Default Name Description

[31:18] RO 14’b0 Reserved

[17] RR 1’b0 VBI_A_OPC_ERR Set when the RISC controller detects a

reserved/unused opcode in the VBI A

instruction sequence.

[16] RR 1’b0 VID_A_OPC_ERR Set when the RISC controller detects a

reserved/unused opcode in the video A

instruction sequence.

[15:14] RO 2’b0 Reserved

[13] RR 1’b0 VBI_A_SYNC Set when number of lines or bytes do not match

the VBI A RISC program expectations.

[12] RR 1’b0 VID_A_SYNC Set when number of lines or bytes do not match

the video A RISC program expectations.

[11:10] RO 2’b0 Reserved

[9] RR 1’b0 VBI_A_OF Set when VBI A FIFO overflow condition is

being handled.

[8] RR 1’b0 VID_A_OF Set when video A FIFO overflow condition is

being handled.

[7:6] RO 2’b0 Reserved

[5] RR 1’b0 VBI_A_RISCI2 Set when the IRQ2 bit in a VBI A RISC

instruction is set.

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3.2.7 Video A Interrupt Masked Status

3.2.8 Video A Interrupt Set Status

3.2.9 Video B Interrupt Mask

[4] RR 1’b0 VID_A_RISCI2 Set when the IRQ2 bit in a video A RISC

instruction is set.

[3:2] RO 2’b0 Reserved

[1] RR 1’b0 VBI_A_RISCI1 Set when the IRQ1 bit in a VBI A RISC

instruction is set.

[0] RR 1’b0 VID_A_RISCI1 Set when the IRQ1 bit in a video A RISC

instruction is set.

Bits Type Default Name Description

[31:18] RO 14’b0 Reserved

[17:0] RO 18’b0 VID_A_INT_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

Bits Type Default Name Description

[31:18] RO 14’b0 Reserved

[17:0] WO 18’b0 VID_INT_SSTAT Writing a 1 to these bits will set the corresponding

bits in the status register.

Bits Type Default Name Description

[31:21] RO 11’b0 Reserved

[20:0] RW 21’b0 VID_B_INT_MSK A value of 1 enables the corresponding interrupt

bit location in the VID_B_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until

the device driver clears or masks the pending

request.

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Registers CX23885 Data Sheet

3.2.10 Video B Interrupt Status

Bits Type Default Name Description

[31:21] RO 11’b0 Reserved

[20] RR 1’b0 TS_BAD_PCKT Set when the MPEG transport stream interface

detects an error (either of the three status check

bits are set and the appropriate error condition is

detected).

[19:18] RO 2’b0 Reserved

[17] RR 1’b0 VBI_B_OPC_ERR Set when the RISC controller detects a reserved/

unused opcode in the VBI B instruction

sequence.

[16] RR 1’b0 VID_B_OPC_ERR Set when the RISC controller detects a reserved/

unused opcode in the video B instruction

sequence.

[15:14] RO 2’b0 Reserved

[13] RR 1’b0 VBI_B_SYNC Set when number of lines or bytes do not match

the VBI B RISC program expectations.

[12] RR 1’b0 VID_B_SYNC Set when number of lines or bytes do not match

the video B RISC program expectations.

[11:10] RO 2’b0 Reserved

[9] RR 1’b0 VBI_B_OF Set when VBI B FIFO overflow condition is being

handled.

[8] RR 1’b0 VID_B_OF Set when video B FIFO overflow condition is

being handled.

[7:6] RO 2’b0 Reserved

[5] RR 1’b0 VBI_B_RISCI2 Set when the IRQ2 bit in a VBI B RISC

instruction is set.

[4] RR 1’b0 VID_B_RISCI2 Set when the IRQ2 bit in a video B RISC

instruction is set.

[3:2] RO 2’b0 Reserved

[1] RR 1’b0 VBI_B_RISCI1 Set when the IRQ1 bit in a VBI B RISC

instruction is set.

[0] RR 1’b0 VID_B_RISCI1 Set when the IRQ1 bit in a video B RISC

instruction is set.

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3.2.11 Video B Interrupt Masked Status

3.2.12 Video B Interrupt Set Status

3.2.13 Video C Interrupt Mask

Bits Type Default Name Description

[31:21] RO 11’b0 Reserved

[20:0] RO 21’b0 VID_B_INT_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

Bits Type Default Name Description

[31:18] RO 14’b0 Reserved

[17:0] WO 18’b0 VID_INT_SSTAT Writing a 1 to these bits will set the

corresponding bits in the status register.

Bits Type Default Name Description

[31:21] RO 11’b0 Reserved

[20:0] RW 21’b0 VID_C_INT_MSK A value of 1 enables the corresponding interrupt

bit location in the VID_C_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until

the device driver clears or masks the pending

request.

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Registers CX23885 Data Sheet

3.2.14 Video C Interrupt Status

3.2.15 Video C Interrupt Masked Status

Bits Type Default Name Description

[31:21] RO 11’b0 Reserved

[20] RR 1’b0 TS_BAD_PCKT Set when the MPEG transport stream interface

detects an error (either of the three status check

bits are set and the appropriate error condition is

detected).

[19:17] RO 3’b0 Reserved

[16] RR 1’b0 VID_C_OPC_ERR Set when the RISC controller detects a reserved/

unused opcode in the instruction sequence.

[15:13] RO 3’b0 Reserved

[12] RR 1’b0 VID_C_SYNC Set when number of lines or bytes do not match

the video RISC program expectations.

[11:9] RO 3’b0 Reserved

[8] RR 1’b0 VID_C_OF Set when video FIFO overflow condition is being

handled.

[7:5] RO 3’b0 Reserved

[4] RR 1’b0 VID_C_RISCI2 Set when the IRQ2 bit in a video RISC

instruction is set.

[3:1] RO 3’b0 Reserved

[0] RR 1’b0 VID_C_RISCI1 Set when the IRQ1 bit in a video RISC

instruction is set.

Bits Type Default Name Description

[31:21] RO 11’b0 Reserved

[20:0] RO 21’b0 VID_C_INT_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

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3.2.16 Video C Interrupt Set Status

3.2.17 Audio Internal Interrupt Mask

3.2.18 Audio Internal Interrupt Status

Bits Type Default Name Description

[31:17] RO 15’b0 Reserved

[16:0] WO 17’b0 VID_C_INT_SSTAT Writing a 1 to these bits will set the

corresponding bits in the status register.

Bits Type Default Name Description

[31:18] RO 14’b0 Reserved

[17:0] RW 18’b0 AUD_INT_INT_MSK A value of 1 enables the corresponding interrupt

bit location in the AUD_INT_INT_STAT register.

Unmasking a bit may generate an interrupt

immediately due to a previously pending

condition. The interrupt remains asserted until

the device driver clears or masks the pending

request.

Bits Type Default Name Description

[31:18] RO 14’b0 Reserved

[17] RR 1’b0 AUD_INT_B_OPC_ERR Set when the RISC controller detects a

reserved/unused opcode in the internal

audio B instruction sequence.

[16] RR 1’b0 AUD_INT_A_OPC_ERR Set when the RISC controller detects a

reserved/unused opcode in the internal

audio A instruction sequence.

[15:14] RO 2’b0 Reserved

[13] RR 1’b0 AUD_INT_B_SYNC Set when number of lines or bytes do not

match the internal audio B RISC program

expectations.

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3.2.19 Audio Internal Interrupt Masked Status

3.2.20 Audio Internal Interrupt Set Status

[12] RR 1’b0 AUD_INT_A_SYNC Set when number of lines or bytes do not

match the internal audio A RISC program

expectations.

[11:10] RO 2’b0 Reserved

[9] RR 1’b0 AUD_INT_B_OF Set when internal audio B FIFO overflow

condition is being handled.

[8] RR 1’b0 AUD_INT_A_OF Set when internal audio A FIFO overflow

condition is being handled.

[7:6] RO 2’b0 Reserved

[5] RR 1’b0 AUD_INT_B_RISCI2 Set when the IRQ2 bit in an internal audio

B RISC instruction is set.

[4] RR 1’b0 AUD_INT_A_RISCI2 Set when the IRQ2 bit in an internal audio

A RISC instruction is set.

[3:2] RO 2’b0 Reserved

[1] RR 1’b0 AUD_INT_B_RISCI1 Set when the IRQ1 bit in an internal audio

B RISC instruction is set.

[0] RR 1’b0 AUD_INT_A_RISCI1 Set when the IRQ1 bit in an internal audio

A RISC instruction is set.

Bits Type Default Name Description

[31:18] RO 14’b0 Reserved

[17:0] RO 18’b0 AUD_INT_INT_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

Bits Type Default Name Description

[31:18] RO 14’b0 Reserved

[17:0] WO 18’b0 AUD_INT_INT_SSTAT Writing a 1 to these bits will set the

corresponding bits in the status register.

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3.2.21 Audio External Interrupt Mask

3.2.22 Audio External Interrupt Status

Bits Type Default Name Description

[31:17] RO 15’b0 Reserved

[16:0] RW 17’b0 AUD_EXT_INT_MSK A value of 1 enables the corresponding

interrupt bit location in the

AUD_EXT_INT_STAT register. Unmasking a bit

may generate an interrupt immediately due to a

previously pending condition. The interrupt

remains asserted until the device driver clears

or masks the pending request.

Bits Type Default Name Description

[31:17] RO 15’b0 Reserved

[16] RR 1’b0 AUD_EXT_OPC_ERR Set when the RISC controller detects a

reserved/unused opcode in the external

audio instruction sequence.

[15:13] RO 3’b0 Reserved

[12] RR 1’b0 AUD_EXT_SYNC Set when number of lines or bytes do not

match the external audio RISC program

expectations.

[11:9] RO 3’b0 Reserved

[8] RR 1’b0 AUD_EXT_OF Set when external audio FIFO overflow

condition is being handled.

[7:5] RO 3’b0 Reserved

[4] RR 1’b0 AUD_EXT_RISCI2 Set when the IRQ2 bit in an external audio

RISC instruction is set.

[3:1] RO 3’b0 Reserved

[0] RR 1’b0 AUD_EXT_RISCI1 Set when the IRQ1 bit in an external audio

RISC instruction is set.

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3.2.23 Audio External Interrupt Masked Status

3.2.24 Audio External Interrupt Set Status

Bits Type Default Name Description

[31:17] RO 15’b0 Reserved

[16:0] RO 17’b0 AUD_EXT_INT_MSTAT These bits are the logical AND of the

corresponding bits in the status and mask

registers.

Bits Type Default Name Description

[31:17] RO 15’b0 Reserved

[16:0] WO 17’b0 AUD_EXT_INT_SSTAT Writing a 1 to these bits will set the

corresponding bits in the status register.

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3.3 Memory Mapped Registers: DMAC

3.3.1 APB DMAC Current Buffer Pointer

Bits Type Default Name Description

[31:24] RO 8’b0 Reserved

[23:2] RO 22’hxxxxxx DMA{x}_PTR1 Current DMA qword or dword address pointer.

Points to next qword or qword transfer location

within source or destination buffer. Always

dword-aligned.

[1:0] RO 2’b00 Reserved

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3.3.2 APB DMAC Current Table Pointer

Bits Type Default Name Description

[31:24] RO 8’b0 Reserved

[23:2] RW* 22’hxxxxxx DMA{x}_PTR2 Current DMA CDT address pointer. Points to

current CDT entry. Always dword-aligned.

[1:0] RO 2’b00 Reserved

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3.3.3 APB DMAC Buffer Limit

Bits Type Default Name Description

[31:11] RO 21’b0 Reserved

[10:0] RW* 11’hxxx DMA{x}_CNT1 Initialize to DMA buffer size in # of owords or

qwords. Increments during DMA data transfers

and reloads when next CDT pointer is fetched.

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3.3.4 APB DMAC Table Size

Bits Type Default Name Description

[31:11

]

RO 21’b0 Reserved

[10:0] RW* 11’hxxx DMA{x}_CNT2 Initialize to DMA CDT size in # of qwords.

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3.4 Memory Mapped Registers: Miscellaneous

Utilities

3.4.1 Timer Counters

3.4.2 Timer Limit Values

Bits Type Default Name Description

[31:0] RO 32’b0 TM_CNT_LDW Lower dword of timer. The timer increments

every 96 ns, from 0 to the limit value, then resets

to 0 and counts again. The maximum value

provides for ~312 days. The upper 16-bits of the

timer are captured for reading at the

TM_CNT_UW register whenever the

TM_CNT_LDW register is read.

Bits Type Default Name Description

[31:16] RO 16’b0 Reserved

[15:0] RO 16’b0 TM_CNT_UW Upper 16-bits of the 48-bit timer, captured at the

time the lower 32-bits were read. The timer

increments every 96 ns, from 0 to the limit value,

then resets to 0 and counts again. The maximum

value provides for ~312 days.

Bits Type Default Name Description

[31:0] RW 32’b0 TM_LMT_LDW When the current count value of the timer

reaches the limit value, an interrupt TM_INT is

set. The periodic timer interrupt event rate is =

10.4 MHz / (TM_LMT + 1). If TM_LMT is set to 0,

TM_CNT remains reset.

Bits Type Default Name Description

[31:16] RO 16’b0 Reserved

[15:0] RW 16’b0 TM_LMT_UW When the current count value of the timer

reaches the limit value, an interrupt TM_INT is

set. The periodic timer interrupt event rate is =

10.4 MHz / (TM_LMT + 1). If TM_LMT is set to 0,

TM_CNT remains reset. TM_CNT is reset

whenever TM_LMT_UW is written.

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3.4.3 GPIO

3.4.4 GPIO Interrupts Sensitivity Mode

3.4.5 Soft Reset

Bits Type Default Name Description

[31:24] RO 8’h00 Reserved

[23:16] RW 8’h00 GP_OE A value of 1 enables corresponding GP_IO bit to

be output on the GPIO pin.

A value of 0 enables corresponding GP_IO bit to

be input on the GPIO pin.

[15:8] RO 8’h00 GP_IN The values from the GPIO pins.

[7:0] RW* 8’h00 GP_OUT The values to drive out on the GPIO pin. This is a

don’t-care if GP_OE is set to 0.

Bits Type Default Name Description

[6:4] WO 3’b000 GP_ISM_SNS Sensitivity mode for interrupt inputs GPIO[TBD].

0 = level-sensitive

1 = edge-sensitive

[2:0] WO 3’b000 GP_ISM_POL Polarity control for interrupt inputs GPIO[TBD].

1 = active-hi or posedge

0 = active-lo or negedge

Note this control inverted from SPIPE for active

low interrupts default.

Bits Type Default Name Description

[31:1] R0 31’b0 Reserved

[0] RW 1’b0 SOFT_RESET Software reset register bit, writing this bit to 1 will

generate reset pulse that reset whole Pecos

except PCI-Express Physical layer.

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3.4.6 GPIO (417 Microcontroller Interface) RW Data

3.4.7 GPIO (417 Microcontroller) Output Enable, Low Active

Bits Type Default Name Description

[31:16] RO 16'b 0 Reserved

[15:0] RW* 16'b 0 MC417_GPIO_RWD Read/Write data register.

The values to drive out on the MC417

GPIO[18:3] pin.

When the RD/WR register is read, each bit reads

back either the PAD input value if the pad is

configured as an input or the latched output

value if it is configured as an output.

MC417 GPIO[18:3] is mapped to pads {UTX,

URX, IRQ_N, GPIO[15:4], select one of

GPIO[3:0] by MC417_GPIO_SEL}

Bits Type Default Name Description

[31:16] RO 16'b 0 Reserved

[15:0] RW* 16'h FFFF MC417_GPIO_OEN Output Enable of GPIO[18:3] pins

When MC417 GPIO Mode is activated,

GPIO[18:3] is mapped to {UTX, URX, IRQ_N,

GPIO[15:4], select one of GPIO[3:0] by

MC417_GPIO_SEL}

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3.4.8 GPIO (417 Microcontroller) Output Enable, Low Active

Bits Type Default Name Description

[31:6] RO 26'b 0 Reserved

[5:4] RW 2'b 11 MC417_SPD_CTL Pad drive strength (or speed) for GPIO[18:4]

pins to be used for 417 microcontroller interface

00 = medium

01 = slow

1x = fast

[3] RO 1'b 0 Reserved

[2:1] RW 2'b 11 MC417_GPIO_SEL Select one of 4 GPIO[3:0] pins as MC417 I/F pin,

default is 2'b11 indicating GPIO[3] is selected as

MC417 GPIO I/F

MC417_GPIO_SEL[1:0] = 2'b11: GPIO[3] is

selected for MC417 I/F pin

MC417_GPIO_SEL[1:0] = 2'b10: GPIO[2] is

selected for MC417 I/F pin

MC417_GPIO_SEL[1:0] = 2'b01: GPIO[1] is

selected for MC417 I/F pin

MC417_GPIO_SEL[1:0] = 2'b00: GPIO[0] is

selected for MC417 I/F pin

[0] RW 1'b 0 UART_GPIO_EN A value of 1 will enable the GPIO[18:16] pins &

GPIO[11] pin for

microcontroller interface

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3.4.9 Clock Delay

Bits Type Default Name Description

[31:20] RO 12’h000 Reserved

[19:16] RW 4’h0 JTCK_DLY_SEL Select programmable delay for JTCK from 0

buffer delay (4’h0) to 15 buffers delay (4’hF).

[15:12] RW 4’h0 PCLK_DLY_SEL Select programmable delay for 62.5 MHz pclk

from 0 buffer delay (4’h0) to 15 buffers delay

(4’hF).

[11:8] RW 4’h1 BCLK_N_DLY_SEL Select programmable delay for 125 MHz bclk_n

from 0 buffer delay (4’h0) to 15 buffers delay

(4’hF).

[7:4] RW 4’h1 BCLK_DLY_SEL Select programmable delay for 125 MHz bclk

from 0 buffer delay (4’h0) to 15 buffers delay

(4’hF).

[3:0] RW 4’h2 MCLK_DLY_SEL Select programmable delay for 250 MHz mclk

from 0 buffer delay (4’h0) to 15 buffers delay

(4’hF).

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3.4.10 Pad Control

Bits Type Default Name Description

[31:26] RO 6’b000000 Reserved

[25:24] RW 2’b00 MISC_SPD Pad drive strength (or speed) for miscellaneous

pins, RESET_OUT_N and TEST, PERST_N

(these are input only for now and not testable):

00 = medium

01 = slow

1x = fast

[23:22] RW 2’b01 GPIO_SPD Pad drive strength (or speed) for GPIO, IRQN

pins:

00 = medium

01 = slow

1x = fast

[21:20] RW 2’b01 UART_SPD Pad drive strength (or speed) for UART interface

pins, UTX, URX:

00 = medium

01 = slow

1x = fast

[19:18] RW 2’b00 TS2_SPD Pad drive strength (or speed) for TS2 interface

pins, TS2_SOP, TS2_DATA, TS2_VAL, and

TS2_CLK:

00 = medium

01 = slow

1x = fast

[17:16] RW 2’b00 TS1_SPD Pad drive strength (or speed) for TS1 interface

pins, TS1_DATA, TS1_VAL, TS1_CLK, and

TS1_SOP:

00 = medium

01 = slow

1x = fast

[15:10] RO 6’b000000 Reserved

[9] RW 1’b1 I2C2_MODE Puts I2C#2 SCL and SDA pads into I2C mode.

0 = I2C2_SDA, I2C2_SCL pads in general-

purpose I/O mode

1 = I2C2_SDA, I2C2_SCL pads in I2C mode

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[8] RW 1’b1 I2C1_MODE Puts I2C#1 SCL and SDA pads into I2C mode.

2 = I2C1_SDA, I2C1_SCL pads in general-

purpose I/O mode

3 = I2C1_SDA, I2C1_SCL pads in I2C mode

[7:3] RO 5’b00000 Reserved

[2] RW 1’b0 TS2_SOP_OE When set, enables the output driver for the

TS2_SOP pin, the Transport Stream 2 start-of-

packet pin.

0 = TS2_SOP in input mode

1 = TS2_SOP in output mode

[1] RW 1’b0 TS1_SOP_OE When set, enables the output driver for the

TS1_SOP pin, the Transport Stream 1 start-of-

packet pin.

0 = TS1_SOP in input mode

1 = TS1_SOP in output mode

[0] RW 1’b0 TS1_OE When set, enables the output driver for the

followingTS1 (Transport Stream 1) data, clock,

and valid pins:

• TS1_VAL

• TS1_CLK

• TS1_DATA[7:0]

To summarize:

0 ts1 pins in input mode

1 ts1 pins in output mode

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3.5 Memory Mapped Registers: Video A Interface

3.5.1 Video A General Purpose Counter

3.5.2 Video A General Purpose Counter Control

3.5.3 Video A DMA Control

Bits Type Default Name Description

[31:16] RO 16’b0 Reserved

[15:0] RO 16’b0 {x}_GP_CNT General purpose counter used by RISC

program.

Bits Type Default Name Description

[1:0] WO 2’b00 {x}_GPCTL General purpose counter control used by RISC

program:

00 = no change

01 = increment

10 = reserved

11 = reset to 0

Bits Type Default Name Description

[7:6] RO 2’b0 Reserved

[5] RW 1’b0 VBI_A_RISC_EN VBI RISC controller enable.

[4] RW 1’b0 VID_A_RISC_EN Video RISC controller enable.

[3:2] RO 2’b0 Reserved

[1] RW 1’b0 VBI_A_FIFO_EN VBI FIFO enable.

[0] RW 1’b0 VID_A_FIFO_EN Video FIFO enable.

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3.5.4 Video A VIP Control

3.5.5 Video A Pixel Format

Bits Type Default Name Description

[31:1] RO 31’h00000000 Reserved

[0] RW 1’b0 VIP_MODE This bit is used to specify the format of the

input data, vip 1.1 or vip 2.0.

1’b0 = VIP 1.1

1’b1 = VIP 2.0

Bits Type Default Name Description

[31:5] RO 28’h0000000 Reserved

[4] RW 1’b0 VID_A_GAMMA_FACT

Gamma Correction removal factor selection

for video channel A.

1’b0 = 2.2 factor (NTSC)

1’b1 = 2.8 factor (PAL & SECAM)

[3] RW 1’b1 VID_A_GAMMA_DIS A value of 0 enables gamma correction

removal for Video channel A. The inverse

gamma correction factor of 2.2 or 2.8 is

determined by the vid_a_gamma_factor

1’b0 = enables gamma correction removal

1’b1 = disables gamma correction removal

[2:0] RW 3’b000 VID_A_FORMAT Video A Color Format

000 = RGB32

001 = RGB24

010 = RGB16

011 = RGB15

100 = YUV2 4:2:2

101 = BtYUV 4:1:1

110 = Y8 (Gray scale)

111 = Y210 (10-bit YCrCb 4:2:2)

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3.5.6 Video A VBI Control

Bits Type Default Name Description

[31:2] RO 30’h00000000 Reserved

[1:0] RW 2’b00 VID_A_VIP_EXT VBI select extension enable

This field determines which lines get captured

as vbi data independent of the lines that are

captured for the video data.

2’b00 = DMA buffer for VBI data will contain

VBLANK number of lines

2’b01 = DMA buffer for VBI data will contains

(VBLANK +1) number of lines

2’b10 = DMA buffer for VBI data will contains

(VBLANK +2) number of lines

2’b01 = DMA buffer for VBI data will contains

(VBLANK +3) number of lines

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3.6 Memory Mapped Registers: Video B Interface

3.6.1 Video B General Purpose Counter

3.6.2 Video B General Purpose Counter Control

Bits Type Default Name Description

[63:0] RW 64’bx {x}_DMA qword port for DMA destination

access.

Bits Type Default Name Description

[31:16] RO 16’b0 Reserved

[15:0] RO 16’b0 {x}_GP_CNT General purpose counter used by

RISC program.

Bits Type Default Name Description

[1:0] WO 2’b00 {x}_GPCTL General purpose counter control used

by RISC program:

00 = no change

01 = increment

10 = reserved

11 = reset to 0

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3.6.3 Video B DMA Control

3.6.4 Video B Source Select

3.6.5 Video B TS Line Length

Bits Type Default Name Description

[7:6] RO 2’b0 Reserved

[5] RW 1’b0 VBI_B_RISC_EN VBI RISC controller enable

[4] RW 1’b0 VID_B_RISC_EN Video RISC controller enable

[3:2] RO 2’b0 Reserved

[1] RW 1’b0 VBI_B_FIFO_EN VBI FIFO enable

[0] RW 1’b0 VID_B_FIFO_EN Video FIFO enable

Bits Type Default Name Description

[31:1] RO 31’b0 Reserved

[0] RW 1’b0 VID_B_SRC_SEL Video B source select

0 = External 656 Video

1 = Parallel MPEG Video

Bits Type Default Name Description

[31:12] RO 20’b0 Reserved

[11:0] RW 12’b0 VID_B_LN_LNGTH Transport stream line length in bytes.

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3.6.6 Video B TS HW SOP Control

Bits Type Default Name Description

[31:24] RO 8’b0 Reserved

[23:16] RW 8’d47 APB_STRT_BYTE Byte start pattern that is searched for

in the mpeg transport stream that

signals start of transport stream. This

is issued every mpeg packet.

[15:4] RW 12’d188 APB_PKT_LNGTH Used to sync/mark detect SOP

[3] RW 1’b0 APB_CAP_ALL A value of 1 allows all data of a

punctured clock stream to be

captured. A value of 0 will result in the

first two packets to be lost. This bit

must only be set to 1 when in

punctured clock mode.

[2] RW 1’b0 APB_AUTO_SOP A value of 1 eliminates the need for

an external start of packet in

punctured clock mode. It must only be

used with APB_SOP_SEL = 00. A

value of 0 allows all other start of

packet modes to be used.

[1:0] RW 2’b00 APB_STRT_FLTR_CNT Defines the number of apb_strt_bytes

that need to be detected before the

mpeg fec interface is declared as

being in sync.

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3.6.7 Video B TS General Control

Bits Type Default Name Description

[31:9] RO 23’b0 Reserved

[8] RW 1’b0 APB_DREQ_POL Polarity of Data Request output

signal.

0 = The polarity is active high. Data

Request will be high when the TS-

CLK_EN register bit that drives it is

high.

1 = The polarity is active low. Data

Request will be low when the

TS_CLK_EN register bit that drives it

is high.

[7] WO 1’b0 APB_STAT_CLR Active-High reset for stat registers.

[6] WO 1’b0 APB_SW_RST Active-High Software reset. Writing a

1 to this bit causes the MPEG TS

logic to be held in reset for 128 pclk

cycles.

[5] RW 1’b0 APB_ERR_ACK Determines whether the interface is in

an error ack mode. This is only valid

while APB_PUNC_CLK is active.

[4] RW 1’b0 APB_BIT_RVRS This reverses each byte-wide input

one byte at a time.

[3] RW 1’b1 APB_SMODE Input Mode Select.

0 – Parallel Mode

1 – Serial Mode

[2] RW 1’b0 APB_PUNC_CLK Determines whether the TS interface

is operating in punctured clock mode.

[1] RW 1’b0 APB_MCLK_POL Polarity of MPEG generated MCLK.

Default means TS inputs are negedge

driven. When asserted high TS inputs

are negedge sampled and assumed

posedge driven.

[0] RO 1’b0 MPEG_IN_SYNC Active-high “in sync” indicator for

MPEG.

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3.6.8 Video B TS Bad Packet Status

3.6.9 Video B TS SOP Status

Bits Type Default Name Description

[31:13] RO 19’b0 Reserved

[12] RW 1’b0 APB_BAD_PKT_CHK Enables bad pkt status and

mpeg_bad_pkt interrupt

[11:0] RO 12’h000 MPG_BAD_PKT_STAT Bad pkt counter status. When

enabled,

counter output is incremented every

time a packet number of bytes

received is less than or greater than

the expected programmed number of

bytes. Counter status is updated at

the falling edge of TS_BAD_PKT

interrupt, generated by the internal

mpeg_ts.

Bits Type Default Name Description

[31:17] RO 15’b0 Reserved

[16] RW 1’b0 APB_TSSOP_POL Polarity select

0 – Active High (default)

1 – Active Low

[15:14] RW 2’b00 APB_SOP_SEL SOP Format.

00–- detects rising edge of TSSOP

input

01–- detects rising edge of TSVALERR

input

10–- detects rise and fall edge of

TSSOP input

11 – detects start byte in data stream

[13] RW 1’b0 APB_SOP_BYTEWIDE SOP width select. Byte wide is only an

option in serial mode.

0 – Bit width

1 – Byte width

[12] RW 1’b0 APB_SOP_SYNC_CHK Enables bad sop status and

mpeg_bad_pkt interrupt

[11:0] RO 12’h000 MPG_BAD_SOP_STAT Bad SOP counter status. When

enabled,

counter output is incremented every

time there is a SOP mis-compare.

Counter status is updated at the falling

edge of TS_BAD_PKT interrupt,

generated by the internal mpeg_ts.

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3.6.10 Video B TS Fifo Overflow Status

3.6.11 Video B TS Valid Miscellaneous

Bits Type Default Name Description

[31:13] RO 19’b0 Reserved

[12] RW 1’b0 APB_FIFO_OVFL_CHK Enables FIFO overflow status and

mpeg_bad_pkt

[11:0] RO 12’h000 MPG_FIFO_OVFL_STAT When enabled the counter output is

incremented every time the mpeg TS

FIFO overflows. Counter status is

updated at the falling edge of

TS_BAD_PKT interrupt, generated by

the internal mpeg_ts.

Bits Type Default Name Description

[31:14] RO 18’b0 Reserved

[13] RW 1’b0 APB_TSVALERR_POL Control for polarity of tsvalerr input.

0 – Active-High (Default)

1 – Active-Low

[12] RW 1’b0 APB_VAL_SEL Selects whether tsvalerr is active.

0–- selects the external tsvalerr

(default)

1–- internally generated valid

[11:0] RW 12’h000 APB_VAL_LNGTH Programmable valid length. Used

when mode requires TS to be

terminated after a count vs. the input

valid (tsvalerr)

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3.6.12 Video B TS Clock Enable

3.6.13 Video B VIP Control

Bits Type Default Name Description

[31:1] RO 31’b0 Reserved

[0] RW 1’b1 VID_TS_CLK_EN TS_CLK enable for TS1

0 = disable TS_CLK

1 = enable TS_CLK

This register bit will also drive the Data

Request output signal to the device that is the

source of the MPEG TS. The Data Request

signal will share a pin with the Start Of Packet

input signal, as they are not needed

simultaneously.

Bits Type Default Name Description

[31:1] RO 31’h00000000 Reserved

[0] RW 1’b0 VID_B_VIP_MODE This bit is used to specify the format of the

input data, vip 1.1 or vip 2.0.

1’b0 = VIP 1.1

1’b1 = VIP 2.0

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3.6.14 Video B Pixel Format

Bits Type Default Name Description

[31:5] RO 28”h0000000 Reserved

[4] RW 1’b0 VID_B_GAMMA_FACT

Gamma Correction removal factor selection

for video channel B.

1’b0 = 2.2 factor (NTSC)

1’b1 = 2.8 factor (PAL & SECAM)

[3] RW 1’b1 VID_B_GAMMA_DIS A value of 0 enables gamma correction

removal for Video channel B. The inverse

gamma correction factor of 2.2 or 2.8 is

determined by the vid_a_gamma_factor

1’b0 = enables gamma correction removal

1’b1 = disables gamma correction removal

[2:0] RW 3’b000 VID_B_FORMAT Video B Color Format

000 = RGB32

001 = RGB24

010 = RGB16

011 = RGB15

100 = YUV2 4:2:2

101 = BtYUV 4:1:1

110 = Y8 (Gray scale)

111 = Y210 (10-bit YCrCb 4:2:2)

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3.7 Memory Mapped Registers: Video C Interface

3.7.1 Video C General Purpose Counter

3.7.2 Video C General Purpose Counter Control

3.7.3 Video C DMA Control

Bits Type Default Name Description

[31:16] RO 16’b0 Reserved

[15:0] RO 16’b0 {x}_GP_CNT General purpose counter used by RISC

program.

Bits Type Default Name Description

[1:0] WO 2’b00 {x}_GPCTL General purpose counter control used by RISC

program:

00 = no change

01 = increment

10 = reserved

11 = reset to 0

Bits Type Default Name Description

[7:5] RO 3’b0 Reserved

[4] RW 1’b0 VID_C_RISC_EN Video RISC controller enable

[3:1] RO 3’b0 Reserved

[0] RW 1’b0 VID_C_FIFO_EN Video FIFO enable

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3.7.4 Video C TS Line Length

3.7.5 Video C TS HW SOP Control

Bits Type Default Name Description

[31:12] RO 20’b0 Reserved

[11:0] RW 12’b0 VID_C_LN_LNGTH Transport stream line length in bytes

Bits Type Default Name Description

[31:24] RO 8’b0 Reserved

[23:16] RW 8’h47 APB_STRT_BYTE Byte start pattern that is searched for

in the mpeg transport stream that

signals start of transport stream. This

is issued every mpeg packet.

[15:4] RW 12’hBC APB_PKT_LNGTH Used to sync/mark detect SOP

[3] RW 1’b0 APB_CAP_ALL A value of 1 allows all data of a

punctured clock stream to be

captured. A value of 0 will result in the

first two packets to be lost. This bit

must only be set to 1 when in

punctured clock mode.

[2] RW 1’b0 APB_AUTO_SOP A value of 1 eliminates the need for

an external start of packet in

punctured clock mode. It must only be

used with APB_SOP_SEL = 00. A

value of 0 allows all other start of

packet modes to be used.

[1:0] RW 2’b00 APB_STRT_FLTR_CNT Defines the number of apb_strt_bytes

that need to be detected before the

mpeg fec interface is declared as

being in sync.

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3.7.6 Video C TS General Control

Bits Type Default Name Description

[31:9] RO 23’b0 Reserved

[8] RW 1’b0 APB_DREQ_POL Polarity of Data Request output

signal.

0 = the polarity is active high. Data

Request will be high when the

TS_CLK_EN register bit that drives it

is high.

1 = the polarity is active low. Data

Request will be low when the

TS_CLK_EN register bit that drives it

is high.

[7] WO 1’b0 APB_STAT_CLR Active-High reset for stat registers.

[6] WO 1’b0 APB_SW_RST Active-High Software reset. Writing a

1 to this bit causes the MPEG TS

logic to be held in reset for 128 pclk

cycles.

[5] RW 1’b0 APB_ERR_ACK Determines whether the interface is in

an error ack mode. This is only valid

while APB_PUNC_CLK is active.

[4] RW 1’b0 APB_BIT_RVRS This reverses each byte-wide input

one byte at a time.

[3] RW 1’b1 APB_SMODE Input Mode Select.

0 – Parallel Mode

1 – Serial Mode

[2] RW 1’b0 APB_PUNC_CLK Determines whether the TS interface

is operating in punctured clock mode.

[1] RW 1’b0 APB_MCLK_POL Polarity of MPEG generated MCLK.

Default means TS inputs are negedge

driven. When asserted high TS inputs

are negedge sampled and assumed

posedge driven.

[0] RO 1’b0 MPEG_IN_SYNC Active-high “in sync” indicator for

MPEG.

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3.7.7 Video C TS Bad Packet Status

3.7.8 Video C TS SOP Status

Bits Type Default Name Description

[31:13] RO 19’b0 Reserved

[12] RW 1’b0 APB_BAD_PKT_CHK Enables bad pkt status and

mpeg_bad_pkt interrupt

[11:0] RO 12’h000 MPG_BAD_PKT_STAT Bad pkt counter status. When enabled,

counter output is incremented every

time a packet number of bytes

received is less than or greater than

the expected programmed number of

bytes. Counter status is updated at the

falling edge of TS_BAD_PKT interrupt,

generated by the internal mpeg_ts.

Bits Type Default Name Description

[31:17] RO 15’b0 Reserved

[16] RW 1’b0 APB_TSSOP_POL Polarity select

0 = Active High (default)

1 = Active Low

[15:14] RW 2’b00 APB_SOP_SEL SOP Format.

00 = detects rising edge of TSSOP

input

01 = detects rising edge of TSVALERR

input

10 = detects rise and fall edge of

TSSOP input

11 = detects start byte in data stream

[13] RW 1’b0 APB_SOP_BYTEWIDE SOP width select. Byte wide is only an

option in serial mode.

0 = Bit width

1 = Byte width

[12] RW 1’b0 APB_SOP_SYNC_CHK Enables bad sop status and

mpeg_bad_pkt interrupt

[11:0] RO 12’h000 MPG_BAD_SOP_STAT Bad SOP counter status. When

enabled,

counter output is incremented every

time there is a SOP mis-compare.

Counter status is updated at the

falling edge of TS_BAD_PKT

interrupt, generated by the internal

mpeg_ts.

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3.7.9 Video C TS Fifo Overflow Status

3.7.10 Video C TS Valid Miscellaneous

Bits Type Default Name Description

[31:13] RO 19’b0 Reserved

[12] RW 1’b0 APB_FIFO_OVFL_CHK Enables FIFO overflow status and

mpeg_bad_pkt.

[11:0] RO 12’h000 MPG_FIFO_OVFL_STAT When enabled the counter output is

incremented every time the mpeg TS

FIFO overflows. Counter status is

updated at the falling edge of

TS_BAD_PKT interrupt, generated by

the internal mpeg_ts.

Bits Type Default Name Description

[31:14] RO 18’b0 Reserved

[13] RW 1’b0 APB_TSVALERR_POL Control for polarity of tsvalerr input.

0 = Active-High (Default)

1 = Active-Low

[12] RW 1’b0 APB_VAL_SEL Selects whether tsvalerr is active.

0 = selects the external tsvalerr (default)

1 = internally generated valid

[11:0] RW 12’h000 APB_VAL_LNGTH Programmable valid length. Used when

mode requires TS to be terminated after

a count vs. the input valid (tsvalerr)

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3.7.11 Video C TS Clock Enable

Bits Type Default Name Description

[31:1] RO 31’b0 Reserved

[0] RW 1’b0 VIDC_TS_CLK_EN TS_CLK_enable for TS2

0 =disable TS_CLK

1 = enable TS_CLK

This register bit will also drive the Data

Request output signal to the device that

is the source of the MPEG TS. The Data

Request signal will share a pin with the

Start Of Packet input signal, as they are

not needed simultaneously.

[12] RW 1’b0 APB_VAL_SEL Selects whether tsvalerr is active.

0 = selects the external tsvalerr (default)

1 = internally generated valid

[11:0] RW 12’h000 APB_VAL_LNGTH Programmable valid length. Used when

mode requires TS to be terminated after

a count vs. the input valid (tsvalerr)

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3.8 Memory Mapped Registers: Internal Audio

Interface

3.8.1 Audio Internal General Purpose Counter

3.8.2 Audio Internal General Purpose Counter Control

3.8.3 Audio Internal DMA Control

Bits Type Default Name Description

[31:16] RO 16’b0 Reserved

[15:0] RO 16’b0 {x}_GP_CNT General purpose counter used by RISC

program.

Bits Type Default Name Description

[1:0] WO 2’b00 {x}_GPCTL General purpose counter control used

by RISC program:

00 = no change

01 = increment

10 = reserved

11 = reset to 0

Bits Type Default Name Description

[7:6] RO 2’b0 Reserved

[5] RW 1’b0 AUD_INT_B_RISC_EN Internal audio B RISC controller enable

[4] RW 1’b0 AUD_INT_A_RISC_EN Internal audio A RISC controller enable

[3:2] RO 2’b0 Reserved

[1] RW 1’b0 AUD_INT_B_FIFO_EN Internal audio B FIFO enable

[0] RW 1’b0 AUD_INT_A_FIFO_EN Internal audio A FIFO enable

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3.8.4 Audio Internal Line Length

3.8.5 Audio Internal Mode Selection

Bits Type Default Name Description

[31:12] RO 20’b0 Reserved

[11:0] RW 12’b0 AUD{x}_LNGTH Internal audio line length in bytes

Bits Type Default Name Description

[31:1] RO 20’b0 Reserved

[0] RW 1’b0 AUD{x}_MODE Internal audio mode:

1 = 32 bits input mode (16 bits L/R)

0 = 48 bits input mode (24 bits L/R)

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3.9 Memory Mapped Registers: External Audio

Interface

3.9.1 Audio External DMA Port

3.9.2 Audio External General Purpose Counter

3.9.3 Audio External General Purpose Counter Control

Bits Type Default Name Description

[63:0] RW

64’bx {x}_DMA qword port for DMA destination access

Bits Type Default Name Description

[31:16] RO 16’b0 Reserved

[15:0] RO 16’b0 {x}_GP_CNT General purpose counter used by RISC

program

Bits Type Default Name Description

[1:0] WO 2’b00 {x}_GPCTL General purpose counter control used

by RISC program:

00 = no change

01 = increment

10 = reserved

11 = reset to 0

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3.9.4 Audio External DMA Control

3.9.5 Audio External Line Length

3.9.6 Audio External Mode Selection

Bits Type Default Name Description

[7:5] RO 3’b0 Reserved

[4] RW 1’b0 AUD_EXT_RISC_EN External audio RISC controller enable

[3:1] RO 3’b0 Reserved

[0] RW 1’b0 AUD_EXT_FIFO_EN External audio FIFO enable

Bits Type Default Name Description

[31:12] RO 20’b0 Reserved

[11:0] RW 12’b0 AUD_EXT_LN_LNGTH External audio line length in bytes

Bits Type Default Name Description

[31:1] RO 20’b0 Reserved

[0] RW 1’b0 AUD_EXT_MODE External audio input mode:

1 = 32 bits input mode (16 bits L/R)

0 = 48 bits input mode (24 bits L/R)

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3.10 Memory Mapped Registers: I2C Master

The I2C protocol defines a method to send and receive a variable number of bytes via

a serial bus that interconnects several IC's. Corona contains an I2C master than can

drive this bus, and the registers below provide the programmable interface to three

I2C masters. There are three sets of registers, one for each I2C master.

First, some background is useful on the basic I2C protocol. The basic I2C protocol for

writes:

1. Send Start sequence (SDA falls while SCL is high)

2. Send 7-bit Device Address

3. Send R/W bit, set to 0

4. Check for Slave Ack, and if received, continue

5. Send variable number of bytes, checking for Ack after each byte

6. Optionally send Stop (SDA rises while SCL is high)

The basic I2C protocol for reads:

1. Send Start (SDA falls while SCL is high)

2. Send 7-bit Device Address

3. Send R/W bit, set to 1

4. Check for Slave Ack, and if received, turnaround bus to let slave drive bus

5. Receive variable number of bytes, send Ack after each byte until done

6. Optionally send stop (SDA rises while SCL is high)

The Stop condition is not important for most slaves, since the next Start (or repeated

Start) will re-initialize its state the same as a Stop would. The Stop is important for

multi-master systems, and as it's a way for a master to relinquish control of the bus.

But while I2C defines only this simple mechanism of transmitting or receiving a

variable number of bytes to/from a specific device address, it is customary for devices

to define the first N bytes of a write (one to three bytes have been observed) as a

subaddress. This subaddress typically functions as an index into a register map. Also,

it is typical for slave devices to support the concept that the byte transmitted after this

subaddress goes to the location specified by that subaddress, and each subsequent

byte goes to an auto incrementing address from the initial point. Reads work in a

similar manner, but since reads cycles do not have a means to send a subaddress, the

convention is that reads come from the last subaddress sent on a write transaction.

Thus, a read of a specific subaddress is often accomplished by transmitting the

subaddress bytes through a write, followed by a read transaction. Each byte from the

read is assumed to come from auto incrementing addresses, starting at the

subaddress sent by the write.

The idea of the programmable register interface described in the following sections is

to allow software to flexibly execute the basic I2C protocol, while providing some

convenience features for devices that conform to a typical subaddress model. The

hardware provides three methods for software to interface to the I2C bus:

1. Software Mode. Directly toggle the SCL and SDA lines, thereby implementing the

protocol through software. (All other modes are hardware mode.)

2. Simple Mode. For writes, specify the Device Address, the number of bytes to send

(0 to 4), and the data bytes themselves. For reads, specify the Device Address,

the number of bytes to receive, and read the received bytes from a register.

I2C_SADDR_LEN is set to 0 for this mode. The I2C_DATA_LEN specifies the

number of bytes to send or receive.

3. Subaddress Mode. This supports directly the subaddress model. For writes, the

hardware automatically inserts a subaddress before the data bytes. The number

of subaddress bytes to insert is controlled by I2C_SADDR_LEN, which can be 1

to 3. For reads, the hardware will automatically insert a subaddress write before

receiving data bytes. This mode provides a couple of features for software. First,

because the subaddress field has an auto increment feature, software need not

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re-write this field each time if is doing multiple write or read transactions to

sequential addresses. Second, the hardware knows which bytes to send to set the

subaddress before issuing a read transaction.

Thus, an important feature is the ability to specify both the number of address bytes,

and the number of data bytes in any given I2C cycle. The hardware also provides

some additional features to optimize hardware mode operation:

1. Extend mode. This allows software to generate any length I2C transaction by

repeatedly accessing the register set. This eliminates the inefficiency of re-

sending the device address and subaddress bytes. By setting I2C_EXTEND,

each time an I2C transaction is triggered, the hardware will just continue the

previous transaction, transmitting or receiving the number of bytes specified in

I2C_DATA_LEN. No Stop or Start transitions will be generated. The current I2C

transaction will be extended until the I2C_EXTEND bit is disabled.

2. Simple read mode. The hardware can support a subaddress field on writes, but

disable the feature that sends an I2C write transaction to set subaddress field

prior to reads. This prevents unnecessary write transactions if the slave device is

keeping track of the subaddress anyway. Set I2C_READ_SA to 0 for simple read

mode.

To trigger a hardware mode I2C cycle, simple write to the I2C{X}_CNTRL dword. For

writes, software should have already written the I2C{X}_DATA and I2C{X}_ADDR

registers. Software can launch another I2C operation after the I2C_XFER_RDY bit is

set. For reads, software should write the I2C{X}_ADDR register before initiating the

read with a write to the I2C{X}_CNTRL dword. After the I2C_XFER_RDY bit is set, the

read data will be available in the I2C{X}_DATA register.

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3.10.1 I2C Address

This DWORD contains address information. Note that the R/W bit, normally bundled

with the I2C Device Address, is not included here, but is specified in the control word.

A write must be performed to the I2C{x}_CTRL register to initiate an I2C transaction.

Bits Type Default Name Description

[31:25] RW 7’h00 I2C_DADDR I2C Device Address. These 7 bits contain the

device address. Note that the 7 bits are left

justified within the byte. These bits are transmitted

for every transaction, after the Start transition is

generated.

[24] RO 1’b0 Reserved

[23:0] RW 1’b1 I2C_SADDR I2C subaddress. For I2C Writes only, these bytes

are sent after the device address is sent. The

I2C_SADDR_LEN field determines how many

bytes are sent, which can be 0 to 3. The

subaddress is right-justified within the three-byte

field, such that if only one byte is transmitted, it

will come from I2C_SADDR[7:0]. The address will

be incremented with each I2C byte transaction, if

I2C_SADDR_INC is set.

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3.10.2 I2C Write Data

This register contains the data bytes to send in a write transaction. If

I2C_SADDR_LEN is set to something other than zero, then these bytes will come after

the subaddress field is transmitted. Otherwise, these bytes define all of the bytes that

are sent. The number of bytes sent depends on the I2C_DATA_LEN parameter, which

can be 0 to 4. The counting and transmitting starts at the least-significant byte

(I2C_WDATA[7:0]). A write must be performed to the I2C{x}_CTRL register to initiate

an I2C transaction.

3.10.3 I2C Control

Writing to this register will trigger an I2C read or write operation based on the

I2C_READ_WRN bit.

Bits Type Default Name Description

[31:0] RW 0x0 I2C_WDATA I2C Write Data. Write data is transmitted least-

significant byte first.

Bits Type Default Name Description

[31:24] RW 8’h9D,

8’h27,

8’h27

I2C_PERIOD Period of I2C Clock

For 12C1_CTRL:

I2C_PERIOD = Period (ns) / 16 (pclk period) * 4 –

Default is set for 99.5 kHz operation (to be less

than or equal to 100 kHz).

For 12C1_CTRL:

I2C_PERIOD = Period (ns) / 16 (pclk period) * 4 –

Default is set for 391 kHz operation (to be less

than or equal to 400 kHz)

For 12C1_CTRL:

I2C_PERIOD = Period (ns) / 16 (pclk period) * 4

Default is set for 1.95 MHz operation (to be less

than 2.0 MHz)

[23:22] RO 2’b0 Reserved

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[21] RO 1’b1 I2C_SCL_IN Reading this bit provides access to the buffered

SCL input pin.

[20] RO 1’b1 I2C_SDA_IN Reading this bit provides access to the buffered

SDA input pin.

[19:18] RO 2’b0 Reserved

[17] RW 1’b1 I2C_SCL_OUT A value of 1 releases the SCL output, and a 0

forces the SCL output low. This override is for

direct software control of the bus. Set I2C_SOFT

to 1 to enable this bit.

[16] RW 1’b1 I2C_SDA_OUT A value of 1 releases the SDA output, and a 0

forces the SDA output low. This override is for

direct software control of the bus. Set I2C_SOFT

to 1 to enable this bit.

[15] RO 1’b0 Reserved

[14:12] RW 3’b001 I2C_DATA_LEN Data Length in Bytes. Determines number of

bytes to send from I2C_DATA after subaddress

field. The I2C engine begins transmitting with

I2C_WDATA[7:0] and proceeds to the MSB for

writes. Similarly, for reads, the I2C engine stores

read data first in I2C_RDATA[7:0] and proceeds to

the MSB.

For writes, the action is as follows:

0 = send no data bytes

1 = write I2C_WDATA[7:0]

2 = write I2C_WDATA[15:0]

3 = write I2C_WDATA[23:0]

4 = write I2C_WDATA[31:0]

5-7 = reserved

For writes, the action is as follows:

0 = read no data bytes

1 = read to I2C_RDATA[7:0]

2 = read to I2C_RDATA[15:0]

3 = read to I2C_RDATA[23:0]

4 = read to I2C_RDATA[31:0]

5-7 = reserved

If the logic automatically generates a write to set

the subaddress for a read operation, then this field

is a don’t-care for the write, and should be set

based on the number of bytes to read.

[11] RW 1’b1 I2C_SADDR_INC Address Auto Increment. When set, the

subaddress field in I2C_SADDR[23:0] is

automatically incremented.

[10] RO 1’b0 Reserved

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[9:8] RW 2’b10 I2C_SADDR_LEN Address Length in Bytes. Determines the number

of bytes to send from I2C1_ADDR as subaddress

field of the I2C write transaction. This field follows

the device address. The transmission starts with

most-significant byte, and which byte this is

depends on I2C_SADDR_LEN. The significance

of the subaddress field is that it can support an

auto increment feature compared with data bytes.

0 = send/read no subaddress field bytes

1 = write/read I2C_SADDR[7:0]

2 = write/read I2C_SADDR[15:0]

3 = write/read I2C_SADDR[23:0]

[7:6] RO 2’b00 Reserved

[5] RW 1’b0 I2C_SOFT I2C mode. When set, software drives the SDA and

SCL directly through the I2C_SDA and I2C_SCL

0 = hardware.

1 = software.

[4] RW 1’b0 I2C_NOSTOP I2C stop mode.

0 = transmit stop at end of transaction.

1 = do not transmit stop at end of transaction.

Hold SCL low.

[3] RW 1’b0 I2C_EXTEND I2C Extend Mode.

0 = each transaction ends with a STOP (unless

I2C_NOSTOP is set) and returns to idle.

1 = Transaction does end with a STOP, and does

not go back to IDLE. The SCL signal remains low.

The next transaction will result in data

transmission or reception only according to

I2C_READ_WRN and I2C_DATA_LEN, without

START or device address transmission.

Note: do not change the I2C_READ_WRN bit

while in Extend mode.

To exit extend mode, send last data transaction

without I2C_EXTEND mode = 0.

[2] RW 1’b0 I2C_SYNC I2C synchronization.

0 = disallows the slave to insert wait states.

1 = allows the slave to insert bit-level clock wait

states.

[1] RW 1’b0 I2C_READ_SA I2C Read with subaddress. When set, I2C read

transaction is preceded with I2C write transaction

that sets subaddress field. This can be used to

avoid unnecessary writes if the I2C slave already

has an internal subaddress register set.

0 = I2C read operations result in a single I2C read

transaction to the Device Address

1 = I2C read operations results in an I2C write

transaction to set the subaddress field, followed

by a read transaction.

[0] RW 1’b0 I2C_READ_WRN I2C Read/Write bit.

0 = Issue I2C Write transaction

1 = Issue I2C Read operation subject to

I2C_READ_SA bit.

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3.10.4 I2C Read Data

The returned data from I2C reads is stored here. The number of bytes received

depends on the I2C_DATA_LEN parameter, which can be 0 to 4. The counting and

storing of received data starts at the least-significant byte (I2C_RDATA[7:0]). A write

must be performed to the I2C{x}_CTRL register to initiate an I2C transaction.

3.10.5 I2C Status

This address contains status information.

Bits Type Default Name Description

[31:0] RO 0x0 I2C_RDATA I2C Read Data. Read data is stored in least-

significant byte first.

Bits Type Default Name Description

[1] RO 1’b0 I2C_XFER_IN_PROG Read or Write transaction is in progress.

[0] RO 1’b0 I2C_RACK Received ack successfully. Indicates that slave

acknowledged all transmitted bytes. Valid when

transaction is no longer in progress.

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3.11 Memory Mapped Registers: UART

3.11.1 UART TxD/RxD Control

3.11.2 UART Baud Rate Divisor

Bits Type Default Name Description

[31:8] RO 24’b0 Reserved

[7] RW 1’b0 LOOP_BACK_EN Connects TxD and RxD internally for loopback

testing.

[6:4] RO 3’b0 Reserved

[3:2] RW 2’b0 RX_TRG_SZ RX trigger size (before RxD interrupt).

00 = 1 byte

01 = 4 byte

10 = 8 byte

11 = 12 byte

[1] RW 1’b0 RX_EN Enable receiver, reset when disabled.

[0] RW 1’b0 TX_EN Enable transmitter, reset when disabled.

Bits Type Default Name Description

[31:16] RO 16’b0 Reserved

[15:0] RW 16’h0197 BRD Divide 62.5 MHz clock by this value to generate

16X baud rate clock. Default value generates

9600 baud.

Bits Type Default Name Description

[31:0] RW 32’b0 Reserved

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3.11.3 UART Interrupt Status Register

3.11.4 UART FIFO Status

Bits Type Default Name Description

[31:9] RO 23’b0 Reserved

[8] RW 1’b0 RXD_TIMEOUT RxD timeout interrupt. Interrupt if RX idle for 4

character periods and data is in RX FIFO.

[7] RW 1’b0 RXD_TIMEOUT_EN Enable RX timeout interrupt

[6] RW 1’b0 FRM_ERR_EN Frame error interrupt enable. A logic 1 enables

interrupts on detected frame error.

[5] RW 1’b0 RXD_RDY_EN Receive buffer trigger level interrupt enable. A

logic 1 enables an interrupt when the RX buffer

is ready.

[4] RW 1’b0 TXD_EMPTY_EN Transmit buffer empty interrupt enable. A logic 1

enables interrupts when the transmit buffer

becomes empty.

[3] RR 1’b0 RXD_OVERFLOW Receive data buffer overflow. This bit is set when

a byte is received while the RxD buffer is full

(RXD_CNT == 16). Cleared when written with a

[2] RR 1’b0 FRM_ERR Frame error pending. Set when a framing error

occurs. Cleared when written with a 1. Received

data should be ignored when this bit is set.

[1] RR 1’b0 RXD_RDY Receive buffer ready. Set when the RX buffer

has reached trigger level. Cleared when written

with a 1.

[0] RR 1’b0 TXD_EMPTY Transmitter empty pending. Set when the

transmit buffer becomes empty. Cleared when

written with a 1.

Bits Type Default Name Description

[31:13] RO 19’b0 Reserved

[12:8] RW 5’b0 TXD_CNT # of bytes in TxD FIFO.

[7:5] RO 3’b0 Reserved

[4:0] RW 5’b0 RXD_CNT # of bytes in RxD FIFO.

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3.12 Rider Registers

This module contains all of the registers required to configure and debug Rider. Two

categories of registers are implemented: PCI Express Registers and Rider Registers.

The PCI Express registers are described in the PCI Express Base Specification, and

are used to configure and operate the PCI Express interface. These registers can only

be written using PCI Express Configuration Write transactions.

Rider is a term used to identify the PCI Express PIPE-compliant Endpoint Controller

Core. The Rider Registers provide extra configuration, controllability, and observability

of the Rider core. These registers can only be written by the Application Layer.

Figure 5 shows the interfaces between the CFG block, the Device Core, and the

Transaction Layer.

Figure 5. CFG Block, Device Core, and Transaction Layer Interfaces

102740_003

Application Layer

Interface Interface

Transaction Layer (TL)

Data Link Layer (DLL)

MAC Layer (MACL)

PCI Express Registers

Rider Registers

Device Core

Rider

Read

Read and

Write

Read and

Write

Internal

Bus

CFG Block

Read

0001

2FF1

3FF1

3001

Configuration

Transactions

Memory

Transactions

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3.12.1 Address Space

The PCI Express Base Specification uses 4096 bytes for the PCI and PCI Express

configuration space. However, the PCI Express features implemented in Rider require

less than 512 bytes. Figure 6 shows the address space used by Rider for PCI Express

registers and Rider registers.

Figure 6. Address Space

3.12.2 Accessing PCI Express Registers

PCI Express Registers can only be written by PCI Express configuration transactions

because they are tightly controlled by the host operating system. If another entity was

able to adjust the PCI Express Registers without the host operating system knowing

about the change, the performance and stability of the PCI Express link or the entire

fabric could be adversely affected.

The Application Layer interface provides a convenient method for the driver or another

entity to observe the values of the PCI Express registers. Since none of the PCI

express registers are cleared upon being read, the application layer read activity will

not interfere with the PCI Express configuration or operation.

102740_004

Footnote:

(1) This space is available for other use.

(2) PCI Express Configuration Transactions always read zeros from this space.

000h

Not Used by

Rider(1) (2)

Rider

Registers

Extended

Capability

Structures

Capability

Structures

PCI

Compatible

Header

FFFh

400h

3FFh

300h

2FFh

100h

0FFh

040h

03Fh

PCI Express Extended

Configuration Space

PCI Configuration Space

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3.12.3 Accessing Rider Registers

The Rider registers are used to observe and adjust the behavior of Rider above and

beyond what is available in the PCI Express registers defined in the PCI Express Base

Specification. In order to ensure compliance with the PCI Express Specification, these

registers’ default values conform to the specification.

The Application Layer interface is used to read and write Rider registers. While it is

possible to read the values of the Rider registers using configuration read

transactions, it is not anticipated that the device driver will use this method.

3.12.4 Register Access Exception - Vital Product Data (VPD)

Vital Product Data (VPD) registers are writable from both the Application Layer and the

Transaction Layer. Specifically, the flag bit in the VPD Capabilities Header and the

VPD Data register need to be able to be written by both agents. The VPD protocol as

described in the Conventional PCI Specification is relied upon to avoid conflicting

writes to these fields.

3.12.5 Register Type Restrictions

In general, PCI Express Registers cannot be written or cleared via the Application

Layer regardless of the register type. Similarly, Rider Registers cannot be written or

cleared via PCI Express Configuration Transactions. A small number of PCI Express

RO Registers can be written by the Application Layer after reset for initialization.

3.12.6 Read-Only Registers

The value of Read-Only registers can be set by hardwiring values, by the Application

Layer initializing values after reset, or by assigning the value to a signal inside of

Rider.

3.12.7 Read-Write Registers

Read-Write registers are assigned default values listed. They are implemented as flip-

flops inside the CFG block and may be written by the Configuration Write Transactions

if they are PCI Express Registers or via the Application Layer interface if they are

Rider registers.

3.12.8 Read-Only; Write-1-to-Clear Registers

Read-Only; Write-1-to-Clear registers are used as status registers. They are asserted

when the corresponding signal inside of Rider is asserted, but are only cleared when a

1 is written to them. This type of register is implemented as a flip-flop inside of the

CFG block.

3.12.9 Sticky Registers

Sticky bits are preserved during hot reset, or cold/warm reset if auxiliary power is

available.

All registers are the outputs of flip-flops. Flip-flops associated with Sticky Read-Only

registers are reset using the signal PE_VAUX_RST_N. All other registers are reset

using PE_FUND_RST_N.

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3.12.10 Initialization

After reset, the register bit CFG_LOCK_INIT_REGS at address RDR_RDRCTL1 is

cleared, which permits the Application Layer to write values to PCI Express Registers

that are required for initialization. The Application Layer can use any method it

chooses to obtain the initialization values.

The initialization process can be divided into three phases: MAC, DLL, and TL. After

the Application Layer initializes the registers required for the LTSSM, it sets the

CFG_MAC_INIT_DONE bit of the RDR_RDRCTL1 register, which allows the LTSSM

to proceed with link training. Next, after the Application Layer initializes the registers

required for flow control initialization of VC0, it sets the CFG_DLL_INIT_DONE bit of

the RDR_RDRCTL1 register, which allows the DLL to begin flow control initialization

for VC0. Lastly, after the Application Layer initializes the registers required for PCI

Express Configuration and Enumeration, it sets the CFG_TL_INIT_DONE bit of the

RDR_RDRCTL1 register, which allows the TL to respond to configuration requests.

This three phase process is provided so that link training and flow control initialization

can commence prior to all register initialization being complete. If the Application

Layer can accomplish all register initialization within the time-outs specified in the PCI

Express Base Specification, all three CFG_*_INIT_DONE bits may be set at once.

The application layer may set the CFG_LOCK_INIT_REGS bit to prevent changes to

the initialization registers.

3.12.11 Interrupt Generation

The CFG block generates two interrupts to the Application Layer. The interrupt

LINERDR_REQ_CPL_INT indicates when a transfer request has been completed. It is

tied directly to CFG_REQ_COMPLETE_INT (RDR_RDRSTAT0[0]). The interrupt line

RDR_MISC_INT indicates when other events occur. It is the logical OR of the masked

signals CFG_VPD_REQ_INT, CFG_REQ_INVALID_INT, CFG_PWR_STATE_INT,

CFG_SLOT_PWR_INT, CFG_VEN_DEF_MSG_INT, and

CFG_HOT_PLUG_MSG_INT (RDR_RDRSTAT0[13:8]).

3.12.12 PCI Express Registers - PCI Compatible Header

The Type column in this section represents the type of register from the perspective of

the Transaction Layer. Register fields in this section cannot be written by the

Application Layer unless indicated by an asterisk (*) in the Type column, in which case

they can be written by the Application Layer when CFG_LOCK_INIT_REGS is not set.

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3.12.13 PCI Device and Vendor ID

3.12.14 PCI Status and Command

Bits Type Default Name Description

[31:16] RO 16’h 8852 CFG_DEVICE_ID Device ID based on BOND_OPTION input to

Rider. Device ID values for each bond option are

set during pre-synthesis configuration of Rider

IP.

[15:0] RO 16’h 14f1 CFG_VENDOR_ID Vendor ID. Set during pre-synthesis

configuration of Rider IP.

Bits Type Default Name Description

[31:31] RR 1‘b0 CFG_STAT_DET_P

ERR

Set if Poisoned TLP is received.

[30:30] RR 1‘b0 CFG_STAT_SIG_SE

Set when fatal or non-fatal error message is sent

and CFG_CMD_SERR_EN is set.

[29:29] RR 1‘b0 CFG_STAT_RCV_M

Set when completion is received (by Rider) with

Unsupported Request status.

[28:28] RR 1‘b0 CFG_STAT_RCV_T

Set when completion is received (by Rider) with

Completer Abort status.

[27:27] RR 1‘b0 CFG_STAT_SIG_TA Set when completion is sent (by Rider) with

Completer Abort status.

[26:25] RO 2’b0 Reserved

[24:24] RR 1‘b0 CFG_STAT_MD_PE

Set when a poisoned completion is received or a

write request being sent is poisoned. Can only

be set when CFG_CMD_PERR_RESP_EN bit is

set.

[23:20] RO 4’b1 Reserved

[19:19] RO 1‘b0 TL_INTX_MSG_OUTST

AND

Indicates INTx message is outstanding.

[18:11] RO 8‘b0 Reserved

[10:10] RW 1‘b0 CFG_GEN_INTX_DI

Disables ability to generate INTx messages.

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3.12.15 PCI Class Code and Revision ID

[9:9] RO 1‘b0 Reserved

[8:8] RW 1‘b0 CFG_CMD_SERR_

Enables detected fatal and non-fatal errors to be

reported to Root Complex.

[7:7] RO 1‘b0 Reserved

[6:6] RW 1‘b0 CFG_CMD_PERR_

RSP_EN

Enables ability to set the Master Data Parity

Error bit (PE_STAT_MD_PERR).

[5:3] RO 3‘b0 Reserved

[2:2] RW 1‘b0 CFG_CMD_BUS_M

STR_EN

Enables ability to issue memory requests,

including MSI messages.

[1:1] RW 1‘b0 CFG_CMD_MEM_E

Enables memory decoder and allows device to

accept memory transactions.

[0:0] RO 1‘b0 Reserved

Bits Type Default Name Description

[31:24] RO 8’h04 CFG_CLASS_CODE Class Code. Set during pre-synthesis

configuration of Rider IP.

[23:16] RO 8‘b0 CFG_SUBCLASS_C

ODE

Subclass Code. Set during pre-synthesis

configuration of Rider IP.

[15:8] RO 8‘b0 CFG_PGM_INTF Programming Interface. Set during pre-synthesis

configuration of Rider IP.

[7:0] RO 8‘b2 CFG_REV_ID Revision ID of the device. Set during pre-

synthesis configuration of Rider IP.

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

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3.12.16 PCI Base Address Register 0

3.12.17 PCI Base Address Register 1

Bits Type Default Name Description

[31:21] RW 11‘b0 CFG_BA0 Lower part of Base Address 0.

[20:0] RO 21‘b0 Reserved

Bits Type Default Name Description

[31:0] RW 32‘b0 CFG_BA1 If RDR_CFG4[2] is set, this field is the upper 32

bits of base address at RDR_CFG4. Otherwise,

this register is read-only.

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

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3.12.18 PCI Subsystem and Subsystem Vendor ID

Bits Type Default Name Description

[31:16] RO 16‘b0 CFG_SUBSYS_ID Subsystem ID; Initialized by the EEPROM.

[15:0] RO 16‘b0 CFG_SUBSYS_VEN

_ID

Subsystem Vendor ID; Initialized by the

EEPROM.

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

Bits Type Default Name Description

[31:0] RO 32‘h0040 Reserved

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

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3.12.19 PCI Interrupts

3.12.20 PCI Express Registers: Capabilities

The Type column in this section represents the type of register from the perspective of

the transaction layer. Register fields in this section cannot be written by the application

layer unless indicated by an asterisk (*) in the Type column, in which case they can be

written by the Application Layer when CFG_LOCK_INIT_REGS is not set.

Bits Type Default Name Description

[31:11] RO 21’b0 Reserved

[10:8] RO 3’b1 CFG_INTX_PIN Interrupt Pin. Indicates which legacy-style INTx

message is used for interrupt. Initialized by the

Application Layer. 3’b001 = INTA, 3’b010 =

INTB, … 3’b100 = INTD.

[7:0] RW 8‘b0 CFG_INTX_LINE Interrupt Line. Contains routing information for

legacy INTx# style interrupts.

Bits Type Default Name Description

[31:0] RO 32’b0 Reserved

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3.12.21 PCI Express Device Capabilities

Bits Type Default Name Description

[31:28] RO 4‘b0 Reserved

[27:26] RO 2‘b0 TL_SLOT_PWR_LIM_S

CALE

Captured Slot Power Limit Scale.

[25:18] RO 8‘b0 TL_SLOT_PWR_LIM_V

Captured Slot Power Limit Value.

[17:15] RO 3‘b0 Reserved

[14:14] RO 1‘b0 CFG_PWR_IND_PR

Power indicator present on card. Initialized by

the Application Layer.

[13:13] RO 1‘b0 CFG_ATTN_IND_PR

Attention indicator present on card. Initialized by

the Application Layer.

[12:12] RO 1‘b0 CFG_ATTN_BUTTO

N_PRES

Attention button present on card. Initialized by

the Application Layer.

[11:9] RO 3‘b0 CFG_L1ASPM_ACC

EPT_LAT

L1 Acceptable Latency; Initialized by the

Application Layer

[8:6] RO 3‘b0 CFG_L0S_ACCEPT_

LAT

L0s Acceptable Latency. Initialized by the

Application Layer.

[5:3] RO 3‘b0 Reserved

[2:0] RO 3‘b0 CFG_MAX_PAYLD_S

Max Payload Size Supported; Set during

configuration of Rider IP.

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3.12.22 PCI Express Device Status and Control

Bits Type Default Name Description

[31:22] RO 10‘b0 Reserved

[21:21] RO 1‘b0 TL_TRANS_PENDIN

1 = there are pending non-posted requests.

[20:20] RO 1‘b0 CFG_AUX_PWR_DE

1 = auxiliary power has been detected;

Initialized by the Application Layer.

[19:19] RO 1‘b0 CFG_UR_RCVD 1 = Unsupported Request (UR) received.

[18:18] RO 1‘b0 CFG_FATAL_ERR_D

1 = one or more fatal errors detected.

[17:17] RO 1‘b0 CFG_NONFATAL_ERR

_DET

1 = one or more non-fatal errors detected.

[16:16] RO 1‘b0 CFG_CORR_ERR_D

1 = one or more correctable errors detected.

[15:15] RO 1‘b0 Reserved

[14:12] RW 3’h2 CFG_MAX_RD_REQ

_SZ

Maximum Read Request Size (default is 512

bytes).

[11:11] RW 1’b1 CFG_NO_SNOOP_E

Enable No Snoop.

[10:10] RW 1‘b0 CFG_AUX_PWR_EN Auxiliary Power Enable. (Sticky)

[9:8] RO 2‘b0 Reserved

[7:5] RW 3‘b0 CFG_MAX_PAYLD_S

Maximum Payload Size (default is 128 bytes).

[4:4] RW 1’b1 CFG_RELAX_ORDE

R_EN

Relaxed Ordering Enable.

[3:3] RW 1‘b0 CFG_UR_RPT_EN Unsupported Request Reporting Enable.

[2:2] RW 1‘b0 CFG_FAT_ERR_RPT

_EN

Fatal Error Reporting Enable.

[1:1] RW 1‘b0 CFG_NONFAT_ERR_RP

T_EN

Non-fatal Error Reporting Enable.

[0:0] RW 1‘b0 CFG_CORR_ERR_RP

T_EN

Correctable Error Reporting Enable.

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3.12.23 PCI Express Link Capabilities

3.12.24 PCI Express Link Status and Control

Bits Type Default Name Description

[31:24] RO 8‘b0 CFG_PORT_NUM Port Number of the Link; Initialized by the

Application Layer.

[23:18] RO 6‘b0 Reserved

[17:15] RO 3‘h2 CFG_L1ASPM_EXIT_L

Corresponds to L1 Exit Latency; Varies with

CFG_COMMON_CLOCK.

If CFG_COMMON_CLOCK is 1’b1, this value is

l1aspm_exit_lat_crc (from RDR_L1_EXIT_LAT

If CFG_COMMON_CLOCK is 1’b0, this value is

l1aspm_exit_lat_arc (from RDR_L1_EXIT_LAT

[14:12] RO 3’h5 CFG_L0S_EXIT_LAT L0s Exit Latency; Varies with

CFG_COMMON_CLOCK.

If CFG_COMMON_CLOCK is 1’b1, this value is

l0s_exit_lat_crc (from RDR_L0S_EXIT_LAT

If CFG_COMMON_CLOCK is 1’b0, this value is

l0s_exit_lat_arc (from RDR_L0S_EXIT_LAT

[11:0] RO 12’hC11 Reserved

Bits Type Default Name Description

[31:29] RO 3‘b0 Reserved

[28:28] RO 1‘b0 CFG_SLOT_CLOCK

_CFG

1 = using clock from connector; 0 = using

independent clock; Initialized by the Application

Layer.

[27:8] RO 20’h01100 Reserved

[7:7] RW 1‘b0 CFG_EXTENDED_S

YNC

1 = forces extended synchronization when

exiting L1 and L0s.

[6:6] RW 1‘b0 CFG_COMMON_CL

OCK

1 = both ends of link are using a common

reference clock.

[5:4] RW 2‘b0 Reserved

[3:3] RW 1‘b0 CFG_RCB Read Completion Boundary; 1 = 128b; 0 = 64b.

[2:2] RO 1‘b0 Reserved

[1:0] RW 2‘b0 CFG_ASPM_CTRL ASPM Control:

00 = disabled;

01 = L0s enabled;

10= L1 ASPM enabled;

11 = L0s & L1 ASPM enabled;

Initialized by the Application Layer.

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3.12.25 Power Management Interface Capabilities

3.12.26 Power Management Control/Status

Bits Type Default Name Description

[31:27] RO 5’hF CFG_PME_SUPPOR

TED

D-states in which PME Message is Supported.

[26:26] RO 1’b1 CFG_D2_SUPPORT

Indicates if D2 state is supported.

[25:25] RO 1’b1 CFG_D1_SUPPORT

Indicates if D1 state is supported.

[24:22] RO 3’h7 CFG_AUX_CURREN

3.3 V AUX current required in D3cold state;

Initialized by the Application Layer.

[21:0] RO 22’h229001 Reserved

Bits Type Default Name Description

[31:16] RO 16‘b0 Reserved

[15:15] RO 1‘b0 CFG_PME_STAT Indicates when device experienced a PME.

(Sticky)

[14:9] RO 6‘b0 Reserved

[8:8] RW 1‘b0 CFG_PME_EN Enables device to send PME messages.

[7:2] RO 6‘b0 Reserved

[1:0] RW 2‘b0 RDR_PWR_STATE Controls power state of the device.

2’b00 = D0

2’b01 = D1

2’b10 = D2

2’b11 = D3hot

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3.12.27 Vital Product Data Capabilities

3.12.28 VPD Data

3.12.29 Message Signaled Interrupt Capabilities

This register is present only if the MSI capability is enabled via the

INCLUDE_MSI_REGS REGISTER at address RDR_RDRCTL1.

Bits Type Default Name Description

[31:31] RW 1‘b0 VPD_FLAG VPD Flag Bit. Writable by both Application and

Transaction Layers. Indicates direction of

transfer and when transfer is complete.

Write: 1’b1 is written to CFG_VPD_FLAG when

CFG_VPD_ADDR is written. AL clears

CFG_VPD_FLAG when write is complete.

Read: 1’b0 is written to CFG_VPD_FLAG when

CFG_VPD_ADDR is written. AL sets

CFG_VPD_FLAG when read is complete (i.e.,

data is available in CFG_VPD_DATA).

[30:16] RW 15‘b0 VPD_ADDR VPD Address. Writable only by Transaction

Layer.

[15:0] RO 16’h A003 Reserved

Bits Type Default Name Description

[31:31] RW 32‘b0 VPD_DATA Vital Product Data. Writable by both Application

and Transaction Layers.

Bits Type Default Name Description

[31:23] RO 9‘b1 Reserved

[22:20] RW 3‘b0 CFG_NUM_MSGS_A

LLOC

Number of messages allocated to the device.

[19:17] RO 3‘b0 CFG_NUM_MSGS_R

Number of messages requested by the device.

Set during RTL configuration of Rider IP.

[16:16] RW 1‘b0 CFG_MSI_EN Enables Message Signaled Interrupts.

[15:0] RO 16’h 05 Reserved

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3.12.30 MSI Address Lower 32 Bits

This register is present only if the MSI capability is enabled via the

INCLUDE_MSI_REGS register at address RDR_RDRCTL1.

3.12.31 MSI Address Upper 32 Bits

This register is present only if the MSI capability is enabled via the

INCLUDE_MSI_REGS register at address RDR_RDRCTL1.

3.12.32 MSI Data Pattern

This register is present only if the MSI capability is enabled via the

INCLUDE_MSI_REGS REGISTER at address RDR_RDRCTL1.

Bits Type Default Name Description

[31:2] RW 30‘b0 CFG_MSI_ARL Lower 32 bits of 64-bit MSI Address.

[1:0] RO 2‘b0 CFG_MSI_ARL MSI Address is Dword aligned; always 2’b00.

Bits Type Default Name Description

[31:0] RW 32‘b0 CFG_MSI_ARU Upper 32 bits of 64-bit MSI Address.

Bits Type Default Name Description

[31:16] RO 16’b0 Reserved

[15:0] RW 16‘b0 CFG_MSI_BASE_DA

Base MSI Data Pattern.

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3.12.33 PCI Express Registers: Extended Capabilities

The Type column in this section represents the type of register from the perspective of

the Transaction Layer. Register fields in this section cannot be written by the

Application Layer unless indicated by an asterisk (*) in the Type column, in which case

they can be written by the Application Layer when CFG_LOCK_INIT_REGS is not set.

3.12.34 AER Uncorrectable Error Status

Bits Type Default Name Description

[31:0] RO 32’h20010001 Reserved

Bits Type Default Name Description

[31:21] RO 11’b0 Reserved

[20:20] RO 1‘b0 CFG_UR_ERR_STAT Unsupported Request Error Status; set by

Transaction Layer. (Sticky)

[19:19] RO 1’b0 Reserved

[18:18] RO 1‘b0 CFG_MALF_TLP_ST

Malformed TLP Status; set by Transaction

Layer. (Sticky)

[17:17] RO 1‘b0 CFG_RCVR_OVFLW_

STAT

Receiver Overflow Status; set by Transaction

Layer. (Sticky)

[16:16] RO 1‘b0 CFG_UNEXP_COMP_S

TAT

Unexpected Completion Status; set by

Transaction Layer. (Sticky)

[15:15] RO 1‘b0 CFG_COMP_ABORT_S

TAT

Completer Abort Status; set by Transaction

Layer. (Sticky)

[14:14] RO 1‘b0 CFG_COMP_TO_ST

Completion Timeout Status; set by Transaction

Layer. (Sticky)

[13:13] RO 1‘b0 CFG_FC_PROT_ERR_

STAT

Flow Control Protocol Error Status; set by

Transaction Layer. (Sticky)

[12:12] RO 1‘b0 CFG_POISONED_TLP_

STAT

Poisoned TLP Status; set by Transaction Layer.

(Sticky)

[11:5] RO 7’b0 Reserved

[4:4] RO 1‘b0 CFG_PROT_ERR_S

TAT

Data Link Protocol Error Status; set by Data Link

Layer. (Sticky)

[3:0] RO 4’b0 Reserved

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3.12.35 AER Uncorrectable Error Mask

Bits Type Default Name Description

[31:21] RO 11’b0 Reserved

[20:20] RW 1‘b0 CFG_UR_ERR_MAS

Unsupported Request Error

[19:19] RO 1’b0 Reserved

[18:18] RW 1‘b0 CFG_MALF_TLP_MA

Malformed TLP Mask.(Sticky)

[17:17] RW 1‘b0 CFG_RCVR_OVFLW_M

ASK

Receiver Overflow Mask. (Sticky)

[16:16] RW 1‘b0 CFG_UNEXP_COMP_M

ASK

Unexpected Completion Mask (Sticky)

[15:15] RW 1‘b0 CFG_COMP_ABORT_M

ASK

Completer Abort Mask. (Sticky)

[14:14] RW 1‘b0 CFG_COMP_TO_MA

Completion Timeout Mask.

[13:13] RW 1‘b0 CFG_FC_PROT_ERR_

MASK

Flow Control Protocol Error Mask. (Sticky)

[12:12] RW 1‘b0 CFG_POISONED_TLP_

MASK

Poisoned TLP Mask. (Sticky)

[11:5] RO 7’b0 Reserved

[4:4] RW 1‘b0 CFG_PROT_ERR_M

ASK

Data Link Protocol Error Mask. (Sticky)

[3:0] RO 1‘b0 Reserved

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3.12.36 AER Uncorrectable Error Severity

Bits Type Default Name Description

[31:21] RO 11‘b0 Reserved

[20:20] RW 1‘b0 CFG_UR_ERR_SEV Unsupported Request Error Severity. (Sticky)

[19:19] RO 1‘b0 Reserved

[18:18] RW 1’b1 CFG_MALF_TLP_SE

Malformed TLP Severity. (Sticky)

[17:17] RW 1’b1 CFG_RCVR_OVFLW_S

Receiver Overflow Severity. (Sticky)

[16:16] RW 1‘b0 CFG_COMP_ABORT_S

Unexpected Completion Severity. (Sticky)

[15:15] RW 1‘b0 CFG_COMP_TO_SEV Completer Abort Severity. (Sticky)

[14:14] RW 1‘b0 CFG_FC_PROT_ERR_

SEV

Completion Timeout Severity. (Sticky)

[13:13] RW 1’b1 CFG_POISONED_TLP_

SEV

Flow Control Protocol Error Severity. (Sticky)

[12:12] RW 1‘b0 CFG_PROT_ERR_S

Poisoned TLP Severity. (Sticky)

[11:5] RO 1‘b0 Reserved

[4:4] RW 1’b1 CFG_COMP_ABORT_

SEV

Data Link Protocol Error Severity. (Sticky)

[3:0] RO 4‘b0 Reserved

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3.12.37 AER Correctable Error Status

3.12.38 AER Correctable Error Mask

Bits Type Default Name Description

[31:13] RO 19‘b0 Reserved

[12:12] RO 1‘b0 CFG_REPLAY_TMR_TO_

STAT

Replay Timer Timeout Status; set by Data Link

Layer. (Sticky)

[11:9] RO 3‘b0 Reserved

[8:8] RO 1‘b0 CFG_REPLAY_NUM_RO_

STAT

Replay Counter (aka, REPLAY_NUM)

Rollover Status; set by Data Link Layer.

(Sticky)

[7:7] RO 1‘b0 CFG_BAD_DLLP_STA

Bad DLLP Status; set by Data Link Layer.

(Sticky)

[6:6] RO 1‘b0 CFG_BAD_TLP_STAT Bad TLP Status; set by Transaction Layer.

(Sticky)

[5:1] RO 5‘b0 Reserved

[0:0] RO 1‘b0 CFG_RCVR_ERR_ST

Receiver Error Status; set by MAC Layer.

(Sticky)

Bits Type Default Name Description

[31:13] RO 19‘b0 Reserved

[12:12] RW 1‘b0 CFG_REPLAY_TMR_TO_M

ASK

Replay Timer Timeout Mask. (Sticky)

[11:9] RO 3‘b0 Reserved

[8:8] RW 1‘b0 CFG_REPLAY_NUM_RO_M

ASK

Replay Counter (aka, REPLAY_NUM)

Rollover Mask. (Sticky)

[7:7] RW 1‘b0 CFG_BAD_DLLP_MASK Bad DLLP Mask. (Sticky)

[6:6] RW 1‘b0 CFG_BAD_TLP_MASK Bad TLP Mask. (Sticky)

[5:1] RO 5‘b0 Reserved

[0:0] RW 1‘b0 CFG_RCVR_ERR_MAS

Receiver Error Mask. (Sticky)

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3.12.39 AER Capability and Control

3.12.40 AER Header Log 0

3.12.41 AER Header Log 1

3.12.42 AER Header Log 2

Bits Type Default Name Description

[31:5] RO 27‘b0 Reserved

[4:0] RO 5‘b0 TL_FIRST_ERR_PT

Bit number of the first error reported in the

Uncorrectable Error Status Register

(RDR_AERUESTA). (Sticky)

Bits Type Default Name Description

[31:0] RO 32‘b0 TL_HDR_LOG_0 First DW of the header of the packet causing the

reported uncorrectable error. (Sticky)

Bits Type Default Name Description

[31:0] RO 32‘b0 TL_HDR_LOG_1 Second DW of the header of the packet causing

the reported uncorrectable error. (Sticky)

Bits Type Default Name Description

[31:0] RO 32‘b0 TL_HDR_LOG_2 Third DW of the header of the packet causing

the reported uncorrectable error. (Sticky)

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3.12.43 AER Header Log 3

3.12.44 Port VC Capability Register 1

Bits Type Default Name Description

[31:0] RO 32‘b0 TL_HDR_LOG_3 Fourth DW of the header of the packet causing

the reported uncorrectable error. (Sticky)

Bits Type Default Name Description

[31:0] RO 32‘h10002 Reserved

Bits Type Default Name Description

[31:7] RO 25‘b0 Reserved

[6:4] RO 3’b1 CFG_NUM_VCS_LP

Number of VCs that comprise the Low-Priority

VC Group.

[3:3] RO 1‘b0 Reserved

[2:0] RO 3’b1 CFG_NUM_ADD_VC

Number of Additional VCs (beyond VC0) that

are supported.

Bits Type Default Name Description

[31:0] RO 32’h 4000006 Reserved

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3.12.45 Port VC Status and Control

3.12.46 VC Resource 0 Capability

Bits Type Default Name Description

[31:17] RO 15‘b0 Reserved

[16:16] RO 1‘b0 CFG_VC_ARB_TABLE_

STAT

1 = New values have been written by

Software into RDR_VCARB[0-7] but have not

been applied.

0 = VC Arbitration Table has been read from

RDR_VCARB[0-7] and applied.

[15:4] RO 12‘b0 Reserved

[3:1] RW 3’h 2 CFG_LPVCG_ARB_SCH

_SEL

Selected arbitration scheme for Low-Priority

VC Group.

[0:0] RW 1‘b0 CFG_LD_VC_ARB_TABL

Writing 1 causes VC arbitration table to be

read and applied; Always reads 0.

Bits Type Default Name Description

[31:17] RO 32‘b0 Reserved

Bits Type Default Name Description

[31:8] RO 24’h800000 Reserved

[7:1] RW 7’h7F CFG_VC0_TCVC_M

Traffic Classes mapped to VC0

[0:0] RO 1’b1 CFG_VC0_TCVC_M

Traffic Class 0 always mapped to VC0.

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3.12.47 VC Resource 0 Control

3.12.48 VC Resource 1 Control

Bits Type Default Name Description

[31:18] RO 14‘b0 Reserved

[17:17] RO 1’b1 DLL_VC0_NEGOT_PEN

DING

For VC0: Indicates status of Flow Control

Initialization.

[16:0] RO 16‘b0 Reserved

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

Bits Type Default Name Description

[31:31] RW 1‘b0 CFG_VC1_EN VC1 Enable

[30:27] RO 4‘b0 Reserved

[26:24] RW 3’b1 CFG_VC1_ID VC1 ID.

[23:8] RO 16‘b0 Reserved

[7:1] RW 7‘b0 CFG_VC1_TCVC_M

Traffic Classes mapped to VC1.

[31:31] RW 1‘b0 CFG_VC1_EN VC1 Enable

[0:0] RO 1‘b0 CFG_VC1_TCVC_M

Bit zero of TC/VC map is hardwired to zero for

VCs other than VC0. TC0 is never mapped to

anything other than VC0.

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3.12.49 VC Resource 1 Status

3.12.50 VC Resource 2 Control

Bits Type Default Name Description

[31:18] RO 14‘b0 Reserved

[17:17] RO 1‘b0 DLL_VC1_NEGOT_P

ENDING

Indicates status of VC negotiation.

[16:0] RO 17‘b0 Reserved

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

Bits Type Default Name Description

[31:31] RW 1‘b0 CFG_VC2_EN VC2 Enable.

[30:27] RO 4‘b0 Reserved

[26:24] RW 3’h 2 CFG_VC2_ID VC2 ID.

[23:8] RO 16‘b0 Reserved

[7:1] RW 7‘b0 CFG_VC2_TCVC_M

Traffic Classes mapped to VC2.

[0:0] RO 1‘b0 CFG_VC2_TCVC_M

Bit zero of TC/VC map is hardwired to zero for

VCs other than VC0. TC0 is never mapped to

anything other than VC0.

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3.12.51 VC Resource 2 Status

3.12.52 VC Resource 3 Control

Bits Type Default Name Description

[31:18] RO 14‘b0 Reserved

[17:17] RO 1‘b0 DLL_VC2_NEGOT_PEN

DING

Indicates status of VC negotiation.

[16:0] RO 17‘b0 Reserved

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

Bits Type Default Name Description

[31:31] RW 1‘b0 CFG_VC3_EN VC3 Enable.

[30:27] RO 4‘b0 Reserved

[26:24] RW 3’h3 CFG_VC3_ID VC3 ID.

[23:8] RO 16‘b0 Reserved

[7:1] RW 7‘b0 CFG_VC3_TCVC_M

Traffic Classes mapped to VC3.

[0:0] RO 1‘b0 CFG_VC3_TCVC_M

Bit zero of TC/VC map is hardwired to zero for

VCs other than VC0. TC0 is never mapped to

anything other than VC0.

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3.12.53 VC Resource 3 Status

3.12.54 VC Arbitration Table Entries 0–7

3.12.55 VC Arbitration Table Entries 8–15

3.12.56 VC Arbitration Table Entries 16–23

Bits Type Default Name Description

[31:18] RO 14‘b0 Reserved

[17:17] RO 1‘b0 DLL_VC3_NEGOT_P

ENDING

Indicates status of VC negotiation.

[16:0] RO 17‘b0 Reserved

Bits Type Default Name Description

[31:0] RW 32‘b0 CFG_VCARB_TBL0 Entries 0-7 in the VC Arbitration Table.

Bits Type Default Name Description

[31:0] RW 32‘b0 CFG_VCARB_TBL1 Entries 8-15 in the VC Arbitration Table.

Bits Type Default Name Description

[31:0] RW 32‘b0 CFG_VCARB_TBL2 Entries 16-23 in the VC Arbitration Table.

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3.12.57 VC Arbitration Table Entries 24–31

3.12.58 VC Arbitration Table Entries 32–39

3.12.59 VC Arbitration Table Entries 40–47

3.12.60 VC Arbitration Table Entries 48–55

3.12.61 VC Arbitration Table Entries 56–63

Bits Type Default Name Description

[31:0] RW 32‘b0 CFG_VCARB_TBL3 Entries 24-31 in the VC Arbitration Table.

Bits Type Default Name Description

[31:0] RW 32‘b0 CFG_VCARB_TBL4 Entries 32-39 in the VC Arbitration Table.

Bits Type Default Name Description

[31:0] RW 32‘b0 CFG_VCARB_TBL5 Entries 40-47 in the VC Arbitration Table.

Bits Type Default Name Description

[31:0] RW 32‘b0 CFG_VCARB_TBL6 Entries 48-55 in the VC Arbitration Table.

Bits Type Default Name Description

[31:0] RW 32‘b0 CFG_VCARB_TBL7 Entries 56-63 in the VC Arbitration Table.

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3.13 Rider Registers – Global

The Type column in this section represents the type of register from the perspective of

the Application Layer. None of the registers in this section can be written by the

Transaction Layer (i.e., via a Configuration Request). RO Register fields in this section

cannot be written by the Application Layer unless indicated by an asterisk (*) in the

Type column, in which case they can be written by the Application Layer when

CFG_LOCK_INIT_REGS is not set.

3.13.1 Rider Status 0

Bits Type Default Name Description

[31:24] RO 8‘b0 Reserved

[23:22] RO 2‘b0 TL_PWR_IND_STATU

Power Indicator Status:

00 = Off

01 = On

10 = Reserved

11 = Blink

[21:20] RO 2‘b0 TL_ATTN_IND_STATU

Attention Indicator Status:

00 = Off

01 = On

10 = Reserved

11 = Blink

[19:14] RO 6‘b0 Reserved

[13:13] RO 1‘b0 CFG_VPD_REQ_INT Vital Product Data Request Interrupt Status.

[12:12] RO 1‘b0 CFG_REQ_INVALID_INT Current Request Invalid Interrupt Status.

[11:11] RO 1‘b0 CFG_PWR_STATE_INT Power State Interrupt Status (indicates when

CFG_PWR_STATE bit was written).

[10:10] RO 1‘b0 CFG_SLOT_PWR_INT Slot Power Limit Updated Interrupt Status.

[9:9] RO 1‘b0 CFG_VEN_DEF_MSG_I

Vendor Defined Message Received Status.

[8:8] RO 1‘b0 CFG_HOT_PLUG_MSG_

INT

Hot-Plug Message Received Status.

[7:1] RO 7‘b0 Reserved

[0:0] RO 1‘b0 CFG_REQ_COMPLETE_

INT

Request Complete Interrupt Status.

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

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3.13.2 Rider Control 0

Bits Type Default Name Description

[31:14] RO 18‘b0 Reserved

[13:13] RW 1‘b0 VPD_REQ_MSK Vital Product Data Request Interrupt Mask;

Active High (1’b1 masks interrupt)

[12:12] RW 1‘b0 REQ_INVALID_MSK Current Request Invalid Interrupt Mask; Active

High

[11:11] RW 1‘b0 PWR_STATE_MSK Power State Interrupt Mask; Active High

[10:10] RW 1‘b0 SLOT_PWR_MSK Slot Power Limit Updated Interrupt Mask; Active

High.

[9:9] RW 1‘b0 VEN_DEF_MSG_MS

Vendor Defined Message Received Interrupt

Mask; Active High.

[8:8] RW 1‘b0 HOT_PLUG_MSG_M

Hot-Plug Message Received Interrupt Mask;

Active High.

[7:1] RO 7‘b0 Reserved

[0:0] RW 1‘b0 REQ_COMPLETE_M

Request Complete Mask; Active High.

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3.13.3 Rider Control 1

Bits Type Default Name Description

[31:10] RO 22‘b0 Reserved

[9:9] RW 1‘b0 EN_AUX_PWR_REG Enables the CFG_AUX_PWR_EN field in

RDR_PEDEVSC:

1’b0: CFG_AUX_PWR_EN is RO

1’b1: CFG_AUX_PWR_EN is RWS.

Note this register is Sticky.

[8:8] RW 1‘b0 INCLUDE_MSI_REG

Includes the MSI Capabilities registers

(RDR_MSICAP, RDR_MSIARL, RDR_MSIARU,

RDR_MSIDATA):

1’b0: MSI Registers are not included.

1’b1: MSI Registers are included (legacy INTx

messages should not be used).

(Sticky)

[7:4] RO 4‘b0 Reserved

[3:3] RW 1‘b0 CFG_TL_INIT_DONE Indicates when register initialization for PCI

Express Configuration/Enumeration is

complete. When clear, this bit causes the TL to

respond to configuration requests with

Configuration Request Retry. This bit must be

1’b1 no later than 1 second after any reset.

[2:2] RW 1‘b0 CFG_DLL_INIT_DON

Indicates when register initialization for Flow

Control Initialization is complete. When clear,

this bit causes the DLL CMSM to wait in the

DL_INACTIVE state until it is set. This bit must

be 1’b1 no later than 1 second after any reset.

[1:1] RW 1‘b0 CFG_MAC_INIT_DO

Indicates when register initialization for the

LTSSM is complete. When clear, this bit will

cause the LTSSM to wait in the

Configuration.LinkWidth.Start sub-state until it is

set, or the 24 ms timeout occurs to send the

LTSSM back to Detect. This bit must be 1’b1 no

later than 1 second after any reset.This register

is not reset when the link goes down (i.e., when

RDR_LINK_DN_RST_N is asserted).

[0:0] RW 1‘b0 CFG_LOCK_INIT_RE

Indicates whether registers available for

initialization are locked (1’b1) or unlocked

(1’b0).

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3.14 Rider Registers: Transaction Layer

3.14.1 Transaction Layer Status 0

Bits Type Default Name Description

[31:29] RO 3‘b0 Reserved

[28:24] RO 5‘b0 TL_DEV_NUM Device Number captured when CfgWr0 packet

is received.

[23:16] RO 8‘b0 TL_BUS_NUM Bus Number captured when CfgWr0 packet is

received.

[15:8] RO 8’h FF CFG_TC_ENABLED Indicates which Traffic Classes are enabled. [7]

= TC7, [6] = TC6, … [0] = TC0.

[7:1] RO 7‘b0 Reserved

[0:0] RO 1‘b0 TL_BUSY Transaction Layer is busy servicing a request

from the Application Layer or Tx Queue is full

and cannot accept any more requests until it

becomes free. When this bit is set, the

Application Layer must not write to registers

RDR_RCADDRL, RDR_RCADDRU,

RDR_EPADDR, and RDR_ALREQC until this

bit is cleared.

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

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3.14.2 TL Control

Bits Type Default Name Description

[31:26] RO 6‘b0 Reserved

[25:25] RW 1’b1 CFG_VDM1_EN CFG_VDM1_EN: Enable the ability to forward

VDM Type 1 Messages to the Application Layer.

Default value is enabled (1'b1).

[24:24] RW 1‘b0 CFG_REQSTAT_PO

P_MODE

Select popping mode for RDR_REQSTAT

1’b0 = next request status available after writing

any value to RDR_REQSTAT

1’b1 = next request status available after

reading RDR_REQSTAT

[23:16] RW 8’h9 CFG_VC0_TIMER Expiration value used for timer to transfer

packets from VC0 when Hardware Fixed

arbitration scheme is used. Units are μs.

[15:10] RW 6’h30 CFG_CPL_TIMEOUT Duration to wait for completion before

generating Completion Timeout error. Units are

chosen by CFG_CPL_TIMER_RES as either 1

ms (default) or 100 μs. Accuracy of reporting the

Completion Timeout error is +0 / -1 resolution

time unit.

[9:9] RW 1‘b0 CFG_CPL_TIMER_R

Completion Timeout Timer Resolution:

1’b0 = 1 ms

1’b1 = 100 μs.

[8:8] RO 1‘b0 Reserved

[7:7] RW 1‘b0 CFG_UR_CPL_MOD

Select mode for data in completions with status

of Unsupported Request in response to

Configuration Read Requests.

1’b0 = completions with UR status do not

contain payload data

1’b1 = completions with UR status have payload

data of all ones.

[6:6] RW 1‘b0 CFG_UNCORR_ERR_

QUIET

When set, an error message is sent only when

the Uncorrectable Error Status bit in

RDR_AERUESTA is not set and future

detection of uncorrectable errors will not result

in an error message until the status bit is

cleared. When this bit is cleared, an error

message is sent whenever an uncorrectable

error is detected by TL.

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3.14.3 Transmit Queue Control

[5:5] RW 1‘b0 CFG_CORR_ERR_Q

UIET

When set, an error message is sent only when

the Correctable Error Status bit in

RDR_AERUESTA is not set and future

detection of correctable errors will not result in

an error message until the status bit is cleared.

When this bit is cleared, an error message is

sent whenever a correctable error is detected by

TL.

[4:4] RW 1‘b1 CFG_RCB_CK_EN Enable checking for Read Completion Boundary

violations and generate a Malformed Packet

error if necessary.

[3:3] RW 1’b1 CFG_BNDRY_CK_E

Enable checking for 4kB boundary violations

and generate a Malformed Packet Error if

necessary.

[2:2] RW 1’b1 CFG_BYTE_EN_CK_

Enable checking for incorrect Byte Enables and

generate Malformed Packet Error if necessary.

[1:1] RW 1‘b0 CFG_RELAX_ORDER_

MSK

Mask the Relaxed Ordering bit when it’s set by

the AL.

[0:0] RW 1’b1 CFG_TAG_ORDER_

Enable the Row D, Col 5 of the Ordering table.

1’b0=disabled, 1’b1=enabled.

Bits Type Default Name Description

[31:25] RO 7‘b0 Reserved

[24:24] RW 1‘b0 CFG_VC_LIMIT_EN Enable limits on number of requests by Virtual

Channel using CFG_TX_VC3_SIZE,

CFG_TX_VC2_SIZE, CFG_TX_VC1_SIZE,

CFG_TX_VC0_SIZE. By default, the entire

queue is shared by all VCs in “first come first

serve” manner.

[23:18] RW 6’h20 CFG_TX_VC3_SIZE Number of requests that can be stored in VC3

Tx Queue.

[17:12] RW 6’h20 CFG_TX_VC2_SIZE Number of requests that can be stored in VC2

Tx Queue.

[11:6] RW 6’h20 CFG_TX_VC1_SIZE Number of requests that can be stored in VC1

Tx Queue.

[5:0] RW 6’h20 CFG_TX_VC0_SIZE Number of requests that can be stored in VC0

Tx Queue.

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3.14.4 AL Request Root Complex Lower Address

3.14.5 AL Request Root Complex Upper Address

3.14.6 AL Request Endpoint Address

Bits Type Default Name Description

[31:2] RW 30‘b0 CFG_RC_ADDR Upper 30 bits of lower 32 bits of Root Complex

Address for the request submitted from the

Application Layer.

[1:0] RO 2‘b0 CFG_RC_ADDR Lower 2 bits of lower 32 bits of Root Complex

Address. Hardwired to zeros.

Bits Type Default Name Description

[31:0] RW 32‘b0 CFG_RC_ADDR Upper 32 bits of Root Complex Address for the

request submitted from the Application Layer.

Bits Type Default Name Description

[31:24] RO 8‘b0 Reserved

[23:0] RW 24‘b0 CFG_EP_ADDR The Endpoint address (i.e., destination or

source address) of Application Layer request.

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3.14.7 AL Request Parameters

When this register is written, the signal CFG_NEW_REQ_WRITTEN is asserted for

one PECLK cycle. The TL block uses this signal to begin capturing the new

transaction request.

Bits Type Default Name Description

[31:20] RW 12‘b0 CFG_AL_LENGTH Length of transfer request in bytes.

[19:17] RW 3‘b0 CFG_AL_OP_TYPE Type of requested transfer:

3'b000:Write

3'b001:Read

3'b010:Vender_Defined Type0 Message

3'b011:Vender_Defined Type1 Message

3'b100:PM_PME Message

3'b101:Hot-Plug

ATTENTION_BUTTON_PRESSED Message

3'b11x:Reserved

[16:16] RO 1‘b0 Reserved

[15:13] RW 3‘b0 CFG_AL_TC Traffic Class of the transfer request.

[12:10] RO 3‘b0 Reserved

[9:8] RW 2‘b0 CFG_AL_ATTR The attribute field of the TLP Header ([9] =

Relaxed Ordering; [8] = No Snoop).

[7:4] RW 4‘b0 CFG_AL_FIRST_BE First DW Byte Enable.

[3:0] RW 4‘b0 CFG_AL_LAST_BE Last DW Byte Enable.

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3.14.8 AL Request Status

The behavior of this register is determined by the CFG_REQSTAT_POP_MODE bit in

the RDR_TLCTL0 register. When CFG_REQSTAT_POP_MODE = 1’b0, any write to

this register will pop the next value into the status. When

CFG_REQSTAT_POP_MODE = 1’b1, any read from this register will pop the next

value into the status.

3.14.9 Transaction Layer Test Control (Flow Control)

When this register is written, the CFG_TST_SET_FC signal is asserted for one

PECLK cycle. This pulse directs the TL to load the appropriate flow control counters

with the values specified in this register.

Bits Type Default Name Description

[31:31] RO 1‘b0 TL_REQ_SUCCESSF

Request has completed successfully.

[30:30] RO 1‘b0 TL_NXT_STAT_RDY 1’b1 = another request has completed and is

ready to be reported.

[29:27] RO 3‘b0 Reserved

[26:24] RO 3‘b0 TL_CPL_OP_TYPE Operation Type of the completed request from

the Application Layer.

[23:0] RO 24‘b0 TL_CPL_EP_ADDR End-point address provided by Rider to associate

a completed request from the Application Layer.

Bits Type Default Name Description

[31:27] RO 5‘b0 Reserved

[26:24] RW 3‘b0 CFG_TST_SET_FC_V

Selects which VC Resource is to be set by this

[23:22] RW 2‘b0 CFG_TST_SET_FC_S

Selects which counters are to be set by this

2’b00: Credits Consumed

2’b01: Credit Limit

2’b10: Credits Allocated

2’b11: Credits Received

[21:20] RW 2‘b0 CFG_TST_SET_FC_T

YPE

Selects the type of counter to be set by

CFG_TST_FC_HDR and CFG_TST_FC_DATA:

2’b00: Posted

2’b01: Non-Posted

2’b10: Completion

2’b11: RESERVED

[19:12] RW 8‘b0 CFG_TST_SET_FC_H

Value to be loaded into the header credit counter.

[11:0] RW 12‘b0 CFG_TST_SET_FC_D

ATA

Value to be loaded into the data credit counter.

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Registers CX23885 Data Sheet

3.14.10 Receive Buffer Control

3.14.11 Virtual Channel Resources 0 and 1 Control

Bits Type Default Name Description

[31:18] RO 14‘b0 Reserved

[17:0] RO 18‘b0 CFG_CPL_RXBUFFER

_SZ

Number of DWords reserved for completions in

Receive Buffer. Used to hold off a MRd

transmitted from Rider if insufficient buffer space

is available for the completion(s).

Bits Type Default Name Description

[31:29] RO 3‘b0 Reserved

[28:16] RW 13’h 3B CFG_VCR0_FC_TIM

Max Payload Size Timer Default

128 bytes 59 (~237 symbol times)

256 bytes 104 (415 symbol times)

512 bytes 140 (~559 symbol times)

1024 bytes 268 (~1071 symbol times)

2048 bytes 524 (~2095 symbol times)

4096 bytes 1036 (~4143 symbol times)

[15:13] RO 3‘b0 Reserved

[12:0] RW 13’h 3B CFG_VCR1_FC_TIM

Expiration value for Flow Control Update timer

for VC Resource 1. Same units and default table

as CFG_VCR0_FC_TIMER.

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3.14.12 Virtual Channel Resources 2 and 3 Control

3.14.13 Virtual Channel Resource 0 Initial Flow Control

Credits

Bits Type Default Name Description

[31:29] RO 3‘b0 Reserved

[28:16] RW 13’h 3B CFG_VCR2_FC_TIM

Expiration value for Flow Control Update timer

for VC Resource 2. Same units and default table

as CFG_VCR0_FC_TIMER.

[15:13] RO 3‘b0 Reserved

[12:0] RW 13’h 3B CFG_VCR3_FC_TIM

Expiration value for Flow Control Update timer

for VC Resource 3. Same units and default table

as CFG_VCR0_FC_TIMER.

Bits Type Default Name Description

[31:25] RO 7‘b0 Reserved

[24:18] RO 7’h 4 CFG_RX_VCR1_NP

H_FC

Number of Flow Control Credits initially

advertised for VCR1 Non-Posted Header. VCR1

must be disabled to write this field.

[17:7] RO 11’h 100 CFG_RX_VCR1_PD_

Number of Flow Control Credits initially

advertised for VCR1 Posted Data. VCR1 must

be disabled to write this field.

[6:0] RO 7’h 4 CFG_RX_VCR1_PH_

Number of Flow Control Credits initially

advertised for VCR1 Posted Headers. VCR1

must be disabled to write this field.

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Registers CX23885 Data Sheet

3.14.14 Virtual Channel Resource 2 Initial Flow Control

Credits

3.14.15 Virtual Channel Resource 3 Initial Flow Control

Credits

Bits Type Default Name Description

[31:25] RO 7‘b0 CFG_RX_VCR2_NP

H_FC

Reserved

[24:18] RO 7’h 4 CFG_RX_VCR2_PD_

Number of Flow Control Credits initially

advertised for VCR2 Non-Posted Header. VCR2

must be disabled to write this field.

[17:7] RO 11’h 100 CFG_RX_VCR2_PH_

Number of Flow Control Credits initially

advertised for VCR2 Posted Data. VCR2 must

be disabled to write this field.

[6:0] RO 7’h 4 CFG_RX_VCR2_NP

H_FC

Number of Flow Control Credits initially

advertised for VCR2 Posted Headers. VCR2

must be disabled to write this field.

Bits Type Default Name Description

[31:25] RO 7‘b0 Reserved

[24:18] RO 7’h 4 CFG_RX_VCR3_NP

H_FC

Number of Flow Control Credits initially

advertised for VCR3 Non-Posted Header. VCR3

must be disabled to write this field.

[17:7] RO 11’h 100 CFG_RX_VCR3_PD_

Number of Flow Control Credits initially

advertised for VCR3 Posted Data. VCR3 must

be disabled to write this field.

[6:0] RO 7’h 4 CFG_RX_VCR3_PH_

Number of Flow Control Credits initially

advertised for VCR3 Posted Headers. VCR3

must be disabled to write this field.

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CX23885 Data Sheet Registers

3.15 Rider Registers: Data Link Layer

These registers are not reset when the link goes down (i.e., when

RDR_LINK_DN_RST_N is asserted).

3.15.1 Data Link Layer Control

3.15.2 Replay Timeout Limits

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

Bits Type Default Name Description

[31:10] RO 22‘b0 Reserved

[9:8] RW 2’h 3 CFG_TST_REPLAY_

NUM_CNT

Sets the number of times the Replay Buffer is

replayed before the link is retrained.

[7:1] RO 7‘b0 Reserved

[0:0] RW 1‘b0 CFG_TST_BYP_FLO

W_CTRL

Bypass Flow Control Initialization.

Bits Type Default Name Description

[31:20] RO 12’h B2 CFG_REPLAY_TO_U

NADJ

Unadjusted Replay Timer limit. Corresponds to

Table 3-4 of PCI Express Base Specification.

Units are 4 symbol times.

[19:10] RO 10’h 3 CFG_RXL0SADJ_CR

Rx_L0s_Adjustment term added to

CFG_REPLAY_TO_UNADJ if L0s is enabled

and common reference clock configuration.

Units are 4 symbol times.

[9:0] RO 10’h 3 CFG_RXL0SADJ_AR

Rx_L0s_Adjustment term added to

CFG_REPLAY_TO_UNADJ if L0s is enabled

and non-common reference clock configuration.

Units are 4 symbol times. (Sticky)

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Registers CX23885 Data Sheet

3.15.3 ACK Latency Timeout Limits

Bits Type Default Name Description

[31:21] RO 11’h 3C CFG_ACKLAT_TO_U

NADJ

Unadjusted Acknowledge Latency Timer limit.

Corresponds to Table 3-5 of PCI Express Base

Specification. Units are 4 symbol times.

[20:17] RO 4‘b0 Reserved

[16:8] RO 9’b1 CFG_P0S2P0_LAT Time for Transmitter to transition from P0s to

P0. Units are 4 symbol times. (Sticky)

[7:0] RO 8‘b0 MAC_TX_N_FTS Number of FTS required to be transmitted when

exiting L0s. Units are 4 symbol times. This value

(x4) is received from the entity on the other side

of the link during link training.

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CX23885 Data Sheet Registers

3.16 Rider Registers: MAC Layer

These registers are not reset when the link goes down (i.e., when

RDR_LINK_DN_RST_N is asserted).

3.16.1 MAC Layer Status 0

Bits Type Default Name Description

[31:16] RO 16‘b0 Reserved

[15:15] RO 1‘b0 MAC_PATTERN_LO

CKED

Indicates when loopback pattern checker

matches the Rx Pattern with the Tx Pattern.

[14:13] RO 2‘b0 Reserved

[12:12] RO 1‘b0 MAC_LINKUP Indicates when link is up.

[11:10] RO 2‘b0 MAC_TXL0S_STATE TxL0s State

[9:8] RO 2‘b0 MAC_RXL0S_STATE RxL0s State

[7:0] RO 8‘b0 MAC_LTSSM_STATE Indicates current state of LTSSM:

00h: Detect.Quiet

01h: Detect.Active

02h: Polling.Active

03h: Polling.Compliance

04h: Polling.Config

05h: Polling.Speed

06h: Config.Linkwidth.Start

07h: Config.Linkwidth.Accept

08h: Config.Lanenum.Wait

09h: Config.Lanenum.Accept

0Ah: Config.Complete

0Bh: Config.Idle

0Ch: Recovery.RcvrLock

0Dh: Recovery.RcvrCfg

0Eh: Recovery.Idle

0Fh: RxL0_TxL0

1Fh: L1.Entry

20h: L1.Idle

21h: L2.Idle

22h: L2.Transmit.Wake

23h: Disabled

30h: Disalbed.Idle

24h: Loopback.Entry

25h: Loopback.Active.Mstr

26h: Loopback.Active.Slv

27h: Loopback.Exit.Mstr

28h: Loopback.Exit.Slv

29h: Hot Reset

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Registers CX23885 Data Sheet

3.16.2 MAC Layer Control 0

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

Bits Type Default Name Description

[31:24] RW 8’h20 CFG_LB_MSTR_TIM

EOUT

Loopback master timeout. Must receive TS1

ordered set with Loopback bit asserted within

this time. Units are 1ms. Maximum is 100 ms.

[23:20] RW 4’hA CFG_LB_MSTR_DK

SEL

Data (0) or Special (1) Symbol select for

Loopback Master Data Register

[23]: Byte 0

[22]: Byte 1

[21]: Byte 2

[20]: Byte 3

[19:18] RO 2‘b0 Reserved

[17:17] RW 1’b1 CFG_LB_COMPLIAN

CE_EN

1’b1 causes TXCOMPLIANCE to be asserted

for the first symbol of the loopback data pattern.

[16:16] RW 1‘b0 CFG_LB_MSTR_EN Enable Loopback Master mode.

[15:9] RO 7‘b0 Reserved

[8:0] RW 9’h127 CFG_SKP_INS_RAT

Skip Insertion Rate. The value of

CFG_SKP_INS_RATE is the number of symbol

times divided by 4 between SKP Ordered Set

Insertion. Recommended values from 295 to

385 (or 1180 to 1538 symbol times). SKP

insertion is disabled if 9’h000 is written to this

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3.16.3 MAC Layer Control 1

3.16.4 MAC Control 2

Bits Type Default Name Description

[31:25] RO 7‘b0 Reserved

[24:16] RW 9’h190 CFG_TXL0S_TIMEO

Controls the time the MAC waits when no TLPs

or DLLPs need to be transmitted before

transitioning to the TxL0s state. Units are 4

symbol times.

[15:0] RW 16‘b0 CFG_TST_LTSSM_G

OTO_STATE

A set bit forces the LTSSM to the specified

state: [0] = Detect [1] = Polling [2] =

Configuration [3] = L0 (4 SKP Ordered Sets

Transmitted) [15:4] = Reserved

Bits Type Default Name Description

[31:17] RO 15‘b0 Reserved

[16:7] RW 10’h380 CFG_TXL1_TIMEOU

Controls the time the MAC waits when no TLPs

or DLLPs need to be transmitted before

transitioning to theL1ASPM state. Units are 4

symbol times.

[6:1] RW 6’h3F CFG_BIST_NUM_TS

1_PA

Number of 16 TS1 Ordered Sets transmitted in

Polling.Active when entering Loopback Master

Mode (CFG_LB_MSTR_EN is 1’b1).

[0:0] RO 1‘b0 CFG_SCRAMBLE_E

N_N

Used in TS1/TS2 Ordered Sets to disable

scrambling at the other end of the link and used

by Rider logic to disable the scrambler. Only

disables scrambling in Configuration State.

Active Low.(Sticky)

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Registers CX23885 Data Sheet

3.16.5 MAC Loopback Master Data

3.16.6 MAC L0s Exit Latencies

Bits Type Default Name Description

[31:24] RW 8’h BC CFG_LB_MSTR_DAT

Byte 0 of Loopback Master Data.

[23:16] RW 8’h B5 CFG_LB_MSTR_DAT

Byte 1 of Loopback Master Data.

[15:8] RW 8’h BC CFG_LB_MSTR_DAT

Byte 2 of Loopback Master Data.

[7:0] RW 8’h 4A CFG_LB_MSTR_DAT

Byte 3 of Loopback Master Data.

Bits Type Default Name Description

[31:30] RO 2‘b0 Reserved

[29:27] RO 3’h 2 L1_EXIT_LAT_CRC L1 ASPMEXIT latency when operating with a

common reference clock

(CFG_COMMON_CLOCK is set).(Sticky)

[26:24] RO 3’h 5 L0S_EXIT_LAT_CRC L0s exit latency when operating with a common

reference clock (CFG_COMMON_CLOCK is

set).(Sticky)

[23:16] RO 8’h 56 CFG_N_FTS_CRC N_FTS when operating with a common

reference clock. This value must be compatible

with l0s_exit_lat_crc.(Sticky)

[15:14] RO 2‘b0 Reserved

[13:11] RO 3’h 2 L1_EXIT_LAT_ARC L1 ASPMEXIT latency when operating with an

asynchronous reference clock

(CFG_COMMON_CLOCK is 1’b0).(Sticky)

[10:8] RO 3’h 5 L0S_EXIT_LAT_ARC L0s exit latency when operating with an

asynchronous reference clock

(CFG_COMMON_CLOCK is 1’b0).(Sticky)

[7:0] RO 8’h 5F CFG_N_FTS_ARC N_FTS when operating with an asynchronous

reference clock. This value must be compatible

with l0s_exit_lat_arc.(Sticky)

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3.17 Audio and Video Core

3.17.1 Serial Slave Registers

3.17.1.1 Host Register 1

Bits Type Default Name Description

[7:7] RW 1‘b 0 FORCE_CHIP_SEL Override the CHIP_SEL pin for I2C address

decode

0 = Use the CHIP_SEL pin for I2C decode

1 = The I2C chip select signal is forced to a one

regardless of the CHIP_SEL pin

[6:6] RW 1‘b 0 SLV_SI_DIS Control the glitch filters and slew rate control in

the I2C pads to enable a faster speed of

operation

0 = glitch filters and slew rate control enabled

1 = glitch filters and slew rate control disabled

[5:5] RW 1‘b 0 AUTO_INC_DIS Control auto-address increment after each byte

transfer

0 = do the auto-address increment

1 = don’t increment the address

[4:4] RW 1‘b 0 PREFETCH_EN Enable prefetch on reads. Prefetch is

unnecessary unless the interface is operated

many times faster than the typical max speed of

400 kHz. However, enabling prefetch can create

problems when reading FIFOs. The prefetch

operation can pop an entry from a FIFO,

whether or not the transaction actually requests

the byte.

[3:2] RO 2‘b 0 Reserved

[1:1] RW 1‘b 0 DIGITAL_PWR_DN Gate digital clocks (SCLK, VCLK, CLKX5,

IFCLK, BBCLK) (This bit can be configured to

gate down CLK5X or VCLK only. See

POWER_CTRL register.)

0 = don’t gate

1 = hold clocks in high state

[0:0] RW 1‘b 0 SLEEP Put the chip in sleep mode. Gate the digital

clocks and power down the analog circuitry.

(Power down of some analog blocks can be

masked when the SLEEP bit is asserted. See

POWER_CTRL register.)

0 = don’t power down

1 = power down

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Registers CX23885 Data Sheet

3.17.1.2 Host Register 2

3.17.1.3 Host Register 3

Bits Type Default Name Description

[7:6] RW 2‘b 1 VREF_PLL_REG Control for PLL supply voltage

[5:5] RW 1‘b 0 PWR_DN_SYS_PLL Power down the SYS PLL

0 = don’t power down

1 = power down

[4:4] RW 1‘b 0 PWR_DN_AUX_PLL Power down the Auxiliary PLL

0 = don’t power down

1 = power down

[3:3] RW 1‘b 0 PWR_DN_VID_PLL Power down the Video Clock PLL

0 = don’t power down

1 = power down

[2:2] RW 1‘b 0 PWR_DN_PLL_REG

Powers down the regulator for the auxiliary

clock PLL.

[1:1] RW 1‘b 0 PWR_DN_PLL_REG

1_3

Powers down the regulator for the video clock

PLL and SYS PLL

[0:0] RW 1‘b 0 PWR_DN_DLL Powers down the ADC DLL

0 = don’t power down

1 = power down

Bits Type Default Name Description

[7:7] RW 1‘b 0 CLK_IN_EN Enables clock from pad to AFE

[6:4] RW 3‘h 7 XTAL_CTRL XTAL amplifier gain

[3:2] RW 2‘b 0 BB_CLK_MODE Controls baseband ADC and PLL reference

clocks.

00=xtal/2

01=xtal

10=clk_28M

11=xtal/2

[1:1] RW 1‘b 0 REF_DIV_PLL Reference clock divider

0=divide by 2

1=no division

[0:0] RW 1‘b 0 REF_SEL_PLL1 Selects PLL1 reference clock.

0= PLL3 divided by 5

1=reference clock

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3.18 Chip Configuration Registers

3.18.1 Baseband Analog Front End and General Chip

Configuration Registers

3.18.1.1 Chip Control

Bits Type Default Name Description

[31:30] RW 2‘b 0 CH3_SRC Selects input pin to the analog front end

Channel 3:

00 = Vin7

01 = Vin8

10 = none

11 = none

[29:28] RW 2‘b 0 CH2_SRC Selects input pin to the analog front end

Channel 2:

00 = Vin4

01 = Vin5

10 = Vin6

11 = none

[27:27] RO 1‘b 0 Reserved

[26:24] RW 3‘b 0 CH1_SRC Selects input pin to the analog front end

Channel 1:

000 = Vin1

001 = Vin2

010 = Vin3

011 = Vin4

100 = Vin5

101 = Vin6

110 = Vin7

111 = Vin8

[23:23] RW 1‘b 0 Reserved

[22:21] RO 2‘b 0 Reserved

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Registers CX23885 Data Sheet

[20:20] RW 1‘b 1 CHIP_ACFG_DIS Auto-config Disable of chip-level registers.

0 = Allow VID_PLL_INT, VID_PLL_FRAC, and

AFE_CTRL fields to be automatically configured

based on square pixel, video format, and input

mode

1 = Disable auto-config

The following fields in the MODE_CTRL (0x400)

VID_FMT_SEL (or auto-detected format)

SQ_PIXEL INPUT_MODE With or without this

bit set, the registers can always be written by

software. The auto-config hardware only writes

the registers when a change in format is

detected. See AFE Control Auto-config, for

details.

[19:19] RO 1‘b 0 Reserved

[18:18] RW 1‘b 0 DUAL_MODE_ADC2 Select the ADC2 input source

0 = Selection is based on the CH_SEL_ADC2

bit field

1 = Toggle the ADC2 input between Channel 2

and Channel 3 on every ADC sample clock

[17:17] RW 1‘b 0 CH_SEL_ADC2 ADC2 input select.

0 = Channel 2

1 = Channel 3

This bit setting has no effect if the

DUAL_MODE_ADC2 bit is set to 1

[16:16] RW 1‘b 0 SOFT_RST Internal reset

0 = De-assert reset

1 = assert reset

[15:0] RO 16‘b 0 DEVICE_ID Device ID

The AV_CORE device ID will return 0.

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3.18.1.2 Baseband AFE Control

Bits Type Default Name Description

[31:29] RW 3‘b 0 DROOP_COMP_INP

UT_DIS

Droop Compensation Input Disable.This 3-bit

bus is used to disable the input to the droop

compensation logic for the 3 input channels.

[2] = droop_comp_input_dis_ch3

[1] = droop_comp_input_dis_ch2

[0] = droop_comp_input_dis_ch1

[28:28] RW 1‘b 0 DROOP_POL Polarity control for DROOP_UP output from

droop compensation correction block.

[27:27] RW 1‘b 0 IREF_SEL Reference current resistor

0 = external resistor

1 = on-chip resistor

[26:26] RW 1‘b 1 EXT_GND_CH3 Channel 3 signal ground

0 = internal ground

1 = external ground

[25:25] RW 1‘b 1 EXT_GND_CH2 Channel 2 signal ground

0 = internal ground

1 = external ground

[24:24] RW 1‘b 1 EXT_GND_CH1 Channel 1 signal ground

0 = internal ground

1 = external ground

[23:23] RW 1‘b 0 BYPASS_CH3 Channel 3 anti-alias filter

0 = use

1 = bypass

[22:22] RW 1‘b 0 BYPASS_CH2 Channel 2 anti-alias filter

0 = use

1 = bypass

[21:21] RW 1‘b 0 BYPASS_CH1 Channel 1 anti-alias filter

0 = use

1 = bypass

[20:20] RW 1‘b 0 DROOP_COMP_CH3 Channel 3 input resistance boosting

0 = disable

1 = enable

[19:19] RW 1‘b 0 DROOP_COMP_CH2 Channel 2 input resistance boosting

0 = disable

1 = enable

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Registers CX23885 Data Sheet

[18:18] RW 1‘b 1 DROOP_COMP_CH1 Channel 1 input resistance boosting

0 = disable

1 = enable

[17:17] RW 1‘b 0 CLAMP_EN_CH3 Channel 3 clamping

0 = disable

1 = enable (power up)

[16:16] RW 1‘b 0 CLAMP_EN_CH2 Channel 2 clamping

0 = disable

1= enable (power up)

[15:15] RW 1‘b 1 CLAMP_EN_CH1 Channel 1 clamping

0 = disable

1 = enable (power up)

[14:14] RW 1‘b 1 AUD_IN_SEL ADC input Select for Audio input paths:

0 = ADC1 input

1 = ADC2 input

[13:13] RW 1‘b 0 LUMA_IN_SEL ADC input Select for Luma input paths:

0 = ADC1 input

1 = ADC2 input

[12:12] RW 1‘b 1 CHROMA_IN_SEL ADC input Select for Chroma input paths:

0 = ADC1 input

1 = ADC2 input

[11:11] RW 1‘b 1 CLAMP_SEL_CH3 Channel 3 Clamp level:

0 = video decoder drives clamp level

1 = fixed at 3'b111 (midcode clamp)

[10:10] RW 1‘b 1 CLAMP_SEL_CH2 Channel 2 Clamp level:

0 = video decoder drives clamp level

1= fixed at 3'b111 (midcode clamp)

[9:9] RW 1‘b 0 CLAMP_SEL_CH1 Channel 1 Clamp level:

0 = video decoder drives clamp level

1 = fixed at 3'b111 (midcode clamp)

[8:8] RW 1‘b 1 VGA_SEL_CH3 Channel 3 VGA gain:

0 = video decoder drives VGA gain setting

1 = audio decoder drives VGA gain setting

[7:7] RW 1‘b 1 VGA_SEL_CH2 Channel 2 VGA gain:

0 = video decoder drives VGA gain setting

1 = audio decoder drives VGA gain setting

[6:6] RW 1‘b 0 VGA_SEL_CH1 Channel 1 VGA gain:

0 = video decoder drives VGA gain setting

1 = audio decoder drives VGA gain setting

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[5:5] RW 1‘b 0 HALF_BW_CH3 Channel 3 anti-alias filter bandwidth reduction

0 = no reduction

1 = reduce by half

[4:4] RW 1‘b 0 HALF_BW_CH2 Channel 2 anti-alias filter bandwidth reduction

0 = no reduction

1 = reduce by half

[3:3] RW 1‘b 0 HALF_BW_CH1 Channel 1 anti-alias filter bandwidth reduction

0 = no reduction

1 = reduce by half

[2:2] RW 1‘b 0 EN_12DB_CH3 Channel 3 extra 12 dB gain

0 = disable

1 = enable

[1:1] RW 1‘b 0 EN_12DB_CH2 Channel 2 extra 12 dB gain

0 = disable

1 = enable

[0:0] RW 1‘b 0 EN_12DB_CH1 Channel 1 extra 12dB gain

0 = disable

1 = enable

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Registers CX23885 Data Sheet

3.18.1.3 Video PLL Integer/Post Divider

3.18.1.4 Video PLL Fractional

Bits Type Default Name Description

[31:14] RO 18‘b 0 Reserved

[13:8] RW 6‘h 4 VID_PLL_POST Video PLL Post Divide

Valid values are 2 to 63 (decimal)

PLL clock frequency = FREF * (M + (N / 225)) /

Post Divide

Default Video PLL frequency = 108.000011

MHz. Assuming reference frequency =

28.636363 MHz

[7:6] RO 2‘b 0 Reserved

[5:0] RW 6‘h F VID_PLL_INT Video PLL integer coefficient (M)

Valid values are 8 to 59 (decimal)

PLL clock frequency = FREF * (M + (N / 225)) /

Post Divide

Default value places VCO in safe operating

range.

Bits Type Default Name Description

[31:25] RO 7‘b 0 Reserved

[24:0] RW 25‘h 2BE2FE VID_PLL_FRAC Video PLL fractional coefficient (N)

Valid values are 0 to 2^25-1

PLL clock frequency = FREF * (M + (N / 225)) /

Post Divide

Default Video PLL frequency = 108.000011

MHz. Assuming reference frequency =

28.636363 MHz

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3.18.1.5 Auxiliary PLL Integer/Post Divider

3.18.1.6 Auxiliary PLL Fractional

Bits Type Default Name Description

[31:22] RO 10‘b 0 Reserved

[21:16] RW 6‘h A AUX_PLL_POST_B Auxiliary PLL Post Divide B

Valid values are 2 to 63 (decimal)

[15:14] RO 2‘b 0 Reserved

[13:8] RW 6‘h 3 AUX_PLL_POST_A Auxiliary PLL Post Divide A

Valid values are 2 to 63 (decimal)

[7:6] RO 2‘b 0 Reserved

[5:0] RW 6‘h 18 AUX_PLL_INT Auxiliary PLL integer coefficient (M)

Valid values are 8 to 59 (decimal)

Default places VCO in safe operating mode at

powerup

Bits Type Default Name Description

[31:25] RO 7‘b 0 Reserved

[24:0] RW 25‘h 1BF0C9D AUX_PLL_FRAC AUX PLL fractional coefficient (N)

(0 to 225 –1)

PLL clock frequency = Crystal frequency * (M +

(N / 225)) / Post Divide

Default is 7680*48e3/28.636363e6

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Registers CX23885 Data Sheet

3.18.1.7 System PLL Integer/Post Divider

3.18.1.8 System PLL Fractional

Bits Type Default Name Description

[31:14] RO 18‘b 0 Reserved

[13:8] RW 6‘h 5 SYS_PLL_POST SYS PLL Post Divide

Valid values are 2 to 63 (decimal)

PLL clock frequency = Crystal frequency * (M +

(N / 225)) / Post Divide

Typical value is 2

[7:6] RO 2‘b 0 Reserved

[5:0] RW 6‘h 13 SYS_PLL_INT SYS PLL integer coefficient (M)

Valid values are 8 to 59 (decimal)

PLL clock frequency = Crystal frequency * (M +

(N / 225)) / Post Divide

Typical value is 0xA

Bits Type Default Name Description

[31:25] RW 7‘b 0 Reserved

[24:0] RW 25‘h 14758E5 SYS_PLL_FRAC SYS PLL fractional coefficient (N)

(0 to 225–1)

PLL clock frequency = Crystal frequency * (M +

(N / 225)) / Post Divide

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CX23885 Data Sheet Registers

3.18.1.9 Pin Control

Bits Type Default Name Description

[31:31] RW 1‘b 0 Reserved

[30:30] RO 1‘b 0 IR_IRQ_STAT Bit is used in OR statement to determine if IRQ

out of AV_CORE is set.

[29:29] RO 1‘b 0 AUD_IRQ_STAT Bit is used in OR statement to determine if IRQ

out of AV_CORE is set.

[28:28] RO 1‘b 0 VID_IRQ_STAT Bit is used in OR statement to determine if IRQ

out of AV_CORE is

[27:26] RO 2‘b 0 Reserved

[25:25] RW 1‘b 0 IRQ_N_OUT_EN Interrupt output enable

[24:24] RW 1‘b 0 IRQ_N_POLAR Interrupt output polarity

[23:22] RW 2‘b 0 I2S_SPD I2S Pad Speed

[21:20] RW 2‘b 0 AGC_SPD AGC_IF/AGC_RF pad speed

[19:18] RW 2‘b 0 IR_SPD IR_TX/IR_RX pad speed

[17:16] RW 2‘b 0 VID_DATA_SPD Video clock and data pad speed

[13:12] RW 2‘b 0 GPIO_SPD GPIO pad speed

[15:14] RW 2‘b 0 VID_CTRL_SPD Video control signals pad speed

[11:11] RW 1‘b 1 AGC_OUT_EN Enable AGC RF and IF outputs

[10:10] RW 1‘b 0 IR_TX_OUT_EN Enable IR transmitter output

[9:9] RW 1‘b 0 VID_DATA_OUT_EN Enable Video Data outputs

[8:8] RW 1‘b 0 VID_CTRL_OUT_EN Enable Video Control signal outputs.

[7:7] RW 1‘b 0 GPIO3_OUT_EN GPIO[3] output enable

[6:6] RW 1‘b 0 GPIO2_OUT_EN GPIO[2] output enable

[5:5] RW 1‘b 0 GPIO1_OUT_EN GPIO[1] output enable

[4:4] RW 1‘b 0 GPIO0_OUT_EN GPIO[0] output enable

[3:0] RW 4‘b 0 GPIO Write GPIO data to pads

Read data at GPIO pads

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Registers CX23885 Data Sheet

3.18.1.10Audio I/O Control

Bits Type Default Name Description

[31:8] RO 24‘b 0 Reserved

[7:7] RW 1‘b 0 I2S_PORT_DIR I2S port direction

0 – output

1 – input

[6:6] RW 1‘b 0 I2S_OUT_SRC I2S port source

0 – Audio Decoder

1 – Analog/Digital Converter

When 1 is selected, the I2S pins will be directly

connected to the A/D Converter I2S ports,

providing full 24b I2S data at the A/D Converter

sample rate.

[5:4] RW 2‘b 0 AUD_CHAN3_SRC Audio channel 3 source

00 - Reserved

01 - I2S input

10 – A/D Converter

11 - Reserved

[3:2] RW 2‘b 0 AUD_CHAN2_SRC Audio Channel 2 Source

00 - Parallel 2 (Audio Decoder Parallel2_SRC

out)

01 - I2S input

10 – A/D Converter

11 - Parallel 2 (Audio Decoder Parallel2_SRC

out)

Parallel 2 SRC source controlled by

PARALLEL2_SRC_OUT_SEL in

BAND_OUT_SEL register

[1:0] RW 2‘b 0 AUD_CHAN1_SRC Audio Channel 1 Source

00 - Parallel 1 (Audio Decoder Parallel1_SRC

out)

01 - I2S input

10 – A/D Converter

11 - Parallel 1 (Audio Decoder Parallel1_SRC

out)

Parallel 1 SRC source controlled by

PARALLEL1_SRC_OUT_SEL in

BAND_OUT_SEL register

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CX23885 Data Sheet Registers

3.18.1.11Audio Lock Control 1

3.18.1.12Audio Lock Control 2

Bits Type Default Name Description

[31:30] RW 2‘h 2 AUD_LOCK_KI_SHIF

The gain applied to the indirect error path of the

loop filter through a left shift from 0 to 3 bit

positions. This is in addition to a default right

shift. This is used to lock the AUX PLL to the

video pixel rate.

[29:28] RW 2‘h 2 AUD_LOCK_KD_SHI

The gain applied to the direct error path of the

loop filter through a left shift from 0 to 3 bit

positions. This is in addition to a default left shift.

This is used to lock the AUX PLL to the video

pixel rate

[27:25] RO 3‘b 0 Reserved

[24:24] RW 1‘b 0 EN_AV_LOCK Enable locking of AUX_PLL to video pixel rate

[23:0] RW 24‘h 1193F8 VID_COUNT Expected count, minus 1 and times 8, for 8x

video PLL clock when the number of audio

clocks is counted as reflected in AUD_COUNT.

Since this number is in terms of eights of an 8x

pixel clock, more resolution is allowed in

defining the audio/video clock ratio.

Bits Type Default Name Description

[31:28] RW 4‘b 1 AUD_LOCK_KI_MUL

The gain applied to the indirect error path of the

loop filter through an unsigned multiply. This is

used to lock the AUX PLL to the video pixel rate

[27:24] RW 4‘b 1 AUD_LOCK_KD_MU

The gain applied to the direct error path of the

loop filter through an unsigned multiply. This is

used to lock the AUX PLL to the video pixel rate

[23:22] RO 2‘b 0 Reserved

[21:20] RW 2‘h 2 AUD_LOCK_FREQ_SH

IFT

The gain applied to the frequency error

(difference in actual vs. expected counts) before

passing to the loop filter. This is in addition to a

default scaling that occurs. There is a default left

or right shift depending on the length of time

over which the sample is collected, as indicated

by the VID_COUNT field.

[19:0] RW 20‘h 5FFF AUD_COUNT Number of audio sample-rate clocks, minus 1, to

count before examining VID_COUNT.

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Registers CX23885 Data Sheet

3.18.1.13Power-Down Control

Bits Type Default Name Description

[31:16] RO 16‘b 0 Reserved

[15:15] RW 1‘b 0 IFCLK_GATE_MSK IFCLK gate mask

0 - DIG_PWR_DN disables IF ADC clock

(IFCLK)

1 – gating of IFCLK inhibited

[14:14] RW 1‘b 0 BBCLK_GATE_MSK BBCLK gate mask

0 - DIG_PWR_DN disables baseband ADC

clock (BBCLK)

1 – gating of BBCLK inhibited

[13:13] RW 1‘b 0 SCLK_GATE_MSK SCLK and I2S_MCLK gate mask

0 - DIG_PWR_DN disables sample clock

(SCLK) and I2S master clock (I2S_MCLK)

1 – gating of SCLK and I2S_MCLK inhibited

[12:12] RW 1‘b 0 CLK5X_GATE_MSK CLK5X gate mask

0 - DIG_PWR_DN disables high-speed audio

clock (CLK5X)

1 – gating of CLK5X inhibited

[11:11] RW 1‘b 0 VCLK_GATE_MSK VCLK gate mask

0 - DIG_PWR_DN disables high-speed video

clock (VCLK)

1 – gating of VCLK inhibited

[10:10] RW 1‘b 0 SLEEP_PLL_MSK PLL sleep mask.

0 - SLEEP powers down PLLs

1 - power down of PLL inhibited

[9:9] RW 1‘b 0 SLEEP_DLL_MSK DLL sleep mask.

0 - SLEEP powers down DLL circuitry

1 - power down inhibited

[8:8] RW 1‘b 0 SLEEP_ANALOG_M

Analog subsystem sleep mask.

0 - SLEEP powers down analog subsystem

1- power down of analog subsystem inhibited

including DLL and PLLs

[7:7] RW 1‘b 0 PWR_DN_CH3 Powers down Channel 3 VGA/filter circuitry.

0 – don’t power down Channel 3

1 - power down Channel 3

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CX23885 Data Sheet Registers

3.18.1.14AFE Diagnostic Control 1

[6:6] RW 1‘b 0 PWR_DN_CH2 Powers down Channel 2 VGA/filter circuitry.

0 – don’t power down Channel 2

1 - power down Channel 2

[5:5] RW 1‘b 0 PWR_DN_CH1 Powers down Channel 1 VGA/filter circuitry.

0 – don’t power down Channel 1

1 - power down Channel 1

[4:4] RW 1‘b 0 PWR_DN_ADC2 Powers down ADC2 circuitry.

0 – don’t power down ADC 2

1 - power down ADC 2

[3:3] RW 1‘b 0 PWR_DN_ADC1 Powers down ADC1 circuitry.

0 – don’t power down ADC 1

1 - power down ADC 1

[2:1] RO 2‘b 0 Reserved

[0:0] RW 1‘b 0 PWR_DN_TUNING Powers down filter tuning circuitry.

0 – don’t power down filter tuning

1 - power down filter tuning

Bits Type Default Name Description

[31:31] RW 1‘b 0 DROOP_CAL_CH3 Droop calibrate enable for channel 3.

While high, the droop comp circuit for channel1

will calibrate.

[30:30] RW 1‘b 0 DROOP_CAL_CH2 Droop calibrate enable for channel 2.

While high, the droop comp circuit for channel1

will calibrate.

[29:29] RW 1‘b 0 DROOP_CAL_CH1 Droop calibrate enable for channel 1.

While high, the droop comp circuit for channel1

will calibrate.

[28:28] RW 1‘b 0 DROOP_CAL_CALC_C

Enable for the droop compensation calibration

where the DAC current is calculated. This

particular enable bit applies to channel 3.

[27:27] RW 1‘b 0 DROOP_CAL_CALC_C

Enable for the droop compensation calibration

where the DAC current is calculated. This

particular enable bit applies to channel 2.

[26:26] RW 1‘b 0 DROOP_CAL_CALC_C

Enable for the droop compensation calibration

where the DAC current is calculated. This

particular enable bit applies to channel 1.

[25:20]

RO 6'h 24 Reserved

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Registers CX23885 Data Sheet

[19:18]

RW 2'b 1 FILTER_BIAS Digital control for the bias current multiplier

00 = 0.5

01 = 1

10 = 1.5

11 = 2

[17:16] RW 2‘b 1 S2DIFF_BIAS Digital control for the single-ended to differential

converter bias multiplier

00 = 0.75

01 = 1

10 = 1.25

11 = 1.5

[15:15] RW 1‘b 0 Reserved

[14:8] RW 7‘h 18 BIAS_CTRL_ADC Digital control for the reference buffer bias

[14:13]

00 = 50 μA default

01 = 62.5 μA

10 = 37.5 μA

11 = 75.0 μA

MSB comparator current [12:11]

00 = 12.5 μA

01 = 6.25 μA

10 = 25.0 uA

11 = 50.0 μA default

Digital control for REFP and REFM [10]

0 = 1.6 V; 0.8 V default

1 = 1.5 V; 0.9 V

Digital control for ADC bias current. [9:8]

00 = 50.0 μA default

01 = 37.5 μA

10 = 62.5 μA

11 = 75.0 μA

[7:4] RO 4‘b 0 Reserved

[3:3] RW 1‘b 0 VREF_CTRL_ADC Digital control for ADC reference voltage

0 = 1.60 V

1 = 1.20 V

[2:1] RO 2‘b 0 Reserved

[0:0] RW 1‘b 0 FOUR_X_CLK_ADC Choose 4x or 5x DLL output

0 = 5x output

1 = 4x output

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CX23885 Data Sheet Registers

3.18.1.15AFE Diagnostics Control 3

Bits Type Default Name Description

[31:26] RO 6‘b 0 Reserved

[25:25] RW 1‘b 0 AUD_DUAL_FLAG_P

Audio Decoder Dual Flag Polarity

Polarity of DUAL_FLAG signal sent to audio

decoder

0 = non-inverted polarity

1 = inverted polarity

[24:24] RW 1‘b 0 VID_DUAL_FLAG_P

Video Decoder Dual Flag Polarity

Polarity of DUAL_FLAG signal sent to video

decoder

0 = non-inverted polarity

1 = inverted polarity

[23:22] RO 2‘b 0 Reserved

[21:21] RO 1‘b 0 TUNING_READY Filter auto-tuning status

0 = not complete

1 = filter tuning complete

[20:16] RO 5‘b 0 TUNE_OUT The tuning code selected by the auto-tune

algorithm.

[15:15] RW 1‘b 0 FORCE_TUNING Auto-tuning code override

0 = don’t override

1 = forces tuning code to value contained in

TUNE_IN field.

[14:13] RO 2‘b 0 Reserved

[12:8] RW 5‘b 0 TUNE_IN Tuning code to be used when FORCE_TUNING

is set. Overrides the value chosen by auto-

tuning.

[7:4] RO 4‘b 0 Reserved

[3:3] RW 1‘b 0 TEST_MODE_CH1 Disables the filter in CH1 test mode

0 = enable filter

1 = disable filter

[2:2] RO 1‘b 0 DISCONNECT_CH1 Connects the differential analog signal at ADC1

input to pins VIN2 and VIN3

0 = don’t connect

1= connect

[1:1] RW 1‘b 0 CH_SEL_ADC1 ADC1 test mode

0 = connect ADC1 to output of filter

1 = connects ADC1 to the output of first VGA

stage

[0:0] RW 1‘b 0 TUNE_FIL_RST Reset Filter tuning logic.

When 1, filter tuning is reset. When set back to

0, filter will auto-tune itself and after a few clocks

return to normal operation.

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Registers CX23885 Data Sheet

3.18.1.16PLL Diagnostic Control

Bits Type Default Name Description

[31:31] RW 1‘b 0 PLL_VDD_TEST Routes internally generated PLL supply voltage

to CLK_AUX pad

[30:29] RW 2‘b 0 PLL_TEST_SEL Selects voltage to test

00=regulator 1

01=regulator 2

10= regulator reference

11= reserved

[28:23]

RO 6'h 2A Reserved

[22:22] RW 1‘b 0 SPD_TST_EN Enables Ring oscillator process speed test

circuit

[21:21] RW 1‘b 0 SPD_TST_SEL Selects between 1.2 V oscillator and 3.3 V

oscillator

0 - 1.2 V

1 - 3.3 V

[20:20] RO 1‘b 0 Reserved

[19:19] RO 1‘b 0 SYS_PLL_UNLOCK System PLL unlock detection

0 = no unlock detected

1 = unlock detected

[18:18] RO 1‘b 0 AUX_PLL_UNLOCK Auxiliary PLL unlock detection

0 = no unlock detected

1 = unlock detected

[17:17] RO 1‘b 0 VID_PLL_UNLOCK Video PLL unlock detection

0 = no unlock detected

1 = unlock detected

[16:16] RO 1‘b 0 SYS_PLL_LOCK Sys PLL lock status

0 = unlocked

1 = locked

[15:15] RO 1‘b 0 AUX_PLL_LOCK Auxiliary PLL lock status

0 = unlocked

1 = locked

[14:14] RO 1‘b 0 VID_PLL_LOCK Video PLL lock status

0 = unlocked

1 = locked

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CX23885 Data Sheet Registers

3.18.1.17AFE Clock Out Control

[13:13] RW 1‘b 0 SYS_PLL_RST SYS PLL reset

0 = don’t reset

1 = reset the video PLL

[12:12] RW 1‘b 0 AUX_PLL_RST Audio PLL reset

0 = don’t reset

1 = reset the video PLL

[11:11] RW 1‘b 0 VID_PLL_RST Video PLL reset

0 = don’t reset

1 = reset the auxiliary PLL

[10:10] RW 1‘b 0 SYS_PLL_DDS SYS PLL delta sigma fractional divide

0 = enable

1 = disable

[9:9] RW 1‘b 0 AUX_PLL_DDS Auxiliary PLL delta sigma fractional divide

0 = enable

1 = disable

[8:8] RW 1‘b 0 VID_PLL_DDS Video PLL delta sigma fractional divide

0 = enable

1 = disable

[7:6] RO 2‘b 0 Reserved

[5:0] RW 6‘h 4 PLL_SPMP PLL charge pump current

Bits Type Default Name Description

[31:5] RO 27‘b 0 Reserved

[4:4] RW 1‘b 1 CLK_OUT_MODE AFE clock pad mode 0 = output 1 = input

[3:0] RW 4‘h 5 CLK_OUT_SEL Selects AFE clock pad output source

Bits Type Default Name Description

[31:0] RO 32‘b 0 Reserved

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Registers CX23885 Data Sheet

Bits Type Default Name Description

[31:0] RO 32‘b 0 Reserved

Bits Type Default Name Description

[31:0] RO 32‘b 0 Reserved

Bits Type Default Name Description

[31:0] RO 32‘b 0 Reserved

Bits Type Default Name Description

[31:0] RO 32‘b 0 Reserved

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CX23885 Data Sheet Registers

3.18.1.18DLL1 Diagnostic Control

3.18.1.19GPIO[23:19] Output Enable

Bits Type Default Name Description

[31:31] RW 19‘b 0 DLL1_BYPASS Clock reference for DLL1 (ADC DLL) input from

clock pad rather than crystal input. Overrides

CLK_OUT_MODE.

[30:29] RO 2‘b 0 Reserved

[28:25] RW 4‘b 0 CURRSET Changes current used in DLL

[24:23] RW 2‘b 0 DLYS MSB adds delay in path of reference. LSB

multiplexes the DLL clock out when high.

[22:20] RW 3‘b 0 DEPTH Used in False Lock Detect: increases stability of

decisions in FLD

111:x7 routes DLL output to test pad

110:x6 puts DLL in “fast” lock mode

[19:17] RW 3‘b 3 COMP_LT Used in False Lock Detect: counts this many

pulses in half period to determine up override

[16:14] RW 3‘b 4 COMP_GT Used in False Lock Detect: counts this many

pulses in half period to determine pulse-swallow

[13:11] RW 3‘b 2 CHPREF Chooses between old false-lock detect scheme

and new.

[10:10] RW 1‘b 0 DOWN_OVRD Overrides the down command to PFD

[9:9] RW 1‘b 0 UP_OVRD Overrides the up command to PFD

[8:8] RW 1‘b 1 FLD False Lock Detect mode

[7:0] RO 8‘b 0 Reserved

Bits Type Default Name Description

[31:5] RO 27‘b 0 Reserved

[4:0] RW 5‘h 1F GPIO2_OUT_ENABL

E_N

output enable for GPIO[23:19]

1 - normal function

0 – GPIO

GPIO[19] map to IR_RX pin GPIO[20] map to

IR_TX pin GPIO[21] map to I2S_SDAT

GPIO[22] map to I2S_WCLK GPIO[23] map to

I2S_BCLK

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Registers CX23885 Data Sheet

3.18.1.20GPIO [23:19] Data Registers

3.18.1.21IFADC Control

Bits Type Default Name Description

[31:21] RO 11‘b 0 Reserved

[20:16] RO 5‘b 0 GPIO2_IN GPIO [23:19] input register

[15:5] RO 11‘b 0 Reserved

[4:0] RW 5‘b 0 GPIO2_OUT GPIO [23:19] data output registers

Bits Type Default Name Description

[31:31] RW 1‘b 0 IF_PWRDN Power down IF ADC

[30:0] RO 31‘b 0 Reserved

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CX23885 Data Sheet Registers

3.19 IR Registers

3.19.1 Infrared Remote registers

3.19.1.1 Control Register

Bits Type Default Name Description

[31:15] RO 17‘b 0 Reserved

[14:14] RW 1‘b 0 R Receive FIFO load on Timer Overflow Disable

0 = Load Rx FIFO with 1s and RX_DATA_LH

level on timer overflow

1 = Do not load Rx FIFO on timer overflow.

(Shut off when noise occurs but must be turned

back on when a real transmission starts)

[13:13] RW 1‘b 0 LBM Loop Back Mode

0 = Transmit and receive operation functions

normally via the IR port’s pins

1 = The output of the transmit modulation logic

is fed into the input of the receive demodulation

logic internal to the IR port. Transmit pin

continues to reflect transmit data, receive pin is

ignored by the IR receive logic

[31:15] RO 17‘b 0 Reserved

[12:12] RW 1‘b 0 CPL Carrier Polarity (Transmitter Only)

0 = If mod/demodulation enabled, ones

transmitted and received as series of carrier

transitions (mark), zeros transmitted and

received as the absence of a carrier or no

transitions (space). If mod/demodulation

disabled, ones transmitted/received as logic

high, zeros as logic low, and the IR_TX_DATA

PIN is driven low when idle.

1 = If mod/demodulation enabled, ones

transmitted and received as the absence of a

carrier or no transitions (space), zeros

transmitted and received as a series of carrier

transitions (mark). If mod/demodulation

disabled, ones transmitted/received as logic low,

zeros as logic high, and the IR_TX_DATA pin is

driven high when idle.

Note: Receive carrier polarity can be changed

by software. No hardware support for this.

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Registers CX23885 Data Sheet

[11:11] RW 1‘b 0 TIC Transmitter Interrupt Control

0 = Transmit FIFO service interrupt/DMA

request asserted when TX FIFO is half full or

less, negated when TX FIFO is more than half

full

1 = Transmit FIFO service interrupt/DMA

request asserted after transmitter becomes idle,

negated when transmitter becomes busy (see

status register below for a description of this

IRQ)

[10:10] RW 1‘b 0 RIC Receiver Interrupt Control

0 = Receive FIFO service interrupt/DMA request

asserted when RX FIFO is half full or greater,

negated when RX FIFO is less than half full.

1 = Receive FIFO service interrupt/DMA request

asserted when RX FIFO is not empty, negated

when RX FIFO is empty.(see status register

below for a description of this interrupt request)

[9:9] RW 1‘b 0 TXE Transmitter Enable

0 = Disable transmitter

1 = Enable transmitter

[8:8] RW 1‘b 0 RXE Receiver Enable

0 = Disable receiver

1 = Enable receiver

[7:7] RW 1‘b 0 TFE Transmit FIFO Enable

0 = Disable and reset transmit FIFO to all zeros

1 = Enable transmit FIFO

[6:6] RW 1‘b 0 RFE Receive FIFO Enable

0 = Disable and reset receive FIFO to all zeros

1 = Enable receive FIFO

[5:5] RW 1‘b 0 MOD Transmit Modulation Enable

0 = Disable transmit carrier modulation, transmit

data as simple logic levels

1 = Enable transmit carrier modulation, transmit

a mark as a burst of IR_TX_DATA pin

transitions, and a space as the absence of

transitions programming the carrier polarity bit

determines whether ones or zeros are encoded

into marks/high or spaces/low

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CX23885 Data Sheet Registers

[4:4] RW 1‘b 0 DMD Receive Demodulation Enable

0 = Disable receive carrier demodulation,

receive data as simple logic levels

1 = Enable receive carrier demodulation, detect

a mark as a series of RX pin transitions, and a

space as the absence of transitions

programming the carrier polarity bit determines

whether marks/high or spaces/low are decoded

as ones or zeros

[3:2] RW 2‘b 0 EDG Receive Edge Detect Control

00 = Disabled

01 = Falling edges trigger RX filter/pulse timer

start/stop

10 = Rising edges trigger RX filter/pulse timer

start/stop

11 = Either edge trigger RX filter/pulse timer

start/stop The RX low pass filter and pulse width

timer starts/ends a pulse duration measurement

each time the programmed edge on the

demodulated input is detected.

[1:0] RW 2‘b 0 WIN Next Predicted Receive Carrier Edge Window

Limits

00 = Next carrier edge predicted to be 16 RX

clocks -3/+3

01 = Next carrier edge predicted to be 16 RX

clocks -4/+3

10 = Next carrier edge predicted to be 16 RX

clocks -3/+4

11 = Next carrier edge predicted to be 16 RX

clocks -4/+4

Once the first rising edge within a carrier burst is

detected, each subsequent rising-edge should

occur 16 RX clock cycles later, plus or minus the

programmed limits above, transitions out of this

range are not detected.

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Registers CX23885 Data Sheet

3.19.1.2 Transmit Clock Divider Register

3.19.1.3 Receive Clock Divider Register

3.19.1.4 Transmit Carrier Duty Cycle Register

Bits Type Default Name Description

[31:16] RO 16‘b 0 Reserved

[15:0] RW 16‘h FFFF TCD Transmit Clock Divider

16-bit value used by the transmit clock down

counter as a modulus value to generate the

transmit clock for the modulator and TX pulse

width timer. Transmit clock counter reloaded any

time this register is written. A value of ‘b00 is not

permitted for the TCD.

Bits Type Default Name Description

[31:16] RO 16‘b 0 Reserved

[15:0] RW 16‘h FFFF RCD Receive Clock Divider

16-bit value used by the receive clock down

counter as a modulus value to generate the

receive clock for the demodulator and RX pulse

width timer. Receive clock counter reloaded any

time this register is written. A value of ‘b00 is not

permitted for the RCD.

Bits Type Default Name Description

[31:4] RO 28‘b 0 Reserved

[3:0] RW 4‘b 0 CDC Transmit Carrier Duty Cycle

0000 = 1 TX clock high and 15 TX clocks low

0001 = 2 TX clocks high and 14 TX clocks low

0010 = 3 TX clocks high and 13 TX clocks low...

1101 = 14 TX clocks high and 2 TX clocks low

1110 = 15 TX clocks high and 1 TX clock low

1111 = 16 TX clocks high and 0 TX clocks low

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CX23885 Data Sheet Registers

3.19.1.5 Status Register

Bits Type Default Name Description

[31:6] RO 26‘b 0 Reserved

[5:5] RO 1‘b 0 TSR Transmit FIFO Service Request

0 = If TIC = 0 in IR_CNTL_REG, transmit FIFO

is more than half full. If TIC=1, transmitter is

busy.

1 = IF TIC= 0, transmit FIFO is half full or less. If

TIC= 1, transmitter is idle. Generate an IRQ

request if the TSE mask bit is set in the

IR_IRQEN_REG

[4:4] RO 1‘b 0 RSR Receive FIFO Service Request

0 = If RIC=0 in IR_CNTL_REG, receive FIFO is

less than half full. If RIC=1, receive FIFO is

empty.

1 = IF RIC = 0, receive FIFO is half full or more.

If RIC= 1, receive FIFO is not empty. Generate

an IRQ request if the RSE mask bit is set in the

IR_IRQEN_REG.

[3:3] RO 1‘b 0 TBY Transmitter Busy (non-interruptible)

0 = Transmitter is idle

1 = Transmitter is busy

[2:2] RO 1‘b 0 RBY Receiver Busy (non-interruptible)

0 = Receiver is idle

1 = Receiver is busy

[1:1] RO 1‘b 0 ROR Receive FIFO Overrun

0 = Receive FIFO contains one or more empty

entries or is full but has not experienced an

overrun

1 = Receive FIFO has experienced an overrun,

generate an IRQ request if the ROE mask bit is

set in the IR_IRQEN_REG

Note: When an overrun occurs, data within the

FIFO remains intact, and any new data from the

RX pulse width counter is lost until the FIFO

once again contains one or more empty entries.

[0:0] RO 1‘b 0 RTO Receive Pulse Width Timer Timeout

0 = Receive pulse width counter has not

reached its limit

1 = Receive pulse width counter has reached its

limit (contains all ones), generate an IRQ

request if the RTE mask bit is set in the IR_IRQ.

Note: Cleared by disabling RXE (Rx enable) bit

of the IR_CNTRL_REG.

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Registers CX23885 Data Sheet

3.19.1.6 Interrupt Enable Register

3.19.1.7 Low Pass Filter Register

Bits Type Default Name Description

[31:6] RO 16‘b 0 Reserved

[5:5] RW 1‘b 1 TSE Transmit FIFO Service Request Interrupt

Enable

0 = Transmit FIFO/Idle interrupt disabled

1 = Transmit FIFO/Idle interrupt enabled

[4:4] RW 1‘b 1 RSE Receive FIFO Service Request Interrupt Enable

0 = Receive FIFO interrupt disabled

1 = Receive FIFO interrupt enabled

[3:2] RO 2‘b 0 Reserved

[1:1] RW 1‘b 1 ROE Receive FIFO Overrun Interrupt Enable

0 = Receive FIFO overrun interrupt disabled

1 = Receive FIFO overrun interrupt enabled

[0:0] RW 1‘b 1 RTE Receive Pulse Width Timer Time-out Interrupt

Enable

0 = Receive pulse width timer time-out interrupt

disabled

1 = Receive pulse width timer time-out interrupt

enabled

Bits Type Default Name Description

[31:16] RO 16‘b 0 Reserved

[15:0] RW 16‘b 0 LPF Low Pass Filter

Modulus 16-bit value used as a modulus value

to filter out pulses below a minimum width. Filter

counter is reloaded with modulus each time

programmed edge is encountered. Counter

decrements using the host bus clock, if next

edge seen before counter reaches zero, pulse

measurement is discarded. If counter reaches

zero it retains this value until the next edge is

seen. Whenever the counter contains a zero,

pulse measurements are saved to the RX FIFO.

A value of 0x0000 disables the filter function,

and values 0x0001 through 0x0004 are not

permitted.

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CX23885 Data Sheet Registers

3.19.1.8 FIFO Register

Bits Type Default Name Description

[31:18] RO 14‘b 0 Reserved

[17:17] RO 1‘b 0 RXNDV Receive Next Data Valid

0 = No more data in the RX FIFO

1 = One or more entries of valid data remain in

RX FIFO

[16:16] RW 1‘b 0 IR_RXTXLVL Transmit/Receive Pin Level

Read: Value of demodulated input at end of RX

pulse width measurement

Write: Value to send to modulator for TX pulse

width count output

[15:0] RW 16‘b 0 IR_RXTXFIFO Transmit/Receive Pulse Width Count/

Measurement Value

Read: Bottom entry of the receive FIFO

Write: Top entry of the transmit FIFO

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Registers CX23885 Data Sheet

3.20 Video Decoder Registers

3.20.1 Basic Video Decoder Mode Control

Bits Type Default Name Description

[31:30] RO 2‘b 0 Reserved

[29:29] RW 1‘b 0 AFD_PAL60_DIS Disable auto-detection of PAL-60 formats.

0 = PAL-60 can be detected and discriminated

from NTSC-443 based on phase alternation

1 = Any 525-line 4.43 format is assumed to be

NTSC-443.

[28:28] RW 1‘b 0 AFD_FORCE_SECA

Force SECAM format when 625 lines are

detected.

0 = The Auto-detect algorithm proceeds

normally.

1 = SECAM format is chosen when a 625-line

format is detected.

[27:27] RW 1‘b 0 AFD_FORCE_PALN

Force PAL-Nc format when 625 lines are

detected.

0 = The Auto-detect algorithm proceeds

normally.

1 = PAL-Nc is chosen when a 625-line format is

detected.

[26:26] RW 1‘b 0 AFD_FORCE_PAL Force PAL-BG format when 625 lines are

detected.

0 = The Auto-detect algorithm proceeds

normally.

1 = PAL-BG/PAL-N is chosen when a 625-line

format is detected according to the

AFD_PAL_SEL bit.

[25:24] RW 2‘b 0 AFD_PALM_SEL Select PAL-M format when 525-lines and 3.58

carrier is detected.

0 = NTSC will be detected according to the

AFD_NTSC_SEL bit.

1 = PAL-M format is chosen when 525 lines and

a 3.58 carrier are detected.

2 = Enable algorithm to dynamically discriminate

between NTSC-M and PAL-M

[23:22] RO 2‘b 0 Reserved

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[21:20] RW 2‘b 0 CKILL_MODE Color Kill Mode. Defines how luma output is

generated when color kill is asserted:

0 = Chroma output is forced to zero, and luma

output is generated from normal comb filter

operation (default)

1 = Chroma output is forced to zero, entire

chroma band is notched from luma output. The

comb filter is forced into notch mode 1. (See

COMB_NOTCH_MODE field.)

2 = Black and White mode.Chroma output is

forced to zero, and entire composite signal is

treated as luma. The comb filtered is forced into

notch mode 3. (See COMB_NOTCH_MODE

field.)

[19:18] RO 2‘b 0 Reserved

[17:17] RO 1‘b 0 CLR_LOCK_STAT Clear HLOCK, VLOCK, and CLOCK status bits

[16:16] RW 1‘b 0 FAST_LOCK_MD Active-high fast lock algorithm select. This

vertical locking algorithm. This has two effects:

1. The fast locking algorithm (1’b1) will lock onto

the first VSYNC that it encounters, regardless of

its position. The normal vertical locking

algorithm (1’b0) will look for a sync within an

expected window. If no sync appears during the

next expected window then it will lock onto the

first subsequent incoming VSYNC.

2. The FAST_LOCKING ALGORITHM (1’b1) will

bypass the 8 field hysteresis that is built into the

field detection logic. In this mode as soon as the

even/odd field is detected, the field signal will

reflect the status. When this is disabled (1’b0)

the field detection needs to be stable for 8

consecutive fields before the field signal will

reflect the change.

[15:15] RW 1‘b 1 WCEN White Crush enable

[14:14] RW 1‘b 1 CAGCEN Chroma AGC enable

[13:13] RW 1‘b 1 CKILLEN Chroma killer enable

[12:12] RW 1‘b 1 AUTO_SC_LOCK Auto chroma subcarrier lock speed select.

0 = Manual mode. Lock speed is determined by

MAN_SC_FAST_LOCK.

1 = Auto Mode. When unlocked, chose fast lock

speed. When locked, choose slow speed.

[11:11] RW 1‘b 0 MAN_SC_FAST_LOCK Manual chroma subcarrier lock speed select.

When set, chooses fast lock speed. This bit is a

don’t-care if the AUTO_SC_LOCK bit is set.

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Registers CX23885 Data Sheet

[10:9] RW 2‘b 0 INPUT_MODE Signal Input Format:

0 – CVBS

1 – Y/C

2 – Y/ half-rate C

3 – Y/U/V

[8:8] RW 1‘b 0 AFD_ACQUIRE By setting to 1 and then 0, forces the auto

format detect state machine to re-evaluate the

incoming video format and update

AFD_FMT_STAT accordingly.

0 = The auto-detect state machine operates

normally.

1 = Auto-detect state machine soft reset. The

auto-detect state machine is forced back to the

INIT state, and held there until the bit is cleared.

[7:7] RW 1‘b 0 AFD_NTSC_SEL This bit is used by the Auto Format Detect block

to differentiate between NTSC-M and NTSC-J.

0 = NTSC-M

1 = NTSC-J

[6:6] RW 1‘b 0 AFD_PAL_SEL This bit is used by the Auto Format Detect block

to differentiate between PAL-N and PAL-

B,D,G,H,I.

0 = PAL-BDGHI

1 = PAL-N

[5:5] RW 1‘b 0 ACFG_DIS Disable auto-config of registers addressed 0x70

to 0x7F based on format.

[4:4] RW 1‘b 0 SQ_PIXEL Square-pixel mode

[3:0] RW 4‘b 0 VID_FMT_SEL Manual video format select value. This value is

used to force the video decoder into a certain

video format when it is non-zero.

4’b0000 AUTO-DETECT

4’b0001 NTSC-M

4’b0010 NTSC-J

4’b0011 NTSC-4.43

4’b0100 PAL-BDGHI

4’b0101 PAL-M

4’b0110 PAL-N

4’b0111 PAL-NC

4’b1000 PAL-60

4’b1100 SECAM

4’b1101 SECAM-60 [currently not supported]

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CX23885 Data Sheet Registers

3.20.1.1 Output Control 1

Bits Type Default Name Description

[31:31] RO 1‘b 0 Reserved

[30:24] RW 7‘b 0 POLAR When bit is set, invert polarity of output.

[0]: VRESET_N

[1]: HRESET_N

[2]: ACTIVE

[3]: FIELD

[4]: CBFLAG

[5]: VACTIVE

[6]: VALID

[23:23] RO 1‘b 0 Reserved

[22:21] RW 2‘b 0 RND_MODE Rounding style for 8b output

00 - standard rounding

01 - rounding controlled by pseudo random

number generator

10 - error diffusion

11 - error diffusion gated with PRNG

[20:20] RW 1‘b 1 VIPCLAMP_EN Clamp luma and chroma data in VIP modes

(i.e., OUT_MODE[1]==1’b1) to 1-254.75.

Affects all output bytes except control codes,

raw data, and ancillary data fields.

[19:19] RW 1‘b 0 VIPBLANK_EN Enable substitution of blanking data during

horizontal and vertical blanking intervals during

VIP modes (i.e., OUT_MODE[1] == 1’b1)

[18:18] RW 1‘b 0 VIP_OPT_AL VIP optional active line enable. In VIP modes,

the transition of the V-bit from 1 to 0 is

determined by either the VBLANK register or

V656BLANK register.

0 = VBLANK

1 = V656BLANK

[17:17] RW 1‘b 0 IDID0_SOURCE Source of IDID0 byte in VIP ancillary data;

0 = IDID0 register

1 = Line Count from VBI Slicer

[16:16] RW 1‘b 0 DCMODE Determines the format of the data count field in

ancillary data in 8-bit mode (MODE10B = 1’b0);

0 = Data Count is number of blocks of 4 UDWs

(with padding)

1 = Data Count is number UDWs

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Registers CX23885 Data Sheet

[15:14] RW 2‘b 0 CLK_GATING Select pixel clock gating scheme.

0X = no gating;

10 = gate with valid output;

11 = gate with logical AND of valid and active

outputs

[13:13] RW 1‘b 1 CLK_INVERT When set, the pixel clock output is inverted.

[12:12] RW 1‘b 0 HSFMT Selects width of HRESET_N.

0 = nominal width;

1 = one pixel clock (VOF_PIXCLK) pulse wide

[11:11] RW 1‘b 0 VALIDFMT Valid signal format.

0 = valid indicates nonscaled pixels;

1 = valid is logical AND of nominal valid and

active, where active is controlled by ACTFMT

[10:10] RW 1‘b 1 ACTFMT Active signal format.

0 = active is composite active;

1 = active is horizontal active

[9:9] RW 1‘b 0 SWAPRAW Switch the positioning of the raw samples

between the luma and chroma data paths.

0 = Even samples on chroma; odd samples on

luma;

1 = Odd samples on chroma; even samples on

luma

[8:8] RW 1‘b 1 CLAMPRAW_EN Enable clamping of raw ADC samples to 1-

254.75 when video output format mode uses

control codes

[7:7] RW 1‘b 0 BLUE_FIELD_EN Enable generation of blue field on output when

decoder loses lock.

[6:6] RW 1‘b 0 BLUE_FIELD_ACT Activate blue field on output regardless of

BLUE_FIELD_EN register.

[5:5] RW 1‘b 1 TASKBIT_VAL Task bit value in VIP 2.0 mode.

[4:4] RW 1‘b 1 ANC_DATA_EN Enable Ancillary Data Insertion for BT.656 or

VIP modes.

[3:3] RW 1‘b 0 VBIHACTRAW_EN Enables raw data output during the horizontal

active region of the vertical blanking interval

[2:2] RW 1‘b 0 MODE10B Selects either 8-bit or 10-bit output for 4:2:2

Luma and Chroma output.

0 = Luma and Chroma Output are rounded to 8

bits;

1 = Luma and Chroma Output have 10 bits of

resolution

[1:0] RW 2‘b 1 OUT_MODE Sets video output format:

00 = ITU-R BT.601 coded video Synchronous

Pixel Interface (SPI);

01 = ITU-R BT.656 control codes

10 = VIP 1.1 control codes

11 = VIP 2.0 control codes

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3.20.1.2 Output Control 2

Bits Type Default Name Description

[31:30] RW 2‘b 0 AUD_GRP This field indicates the Audio group that

particular data flow belongs to.

2’b00: Audio Group1

2’b01: Audio Group2

2’b10: Audio Group3

2’b11: Audio Group4

[29:28] RW 2‘b 0 SAMPLE_RATE This indicates the sampling rate of the audio

data available for insertion in the FIFOs.

2’b00: 48 kHz

2’b01: 44.1 kHz

2’b10: 32 kHz

2’b11: Reserved

[27:27] RW 1‘b 0 AUD_ANC_EN This bit enables audio ancillary data

insertion.This bit along with the respective

enables for the FIFO will enables data

insertion.For example, to enable FIFO_A data

insertion, AUD_ANC_EN has to be 1’b1 and

EN_A has to be 1’b1.

[26:26] RW 1‘b 0 EN_C This bit enables data insertion from the FIFO_C

in the VOF into the output stream.

[25:25] RW 1‘b 0 EN_B This bit enables data insertion from the FIFO_B

in the VOF into the output stream

[24:24] RW 1‘b 0 EN_A This bit enables data insertion from the FIFO_A

in the VOF into the output stream

[23:20] RO 4‘b 0 Reserved

[19:18] RW 2‘b 0 IDID1_LSB Value for IDID1byte in VIP ancillary data.([1:0]

are used for enabling 10-bit mode.)

[17:16] RW 2‘b 0 IDID0_LSB Value for IDID0 byte in VIP ancillary data.([1:0]

are used for enabling 10-bit mode.)

[15:8] RW 8‘h 80 IDID1_MSB Value for IDID1 byte in VIP ancillary data.([9:2]

are used in 8-bit mode.)

[7:0] RW 8‘b 0 IDID0_MSB Value for IDID0 byte in VIP ancillary data.([9:2]

are used in 8-bit mode.)

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Registers CX23885 Data Sheet

3.20.1.3 General Status

Bits Type Default Name Description

[31:24] RO 8‘b 0 Reserved

[23:23] RO 1‘b 0 VCR_DETECT VCR detection status

[22:22] RO 1‘b 0 SPECIAL_PLAY_N Special Play mode. Active-low special play

mode (fast forward, rewind, pause or slow

motion). This is used to disable certain

algorithms when not in a normal play mode.

Special play mode is assumed when the

detected VSYNC falls outside of a narrow 2 line

expected window.

[21:21] RO 1‘b 0 VPRES Active-high video present. Indication of the

presence of a reasonable video signal, one that

we can lock onto horizontally or both

horizontally & vertically. If VPRES_VERT_EN =

0 then VPRES is dependant upon the location of

the last 32 HSYNC pulses relative to their

expected location. If VPRES_VERT_EN = 1

then VPRES is dependant upon both the

location of the last 16 VSYNC pulses and the

last 32 HSYNC pulses relative to their expected

locations.

[20:20] RO 1‘b 0 AGC_LOCK VGA lock status

[19:19] RO 1‘b 0 CSC_LOCK Color Subcarrier lock status

[18:18] RO 1‘b 0 VLOCK Vertical lock status

[17:17] RO 1‘b 0 SRC_LOCK Sample Rate Converter lock Status

[16:16] RO 1‘b 0 HLOCK Horizontal lock status

[15:15] RO 1‘b 0 VSYNC_N Vertical sync, active low

[14:14] RO 1‘b 0 SRC_FIFO_UFLOW Sample Rate Converter FIFO Underflow

[13:13] RO 1‘b 0 SRC_FIFO_OFLOW Sample Rate Converter FIFO Overflow

[12:12] RO 1‘b 0 FIELD Field status (even/odd)

[11:8] RO 4‘b 1 AFD_FMT_STAT Current detected Format

[7:7] RO 1‘b 0 MV_TYPE2_PAIR Macrovision Type 2 pair detected

[6:6] RO 1‘b 0 MV_T3CS A 1 indicates the presence of type 3 of the color

stripe process. A one here always triggers 1 in

the MV_CS bit.

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3.20.1.4 Interrupt Status and Mask

[5:5] RO 1‘b 0 MV_CS Macrovision Color Striping Detected

[4:4] RO 1‘b 0 MV_PSP Macrovision Pseudo Sync Pulses detected

[3:2] RO 2‘b 0 Reserved

[1:0] RO 2‘b 0 MV_CDAT Macrovision Copy Control Bits as described in

the Macrovision spec. This an encoding of the

same information that is contained in MV_CS,

MV_T3CS, and MV_PSP.

Bits Type Default Name Description

[31:31] RO 1‘b 1 Reserved

[30:30] RW 1‘b 1 WSS_DAT_AVAIL_M

When set, WSS_DAT_AVAIL_STAT is masked

from generating an interrupt.

[29:29] RW 1‘b 1 GS2_DAT_AVAIL_MS

When set, GS2_DAT_AVAIL_STAT is masked

from generating an interrupt.

[28:28] RW 1‘b 1 GS1_DAT_AVAIL_MS

When set, GS1_DAT_AVAIL_STAT is masked

from generating an interrupt.

[27:27] RW 1‘b 1 CC_DAT_AVAIL_MS

When set, CC_DAT_AVAIL_STAT is masked

from generating an interrupt.

[26:26] RW 1‘b 1 VPRES_CHANGE_M

When set, VPRES_CHANGE_STAT is masked

from generating an interrupt.

[25:25] RW 1‘b 1 MV_CHANGE_MSK When set, MV_CHANGE_STAT is masked from

generating an interrupt.

[24:24] RW 1‘b 1 END_VBI_EVEN_MS

When set, END_VBI_EVEN_STAT is masked

from generating an interrupt.

[23:23] RW 1‘b 1 END_VBI_ODD_MSK When set, END_VBI_ODD_STAT is masked

from generating an interrupt.

[22:22] RW 1‘b 1 FMT_CHANGE_MSK When set, FMT_CHANGE_STAT is masked

from generating an interrupt.

[21:21] RW 1‘b 1 VSYNC_TRAIL_MSK When set, VSYNC_TRAIL_STAT is masked

from generating an interrupt.

[20:20] RW 1‘b 1 HLOCK_CHANGE_M

When set, HLOCK_CHANGE_STAT is masked

from generating an interrupt.

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Registers CX23885 Data Sheet

[19:19] RW 1‘b 1 VLOCK_CHANGE_M

When set, VLOCK_CHANGE_STAT is masked

from generating an interrupt.

[18:18] RW 1‘b 1 CSC_LOCK_CHANGE

_MSK

When set, CSC_LOCK_CHANGE_STAT is

masked from generating an interrupt.

[17:17] RW 1‘b 1 SRC_FIFO_UFLOW_M

When set, SRC_FIFO_UFLOW_STAT is

masked from generating an interrupt.

[16:16] RW 1‘b 1 SRC_FIFO_OFLOW_M

When set, SRC_FIFO_OFLOW_STAT is

masked from generating an interrupt.

[15:15] RO 1‘b 0 Reserved

[14:14] RO 1‘b 0 WSS_DAT_AVAIL_S

TAT

VBI FIFO for Wide-Screen-Signaling has data

(not empty)

[13:13] RO 1‘b 0 GS2_DAT_AVAIL_ST

VBI FIFO for Gemstar 2X has data (not empty)

[12:12] RO 1‘b 0 GS1_DAT_AVAIL_ST

VBI FIFO for Gemstar 1X has data (not empty)

[11:11] RO 1‘b 0 CC_DAT_AVAIL_STA

VBI FIFO for Closed Caption has data (not

empty)

[10:10] RO 1‘b 0 VPRES_CHANGE_S

TAT

A change in the VPRES (video present) status

bit sets this bit.

[9:9] RO 1‘b 0 MV_CHANGE_STAT A change in the MV_CDAT field sets this bit.

[8:8] RO 1‘b 0 END_VBI_EVEN_ST

The end of the VBI region of an even field sets

this bit.

[7:7] RO 1‘b 0 END_VBI_ODD_STA

The end of the VBI region of an odd field sets

this bit.

[6:6] RO 1‘b 0 FMT_CHANGE_STA

A change in the detected video format sets this

bit.

[5:5] RO 1‘b 0 VSYNC_TRAIL_STAT The falling edge of the detected VSYNC sets

this bit.

[4:4] RO 1‘b 0 HLOCK_CHANGE_S

TAT

A change in the horizontal lock status sets this

bit.

[3:3] RO 1‘b 0 VLOCK_CHANGE_S

TAT

A change in the vertical lock status sets this bit.

[2:2] RO 1‘b 0 CSC_LOCK_CHANGE_

STAT

A change in the Color Subcarrier Lock status

sets this bit.

[1:1] RO 1‘b 0 SRC_FIFO_UFLOW_S

TAT

The detection of a SRC FIFO Underflow sets

this bit.

[0:0] RO 1‘b 0 SRC_FIFO_OFLOW_S

TAT

The detection of a SRC FIFO Overflow sets this

bit.

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CX23885 Data Sheet Registers

3.20.1.5 Luma Data Path Control

Bits Type Default Name Description

[31:24] RO 8‘b 0 Reserved

[23:22] RW 2‘b 0 LUMA_CORE_SEL Luma coring threshold select. This value

determines the cutoff threshold for the luma

coring logic.

2’b00 = no coring

2’b01 = coring threshold set to +/- 16

2’b10 = coring threshold set to +/- 32

2’b11 = coring threshold set to +/- 64As a result,

any pixel value between the selected threshold

limits will result in 0.

[21:20] RW 2‘b 0 RANGE Selects the allowed luma output range. This

allows the user to select between three possible

output ranges.

2’b00 = range: 64 – 1016 Nominal 656 range

with excursions allowed up to 1016.

2’b01 = range: 4 – 1016 Nominal 656 range with

excursions allowed up to 1016 and down to 4.

2’b1x = range: 0 – 1023 Full-range.

[19:19] RO 1‘b 0 Reserved

[18:18] RW 1‘b 0 PEAK_EN Peaking enable

[17:16] RW 2‘b 0 PEAK_SEL Select for peaking filter response (reg). This

value selects from the four available peaking

filter responses.

2’b00 = +2.0 dB response @ center freq

2’b01 = +3.5 dB response @ center freq

2’b10 = +5.0 dB response @ center freq

2’b11 = +6.0 dB response @ center freq

[15:8] RW 8‘h 80 CNTRST Contrast multiply value. This value is a 1.7

number that is multiplied by the luma level to

produce an adjusted luma signal. The resulting

range of the contrast multiplication factor is 0 to

1.996.

[7:0] RW 8‘b 0 BRITE Brightness offset. This value is effectively an

offset that is added to the luma signal to

produce a brighter output.

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Registers CX23885 Data Sheet

3.20.1.6 Horizontal Scaling Control

3.20.1.7 Vertical Scaling Control

Bits Type Default Name Description

[31:26] RO 6‘b 0 Reserved

[25:24] RW 2‘b 0 HFILT Low pass filter select. This is used in the

LUMA_LPF block to determine which of the

three filters or the auto mode should be used.

2’b00 Auto Mode

2’b01 CIF

2’b10 QCIF

2’b11 ICON

[23:0] RW 24‘b 0 HSCALE Horizontal Scaling Ratio (HSCALE = (scaling

ratio–1)*220).

Bits Type Default Name Description

[31:25] RO 6‘b 0 Reserved

[24:24] RW 1‘b 0 LINE_AVG_DIS PAL line average disable.

0 = PAL line averaging is enabled. Adjacent

lines are averaged together to produce output

lines. (default)

1 = PAL line averaging is disabled.

[23:20] RO 4‘b 0 Reserved

[19:19] RW 1‘b 1 VS_INTRLACE VS Interlace Format. The initial output phase

must alternate if the scaled images are to be

interlaced.

0 = Non-interlace VS

1 = Interlace VS

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3.20.1.8 Chroma Data Path Control

[18:16] RW 3‘b 0 VFILT These bits control the number of taps in the

Vertical Scaling Filter. The number of taps must

be chosen in conjunction with the horizontal

scale factor to ensure the needed data does not

overflow the internal FIFO.

vfilt[1:0]

Interpolation

00 = 2-tap interpolation.(*)

01 = 3-tap interpolation.(**)

10 = 4-tap interpolation.(***)

11 = 5-tap interpolation.(***)

vfilt[2] - Reserved

(*) Available at all resolutions

(**) Available if scaling to less than 385

horizontal active pixels

(***) Available if scaling to less than 193

horizontal active pixels

[15:13] RO 3‘b 0 Reserved

[12:0] RW 13‘b 0 VSCALE Vertical Scaling Ratio (VSF = 216 – (scaling ratio

- 1)*29)

Bits Type Default Name Description

[31:30] RO 2‘b 0 Reserved

[29:29] RW 1‘b 1 C_LPF_EN Enables chroma low pass filter in chroma

processing block

[28:26] RW 3‘b 0 CHR_DELAY Chroma Delay. A signed number representing

the number of pixels the chroma is delayed

relative to the luma. A value of 0 matches the

luma to chroma. Valid values are:

110 = –2

111 = –1

000 = 0

001 = +1

010 = +2

others = 0

[25:24] RW 2‘b 0 C_CORE_SEL Chroma coring select.

00 = no coring

01 = +/– 7

10 = +/– 15

11 = +/– 31

[23:16] RW 8‘b 0 HUE Hue adjust.

[15:8] RW 8‘h 80 VSAT Saturation adjust for V chroma.

[7:0] RW 8‘h 80 USAT Saturation adjust for U chroma.

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Registers CX23885 Data Sheet

3.20.1.9 VBI Line Data Type Control 1

Bits Type Default Name Description

[31:24] RW 8‘b 0 VBI_MD_LINE4 4th VBI line data type

[23:16] RW 8‘b 0 VBI_MD_LINE3 3rd VBI line data type

[15:8] RW 8‘b 0 VBI_MD_LINE2 2nd VBI line data type

[7:0] RW 8‘b 0 VBI_MD_LINE1 1st VBI line data type

Lines are numbered relative to first line after

VSYNC, which is line 10 for 525-line standards

and line 6 for 625-line standards. The

VBI_VOFFSET field is added to these lines to

determine the 1st VBI line. (VBI_VOFFSET is by

default 0 for 525-line standards, and 1 for 625-

line standards.)The mode consists of 4 bits as

listed below. The most significant nibble is used

for the odd field and the least significant nibble

is used for the even field.

525 line modes:

0000 = no VBI data slicing

0001 = WST525-B

0010 = WST525-C (NABTS)

0011 = WST525-D (Moji)

0100 = WSS525

0101 = VITC525

0110 = CC525

0111 = Gemstar 1x

1000 = Gemstar 2x

1010 = Custom VBI1

1011 = Custom VBI2

1100 = Custom VBI3

625 line modes:

0000 = no VBI data slicing

0001 = WST625-B

0010 = WST625-A

0011 = RESERVED

0100 = WSS625

0101 = VITC625

0110 = CC625

1000 = RESERVED

1001 = VPS

1010 = Custom VBI1

1011 = Custom VBI2

1100 = Custom VBI3

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CX23885 Data Sheet Registers

3.20.1.10VBI Line Data Type Control 2

3.20.1.11VBI Line Data Type Control 3

3.20.1.12VBI Line Data Type Control 4

Bits Type Default Name Description

[31:24] RW 8‘b 0 VBI_MD_LINE8 8th VBI line data type

[23:16] RW 8‘b 0 VBI_MD_LINE7 7th VBI line data type

[15:8] RW 8‘b 0 VBI_MD_LINE6 6th VBI line data type

[7:0] RW 8‘b 0 VBI_MD_LINE5 5th VBI line data type

Bits Type Default Name Description

[31:24] RW 8‘b 0 VBI_MD_LINE12 12th VBI line data type

[23:16] RW 8‘b 0 VBI_MD_LINE11 11th VBI line data type

[15:8] RW 8‘b 0 VBI_MD_LINE10 10th VBI line data type

[7:0] RW 8‘b 0 VBI_MD_LINE9 9th VBI line data type

Bits Type Default Name Description

[31:24] RW 8‘b 0 VBI_MD_LINE16 16th VBI line data type

[23:16] RW 8‘b 0 VBI_MD_LINE15 15th VBI line data type

[15:8] RW 8‘b 0 VBI_MD_LINE14 14th VBI line data type

[7:0] RW 8‘b 0 VBI_MD_LINE13 13th VBI line data type

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Registers CX23885 Data Sheet

3.20.1.13VBI Line Data Type Control 5

3.20.1.14VBI Frame Code Config

Bits Type Default Name Description

[31:8] RO 24‘b 0 Reserved

[7:0] RW 8‘b 0 VBI_MD_LINE17 17th VBI line data type

Bits Type Default Name Description

[31:24] RW 8‘b 0 FC_ALT2 Alternate frame code used when VBIMODE

matches FC_ALT2_TYPE.

[23:16] RW 8‘b 0 FC_ALT1 Alternate frame code used when VBIMODE

matches FC_ALT1_TYPE.

[15:12] RW 4‘b 0 FC_ALT2_TYPE When this field matches the VBIMODE setting

for a particular line, the FC_ALT2 frame code is

used instead of the default frame code

associated with a given auto-config mode. This

allows using an alternate frame code for any

given auto-config mode.

[11:8] RW 4‘b 0 FC_ALT1_TYPE When this field matches the VBIMODE setting

for a particular line, the FC_ALT1 frame code is

used instead of the default frame code

associated with a given auto-config mode. This

allows using an alternate frame code for any

given auto-config mode.

[7:1] RO 7‘b 0 Reserved

[0:0] RW 1‘b 0 FC_SEARCH_MODE Frame Code Search Mode. Allows dynamic

search for frame code:

0 = Frame code match is declared only if frame

code (start code, data run-in) is found at

expected bit position.

1 = Frame code match is declared upon

discovering the first bit sequence that matches

the expected pattern.The second option

(FC_SEARCH_MODE = 1) only works for

common frame code lengths of 3, 8, 12, 16, and

24.

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CX23885 Data Sheet Registers

3.20.1.15VBI Miscellaneous Config1

Bits Type Default Name Description

[31:20] RW 12‘h FFF TTX_PKTADRU Teletext packet address upper limit for packet

filtering purposes, enabled when

VBIx_TTX_MODE = 1.

[19:8] RW 12‘b 0 TTX_PKTADRL Teletext packet address lower limit for packet

filtering purposes, enabled when

VBIx_TTX_MODE = 1.

[7:6] RO 2‘b 0 Reserved

[5:5] RW 1‘b 0 MOJI_PACK_DIS Moji Packing Disable.

0 = WST525, System D formats cause the

decoder to extract the first 6 bits for the first byte

packet. The subsequent bit stream is packed

into standard byte packets.

1 = The WST525, System D bit stream is

packed into byte packets in a normal fashion.

[4:4] RW 1‘b 0 VPS_DEC_DIS VPS bi-phase decode disable.

0 = VPS formats are decoded based on a two-

bit bi-phase pattern

1 = Raw slice bits are transmitted.

[3:2] RW 2‘b 1 CRI_MARG_SCALE Clock run-in margin scale. Used to loosen or

tighten lock criteria for clock run-in.

0 = Divide default timing margin by 2.

1 = Use default timing margin.

2 = Multiply default timing margin by 2.

3 = Multiply default timing margin by 4.

[31:20] RW 12‘h FFF TTX_PKTADRU Teletext packet address upper limit for packet

filtering purposes, enabled when

VBIx_TTX_MODE = 1.

[1:1] RW 1‘b 1 EDGE_RESYNC_EN Enable dynamic timing resynchronization based

on edge detection.

0 = Sample point timing is determined by initial

edge synchronization during clock run-in

1 = Sample point timing is re-synchronized upon

detecting any edge during data pattern.

[0:0] RW 1‘b 0 ADAPT_SLICE_DIS Disable adaptive slice level.

0 = Slice level comes from averaging points in

clock run-in

1 = Slice level is set to pre-determined level

based on mode.

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Registers CX23885 Data Sheet

3.20.1.16VBI Miscellaneous Config2

Bits Type Default Name Description

[31:28] RO 4‘b 0 Reserved

[27:24] RW ‘b0 HAMMING_TYPE When this field matches the VBIMODE setting

for a particular line, hamming comparison is

enabled for that type. Leave this field at 4’h0 to

disable the feature. When enabled, the least-

significant four bits of the framing code are used

for hamming comparison.

[23:20] RO 4‘b 0 Reserved

[19:19] RW 1b 0 WSS_FIFO_RST When = 1, reset WSS payload FIFO.

[18:18] RW 1‘b 0 GS2_FIFO_RST When = 1, reset Gemstar2x payload FIFO.

[17:17] RW 1‘b 0 GS1_FIFO_RST When = 1, reset Gemstar1x payload FIFO.

[16:16] RW 1‘b 0 CC_FIFO_RST When = 1, reset Closed Caption/XDS payload

FIFO.

[15:12] RO 4‘b 0 Reserved

[11:8] RW 4‘h C VBI3_SDID SDID to use when VBI_CUST3 data type is

selected.

[7:4] RW 4‘h B VBI2_SDID SDID to use when VBI_CUST3 data type is

selected.

[3:0] RW 4‘h A VBI1_SDID SDID to use when VBI_CUST1 data type is

selected.

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CX23885 Data Sheet Registers

3.20.1.17VBI Payload 1

3.20.1.18VBI Payload 2

Bits Type Default Name Description

[31:24] RO 8‘b0 GS1_FIFO_DAT Gemstar1x payload data.Data pointer advanced

after reading this byte.

[23:16] RO 8‘b0 GS1_STAT See description of CC_STAT byte,

[15:8] RO 8‘b0 CC_FIFO_DAT CC/XDS payload data.Data pointer advanced

after reading this byte.

[7:0] RO 8‘b0 CC_STAT Generic payload status format:

Bit 7 – PARERR

0 – No parity error detected

1 – Parity error detected

Bit 6 - FF

0 – FIFO not full

1 – FIFO full

Bit 5 – DA

0 – FIFO is empty

1 – One or more bytes available for read

Bit 4 - CC/XDS

0 – CC byte (odd field)

1 – XDS byte (even field)

Bits 3-2 – RESERVED

Bits 1-0 - BYTE_NUM

BYTE_NUM describes byte number within a

field. For payloads larger than four, the number

will wrap.

00 – byte 1

01 – byte 2

02 – byte 3

03 – byte 4

Bits Type Default Name Description

[31:24] RO 8‘b0 WSS_FIFO_DAT Wide Screen Signalling payload data.Data

pointer advanced after reading this byte.

[23:16] RO 8‘b0 WSS_STAT See description of CC_STAT byte. (PARERR

will be held at 0.)

[15:8] RO 8‘b0 GS2_FIFO_DAT Gemstar2x payload data.Data pointer advanced

after reading this byte.

[7:0] RO 8‘b0 GS2_STAT See description of CC_STAT byte.

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Registers CX23885 Data Sheet

3.20.1.19VBI Custom Mode 1, Config1

3.20.1.20VBI Custom Mode 1, Config2

Bits Type Default Name Description

[31:31] RO 1‘b0 Reserved

[30:24] RW 7‘h2c VBI1_CRIWIN Specifies the time window during which edge

detection (positive and negative) is inhibited.

This window is based on the clock run-in

frequency. Avoids spurious edges from being

detected.VBI1_CRIWIN = 4 * PIXEL_RATE *

CLOCK_RUNIN_HALF_PERIOD * war; war =

window ratio, portion of cycle to inhibit detection;

[23:20] RW 4‘b1 VBI1_SLICE_DIST Slice level sample distance. Controls how often

samples are taken for the adaptive slice level

routine. Distance is defined in terms of 1/8 of a

bit period time, where the bit period is defined by

bit INC. The parameter describes the number of

points where samples are NOT taken.

Therefore, to take one sample every four points,

put three in this field.

[19:8] RW 12‘h99 VBI1_BITINC Value used to increment 14-bit counter

measures the bit sample rate. A bit is sampled

when the 14-bit counter rolls over. The bit

sample rate defines the rate at which the

waveform is sampled during the payload. For bi-

phase encoding modes, this sampling rate

should be set to six times the effective bit rate.

VBI1_BITINC = 214 / ((4 * PIXEL_RATE) / bit

SAMPLE_RATE)

[7:0] RW 8‘h70 VBI1_HDELAY Delay from internal HRESET signal to start of

Clock Run-in in number of pixel clock

cycles.VBI1_HDELAY = (HDELAY (us)*

PIXEL_RATE (MHz)) – 13.

Bits Type Default Name Description

[31:29] RO 3‘b0 Reserved

[28:24] RW 5‘h3 VBI1_FC_LENGTH Number of start bits (or frame code bits)

[23:0] RW 24‘b1 VBI1_FRAME_CODE Start code bit pattern in transmission order

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3.20.1.21VBI Custom Mode 1, Config3

Bits Type Default Name Description

[31:31] RW 1‘b0 VBI1_HAM_EN Enable hamming comparison for framing

comparison when this bit is set. When set,

VBI1_FRAME_CODE[3:0] are used for

hamming comparison.

[30:28] RW 3‘h2 VBI1_FIFO_MODE Determines which payload FIFO is loaded.

000 = Don’t load to payload FIFO

001 = Load to Gemstar 1x FIFO

010 = Load to CC FIFO011 = Load to WSS

FIFO

100 = Load to Gemstar 2x FIFO

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Registers CX23885 Data Sheet

[27:24] RW 4‘h6 VBI1_FORMAT_TYP

Specifies basic VBI decoding model. Find the

standard format which most closely matches the

intended format, and program this field to match

the type field encoding specified in the

VBI_MD_LINEX registers. Special operating

modes are enabled based on the format type as

described below:

Format type

# of lines

Feature

0000

n.a.

No special features currently defined

0101, 1010, 0011

n.a.

Teletext – enable packet address filter

0011

525

Enable Moji style byte alignment – first six bits

go into separate byte packet

0100

525

Wide-screen-signaling – assume signal includes

single sync pulse, and no frame code.

0100

625

Wide-screen-signaling – implement WSS625-

style bi-phase decoding

0101

n.a

VITC – assume sync pulses every 8 bits

0110, 0111, 1000

n.a.

Closed caption – assume 50 IRE signal

amplitude

1001

n.a.

VPS - implement VPS-style bi-phase decoding

[23:16] RW 8‘h8 VBI1_PAYLD_LENGT

Number of data bits to be captured, divided by

two. If N is the number of bits in the payload,

program this register with N/2.

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CX23885 Data Sheet Registers

3.20.1.22VBI Custom Mode 2, Config1

[15:12] RW 4‘hC VBI1_CRI_LENGTH Number of clock run-in edges expected in the

CRI period. This does not include the edge that

transitions into the frame or start code, and this

is an N-1 parameter. For example, in a teletext

waveform with 16 bit periods and 16 edges,

program 4'hF in this register. For closed caption

with 6.5 bit periods, but 13 edges, program

4'hC.This number is both used to specify the

point at which to begin looking for the frame

code, and to measure the elapsed time to

determine frequency lock. (See

VBI1_CRI_TIME and VBI1_CRI_MARGIN.)

[11:8] RW 4‘h4 VBI1_CRI_MARGIN This field specifies the margin around

vbi1_cri_time in which the measured time of the

Clock Run-in period can fall. See vbi1_cri_time.

This is in units of eights of the bit period defined

by vbi1_bitinc.

[7:0] RW 8‘hD VBI1_CRI_TIME Expected time period of Clock Run-in period in

terms of halves of the bit period specified in

vbi1_bitinc. The algorithm detects the number of

edges specified in vbi1_cri_length and

compares the elapsed time with this parameter.

If the result is within vbi1_cri_margin of this

parameter, then the waveform is decoded.

Bits Type Default Name Description

[31:31] RO 1‘b0 Reserved

[30:24] RW 7‘h54 VBI2_CRIWIN See descriptions for VBI_CUST1_CFG

equivalent.

[23:20] RW 4‘b0 VBI2_SLICE_DIST See descriptions for VBI_CUST1_CFG

equivalent.

[19:8] RW 12‘h88 VBI2_BITINC See descriptions for VBI_CUST1_CFG

equivalent.

[7:0] RW 8‘h77 VBI2_HDELAY See descriptions for VBI_CUST1_CFG

equivalent.

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Registers CX23885 Data Sheet

3.20.1.23VBI Custom Mode 2, Config2

3.20.1.24VBI Custom Mode 2, Config3

Bits Type Default Name Description

[31:29] RO 3‘b0 Reserved

[28:24] RW 5‘b0 VBI2_FC_LENGTH See descriptions for VBI_CUST1_CFG

equivalent.

[23:0] RW 24‘b0 VBI2_FRAME_CODE See descriptions for VBI_CUST1_CFG

equivalent.

Bits Type Default Name Description

[31:31] RW 1‘b0 VBI2_HAM_EN See descriptions for VBI_CUST1_CFG

equivalent.

[30:28] RW 3‘h3 VBI2_FIFO_MODE See descriptions for VBI_CUST1_CFG

equivalent.

[27:24] RW 4‘h4 VBI2_FORMAT_TYP

See descriptions for VBI_CUST1_CFG

equivalent.

[23:16] RW 8‘hA VBI2_PAYLD_LENGT

See descriptions for VBI_CUST1_CFG

equivalent.

[15:12] RW 4‘h1 VBI2_CRI_LENGTH See descriptions for VBI_CUST1_CFG

equivalent.

[11:8] RW 4‘h4 VBI2_CRI_MARGIN See descriptions for VBI_CUST1_CFG

equivalent.

[7:0] RW 8‘h2 VBI2_CRI_TIME See descriptions for VBI_CUST1_CFG

equivalent.

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CX23885 Data Sheet Registers

3.20.1.25VBI Custom Mode 3, Config1

3.20.1.26VBI Custom Mode 3, Config2

Bits Type Default Name Description

[31:31] RO 1‘b0 Reserved

[30:24] RW 7hb6 VBI3_CRIWIN See descriptions for VBI_CUST1_CFG

equivalent.

[23:20] RW 4‘h3 VBI3_SLICE_DIST See descriptions for VBI_CUST1_CFG

equivalent.

[19:8] RW 12‘h6CA VBI3_BITINC See descriptions for VBI_CUST1_CFG

equivalent.

[7:0] RW 8‘h6E VBI3_HDELAY See descriptions for VBI_CUST1_CFG

equivalent.

Bits Type Default Name Description

[31:29] RO 3‘b0 Reserved

[28:24] RW 5‘h8 VBI3_FC_LENGTH See descriptions for VBI_CUST1_CFG

equivalent.

[23:0] RW 24‘hE7 VBI3_FRAME_CODE See descriptions for VBI_CUST1_CFG

equivalent.

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Registers CX23885 Data Sheet

3.20.1.27VBI Custom Mode 3, Config3

3.20.1.28Horizontal Timing Control

Bits Type Default Name Description

[31:31] RW 1‘b0 VBI3_HAM_EN See descriptions for VBI_CUST1_CFG

equivalent.

[30:28] RW 3‘b0 VBI3_FIFO_MODE See descriptions for VBI_CUST1_CFG

equivalent.

[27:24] RW 4‘h2 VBI3_FORMAT_TYP

See descriptions for VBI_CUST1_CFG

equivalent.

[23:16] RW 8‘h84 VBI3_PAYLD_LENGT

See descriptions for VBI_CUST1_CFG

equivalent.

[15:12] RW 4hbF VBI3_CRI_LENGTH See descriptions for VBI_CUST1_CFG

equivalent.

[11:8] RW 4‘h6 VBI3_CRI_MARGIN See descriptions for VBI_CUST1_CFG

equivalent.

[7:0] RW 8‘h20 VBI3_CRI_TIME See descriptions for VBI_CUST1_CFG

equivalent.

Bits Type Default Name Description

[31:24] RW 8‘h5B BGDEL_CNT Burst gate delay. The last four clocks of this

period are used to generate the window during

which the color burst is sampled. It is the delay,

in pixel clocks, between the leading edge of

HSYNC and the center of the color burst, plus

two. The additional two clocks will center the

four-clock burst accumulate window in the

center of the burst.

[23:22] RO 2‘b0 Reserved

[21:12] RW 10‘h2D0 HACTIVE_CNT Horizontal active region duration. It is the

number of pixels in the active region of the line.

[11:10] RO 2‘b0 Reserved

[9:0] RW 10‘h7A HBLANK_CNT Horizontal blanking delay. It is number of pixels

between the leading edge of HSYNC and the

start of active video

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3.20.1.29Vertical Timing Control

3.20.1.30Sample Rate Convert and Comb Filter

Bits Type Default Name Description

[31:24] RW 8‘h18 V656BLANK_CNT Vertical blanking for 656 output. Determines the

timing of the internal v656blank signal. It allows

us to control the v-bit transition in the 656 output

independently of the VBLANK signal seen by

the rest of the chip. The counter starts 12 half-

lines before the expected trailing edge of

VRESET. Thus it must = VBLANK_CNT + ‘b04

to have VBANK and v656blank line up.

[23:22] RO 2‘b0 Reserved

[21:12] RW 10‘h1E7 VACTIVE_CNT Vertical active region duration. It is the number

of half lines in the vertical active region. This

set.

[11:10] RO 2‘b0 Reserved

[9:0] RW 10h‘14 VBLANK_CNT Vertical blanking interval. Determines the start

of the internal VBLANK signal. It is the number

of half lines between the trailing edge of

VRESET and the start of active video.

Bits Type Default Name Description

[31:31] RO 1‘b1 Reserved

[30:30] RW 1‘b1 CCOMB_3LN_EN Enables the adaptation algorithm to choose the

3 line chroma comb.

[29:29] RW 1‘b1 CCOMB_2LN_EN Enables the adaptation algorithm to choose the

2-line chroma comb.

[28:27] RW 2‘b0 Reserved

[26:26] RW 1‘b1 LCOMB_3LN_EN Enables the adaptation algorithm to choose the

3 line luma comb.

[25:25] RW 1‘b1 LCOMB_2LN_EN Enables the adaptation algorithm to choose the

2-line luma comb.

[24:24] RW 1‘b0 Reserved

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Registers CX23885 Data Sheet

[23:22] RW 2‘b1 LUMA_LPF_SEL Selects Luma low-pass filter bandwidth:0 low

(~600 kHz),1 medium (~1 MHz)2 high

(~1.5MHz)3 reserved

[21:20] RW 2‘b1 UV_LPF_SEL Selects U/V low-pass filter bandwidth:0 low

(~600 kHz),1 medium (~1 MHz)2 high

(~1.5MHz)3 reserved

[19:10] RW 10‘h8 Reserved

[9:0] RW 10‘h21F SRC_DECIM_RATIO Default phase increment (N = 256 * Fin/Fpix).Fin

= ADC sampling frequency. Fpix = pixel rate

(should be consistent with SQUARE_PIXEL

setting.)

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3.20.1.31Chroma Config and VBI Offset

3.20.1.32Field Counter

CHROMA_VBIOFF_CFG

Address: 0x47C

Bits Type Default Name Description

[31:29] RO 3‘b0 Reserved

[28:24] RW 5‘b0 VBI_VOFFSET The offset in lines from VRESET to enable the

VBI Slicer to capture data.

[23:20] RO 4‘b0 Reserved

[19:0] RW 20‘h87C1F SC_STEP Chroma subcarrier DTO step size,

Fsc/Fpix* 221

where Fsc = subcarrier frequency, and Fpix =

pixel rate. However, the pixel rate used in this

calculation should be based on the exact pixel

rate that is defined in the SRC_DECIM_RATIO

field of the SRC_COMB_CFG register above:

(Fpix = 256/SRC_DECIM_RATIO * Fin).

[Note: this does not imply that the effective pixel

rate is only as accurate as this equation. This

equation just determines the initial pixel rate,

which will then be fine-tuned to achieve the

exact ratio. However, the initial subcarrier

frequency must be based on the initial pixel

rate.]

Bits Type Default Name Description

[31:10] RO 22‘b0 Reserved

[9:0] RO 10‘b0 FIELD_COUNT Counts fields continuously, and wraps around

when it reaches the max count of ‘b3FF. It is

reset to zero by writing to either byte.

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Registers CX23885 Data Sheet

3.20.1.33Miscellaneous Timing Control

Bits Type Default Name Description

[31:30] RW 2‘b1 DEBOUNCE_COUNT Number of consecutive fields of detected video

format stability required before switching video

formats. This period is provided to help prevent

us from erroneously switching detected formats

due to noise or other very short term errors.

2’b00: 2 consecutive fields of stability

2’b01: 4 consecutive fields of stability

2’b10: 8 consecutive fields of stability

2’b11: 16 consecutive fields of stability

[29:28] RW 2‘b0 VT_LINE_CNT_HYS

Number of consecutive fields with approximately

525/2 or 625/2 lines before changing the

detected line count, VT_LINE_CNT, input to the

auto format detect state machine.

2’b00: 2 consecutive fields with approximately

525/2 or 625/2 lines

2’b01: 4 consecutive fields with approximately

525/2 or 625/2 lines

2’b10: 8 consecutive fields with approximately

525/2 or 625/2 lines

2’b11: 16 consecutive fields with approximately

525/2 or 625/2 lines

[27:16] RO 12‘b0 Reserved

[15:15] RW 1‘b0 VPRES_VERT_EN Enable for the vertical portion of the video

present logic. When enabled, the VPRES logic

reflects when the video is both locked vertically

and horizontally. Otherwise the VPRES reflects

the horizontal locking only.

[14:12] RO ‘b0 Reserved

[11:11] RW 1‘b0 HR32 This bit controls the width of the HRESET

output.A logic 1 indicates a 32 clock wide

HRESET while a logic 0 indicates that HRESET

is 64 clocks wide.

[10:10] RW 1‘b0 TDALGN Aligns start of decimation with even or odd field.

0 – start on odd field

1 – start on even field

[9:9] RW 1‘b0 TDFIELD This signal is an indication of whether the

temporal decimation is done on a frame (0) or

field (1) basis.

[8:6] RO 3‘b0 Reserved

[5:0] RW 6‘b0 TEMPDEC This signal is the control for the temporal

decimation logic. This value is the number of

fields or frames to discard out of 50 (625/50) or

60 (525/60). This value should not exceed 60 for

a 60 Hz system or 50 for a

50 Hz system.

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CX23885 Data Sheet Registers

3.20.1.34DFE Control 1

3.20.1.35DFE Control 2

Bits Type Default Name Description

[31:31] RW 1‘b1 CLAMP_AUTO_EN Analog clamp setting is tied to VGA gain

[30:30] RW 1‘b1 AGC_AUTO_EN AGC enable

0 = freeze/manual

1 = auto mode

[29:29] RW 1‘b1 VGA_CRUSH_EN ADC overflow protection enable (decreases

VGA_SYNC if ADC overflows)

[28:28] RW 1‘b1 VGA_AUTO_EN VGA enable (0 = freeze/manual, 1 = auto mode)

[27:27] RW 1‘b1 VBI_GATE_EN Enable gating of back porch updates during

vertical blanking interval

[26:24] RW 3‘b0 CLAMP_LEVEL Analog clamp setting (if CLAMP_AUTO_EN = 0)

[23:20] RO 4'h 2 Reserved

[19:8] RW 12‘h100 AGC_GAIN R/W register for AGC digital gain (can be written

when AGC_AUTO_EN = 0)

[7:6] RO 2‘b0 Reserved

[5:0] RW 6‘h20 VGA_GAIN R/W register for VGA gain (can be written when

VGA_AUTO_EN = 0)

Bits Type Default Name Description

[31:24] RO 8‘b0 Reserved

[23:16] RW 8‘h10 VGA_ACQUIRE_RA

NGE

Maximum error of sync height before declaring

VGA lock

[15:8] RW 8‘h40 VGA_TRACK_RANG

Minimum error of sync height before losing VGA

lock

[7:0] RW 8‘hDC VGA_SYNC Sync pulse height out of ADC (VGA_SYNC =

2N)

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Registers CX23885 Data Sheet

3.20.1.36DFE Control 3

3.20.1.37PLL Loop Filter Control

Bits Type Default Name Description

[31:24] RW 8‘hCD BP_PERCENT Percent of line expected to be above or equal to

backporch threshold. Used in sync slicing

algorithm for initial sync location.

[23:16] RW 8‘h3F DFT_THRESHOLD Correlator threshold for SC detect (threshold =

256 * setting)

[15:12] RO 4‘b0 Reserved

[11:10] RW 2‘b0 SYNC_WIDTH_SEL Selects minimum sync width used to qualify

sync detection

2'b00 - 40 sample clocks

2'b01 - 32 sample clocks

2'b1X - Minimum sync width controlled by VCR

detect status. When a VCR is detected,

minimum sync width is 32, otherwise 40

[9:8] RW 2‘b2 BP_LOOP_GAIN Backporch level detect control loop gain = 2^n /

[7:6] RW 2‘b2 SYNC_LOOP_GAIN Sync level detect control loop gain = 2^n / 4

[5:4] RO 2‘b0 Reserved

[3:2] RW 2‘b2 AGC_LOOP_GAIN AGC control loop gain = 2^n / 1024

[1:0] RW 2‘b2 DCC_LOOP_GAIN Backporch clamp control loop gain = 2^n / 4

Bits Type Default Name Description

[31:24] RW 8‘h 16 PLL_KD PLL control loop direct gain = 1/2n

[23:16] RW 8‘h 1F PLL_KI PLL control loop indirect gain = 1/2(n+11)

[15:0] RW 16‘h 300 PLL_MAX_OFFSET Video PLL maximum adjustment offset =29 *

PLL_MAX_OFFSET

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CX23885 Data Sheet Registers

3.20.1.38Horizontal Timing Loop Control

Bits Type Default Name Description

[31:20] RO 12‘b 0 Reserved

[19:19] RW 1‘b 0 AUTO_LOCK_SPD Enables automatic loop filter speed control.

[18:18] RW 1‘b 0 MAN_FAST_LOCK Enables fast loop speed if AUTO_LOCK_SPD is

not set.

[17:17] RW 1‘b 0 HTL_15K_EN Enables the 15 kHz digital PLL line locking

algorithm.

[16:16] RW 1‘b 0 HTL_500K_EN Enables the 500 kHz LPF data to be used for

locking (CVBS only).

[15:8] RW 8‘h 20 HTL_KD Horizontal Tracking Loop direct gain = 1/2n

[7:0] RW 8‘h 40 HTL_KI Horizontal Tracking Loop indirect gain = 1/2n

Bits Type Default Name Description

[31:24] RW 8‘h20 COMB_PHASE_

LIMIT

Comb filter is enabled when the burst phase

difference between adjacent lines is measured

to be less than this limit. The phase difference is

measured by taking the burst phase of the

current line and subtracting it from the phase of

a vertically aligned burst sample points in the

previous lines, allowing for the expected phase

shift. Lack of alignment shows that there is too

much horizontal jitter to enable comb filter.

[23:16] RW 8‘h50 CCOMB_ERR_LIMIT Maximum comb error before falling back to

notch filter mode.

[15:8] RW 8‘b0 LUMA_THRESHOLD Minimum chroma amplitude before using luma

comb filter.

[7:0] RW 8‘h14 LCOMB_ERR_LIMIT Maximum comb error before falling back to

complimentary filter mode.

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Registers CX23885 Data Sheet

3.20.1.39White Crush Control

Bits Type Default Name Description

[31:23] RO 9‘b0 Reserved

[22:22] RW 1‘b0 WTW_EN Active-high enable for the white crush whiter-

than-white peak threshold.1’b0 = 100 IRE peak

threshold1’b1 = 110 IRE peak threshold

[21:21] RW 1‘b0 CRUSH_FREQ White Crush Adjust frequency. This bit is used

to determine whether to perform the white crush

adjustments on a field or frame basis(0=field

rate, 1=frame rate)

[20:20] RW 1‘b0 MAJ_SEL_EN Enables adaptive majority select logic

[19:18] RW 2‘h3 MAJ_SEL White crush majority comparison point select

bits. This value is the intensity threshold that the

white crush logic compares each pixel to in

order to determine if the majority of the image is

too dark.2’h0 ¾ maximum luma2’h1 ½

maximum luma2’h2 ¼ maximum luma2’h3

Automatic

[17:15] RO 3‘b0 Reserved

[14:9] RW 6‘b1 SYNC_TIP_REDUCE White crush decrement value. This value is the

step amount that the sync height can be

decreased by the white crush logic on any

single adjustment.

[8:6] RO 3‘b0 Reserved

[5:0] RW 6‘hF SYNC_TIP_INC Sync tip increment value. This value is the step

amount that the sync height can be increased

by the white crush logic on any single

adjustment.

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CX23885 Data Sheet Registers

3.20.1.40Soft Reset Control

Bits Type Default Name Description

[31:16] RO 16‘b0 Reserved

[15:15] RW 1‘b0 VD_SOFT_RST Video Decoder Soft Reset.Resets video

decoder core, pending mask bits for each

module.

[14:12] RO 3‘b0 REG_SOFT_RST Masks soft reset for Register module.

[11:11] RW 1‘b0 REG_RST_MSK Masks soft reset for Video Output Formatter

module.

[10:10] RW 1‘b0 VOF_RST_MSK Masks soft reset for Macrovision Detect module.

[9:9] RW 1‘b0 MVDET_RST_MSK Masks soft reset for VBI Slicer module.

[8:8] RW 1‘b0 VBI_RST_MSK Masks soft reset for Scaling module.

[7:7] RW 1‘b0 SCALE_RST_MSK Masks soft reset for Chroma Data Path module.

[6:6] RW 1‘b0 CHROMA_RST_MSK Masks soft reset for Register module.

[5:5] RW 1‘b0 LUMA_RST_MSK Masks soft reset for Luma Data Path module.

[4:4] RW 1‘b0 VTG_RST_MSK Masks soft reset for Video Timing Generator

module.

[3:3] RW 1‘b0 YCSEP_RST_MSK Masks soft reset for YC Separation module.

[2:2] RW 1‘b0 SRC_RST_MSK Masks soft reset for Sample Rate Converter

module.

[1:1] RW 1‘b0 DFE_RST_MSK Masks soft reset for Digital Front End module.

[0:0] RO 1‘b0 Reserved

Bits Type Default Name Description

[31:0] RO 326‘b0 Reserved

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Registers CX23885 Data Sheet

3.20.1.41Version ID

Bits Type Default Name Description

[31:8] RO 24‘b0 Reserved

[7:0] RO 8‘h4 REV_ID Revision ID. The initial value is set to 8’h01. This

refers to the revision of the video decoder core

only, and should not be confused with the chip-

level revision ID.

Bits Type Default Name Description

[31:0] RO ‘b0 Reserved

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CX23885 Data Sheet Registers

3.20.1.42VBI Passthrough Control

Bits Type Default Name Description

[31:22] RO 10‘b0 Reserved

[21:21] RW 1‘b0 VBI_PASS_MD Enable special passthrough mode processing of

VBI line according to the PASS_LINE_CTRL

field. These special pass through modes allow

an encoder to reproduce VBI data waveforms

and test signals by processing the output of the

video decoder:

0 = Y/C separation operates in normal adaptive

comb filter mode on all lines equally.

1 = First 20 lines following VSYNC (VRESET)

are processed according to special pass-

through modes described in

PASS_LINE_CTRL.

[20:20] RW 1‘b0 VBI_SETUP_DIS Disable the luma-decoding path from

subtracting the setup or pedestal during VBI

lines. This bit is a don’t-care for video formats

that do not contain a pedestal. This bit allows

the proper decoding of VBI data waveforms and

video test signals that contain levels below the

pedestal.

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Registers CX23885 Data Sheet

[19:0] RW 20‘b0 PASS_LINE_CTRL On a line-by-line basis, selects the method for

encoding the waveform in the VBI. Each line is

controlled by it’s own bit in the vector. This

control will extend into the beginning of the

active region to control out Closed Caption lines

are processed. The lines that are within the VBI

are processed as follows:

0 = Y/C Separation operates in chroma

notch mode – output of chroma bandpass filter

is sent to chroma path, and subtracted from the

luma path.

1 = Y/C Separation operates in Black & White

mode – all input bandwidth is sent to luma path,

none to chroma path.

Lines inside the active region are processed as

follows:

0 = Y/C Separation operates in normal

adaptive comb filter mode

1 = Y/C Separation operates in Black &

White mode.

The line control starts at the first line after vsync

(vreset), which is line 10 for 525 line modes, and

line 6 for 625-line modes. The correspondence

between the individual bits of pass_line_ctrl and

the field line numbers is shown below.

Bits Type Default Name Description

[31:0] RO 32‘b0 Reserved

Bit Line, 525-line mode Line, 625-line

mode

010 6

111 7

212 8

19 29 25

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CX23885 Data Sheet Registers

3.21 Audio Decoder Registers

3.21.1 8051 Configuration

Bits Type Default Name Description

[31:29] RO 3‘b 0 Reserved

[28:28] RW 1‘b 0 START_8051 0 – 8051 is stopped

1 – 8051 is running

[27:27] RW 1‘b 0 DL_ENABLE Download Enable

[26:26] RW 1‘b 0 DL_AUTO_INC Increment Mode

0 = Increment on Write

1 = Increment on Read

[25:24] RW 2‘b 0 DL_MAP Memory Map Mode

[23:16] RW 8‘b 0 DL_DATA_CTL Refer to Audio Decoder spec. for operation

Control data port for 8051 code download

[15:0] RW 16‘b 0 DL_ADDR Address byte for 8051 code download

Only Byte access guarantees correct operation.

Refer to Audio Decoder Spec. for operation

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Registers CX23885 Data Sheet

3.21.2 Format Detection and Subcarrier Monitoring

Bits Type Default Name Description

[31:24] RO 8‘b0 SPARE_STATUS1 Spare Status Register for future use

[23:16] RO 8‘b0 SPARE_STATUS0 Spare Status Register for future use

[15:8] RO 8‘b0 MOD_DET_STATUS1 Detected audio standard

0x00: Mono

0x01: Stereo

0x02: Dual

0x04: Tri

0x10: SAP

[7:0] RO 8‘b0 MOD_DET_STATUS0 Detected audio standard

0x00: BTSC

0x01: EIAJ

0x02: A2 M

0x03: A2 BG

0x04: A2 DK1

0x05: A2 DK2

0x06: A2 DK3

0x07: A1 I

0x08: AM L

0x09: NICAM BG

0x0A: NICAM DK

0x0B: NICAM I

0x0C: NICAM L

0x0D: BTSC/EIAJ/A2 M mono

0xFF: undefined

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3.21.3 User Preference

Bits Type Default Name Description

[31:28] RW 4‘b0 SPARE_CTL0 Spare Control Register for future use

[27:27] RW 1‘b0 TUNER_OUTPUT_F

ORMAT

0 – 2nd IF

1 – AF

[26:26] RW 1‘b0 FORMAT_65MHZ 0 – system DK

1 – system L

[25:24] RW 2‘b0 FORMAT_45MHZ 00 – BTSC

01 – EIAJ

10 – A2 M

[23:23] RO 1‘b0 DIS_DBX DBX processing is disabled by bond option

[22:22] RO 1‘b0 DIS_BTSC BTSC processing is disabled by bond option

[21:21] RO 1‘b0 DIS_NICAM_A2 NICAM/A2 processing is disabled by bond

option

[20:20] RO 1‘b0 VIDEO_PRESENT Video present signal from video decoder

[19:16] RO 4‘b0 DW8051_VIDEO_FOR

MAT

Detected video format by video decoder

[15:14] RW 2‘b0 FM_DEVIATION 00 – Normal FM

01 – High deviation FM – up to 360 kHz

10 – Very high deviation FM – up to 540 kHz

[13:13] RW 1‘b0 DE_EMPHASIS_TIM

0 – 75 de-emphasis

1 – 50 de-emphasis

[12:12] RW 1‘b0 MUTE_NO_PREF_MO

1 – Mute output if the preferred mode is not

available

[11:8] RW 4‘b0 PREF_MODE 0: Mono1 – Whatever is the currently broadcast

audio format, force to mono channel, L+R for

BTSC and EIA-J, FM1 for A2 or FM/AM for

NICAM.

1: Mono2 – language B

2: Mono3 – NICAM stereo forced mono

3: Mono4 – language C

4: Stereo

5: Dual1 – language A/C

6: Dual2 – language B/C

7: Dual3 – language A/B

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Registers CX23885 Data Sheet

[7:4] RW 4‘b0 AUD_STANDARD 0: BTSC

1: EIAJ

2: A2 M

3: A2 BG

4: A2 DK1

5: A2 DK2

6: A2 DK3

7: A1 I

8: AM L

9: NICAM BG

A: NICAM DK

B: NICAM I

C: NICAM L

D: FM radio

F: Automatic standard detection

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[3:0] RW 4‘b0 AUD_MODE Force audio mode: NOTE: (Applicable for

AUD_STANDARD = 0to E)

0: MONO1 (LANGUAGE A/Mono L+R channel

for BTSC,EIAJ,A2))

1: MONO2 (LANGUAGE B)

2: MONO3 (STEREO forced MONO)

3: MONO4 (NICAM ANALOG)

4: STEREO

5: DUAL1 (AB)

6: DUAL2 (AC)(FM)

7: DUAL3 (BC)(FM)

8: DUAL4 (AC)(AM)

9: DUAL5 (BC)(AM)

A: SAP

Audio system: NOTE: (Applicable for

AUD_STANDARD = F)

0: BG (Auto-detect NICAM BG/A2-BG,

Autodetect Mode)

1: DK1 (Auto-detect NICAM DK/A2-DK1, check

FM_DEVIATION, Auto-detect Mode)

2: DK2 (Auto-detect NICAM DK/A2-DK2, Auto-

detect Mode)

3: DK3 (Auto-detect NICAM DK/A2-DK3, Auto-

detect Mode)

4: I (Auto-detect NICAM I/A1, Auto-detect

Mode)

5: L (Auto-detect NICAM L/AM-L, Auto-detect

Mode)

6:BTSC (check TUNER_OUTPUT_FORMAT,

Auto-detect Mode)

7: EIAJ (Auto-detect Mode)

8: A2-M (Auto-detect Mode)

9:FM Radio (check

TUNER_OUTPUT_FORMAT, check

DE_EMPHASIS_TIME, Auto-detect Mode)

F: Automatic standard and mode detection,

except for FM Radio and AF standards

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Registers CX23885 Data Sheet

3.21.4 8051 Interrupt

Bits Type Default Name Description

[31:31] RO 1‘b0 VIDEO_PRESENT_C

HANGE

1 – video present status changed

[30:30] RO 1‘b0 VIDEO_CHANGE 1 – Video format changed

0 – No

[29:29] RO 1‘b0 RDS_READY 1 – RDS data ready interrupt asserted

0 – RDS data ready interrupt negated

[28:28] RO 1‘b0 Reserved

[27:27] RO 1‘b0 NICAM_BIT_ERROR

_TOO_HIGH

1 – Nicam bit error rate too high interrupt

asserted

0 – Nicam bit error rate too high interrupt

negated

[26:26] RO 1‘b0 NICAM_LOCK NICAM change to locked

1 – change happened

0 – No change

[25:25] RO 1‘b0 NICAM_UNLOCK NICAM change to unlocked

1 – change happened

0 – No change

[24:24] RO 1‘b0 DFT4_TH_CMP DFT 4 threshold compare status

1 – exceed threshold

0 – within threshold

[23:22] RO 1‘b0 Reserved

[21:21] RO 1‘b0 LOCK_IND_INT QPSK lock indicator status register

1 - QPSK locked

0 - not locked

[20:20] RO 1‘b0 DFT3_TH_CMP DFT 3 threshold compare status

1 – exceed threshold

0 – within threshold

[19:19] RO 1‘b0 DFT2_TH_CMP DFT 2 threshold compare status

1 – exceed threshold

0 – within threshold

[18:18] RO 1‘b0 DFT1_TH_CMP DFT 1 threshold compare status

1 – exceed threshold

0 – within threshold

[17:17] RO 1‘b0 FM2_DFT_TH_CMP FM 2 DFT threshold compare status

1 – exceed threshold

0 – within threshold

[16:16] RO 1‘b0 FM1_DFT_TH_CMP FM 1 DFT threshold compare status

1 – exceed threshold

0 – within threshold

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[15:15] RW 1‘b0 VIDEO_PRESENT_E

1 – video present status changed interrupt

enabled

0 – video present status changed interrupt

disabled

[14:14] RW 1‘b0 VIDEO_CHANGE_E

1 – Video format changed interrupt enabled

0 – Video format changed interrupt disabled

[13:13] RW 1‘b0 RDS_READY_EN 1 – RDS data ready interrupt enabled

0 – RDS data ready interrupt disabled

[12:12] RW 1‘b0 Reserved

[11:11] RW 1‘b0 NICAM_BIT_ERROR

_TOO_HIGH_EN

1 – Nicam bit error rate too high interrupt

enabled

0 – Nicam bit error rate too high interrupt

disabled

[10:10] RW 1‘b0 NICAM_LOCK_EN 1 - NICAM change to locked interrupt enabled

0 – NICAM change to locked interrupt disabled

[9:9] RW 1‘b0 NICAM_UNLOCK_E

1 - NICAM change to unlocked interrupt enabled

0 - NICAM change to unlocked interrupt

disabled

[8:8] RO 1‘b0 DFT4_TH_CMP_EN 1 - DFT 4 threshold compare interrupt enabled

0 – DFT 4 threshold compare interrupt disabled

[7:7] RO 1‘b0 Reserved

[6:6] RW 1‘b0 LOCK_IND_INT_CTL QPSK lock indicator interrupt control

0 - disabled

1 - enabled

[5:5] RW 1‘b0 BB_SRC_INT_CTL baseband SRC interrupt control

0 – interrupt disabled

1 – interrupt enable

[4:4] RW 1‘b0 DFT3_INT_CTL DFT3 interrupt control

0 – interrupt disabled

1 – interrupt enable

[3:3] RW 1‘b0 DFT2_INT_CTL DFT2 interrupt control

0 – interrupt disabled

1 – interrupt enable

[2:2] RW 1‘b0 DFT1_INT_CTL DFT 1 interrupt control

0 – interrupt disabled

1 – interrupt enable

[1:1] RW 1‘b0 FM2_DFT_INT_CTL FM 2 DFT interrupt control

0 – interrupt disabled

1 – interrupt enable

[0:0] RW 1‘b0 FM1_DFT_INT_CTL FM 1 DFT interrupt control

0 – interrupt disabled

1 – interrupt enable

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Registers CX23885 Data Sheet

3.21.5 General Control/Interrupt Control/Rev Number/Soft

Reset

Bits Type Default Name Description

[31:31] RO 1‘b0 RDS_INT 1- RDS data ready interrupt asserted

[30:30] RO 1‘b0 NBER_INT 1 – NICAM bit error rate too high interrupt

asserted

[29:29] RO 1‘b0 NLL_INT 1 – NICAM lost lock interrupt asserted

[28:28] RO 1‘b0 IFL_INT 1 – IF signal lost interrupt asserted

[27:27] RO 1‘b0 FDL_INT 1 – Format detection loop complete interrupt

asserted

[26:26] RO 1‘b0 AFC_INT 1 – Audio format change interrupt asserted

[25:25] RO 1‘b0 AMC_INT 1 – Audio mode change interrupt asserted

[24:24] RO 1‘b0 Reserved

[23:23] RW 1‘b1 RDS_INT_DIS 0 – RDS data ready interrupt enabled

1 – Disabled

[22:22] RW 1‘b1 NBER_INT_DIS 0 – NICAM bit error rate too high interrupt

enabled

1 – Disabled

[21:21] RW 1‘b1 NLL_INT_DIS 0 – NICAM lost lock interrupt enabled

1 – Disabled

[20:20] RW ‘b1 IFL_INT_DIS 0 – IF signal lost interrupt enabled

1 – Disabled

[19:19] RW ‘b1 FDL_INT_DIS 0 – Format detection loop complete interrupt

enabled

1 – Disabled

[18:18] RW 1‘b1 FC_INT_DIS 0 – Audio format change interrupt enabled

1 – Disabled

[17:17] RW 1‘b1 AMC_INT_DIS 0 – Audio mode change interrupt enabled (i.e.,

mono to stereo, stereo to SAP)

1 – Disabled

[16:16] RW 1‘b1 Reserved

[15:8] RO 1‘b4 REV_NUM Merlin design revision number register

[7:5] RO 1‘b0 Reserved

[4:4] RW 1‘b0 DBX_SOFT_RESET DBX soft reset

[3:3] RW 1‘b0 AD_SOFT_RESET Analog demod soft reset

[2:2] RW 1‘b0 SRC_SOFT_RESET Baseband SRC soft reset

[1:1] RW 1‘b0 CDMOD_SOFT_RESE

CDMOD Soft reset

[0:0] RW 1‘b0 SOFT_RESET Soft reset to ensure smooth transition of

operation modes*Write with 1 to clear interrupt

flag

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CX23885 Data Sheet Registers

3.21.6 Audio Analog AGC

Bits Type Default Name Description

[31:31] RW 1‘b0 AFE_12DB_EN Enables a +12 dB gain in the analog front end

(AFE). When using a filtered sound-IF output

from a tuner, the signals level is typically about

100 mVrms. In this case the gain should be

enabled. When the sound IF is not filtered, the

output will be closer to 1Vrms, so this gain

should not be used

[30:30] RW 1‘b0 AAGC_DEFAULT_EN Enables bypass of the AGC

[29:24] RW 6‘h20 AAGC_DEFAULT Bypass value for the AGC when

AAGC_DEFAULT_EN is asserted.

[23:23] RO 1‘b0 Reserved

[22:21] RW 2‘b0 AAGC_GAIN Controls the gain of the AGC feedback.

[20:16] RW 5‘hE AAGC_TH Control AGC error threshold

[15:14] RO 2‘b0 Reserved

[13:8] RW 6‘h9 AAGC_HYST2 Controls the wide range hysteresis of the AGC.

[7:6] RO 2‘b0 Reserved

[5:0] RW 6‘h5 AAGC_HYST1 Controls the tight range hysteresis of the AGC.

Bits Type Default Name Description

[31:0] RW 32‘b0 Reserved

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Registers CX23885 Data Sheet

3.21.7 Phase Fix/Dematrix/Analog Demod Source Select/

Prescaler

Bits Type Default Name Description

[31:28] RW 4‘b0 Reserved

[27:24] RW 4‘b0 I2S_IN_SHIFT I2S input shift. Signed 2’s complement format.

Shift left or right by this amount.This bit value is

used to set the gain or attenuate mode, and

value. If Bit[3] = 0 then gain. If Bit [3] = 1 then

attenuate. Bits [2:0] set the value for gain or

attenuate.

[23:16] RW 8‘b0 DEMATRIX_SEL_CT

00001000 – BTSC force mono

00001001 – BTSC force SAP

00001010 – BTSC force stereo

00001011 – BTSC force dual

00010000 – A2 force mono

100010001 – A2 force mono 2

00010010 – A2 force stereo

00010011 – A2 force dual

00100000 – EIAJ force mono

100100001 – EIAJ force mono 2

00100010 – EIAJ force stereo

00100011 – EIAJ force dual

01000000 – NICAM FM force mono 1 – A

01000001 – NICAM FM force mono 2 – B

01000010 – NICAM FM force mono 3 – (A+B)/2

for stereo source

01000011 – NICAM FM force mono 4 – C

analog

01000100 – NICAM FM force stereo

01000101 – NICAM FM force dual 1 – A/

C01000110 – NICAM FM force dual 2 – B/C

01000111 – NICAM FM force dual 3 – A/B

01001000 – NICAM AM force mono 1 – A

01001001 – NICAM AM force mono 2 – B

01001010 – NICAM AM force mono 3 – (A+B)/2

for stereo source

01001011 – NICAM AM force mono 4 – C

analog

01001100 – NICAM AM force stereo

01001101 – NICAM AM force dual 1 – A/C

01001110 – NICAM AM force dual 2 – BC

01001111 – NICAM AM force dual 3 – A/B

10000000 – FM force mono

10000010 – FM force stereo

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CX23885 Data Sheet Registers

3.21.8 Path 1 Source Select

[15:11] RO 5‘b0 Reserved

[10:10] RW 1‘b0 DMTRX_BYPASS Dematrix bypass enable bit

1 – force Dematrix block use mode set above

0 – system decide dematrix mode

[9:8] RW 2‘b0 DEMATRIX_MODE 0 – Dematrix Sum/Diff

1 – Dematrix Sum/R2 – Dematrix LR3 –

Dematrix Mono

[7:6] RO 2‘b0 Reserved

[5:5] RW 1‘b0 PH_DBX_SEL Selects DBX input to be channel 2 when

asserted.

[4:4] RW 1‘b0 PH_CH_SEL Selects channel to be phase delayed

0 – channel 1

1 – channel 2

[3:0] RW 4‘h9 PHASE_FIX Phase fix delay measured in samples of delay at

the output sample rate

Bits Type Default Name Description

[31:29] RO 3‘b0 Reserved

[28:24] RW 5‘b1 PATH1_MUTE_CTL 5’h01: SOFT_MUTE_EN (soft mute)

5’h02: SRC_MUTE_EN (source mute)

5’h04: I2S_MUTE_EN (I2S mute)

5’h08: PAR_MUTE_EN (parallel output mute)

5’h10: Reserved

[23:22] RO 2‘b0 Reserved

[21:20] RW 2‘b0 PATH1_AVC_CG Define AVC compression gain

00 – 1

01 – 1.5

10 – 2

11 – 4

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Registers CX23885 Data Sheet

[19:16] RW 4‘h6 PATH1_AVC_RT Define AVC release time

0000 – 0

0001 – 10ms

0010 – 20ms

0011 – 100ms

0100 – 500ms

0101 - 1s

0110 – 2s

0111 – 4s

1000 – 8s

Suggested Values: 20ms, 2s, 4s, 8s

[15:12] RW 4‘h3 PATH1_AVC_AT Define AVC attack time

0000 – 0

0001 – 10ms

0010 – 20ms

0011 – 100ms

0100 – 500ms

0101 - 1s

0110 – 2s

0111 – 4s

1000 – 8s

Suggested values: 10ms, 100ms, 500ms, 1s

[11:11] RW 1‘b1 PATH1_AVC_STERE

0: Independence Mode

1: Stereo Mode

[10:8] RW 3‘b0 PATH1_AVC_CR Define AVC compression ratio

000 – 2:1

001 – 4:1

010 – 8:1

011 – 16:1

100 – 32:1

101 ~ 111 Reserved

Suggested values: 2:1, 4:1, 8:1, 16:1

[7:4] RW 4‘h7 PATH1_AVC_RMS_C

Define AVC time gain for level detection

0000 – 0

0001 – 10ms

0010 – 20ms

0011 – 100ms

0100 – 500ms

0101 – 1s

0110 – 2s

0111 – 4s

1111 – 8s

Suggested values: 0, 20ms, 2s, 4s

[3:0] RW 4‘b0 PATH1_SEL_CTL 0 – Analog Demod Main Channel

1 – Analog Demod Sub Channel

2 – I2S3

3 – Reserved

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CX23885 Data Sheet Registers

3.21.9 Path 1 Volume/Balance Control

3.21.10 Path 1 Equalizer Control

Bits Type Default Name Description

[31:16] RW 16‘h7FFF PATH1_AVC_THRESH

OLD

Define AVC Threshold

[15:15] RW 1‘b0 PATH1_BAL_LEFT Select left channel for balance control if 1, select

right channel if 0

[14:8] RW 7‘b0 PATH1_BAL_LEVEL Attenuation to be provided to the selected

channel in dB. Range is 0 to – 96 dB in 1 dB

steps

[7:0] RW 8‘h24 PATH1_VOLUME Volume control in dB steps. +18dB to –96dB in

½ dB steps

Bits Type Default Name Description

[31:30] RO 2‘b0 Reserved

[29:24] RW 6‘b18 PATH1_EQ_TREBLE_

VOL

Equalizer Treble Volume control in dB steps.

+12dB to –12dB in ½ dB steps

[23:22] RO 2‘b0 Reserved

[21:16] RW 6‘h18 PATH1_EQ_MID_VO

Equalizer Mid-tone Volume control in dB steps.

+12dB to –12dB in ½ dB steps

[15:14] RO 2‘b0 Reserved

[13:8] RW 6‘h18 PATH_EQ_BASS_VO

Equalizer Bass Volume control in dB steps.

+12dB to –12dB in ½ dB steps

[7:1] RO 7‘b0 Reserved

[0:0] RW 1‘b0 PATH1_EQ_BAND_S

Equalizer band selection

0 – 500 Hz, 1 kHz, 2 kHz1 – 450 Hz, 1.5 kHz, 5

kHz

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Registers CX23885 Data Sheet

3.21.11 Path 1 Soft Clip Control

Bits Type Default Name Description

[31:16] RW 16‘h7FFF PATH1_SC_THRESHO

Define SC Threshold

[15:12] RW 4‘h3 PATH1_SC_RT Define SC release time

0000 – 0

0001 – 10ms

0010 – 20ms

0011 – 100ms

0100 – 500ms

0101 - 1s

0110 – 2s

0111 – 4s

1000 – 8s

Suggested values: 10ms, 100ms, 500ms, 1s

[11:8] RW 4‘h3 PATH1_SC_AT Define SC attack time

0000 – 0

0001 – 10ms

0010 – 20ms

0011 – 100ms

0100 – 500ms

0101 - 1s

0110 – 2s

0111 – 4s

1000 – 8s

Suggested values: 10ms, 100ms, 500ms, 1s

[7:7] RW 1‘b1 PATH1_SC_STEREO 0: Independence Mode

1: Stereo Mode

[6:4] RW 3‘h2 PATH1_SC_CR Define SC compression ratio

000 – 2:1

001 – 4:1

010 – 8:1

011 – 16:1

100 – 32:1

101 ~ 111 Reserved

Suggested values: 4:1, 8:1, 16:1, 32:1

[3:0] RW 4‘h3 PATH1_SC_RMS_CON Define SC time gain for level detection

0000 – 0

0001 – 10ms

0010 – 20ms

0011 – 100ms

0100 – 500ms

0101 - 1s

0110 – 2s

0111 – 4s

1111 – 8s

Suggested values: 0, 10ms, 100ms, 1s

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CX23885 Data Sheet Registers

3.21.12 Path 2 Source Select

Bits Type Default Name Description

[31:26] RO 6‘b0 Reserved

[25:24] RW 2‘b1 PATH2_MUTE_CTL Bit 0: SOFT_MUTE_EN (soft mute enable)

Bit 1: SRC_MUTE_EN (source mute)

[23:22] RO 2‘b0 Reserved

[21:20] RW 2‘b0 PATH2_AVC_CG Define AVC compression gain

00 – 1

01 – 1.5

10 – 2

11 – 4

[19:16] RW 4‘h6 PATH2_AVC_RT Define AVC release time

0000 – 0

0001 – 10 ms

0010 – 20 ms

0011 – 100 ms

0100 – 500 ms

0101 - 1s

0110 – 2s

0111 – 4s

1000 – 8s

Suggested Values: 20 ms, 2 s, 4 s, 8 s

[15:12] RW ‘b3 PATH2_AVC_AT Define AVC attack time

0000 – 0

0001 – 10 ms

0010 – 20 ms

0011 – 100 ms

0100 – 500 ms

0101 - 1s

0110 – 2s

0111 – 4s

1000 – 8s

Suggested values: 10 ms, 100 ms, 500 ms, 1 s

[11:11] RW ‘b1 PATH2_AVC_STERE

0: Independence Mode

1: Stereo Mode

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Registers CX23885 Data Sheet

[10:8] RW ‘b0 PATH2_AVC_CR Define AVC compression ratio

000 – 2:1

001 – 4:1

010 – 8:1

011 – 16:1

100 – 32:1

101 ~ 111 Reserved

Suggested values: 2:1, 4:1, 8:1, 16:1

[7:4] RW ‘b7 PATH2_AVC_RMS_C

Define AVC time gain for level detection

0000 - 0

0001 - 10 ms

0010 - 20 ms

0011 - 100 ms

0100 - 500 ms

0101 - 1s

0110 - 2s

0111 - 4s

1111 - 8s

Suggested values: 0, 20 ms, 2 s, 4 s

[3:0] RW ‘b0 PATH2_SEL_CTL 0 - Analog Demod Main Channel

1 - Analog Demod Sub Channel

2 - I2S

3 - Reserved

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CX23885 Data Sheet Registers

3.21.13 Path 2 Volume/Balance Control

3.21.14 Path 2 Equalizer Control

Bits Type Default Name Description

[31:16] RW 16‘h 7FFF PATH2_AVC_THRESH

OLD

Define AVC Threshold

[15:15] RW 1‘b 0 PATH2_BAL_LEFT Select left channel for balance control if 1, select

right channel if 0

[14:8] RW 7‘b 0 PATH2_BAL_LEVEL Attenuation to be provided to the selected

channel in dB. Range is 0 to – 96 dB in 1 dB

steps

[7:0] RW 8‘h 24 PATH2_VOLUME Volume control in dB steps. +18dB to –96dB in

½ dB steps

Bits Type Default Name Description

[31:30] RO 2‘b 0 Reserved

[29:24] RW 6‘h 18 PATH2_EQ_TREBLE_

VOL

Equalizer Treble Volume control in dB steps.

+12dB to –12dB in ½ dB steps

[23:22] RO 2‘b 0 Reserved

[21:16] RW 6‘h 18 PATH2_EQ_MID_VO

Equalizer Mid-tone Volume control in dB steps.

+12dB to –12dB in ½ dB steps

[15:14] RO 2‘b 0 Reserved

[13:8] RW 6‘h 18 PATH2_EQ_BASS_V

Equalizer Bass Volume control in dB steps.

+12dB to –12dB in ½ dB steps

[7:1] RO 7‘b 0 Reserved

[0:0] RW 1‘b 0 PATH2_EQ_BAND_S

Equalizer band selection

0 – 500 Hz, 1 kHz, 2 kHz

1 – 450 Hz, 1.5 kHz, 5 kHz

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Registers CX23885 Data Sheet

3.21.15 Path 2 Soft Clip Control

Bits Type Default Name Description

[31:16] RW 16’h 7FFF PATH2_SC_THRESHO

Define SC Threshold

[15:12] RW 4‘h 3 PATH2_SC_RT Define SC release time

0000 – 0

0001 – 10 ms

0010 – 20 ms

0011 – 100 ms

0100 – 500 ms

0101 - 1 s

0110 – 2 s

0111 – 4 s

1000 – 8 s

Suggested values: 10 ms, 100 ms, 500 ms, 1 s

[11:8] RW 4‘h 3 PATH2_SC_AT Define SC attack time

0000 – 0

0001 – 10 ms

0010 – 20 ms

0011 – 100 ms

0100 – 500 ms

0101 - 1 s

0110 – 2 s

0111 – 4 s

1000 – 8 s

Suggested values: 10 ms, 100 ms, 500 ms, 1 s

[7:7] RW 1‘b 1 PATH2_SC_STEREO 0: Independence Mode1: Stereo Mode

[6:4] RW 3‘h 2 PATH2_SC_CR Define SC compression ratio

000 – 2:1

001 – 4:1

010 – 8:1

011 – 16:1

100 – 32:1

101 ~ 111 Reserved

Suggested values: 4:1, 8:1, 16:1, 32:1

[3:0] RW 4‘h 3 PATH2_SC_RMS_C

Define SC time gain for level detection.

0000 – 0

0001 – 10 ms

0010 – 20 ms

0011 – 100 ms

0100 – 500 ms

0101 - 1 s

0110 – 2 s

0111 – 4 s

1111 – 8 s

Suggested values: 0, 10 ms, 100 ms, 1 s

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CX23885 Data Sheet Registers

3.21.16 Sample Rate Converter Control

Bits Type Default Name Description

[31:8] RO 24‘b 0 SRC_STATUS FIFO status, OF = OverFlow UF = UnderFlow

[11:8] SRC6 Right OF/UF – Left OF/UF

[15:12] SRC5 Right OF/UF – Left OF/UF

[19:16] SRC4 Right OF/UF – Left OF/UF

[23:20] SRC3 Right OF/UF – Left OF/UF

[27:24] SRC6: SRC5: SRC4: SRC3 FIFO

Pointer bigger than or equal to 12, used for

checking the pointer level during loop filter

adaptation so as to improve FIFO sizing.

[31:28] SRC6: SRC5: SRC4: SRC3 FIFO

Pointer less than or equal to 3, used for

checking the pointer level during loop filter

adaptation so as to improve FIFO sizing.

[7:2] RW 6‘h 3F FIFO_LF_EN Enable SRC FIFO loop filter

[7]: SRC6 FIFO loop filter enable

….

[2]: SRC1 FIFO loop filter enable

[1:1] RW 1‘b 0 BYPASS_LI Bypass linear interpolation

[0:0] RW 1‘b 0 BYPASS_PF Latest input sample feeds through SRCs but

decimation/interpolation timing remains.

** WC Same as RW, but software writing a 1

resets corresponding bit location, writing 0 has

no effect.

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Registers CX23885 Data Sheet

3.21.17 Sample Rate Converter Loop Filter Coefficients

3.21.18 SRC1 Control

Bits Type Default Name Description

[31:16] RW 16'h 3333 LOOP_FILTER_COE

KD, direct gain of proportional path

[19:16] SRC3_KD, valid data 3,4,5,6,7

[23:20] SRC4_KD, valid data 3,4,5,6,7

[27:24] SRC5_KD, valid data 3,4,5,6,7

[31:28] SRC6_KD,validdata 3,4,5,6,7

Default to 5 for all SRCs; invalid setting results

in the default.

[15:0] RW 16'h 8888 LOOP_FILTER_COE

KI, indirect gain of integrated path

[3:0] SRC3_KI, valid data 6,7,8,9,10

[7:4] SRC4_KI, valid data 6,7,8,9,10

[11:8] SRC5_KI, valid data 6,7,8,9,10

[15:12] SRC6_KI, valid data 6,7,8,9,10

Default to 8 for all SRCs; invalid setting results

in the default.

Bits Type Default Name Description

[31:28] RO 4‘b 0 Reserved

[27:24] RW 4‘h 8 SRC1_FIFO_RD_TH SRC 1 FIFO threshold for Read Enable. Apply

to both left channel and right channel.

[23:18] RO 6‘b 0 Reserved

[17:0] RW 18‘h 1867C SRC1_PHASE_INC SRC 1 phase increment calculated by (Fin/Fout)

* 216, default Fin = Fout

Shared by left channel and right channel.

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3.21.19 SRC2 Control

3.21.20 SRC3 Control

3.21.21 SRC4 Control

Bits Type Default Name Description

[31:28] RO 4‘b 0 Reserved

[27:24] RW 4‘h 8 SRC2_FIFO_RD_TH SRC 2 FIFO threshold for Read Enable. Apply

to both left channel and right channel.

[23:18] RO 6‘b 0 Reserved

[17:0] RW 18‘h 1867C SRC2_PHASE_INC SRC 2 phase increment calculated by (Fin/Fout)

* 216, default Fin = Fout

Shared by left channel and right channel.

Bits Type Default Name Description

[31:28] RO 4‘b 0 Reserved

[27:24] RW 4‘h 8 SRC3_FIFO_RD_TH SRC 3 FIFO threshold for Read Enable. Apply

to both left channel and right channel.

[23:18] RO 6‘b 0 Reserved

[17:0] RW 18‘h 14FAA SRC3_PHASE_INC SRC 3 phase increment calculated by (Fin/Fout)

* 216, default Fin = Fout

Shared by left channel and right channel.

Bits Type Default Name Description

[31:28] RO 4‘b 0 Reserved

[27:24] RW 4‘h 8 SRC4_FIFO_RD_TH SRC 4 FIFO threshold for Read Enable. Apply

to both left channel and right channel.

[23:18] RO 6‘b 0 Reserved

[17:0] RW 18‘h 14FAA SRC4_PHASE_INC SRC 4 phase increment calculated by (Fin/Fout)

* 216, default Fin = Fout

Shared by left channel and right channel.

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Registers CX23885 Data Sheet

3.21.22 SRC5 Control

3.21.23 SRC6 Control

Bits Type Default Name Description

[31:28] RO 4‘b 0 Reserved

[27:24] RW 4‘h 8 SRC5_FIFO_RD_TH SRC 5 FIFO threshold for Read Enable. Apply

to both left channel and right channel.

[23:18] RO 6‘b 0 Reserved.

[17:0] RW 18‘h 10453 SRC5_PHASE_INC SRC 5 phase increment calculated by (Fin/Fout)

* 216, default Fin = Fout

Shared by left channel and right channel.

Bits Type Default Name Description

[31:28] RO 4‘b 0 Reserved

[27:24] RW 4‘h 8 SRC6_FIFO_RD_TH SRC 6 FIFO threshold for Read Enable. Apply

to both left channel and right channel.

[23:18] RO 6‘b 0 Reserved

[17:0] RW 18‘h 14FAA SRC6_PHASE_INC SRC 6 phase increment calculated by (Fin/Fout)

* 216, default Fin = Fout

Shared by left channel and right channel.

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3.21.24 Output Selects/Bypass Control

Bits Type Default Name Description

[31:30] RW 2‘b 0 SRC6_IN_SEL SRC input source select.

00 – select from path 1 output

01 – select from path 2 output

10 – select from de-matrix stereo

11 – select from mono/SAP output

[29:28] RW 2‘b 1 SRC6_CLK_SEL SRC output fifo read select

00 – select from I2S WS

01 – Reserved

10 – select from NICAM ENABLE (64 kHz)

11 – select from SRC6 FIFO write

[27:26] RW 2‘b 0 SRC5_IN_SEL SRC input source select.

00 – select from analog demod OUTA, OUTC

01 – select from analog demod RDS output

10 – select from de-matrix stereo

11 – select from mono/SAP output

[25:24] RW 2‘h 2 SRC5_CLK_SEL SRC output fifo read select

00 – select from I2S WS

01 – Reserved

10 – select from NICAM ENABLE (64 kHz)

11 – select from SRC5 FIFO write

[23:22] RW 2‘h 2 SRC4_IN_SEL SRC input source select.

00 – select from path 1 output

01 – select from path 2 output

10 – select from de-matrix stereo

11 – select from mono/SAP output

[21:20] RW 2‘h 3 SRC4_CLK_SEL SRC output fifo read select

00 – select from I2S WS

01 – Reserved

10 – select from NICAM ENABLE (64 kHz)

11 – select from SRC4 FIFO write

[19:18] RW 2‘b 0 SRC3_IN_SEL SRC input source select.

00 – select from path 1 output

01 – select from path 2 output

10 – select from de-matrix stereo

11 – select from mono output

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Registers CX23885 Data Sheet

[17:16] RW 2‘b 0 SRC3_CLK_SEL SRC output fifo read select

00 – select from I2S WS

01 – Reserved

10 – select from NICAM ENABLE (64 kHz)

11 – select from SRC3 FIFO write

[15:8] RW 8‘b 0 BASEBAND_BYPASS_

CTL

Baseband block bypass control

0 – Normal operation

1 – The block is bypassed

bit

7 – path2 soft-clip

6 – path2 volume/balance control

5 – path2 equalizer

4 – path2 automatic volume control

3 – path1 soft-clip

2 – path1 volume/balance control

1 – path1 equalizer

0 – path1 automatic volume control

[7:6] RO 2‘h 3 Reserved

[5:4] RW 2‘b 0 I2S_SRC_SEL Output source select.

00 – select from SRC 3

01 – select from SRC 4

10 – select from SRC 5

11 – select from SRC 6

[3:2] RW 2‘h 2 PARALLEL2_SRC_S

Output source select.

00 – select from SRC 3

01 – select from SRC 4

10 – select from SRC 5

11 – select from SRC 6

[1:0] RW 2‘b 1 PARALLEL1_SRC_S

Output source select.

00 – select from SRC 3

01 – select from SRC 4

10 – select from SRC 5

11 – select from SRC 6

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CX23885 Data Sheet Registers

3.21.25 I2S Input Control Register

Bits Type Default Name Description

[31:11] RO 21‘b 0 Reserved

[10:10] RW 1‘b 0 I2S_UP2X_BW20K 20 kHz upsample by 2 bandwidth

1 - 20 kHz bandwidth (44.1 - 64 kHz sample

rate)

0 - 15 kHz bandwidth (32 kHz sample rate)

[9:9] RW 1‘b 0 I2S_UP2X_BYPASS 0 = normal operation

1 = up sample by 2 block is bypassed for input

sample rate higher than 64 kHz

[8:8] RW 1‘b 0 I2S_IN_MASTER_MOD

0 = Slave operation

1 = Master: SCK_OUT, and WS_OUT are

generated

[7:7] RW 1‘b 0 I2S_IN_SONY_MOD

0 = Philips mode: 2nd SCK rising edge after WS

transition for first bit of audio word.

1 = Sony mode: 1st SCK rising edge after WS

transition for first bit of audio word.

[6:6] RW 1‘b 0 I2S_IN_RIGHT_JUST 0 = left justified serial data

1 = right justified meaning aligned with

[5:5] RW 1‘b 0 I2S_IN_WS_SEL Control for Word Select (WS_IN/WS_OUT)

polarity.

0 = Left sample on WS=0

1 = Left sample on WS=1

[4:0] RW 5‘b 0 I2S_IN_BCN_DEL Controls a number of SCK_IN cycles delay for

programmable Right justify mode.

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Registers CX23885 Data Sheet

3.21.26 I2S Output Control Register

Bits Type Default Name Description

[31:17] RO 15‘b 0 Reserved

[16:16] RW 1‘b 0 I2S_OUT_SOFT_RESE

T_EN

I2S output soft reset control

1: soft reset will reset I2S output

0: soft reset do not reset I2S output

[15:9] RO 7‘b 0 Reserved

[8:8] RW 1‘b 1 I2S_OUT_MASTER_M

ODE

0 = Slave operation

1 = Master: SCK_OUT, and WS_OUT are

generated

[7:7] RW 1‘b 0 I2S_OUT_SONY_MO

0 = Philips mode: 2nd SCK rising edge after WS

transition for first bit of audio word.

1 = Sony mode: 1st SCK rising edge after WS

transition for first bit of audio word.

[6:6] RW 1‘b 0 I2S_OUT_RIGHT_JU

0 = left justified serial data

1 = right justified meaning aligned with

[5:5] RW 1‘b 0 I2S_OUT_WS_SEL Control for Word Select (WS_IN/WS_OUT)

polarity.

0 = Left sample on WS=0

1 = Left sample on WS=1

[4:0] RW 5‘b 0 I2S_OUT_BCN_DEL Controls a number of SCK_IN cycles delay for

programmable Right justify mode.

Bits Type Default Name Description

[31:0] RO 32‘b 0 Reserved

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3.21.27 Autoconfiguration Control

Bits Type Default Name Description

[31:4] RO 28'b 0 Reserved

[3:0] RW 4'b 0 AUTOCONFIG_MOD

Audio Standard

0:BTSC

1:FM Radio

2:EIA-J

3:A2-BG

4:NICAM AM/FM

5:NICAM High Deviation FM

6:NICAM Very High Deviation FM

7:AF FM - baseband FM input, bypass first

rotator and FM decoder

8: A1

9:A2-M

A:A2-DK

Bits Type Default Name Description

[31:0] RO 32'b 0 Reserved

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Registers CX23885 Data Sheet

3.22 Audio ADC Registers

Unless specified explicitly, the same register control is applicable to both left channel

and right channel.

3.22.1 Delta-Sigma ADC Miscellaneous Register 1

3.22.2 Delta-Sigma ADC Miscellaneous Register 2

Bits Type Default Name Description

[7:7] RW 1’b1 DYN_DIT_EN Enables dynamic dithering.

[6:6] RW 1’b1 DIT_EN Enables dithering.

[5:5] RW 1’b0 RND_MODE Switches between two different length LFSRs.

[4:4] RW 1’b1 STAB_DET_EN Enables stability detector.

[3:3] RO 1’b0 Reserved

[2:0] RW 3’h2 STAB_TH Sets threshold for stability detection in delta-

sigma.

Bits Type Default Name Description

[7:2] RO 6’b0 Reserved

[1:0] RW 2’h3 DIT_REF Changes the dither amplitude used in dynamic

dithering.

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3.22.3 Chopper Clocks Enable Register

3.22.4 Chopper Clock Reference and Bandgap Divide

Settings

3.22.5 Chopper Clock S2D Divide Settings

Bits Type Default Name Description

[7:5] RO 3’b0 Reserved

[4:4] RW 1’b1 CHP_CLK_EN_REF Enables chopper clock for refbuf and bandgap.

[3:3] RW 1’b1 CHP_CLK_EN_S2D Enables chopping for S2D.

[2:2] RW 1’b0 CHP_CLK_MODE Changes the M variable described in

CHP_CLKDV_REF for the bandgap from 6 to 8.

[1:1] RW 1’b1 CHP_EN_BG Enables chopping for bandgap.

[0:0] RW 1’b1 CHP_EN_REFBUF Enables chopping for refbuf.

Bits Type Default Name Description

[7:5] RO 3’b0 Reserved

[4:0] RW 5’h8 CHP_CLKDV_REF Changes the reference buffers and bandgap

chopper frequency:

Reference buffer CHOP CLK: (PLL_CLK)/

(10*6*2n) where 0<n<32.

Bandgap CHOP CLK: (PLL_CLK)/(10*M*2n)

where 0<n<32 and M is determined by the

CHP_CLK_MODE bit.

Bits Type Default Name Description

[7:5] RO 3’b0 Reserved

[4:0] RW 5’h8 CHP_CLKDV_S2D Change S2D chopper frequency, (PLL_CLK)/

(8*10*2n) (where 0<n<32)

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Registers CX23885 Data Sheet

3.22.6 Bandgap Testing Register

3.22.7 SD2 MUX Control for Right Channel

3.22.8 SD2 MUX Control for Left Channel

Bits Type Default Name Description

[7:5] RO 3’b0 Reserved

[6:6] RW 1’b0 OCURR_REFBUF Increases refbuf current by 66%.

0 = nom

1 = 66% more current.

[5:5] RW 1’b0 TEST_BG Bypass refbuf, route bandgap to reference pin.

[4:4] RW 1’b0 BIAS_SEL Bases all Audio ADC currents off either Audio

ADC bandgap or a current external from audio

ADC.

0 = internal

1 = external from audio ADC

[3:3] RO 1’b0 Reserved

[2:0] RW 3’h3 BG_TRIM Changes the output voltage (slightly) and temp

coefficient for tuning of bandgap over PVT.

Bits Type Default Name Description

[7:5] RO 3’b0 Reserved

[4:0] RW 5’h13 SW_CTRL_S2D_R Changes input switches for right channel.

Bits Type Default Name Description

[7:5] RO 3’b0 Reserved

[4:0] RW 5’h13 SW_CTRL_S2D_L Changes input switches for left channel.

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CX23885 Data Sheet Registers

3.22.9 S2D Bias and Startup Control

Bits Type Default Name Description

[7:5] RO 3’b0 Reserved

[4:4] RW 1’b0 S2D_STRTL_N Disables S2D startup circuitry:

0 = startup circuit on

1 = startup circuit off

[3:2] RW 2’h2 AMP_BIAS_S2D Changes bias for amp in S2D:

[1:0] RW 2’h2 CMFB_BIAS_S2D Changes bias for CMFB in S2D:

<1> <0> Amp Current

Base*4

Base*3

Base*2

Base

<1> <0> CMFB Current

Base*4

Base*3

Base*2

Base

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3.22.10 Delta-Sigma ADC Amplifier Bias Registers

3.22.11 Miscellaneous Testing Register

Bits Type Default Name Description

[7:5] RO 3’b0 Reserved

[4:4] RW 1’b0 COMP_BIAS Changes comparator bias in delta-sigma:

1 = 50% more current

0 = base current

[3:2] RW 2’b1 AMP1_BIAS Changes first amplifier bias in delta-sigma:

<0>: 1 = 66% more current from base

<1>: 1 = 33% more current from base

[1:0] RW 2’b1 AMP2_BIAS Changes second amplifier bias in delta-sigma:

<0>: 1 = 66% more current from base

<1>: 1 = 33% more current from base

Bits Type Default Name Description

[7:6] RO 2’b0 Reserved

[5:5] RW 1’b1 CLK_EN Enables clock to delta-sigma and decimation

filter.

[4:4] RW 1’b0 CLK_SEL Selects clock from CLK_IN OR CLK_TEST:

0 = differential PLL CLK Input

1 = ALTERNATE CLK input

[3:3] RW 1’b0 CH_SEL Selects channel:

0 = channel 1

1 = channel 2

[2:2] RW 1’b0 TEST_S2D Puts S2D into test mode:

0 = normal mode

1 = test mode

[1:1] RW 1’b0 DS_MUTE_L Mutes left channel

[0:0] RW 1’b0 DS_MUTE_R Mutes right channel

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CX23885 Data Sheet Registers

3.22.12 Power Down Register

3.22.13 DS and S2D Stability Register

3.22.14 Dynamic Dither Amplitude Read Register

Bits Type Default Name Description

[7:6] RO 2’b0 Reserved

[5:5] RW 1’b0 PWR_DN_REFBUF Powers down rebuf.

[4:4] RW 1’b0 PWR_DN_BANDG Powers down bandgap.

[3:3] RW 1’b0 PWR_DN_DS_L Powers down S2D left channel.

[2:2] RW 1’b0 PWR_DN_DS_R Powers down S2D right channel.

[1:1] RW 1’b0 PWR_DN_S2D_L Powers down S2D left channel.

[0:0] RW 1’b0 PWR_DN_S2D_R Powers down S2D right channel.

Bits Type Default Name Description

[7:4] RO 1’b0 Reserved

[3:3] RO 1’b0 S2D_STRT_R Reads stability of right channel S2D.

[2:2] RO 1’b0 S2D_STRT_L Reads stability of left channel S2D.

[1:1] RO 1’b0 STAB_FLAG_R Reads right channel delta-sigma stability.

[0:0] RO 1’b0 STAB_FLAG_L Reads left channel delta-sigma stability.

Bits Type Default Name Description

[7:4] RO 4’b0 DIT_AMPL_L Reads dynamic dither amplitude for left channel.

[3:0] RO 4’b0 DIT_AMPL_R Reads dynamic dither amplitude for right

channel.

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Registers CX23885 Data Sheet

3.22.15 Digital Control Register 1

This register specifies decimation output rate and scale.

Bits Type Default Name Description

[7:4] RW 4’h7 SCALE Digital output full-range scale enable

4'b0000: 1.0

4’b0001: 1+16/64

4’b0010: 1+18/64

4’b0011: 1+20/64

4’b0100: 1+22/64

4’b0101: 1+24/64

4’b0110: 1+26/64

4’b0111: 1+27/64

4’b1000: 1+28/64

4’b1001: 1+29/64

4’b1010: 1+30/64

4’b1011: 1+32/64

4’b1100 ~ 4’b1111: Reserved

[3:0] RW 4’b1 RATE_SEL Select output rate (96/64/88.2 kHz)

4’b0000: Reserved

4’b0001: 96 kHz

4’b0010: 64 kHz

4’b0011: Reserved

4’b0100: 88.2 kHz

4’b0101: Reserved

4’b0110 ~ 4’b1111: Reserved

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CX23885 Data Sheet Registers

3.22.16 Digital Register 2

This register specifies various mode control including Injection Mode, FCLK polarity,

and Bypass Modulator so Modulator output is directly placed on I2S I/F

(I2S_DATA_SEL).

Bits Type Default Name Description

[7:7] RW 1’b0 INJ_MODE Delta Sigma modulator is bypassed and DSM

samples are injected through INJ_DL for left

channel and INJ_DR for right channel, all at

DSM sampling speed. Refer to Corona pad

description for the pads associated.

[6:5] RO 2’b0 Reserved

[4:4] RW 1’b0 SOFT_RST High active soft reset, initializes digital registers.

[3:3] RW 1’b1 FCLK_POL Digital clock polarity control

0: aligned in phase with analog modulator clock

1: aligned out phase (180deg) with modulator

clk

[2:1] RO 2’b0 Reserved

[0:0] RW 1’b0 I2S_DATA_SEL Select internal signals placed on Audio ADC

output I2S I/F

0: Audio ADC Normal Operation, decimation

output

1: Delta Sigma Modulator Output (24 bits)

Note: SONY_PHILLIP Mode Control and LRCK

Polarity Control apply to all I2S_DATA_SEL

Bits Type Default Name Description

[7:0] RO 8’b0 Reserved

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Registers CX23885 Data Sheet

3.22.17 I2S_TX_CFG

Bits Type Default Name Description

[7:2] RO 6’b0 Reserved

[1:1] RW 1’b1 SONY_PHILLIP_MO

1: Sony Mode

0: Phillip Mode

Must be configured the same as I2S Rx in

Corona.

[0:0] RW 1’b0 LRCK_POL Specify the I2S Tx LRCK polarity.

0: low for left channel

1: low for right channel

Bits Type Default Name Description

[7:0] RO 8’b0 Reserved

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4Thermal/Mechanical

Information

4.1 Introduction

The ETQFP package features an exposed die paddle to improve both thermal and

electrical performance. To make optimum use of these performance improvements,

the PCB must be designed with this technology in mind. This section focuses on the

specifics of integrating the ETQFP into the PCB design.

4.2 Center Pad Geometry

To take advantage of the ETQFP performance improvements, a solder-tinned-copper

pad with thermal vias is required on the PCB.

This thermal via pattern represents a copper cross section in the barrel of the thermal

via of approximately 1 percent of the total center pad area. For the exposed region of

the center pad, if the plating thickness is not sufficient enough to effectively plug the

barrel of the via when plated, the solder mask should be used to cap the vias with a

dimension equal to the via diameter + 0.1 mm minimum. This prevents the solder from

being wicked through the thermal via and potentially creating a solder void in the

region between the package bottom and the center pad on the surface of the PCB.

NOTE: Please contact your Conexant representative for additional thermal

information regarding the CX23885.

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4.3 Mechanical Drawing

Figure 7 provides a mechanical drawing of the 128-pin ETQFP. Figure 8 provides a

diagram of the exposed pad.

Figure 7. 128-Pin ETQFP

Figure 8. Exposed Pad

102740_005

Control Dimensions are in Milimeters

102740_006

NOTES:

1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm

per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.

2. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not

cause the lead width to exceed the maximum b dimension by more than 0.08 mm.

Dambar cannot be located on the lower radius or the foot. Miminum space between

protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm Pitch packages.

3. All dimensions of 128L were based on those of 120L, since they are not mentioned in

JEDEC Spec MS-026.

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5Electrical Information

5.1 DC Electrical Parameters

Table 5. Absolute Maximum Ratings

Parameters Min Typ Max Units

VAA (measured to VSS) — — 5 V

VDDO (measured to VSSO) — — 5 V

VDD 1.8 V supply pins (measured to VSS) — — 3 V

VDD 1.2 V supply pins (measured to VSS) — — 2 V

Voltage on any signal pin (see note below) VSSO - 0.5 — VDDO + 0.5 Vpp

Analog input voltage — — VAA + 0.5 V

Operating temperature 0 — 70 °C

Storage temperature –65 — +150 °C

Junction temperature — — +125 °C

Peak reflow temperature — — 260 °C

GENERAL NOTE:

1. Stresses above those listed may cause permanent damage to the device. This is a stress rating only and

functional operation at these or any other conditions above those listed in the operational section of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods

may affect device reliability.

2. This device employs high-impedance CMOS devices on all signal pins. It must be handled as an ESD sensitive

device. Voltage on any signal pin that exceeds the power supply voltage by more than +0.5 V, or drops

below ground by more than 0.5 V can induce destructive latchup.

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Table 6. Recommended Operating Conditions

Parameters Symbols Min Typ Max Units

Analog power supply VAA_PLL 3.135 3.3 3.465 V

VAA_CHx

VAA_ADCx

VAA_XTAL

VAA_DSx

Core power 1.2 V supply VDD 1.14 1.2 1.26 V

VDDA

VDDTA

Core power 1.8 V Supply VDDT 1.71 1.8 1.89 V

VDDTO

VDDRO

Digital I/O power supply VDDIO 3 3.3 3.6 V

VDDO_PLL

Analog input CVBS or luma amplitude range (AC

coupling required)

Yin0.512Vp-p

Analog input chroma amplitude range

(AC coupling required)

Cin0.112Vp-p

Analog audio input Ain — 2.262 2.828 Vp-p

Ambient operating temperature Ta 0 — 70 °C

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CX23885 Data Sheet Electrical Information

5.2 AC Electrical Parameters

Table 7. Signal Characteristics

Parameters Symbol Min Typ Max Units

Digital Inputs

Input high voltage VIH 2 — VDDO + 0.5 V

Input low voltage VIL –0.5 — 0.8 V

Input high current (Vin = 2.4 V) IIH 1 µA

Input low current (Vin = 0.4 V) IIL –1 µA

Input capacitance (1MHz, 2.4 V) Ci 7 pF

Crystal Inputs (XTI, XTO)

Input low voltage VIL –0.5 — 0.4 V

Input high voltage VIH 2.4 — VDDO + 0.5 V

Digital Outputs

Output voltage high (IOH = -400 µA) VOH 2.4 — VDDO V

Output voltage low (IOL = 4 mA) VOL 0 — 0.4 V

Three-state current IOZ — — 10 µA

Analog input capacitance Ca 5 pF

Table 8. Clock Timing Parameters

Parameters Symbol Min Typ Max Units

XTI / XTO

Crystal cycle time 1 34.919 34.921 34.922 ns

High time 2 17.46 ns

Low time 3 17.46 ns

ITU-R BT.656 Operation

PIXCLK frequency 4 — 27 — MHz

PIXCLK duty cycle 5 45 55 %

PIXCLK to data delay (see note) 6 5 ns

GENERAL NOTE:

1. Data delay value is measured relative to the rising edge of PIXCLK but note that PIXCLK can be inverted for

systems requiring data to output relative to the falling edge of PIXCLK.

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Table 9. Control Signal Timing

Parameters Symbol Min Typ Max Units

VIP Input Port

Data to VIPCLK setup 8 5 — — ns

Data to VIPCLK hold 9 0 — — ns

VIP Output Port

PIXCLK to timing/indicator delay 10 — — 11 ns

Table 10. Power Supply Currents

Parameters Symbol Min Typ Max Units

Analog current IAA 165 173 mA

Digital core current (1.2 V) IDD1.2 300 415 mA

Digital core current (1.8 V) IDD1.8 129 132 mA

Digital I/O current IDDIO 15 40 mA

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6Connecting the CX23885 to the

CX23417

6.1 CX23885 and CX23417 Pin Connections

Table 11 lists the CX23885 pins that are to be connected to the CX23417. Each row

indicates a connection.

NOTE: Pin 113 of CX23885 is connected to two pins on the CX23417.

Table 11. CX23885 and CX23417 Pin Connections (1 of 2)

CX23885 CX23417

Pin Number Pin Name Coordinate Pin Number

53 GPIO15 U12 MIRDY#

59 GPIO14 P16 MIADDR3

60 IRQ_N (GPIO[16]) R11 MICS#

61 URX (GPIO[17]) P15 MIRD#

62 UTX (GPIO[18]) U14 MIWR#

64 GPIO13 R17 MIADDR2

65 GPIO12 L14 MIADDR1

67 GPIO11 M15 MIADDR0

68 TS2_SOP H17 STRODREQ#

69 TS2_VAL H16 STRODVLD#

70 TS2_CLK G17 STROCLK

71 TS2_DAT J17 STRODATA7

74 TS1_CLK C8 LLC

76 GPIO10 U3 MIDATA7

86 GPIO9 U4 MIDATA6

87 GPIO8 R6 MIDATA5

92 GPIO3 U6 MIDATA0

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Connecting the CX23885 to the CX23417 CX23885 Data Sheet

95 GPIO4 R7 MIDATA1

100 GPIO5 T6 MIDATA2

101 GPIO6 U5 MIDATA3

103 I2S_BCLK (GPIO[23]) B7 AICLKIN

104 I2S_WCLK (GPIO[22]) A6 AILRIN

105 I2S_SDAT (GPIO[21]) A7 AIDAT

111 GPIO[7] T5 MIDATA4

113 AUX_PLL_CLK C6 RCLK

G17 STROCLK

Table 11. CX23885 and CX23417 Pin Connections (2 of 2)

CX23885 CX23417

Pin Number Pin Name Coordinate Pin Number

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