April 2008 Rev 4 1/27
1
M34D64-W
64 Kbit serial I²C bus EEPROM
with hardware write control on top quarter of memory
Features
■Two-wire I2C serial interface
supports 400 kHz protocol
■Single supply voltage:
– 2.5 to 5.5 V for M34D64-W
■Hardware write control of the top quarter of
memory
■byte and page write (up to 32 bytes)
■Random and Sequential Read modes
■Self-timed programming cycle
■Automatic address incrementing
■Enhanced ESD/latch-up protection
■More than 1 000 000 Write cycles
■More than 40-year data retention
■Packages
–ECOPACK
® (RoHS compliant)
SO8 (MN)
150 mil width
www.st.com
Contents M34D64-W
2/27
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.5 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.2 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.3 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.6.4 Power-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1 Start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2 Stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 Acknowledge bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6 Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7 Byte Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.8 Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.9 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . . 16
3.10 Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.11 Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.12 Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.13 Sequential Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.14 Acknowledge in Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
M34D64-W Contents
3/27
5 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
List of tables M34D64-W
4/27
List of tables
Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3. Most significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Least significant byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Input parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 11. AC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 24
Table 13. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
M34D64-W List of figures
5/27
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Memory map showing write control area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Maximum RL value versus bus capacitance (CBUS) for an I2C bus . . . . . . . . . . . . . . . . . . 10
Figure 6. I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Write mode sequences with WC = 0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Read mode sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 24
Description M34D64-W
6/27
1 Description
The M34D64-W are I2C-compatible electrically erasable programmable memory (EEPROM)
devices organized as 8192 x 8 bits.
These devices are compatible with the I2C memory protocol. This is a two-wire serial
interface that uses a bidirectional databus and serial clock. The devices carry a built-in 4-bit
Device Type Identifier code (1010) in accordance with the I2C bus definition.
The device behaves as a slave in the I2C protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are initiated by a Start condition, generated
by the bus master. The Start condition is followed by a Device Select Code and Read/Write
bit (RW) (as described in Table 2.: Device select code), terminated by an acknowledge bit.
When writing data to the memory, the device inserts an acknowledge bit during the 9th bit
time, following the bus master’s 8-bit transmission. When data is read by the bus master, the
bus master acknowledges the receipt of the data byte in the same way. Data transfers are
terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.
Figure 1. Logic diagram
Table 1. Signal names
Signal name Function Direction
E0, E1, E2 Chip Enable Input
SDA Serial Data I/O
SCL Serial Clock Input
WC Write Control Input
VCC Supply voltage
VSS Ground
AI02850c
3
E0-E2 SDA
VCC
M34D64-W
WC
SCL
VSS
Signal description M34D64-W
8/27
2 Signal description
2.1 Serial Clock (SCL)
This input signal is used to strobe all data in and out of the device. In applications where this
signal is used by slave devices to synchronize the bus to a slower clock, the bus master
must have an open drain output, and a pull-up resistor must be connected from Serial Clock
(SCL) to VCC. (Figure 5 indicates how the value of the pull-up resistor can be calculated). In
most applications, though, this method of synchronization is not employed, and so the pull-
up resistor is not necessary, provided that the bus master has a push-pull (rather than open
drain) output.
2.2 Serial Data (SDA)
This bidirectional signal is used to transfer data in or out of the device. It is an open drain
output that may be wire-OR’ed with other open drain or open collector signals on the bus. A
pull up resistor must be connected from Serial Data (SDA) to VCC. (Figure 5 indicates how
the value of the pull-up resistor can be calculated).
2.3 Chip Enable (E0, E1, E2)
These input signals are used to set the value that is to be looked for on the three least
significant bits (b3, b2, b1) of the 7-bit device select code. These inputs must be tied to VCC
or VSS, to establish the device select code as shown in Figure 3. When not connected (left
floating), these inputs are read as low (0,0,0).
Figure 3. Device select code
2.4 Write Control (WC)
The hardware Write Control pin (WC) is useful for protecting the top quarter of the memory
(as shown in Figure 4.) from inadvertent write. The Write Control signal is used to enable
(WC = VIL) or disable (WC = VIH) write instructions to the top quarter of the memory area.
When unconnected, the WC input is internally read as VIL, and write operations are allowed.
Ai15122
VCC
M34xxx
VSS
Ei
VCC
M34xxx
VSS
Ei
M34D64-W Signal description
9/27
2.5 VSS ground
VSS is the reference for the VCC supply voltage.
2.6 Supply voltage (VCC)
2.6.1 Operating supply voltage VCC
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Ta b l e 7 ). In order to
secure a stable DC supply voltage, it is recommended to decouple the VCC line with a
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package
pins.
This voltage must remain stable and valid until the end of the transmission of the instruction
and, for a Write instruction, until the completion of the internal write cycle (tW).
2.6.2 Power-up conditions
When the power supply is turned on, VCC rises from VSS to VCC, the VCC rise time must not
vary faster than 1 V/µs.
2.6.3 Device reset
In order to prevent inadvertent write operations during power-up, a power-on-reset (POR)
circuit is included. At power-up (continuous rise of VCC), the device does not respond to any
instruction until VCC has reached the power-on-reset threshold voltage (this threshold is
lower than the minimum VCC operating voltage defined in Ta bl e 7 ). When VCC passes over
the POR threshold, the device is reset and enters the Standby Power mode. It must not be
accessed until VCC reaches a valid and stable VCC voltage within the specified [VCC(min),
VCC(max)] range.
In a similar way, during power-down (continuous decrease in VCC), as soon as VCC drops
below the power-on-reset threshold voltage, the device stops responding to any instruction
sent to it.
2.6.4 Power-down conditions
During power-down (continuous decrease in VCC), the device must be in Standby Power
mode (mode reached after decoding a Stop condition, assuming that there is no internal
Write cycle in progress).
Signal description M34D64-W
10/27
Figure 4. Memory map showing write control area
Figure 5. Maximum RL value versus bus capacitance (CBUS) for an I2C bus
AI03114C
1FFFh
Write Controlled
Area
1000h
0000h
0800h
1800h
1
10
100
10 100 1000
Bus line capacitor (pF)
Bus line pull-up resistor
(k )
fC = 400 kHz, tLOW = 1.3 µs
Rbus x Cbus time
constant must be less than
500 ns
I²C bus
master M34D64
R
bus
V
CC
C
bus
SCL
SDA
ai15127
M34D64-W Signal description
11/27
Figure 6. I2C bus protocol
Table 2. Device select code
Device type identifier(1)
1. The most significant bit, b7, is sent first.
Chip Enable address(2)
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
RW
b7 b6 b5 b4 b3 b2 b1 b0
Device select
code 1010E2E1E0RW
Table 3. Most significant byte
b15 b14 b13 b12 b11 b10 b9 b8
Table 4. Least significant byte
b7 b6 b5 b4 b3 b2 b1 b0
SCL
SDA
SCL
SDA
SDA
Start
condition
SDA
Input
SDA
Change
AI00792c
Stop
condition
123 789
MSB ACK
Start
condition
SCL 123 789
MSB ACK
Stop
condition
Device operation M34D64-W
12/27
3 Device operation
The device supports the I2C protocol. This is summarized in Figure 6.: I2C bus protocol. Any
device that sends data on to the bus is defined to be a transmitter, and any device that reads
the data to be a receiver. The device that controls the data transfer is known as the bus
master, and the other as the slave device. A data transfer can only be initiated by the bus
master, which will also provide the serial clock for synchronization. The M34D64-W device is
always a slave in all communications.
3.1 Start condition
Start is identified by a falling edge of Serial Data (SDA) while Serial Clock (SCL) is stable in
the high state. A Start condition must precede any data transfer command. The device
continuously monitors (except during a Write cycle) Serial Data (SDA) and Serial Clock
(SCL) for a Start condition, and will not respond unless one is given.
3.2 Stop condition
Stop is identified by a rising edge of Serial Data (SDA) while Serial Clock (SCL) is stable
and driven high. A Stop condition terminates communication between the device and the
bus master. A Read command that is followed by NoAck can be followed by a Stop condition
to force the device into the Standby mode. A Stop condition at the end of a Write command
triggers the internal EEPROM Write cycle.
3.3 Acknowledge bit (ACK)
The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter,
whether it be bus master or slave device, releases Serial Data (SDA) after sending eight bits
of data. During the 9th clock pulse period, the receiver pulls Serial Data (SDA) low to
acknowledge the receipt of the eight data bits.
3.4 Data input
During data input, the device samples Serial Data (SDA) on the rising edge of Serial Clock
(SCL). For correct device operation, Serial Data (SDA) must be stable during the rising edge
of Serial Clock (SCL), and the Serial Data (SDA) signal must change only when Serial Clock
(SCL) is driven low.
M34D64-W Device operation
13/27
3.5 Memory addressing
To start communication between the bus master and the slave device, the bus master must
initiate a Start condition. Following this, the bus master sends the Device Select Code,
shown in Table 2.: Device select code (on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable
“Address” (E2, E1, E0). To address the memory array, the 4-bit Device Type Identifier is
1010b.
Up to eight memory devices can be connected on a single I2C bus. Each one is given a
unique 3-bit code on the Chip Enable (E0, E1, E2) inputs. When the Device Select Code is
received on Serial Data (SDA), the device only responds if the Chip Enable Address is the
same as the value on the Chip Enable (E0, E1, E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations.
If a match occurs on the Device Select code, the corresponding device gives an
acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match
the Device Select code, it deselects itself from the bus, and goes into Standby mode.
Table 5. Operating modes
Mode RW bit WC (1)
1. X = VIH or VIL.
Bytes Initial sequence
Current Address Read 1 X 1 Start, Device Select, RW = 1
Random Address Read 0X1Start, Device Select, RW = 0, Address
1 X reStart, Device Select, RW = 1
Sequential Read 1 X ≥ 1 Similar to Current or Random Address
Read
Byte Write 0 VIL 1 Start, Device Select, RW = 0
Page Write 0 VIL ≤ 32 Start, Device Select, RW = 0
Device operation M34D64-W
14/27
Figure 7. Write mode sequences with WC = 0 (data write enabled)
3.6 Write operations
Following a Start condition the bus master sends a Device Select Code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 7.: Write mode
sequences with WC = 0 (data write enabled), and waits for two address bytes. The device
responds to each address byte with an acknowledge bit, and then waits for the data byte(s).
Writing to the memory may be inhibited if Write Control (WC) is driven high. Any Write
instruction with Write Control (WC) driven high (during a period of time from the Start
condition until the end of the two address bytes) will not modify the contents of the top
quarter of the memory.
Each data byte in the memory has a 16-bit (two byte wide) address. The Most Significant
Byte (Table 3.: Most significant byte) is sent first, followed by the Least Significant Byte ( : ).
Bits b15 to b0 form the address of the byte in memory.
When the bus master generates a Stop condition immediately after the Ack bit (in the “10th
bit” time slot), either at the end of a Byte Write or a Page Write, the internal EEPROM Write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write
cycle.
During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does
not respond to any requests.
Stop
Start
Byte Write Dev sel Byte addr Byte addr Data in
WC
Start
Page Write Dev sel Byte addr Byte addr Data in 1
WC
Data in 2
AI01106d
Page Write
(cont'd)
WC (cont'd)
Stop
Data in N
ACK
R/W
ACK ACK ACK
ACK ACK ACK ACK
R/W
ACKACK
M34D64-W Device operation
15/27
3.7 Byte Write
After the Device Select code and the address bytes, the bus master sends one data byte. If
the addressed location is Write-protected (top quarter of the memory), by Write Control
(WC) being driven high, the location is not modified. The bus master terminates the transfer
by generating a Stop condition, as shown in Figure 7.: Write mode sequences with WC = 0
(data write enabled).
3.8 Page Write
The Page Write mode allows up to 32 bytes to be written in a single Write cycle, provided
that they are all located in the same ’row’ in the memory: that is, the most significant
memory address bits (b12-b5) are the same. If more bytes are sent than will fit up to the end
of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to
become overwritten in an implementation dependent way.
The bus master sends from 1 to 32 bytes of data. If Write Control (WC) is high, the contents
of the addressed top quarter of the memory location are not modified. After each byte is
transferred, the internal byte address counter (the 5 least significant address bits only) is
incremented. The transfer is terminated by the bus master generating a Stop condition.
Device operation M34D64-W
16/27
Figure 8. Write cycle polling flowchart using ACK
3.9 Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy
of the data from its internal latches to the memory cells. The maximum Write time (tw) is
shown in Table 11.: AC characteristics, but the typical time is shorter. To make use of this, a
polling sequence can be used by the bus master.
The sequence, as shown in Figure 8.: Write cycle polling flowchart using ACK, is:
●Initial condition: a Write cycle is in progress.
●Step 1: the bus master issues a Start condition followed by a Device Select Code (the
first byte of the new instruction).
●Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and
the bus master goes back to Step 1. If the device has terminated the internal Write
cycle, it responds with an Ack, indicating that the device is ready to receive the second
part of the instruction (the first byte of this instruction having been sent during Step 1).
Write cycle
in progress
AI01847d
Next
operation is
addressing the
memory
Start condition
Device select
with RW = 0
ACK
returned
YES
NO
YESNO
ReStart
Stop
Data for the
Write operation
Device select
with RW = 1
Send address
and receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YESNO Start
condition
Continue the
Write operation
Continue the
Random Read operation
M34D64-W Device operation
17/27
Figure 9. Read mode sequences
1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes)
must be identical.
3.10 Read operations
Read operations are performed independently of the state of the Write Control (WC) signal.
3.11 Random Address Read
A dummy Write is performed to load the address into the address counter (as shown in
Figure 9.: Read mode sequences) but without sending a Stop condition. Then, the bus
master sends another Start condition, and repeats the Device Select Code, with the
Read/Write bit (RW) set to 1. The device acknowledges this, and outputs the contents of the
addressed byte. The bus master must not acknowledge the byte, and terminates the transfer
with a Stop condition.
Start
Dev sel * Byte addr Byte addr
Start
Dev sel Data out 1
AI01105d
Data out N
Stop
Start
Current
Address
Read
Dev sel Data out
Random
Address
Read
Stop
Start
Dev sel * Data out
Sequential
Current
Read
Stop
Data out N
Start
Dev sel * Byte addr Byte addr
Sequential
Random
Read
Start
Dev sel * Data out 1
Stop
ACK
R/W
NO ACK
ACK
R/W
ACK ACK ACK
R/W
ACK ACK ACK NO ACK
R/W
NO ACK
ACK ACK ACK
R/W
ACK ACK
R/W
ACK NO ACK
Device operation M34D64-W
18/27
3.12 Current Address Read
The device has an internal address counter which is incremented each time a byte is read.
For the Current Address Read operation, following a Start condition, the bus master only
sends a Device Select Code with the Read/Write bit (RW) set to 1. The device
acknowledges this, and outputs the byte addressed by the internal address counter. The
counter is then incremented. The bus master terminates the transfer with a Stop condition,
as shown in Figure 9.: Read mode sequences, without acknowledging the byte.
3.13 Sequential Read
This operation can be used after a Current Address Read or a Random Address Read. The
bus master does acknowledge the data byte output, and sends additional clock pulses so
that the device continues to output the next byte in sequence. To terminate the stream of
bytes, the bus master must not acknowledge the last byte, and must generate a Stop
condition, as shown in Figure 9.: Read mode sequences.
The output data comes from consecutive addresses, with the internal address counter
automatically incremented after each byte output. After the last memory address, the
address counter ‘rolls-over’, and the device continues to output data from memory address
00h.
3.14 Acknowledge in Read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment
during the 9th bit time. If the bus master does not drive Serial Data (SDA) low during this
time, the device terminates the data transfer and switches to its Standby mode.
M34D64-W Initial delivery state
19/27
4 Initial delivery state
The device is delivered with all bits in the memory array set to 1 (each byte contains FFh).
5 Maximum rating
Stressing the device outside the ratings listed in Table 6: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only, and operation of the
device at these, or any other conditions outside those indicated in the operating sections of
this specification, is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 6. Absolute maximum ratings
Symbol Parameter Min. Max. Unit
TAAmbient operating temperature –40 130 °C
TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering see note (1)
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
°C
VIO Input or output range –0.50 6.5 V
VCC Supply voltage –0.50 6.5 V
VESD Electrostatic discharge voltage (human body model)(2)
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114, C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω)
–4000 4000 V
DC and AC parameters M34D64-W
20/27
6 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the measurement conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Figure 10. AC measurement I/O waveform
Table 7. Operating conditions
Symbol Parameter Min. Max. Unit
VCC Supply voltage 2.5 5.5 V
TAAmbient operating temperature –40 85 °C
Table 8. AC measurement conditions
Symbol Parameter Min. Max. Unit
CLLoad capacitance 100 pF
Input rise and fall times 50 ns
Input levels 0.2VCC to 0.8VCC V
Input and output timing reference levels 0.3VCC to 0.7VCC V
Table 9. Input parameters
Symbol Parameter(1)
1. Sampled only, not 100% tested.
Test condition Min.Max.Unit
CIN Input capacitance (SDA) 8 pF
CIN Input capacitance (other pins) 6 pF
ZWCL WC input impedance VIN < 0.5 V 50 300 kΩ
ZWCH WC input impedance VIN > 0.7VCC 500 kΩ
tNS
Pulse width ignored
(input filter on SCL and SDA) Single glitch 100 ns
AI00825c
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and output
timing reference levels
Input levels
M34D64-W DC and AC parameters
21/27
Table 10. DC characteristics
Symbol Parameter Test condition (in addition to
those in Table 7)Min. Max. Unit
ILI
Input leakage current
(SCL, SDA)
VIN = VSS or VCC
device in Standby mode ± 2 µA
ILO Output leakage current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA
ICC Supply current VCC = 2.5 V, fc= 400 kHz
(rise/fall time < 50 ns) 1mA
ICC1 Standby supply current VIN = VSS or VCC, VCC = 5 V 10 µA
VIN = VSS or VCC, VCC = 2.5 V 2 µA
VIL
Input low voltage
(E2, E1, E0, SCL, SDA) –0.3 0.3VCC V
Input low voltage (WC)–0.30.5V
VIH
Input high voltage
(E2, E1, E0, SCL, SDA, WC)0.7VCC VCC+1 V
VOL Output low voltage IOL = 2.1 mA, VCC = 2.5 V 0.4 V
DC and AC parameters M34D64-W
22/27
Table 11. AC characteristics
Test conditions specified in Table 8.: AC measurement conditions and Table 7.: Operating
conditions
Symbol Alt. Parameter Min. Max. Unit
fCfSCL Clock frequency 400 kHz
tCHCL tHIGH Clock pulse width high 600 ns
tCLCH tLOW Clock pulse width low 1300 ns
tCH1CH2 tRClock rise time 300 ns
tCL1CL2 tFClock fall time 300 ns
tDH1DH2(1)
1. Sampled only, not 100% tested.
tRSDA rise time 20 300 ns
tDL1DL2(1) tFSDA fall time 20 300 ns
tDXCX tSU:DAT Data in setup time 100 ns
tCLDX tHD:DAT Data in hold time 0 ns
tCLQX tDH Data out hold time 200 ns
tCLQV(2)
2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or
rising edge of SDA.
tAA Clock low to next data valid (access time) 200 900 ns
tCHDX(3)
3. For a reStart condition, or following a Write cycle.
tSU:STA Start condition setup time 600 ns
tDLCL tHD:STA Start condition hold time 600 ns
tCHDH tSU:STO Stop condition setup time 600 ns
tDHDL tBUF
Time between Stop condition and next Start
condition 1300 ns
tWtWR Write time 5 ms
M34D64-W DC and AC parameters
23/27
Figure 11. AC waveforms
SCL
SDA In
SCL
SDA Out
SCL
SDA In
tCHCL
tDLCL
tCHDX
Start
condition
tCLCH
tDXCXtCLDX
SDA
Input
SDA
Change
tCHDH tDHDL
Stop
condition
Data Valid
tCLQV tCLQX
tCHDH
Stop
condition
tCHDX
Start
condition
Write cycle
tW
AI00795d
Start
condition
tCHCL
Package mechanical data M34D64-W
24/27
7 Package mechanical data
Figure 12. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
1. Drawing is not to scale.
Table 12. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Typ Min Max Typ Min Max
A 1.75 0.0689
A1 0.1 0.25 0.0039 0.0098
A2 1.25 0.0492
b 0.28 0.48 0.011 0.0189
c 0.17 0.23 0.0067 0.0091
ccc 0.1 0.0039
D 4.9 4.8 5 0.1929 0.189 0.1969
E 6 5.8 6.2 0.2362 0.2283 0.2441
E1 3.9 3.8 4 0.1535 0.1496 0.1575
e1.27- - 0.05- -
h 0.25 0.5 0.0098 0.0197
k 0°8° 0°8°
L 0.4 1.27 0.0157 0.05
L1 1.04 0.0409
SO-A
E1
8
ccc
b
e
A
D
c
1
E
h x 45˚
A2
k
0.25 mm
L
L1
A1
GAUGE PLANE
M34D64-W Part numbering
25/27
8 Part numbering
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
Table 13. Ordering information scheme
Example: M34D64 – W MN 6 T P
Device type
M34 = I2C application-specific standard product serial
access EEPROM
Device function
64 = 64 Kbit (8192 × 8)
Operating voltage
W = VCC = 2.5 to 5.5 V
Package
MN = SO8 (150 mils width)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard packing
T = Tape and reel packing
Plating technology
P = ECOPACK® (RoHS compliant)
Revision history M34D64-W
26/27
9 Revision history
Table 14. Document revision history
Date Revision Changes
23-Mar-1999 1.0 Document written
09-Jun-1999 1.1 Memory Map illustration added. Line removed from Tab-2
16-Nov-2000 1.2 M34D32 removed; PSDIP8 package removed; 4.5 to 5.5V and 1.8 to
3.6V ranges removed; 0 to 70°C and -20 to 85°C ranges removed
13-Sep-2002 2.0 New edition. TSSOP8 package added
04-Apr-2003 2.1
Addresses on Memory Map figure corrected.
tW of 5ms offered on certain versions of the device (bearing process
identification letter “B”)
23-Oct-2007 3
M34D64-R root part number removed (R voltage range removed).
TSSOP8 package removed. SO8N packages are ECOPACK® compliant.
SO8N package specifications updated (sse Section 7: Package
mechanical data). Note removed below Table 9: Input parameters.
Table 6: Absolute maximum ratings and related notes modified.
Section 2: Signal description modified. Power On Reset: VCC Lock-Out
Write Protect section removed.
Rise/fall time conditions modified for ICC in Table 10: DC characteristics.
Write time tW updated in Table 11: AC characteristics.
Figure 11: AC waveforms modified. Minor text changes.
17-Apr-2008 4
Obsolete product(s) watermark removed.
Section 2.6.3: Device reset updated. Figure 5: Maximum RL value versus
bus capacitance (CBUS) for an I2C bus updated. Small text changes.
M34D64-W
27/27
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