1
SY10E111
SY100E111
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
BLOCK DIAGRAM
IN
VBB
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
IN
EN
FEATURES
Low skew
Extended 100E VEE range of –4.2V to –5.5V
Guaranteed skew limits
Differential design
VBB output
Enable input
Fully compatible with industry standard 10KH, 100K
I/O levels
75K input pulldown resistors
Fully compatible with ON Semiconductor
MC10E/100E111
Available in 28-pin PLCC package
The SY10/100E111 are low skew 1-to-9 differential
drivers designed for clock distribution in new, high-
performance ECL systems. They accept one differential or
single-ended input, with VBB used for single-ended
operation. The signal is fanned out to nine identical
differential outputs. An enable input is also provided such
that a logic HIGH disables the device by forcing all Q
outputs LOW and all /Q outputs HIGH.
The device is specifically designed and produced for low
skew. The interconnect scheme and metal layout are
carefully optimized for minimal gate-to-gate skew within
the device. Wafer characterization and process control
ensure consistent distribution of propagation delay from lot
to lot. Since the E111 shares a common set of “basic”
processing with the other members of the ECLinPS™
family, wafer characterization at the point of device
personalization allows for tighter control of parameters,
including propagation delay.
To ensure that the skew specification is met, it is
necessary that both sides of the differential output are
terminated into 50, even if only one side is being used. ln
most applications, all nine differential pairs will be used
and, therefore, terminated. In the case where fewer than
nine pairs are used, it is necessary to terminate at least the
output pairs on the same package side (i.e. sharing the
same VCCO as the pair(s) being used on that side) in order
to maintain minimum skew.
The VBB output is intended for use as a reference
voltage for single-ended reception of ECL signals to that
device only. When using VBB for this purpose, it is
recommended that VBB is decoupled to VCC via a 0.01µF
capacitor.
1:9 DIFFERENTIAL CLOCK
DRIVER WITH ENABLE
DESCRIPTION
SY10E111
SY100E111
Rev.: E Amendment: /0
Issue Date: March 2006
Pin Function
IN, /IN Differential Input Pair
/EN Enable Input
Q0, /Q0 — Q8, /Q8 Differential Outputs
VBB VBB Output
VCCO VCC to Output
PIN NAMES
2
SY10E111
SY100E111
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
TIMING DIAGRAMS
Figure 1. Set-up Time
IN
ts
/IN
/EN
/Q
Q
50% 75 mV
75 mV
Figure 3. Release Time
IN
tr
/IN
/EN
Q
/Q
50%
Figure 2. Hold Time
IN
t
H
/IN
/EN
Q
/Q
50%
75 mV
75 mV
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
Package Operating Package Lead
Part Number Type Range Marking Finish
SY10E111JI J28-1 Industrial SY10E111JI Sn-Pb
SY10E111JITR(2) J28-1 Industrial SY10E111JI Sn-Pb
SY100E111JI J28-1 Industrial SY100E111JI Sn-Pb
SY100E111JITR(2) J28-1 Industrial SY100E111JI Sn-Pb
SY10E111JC J28-1 Commercial SY10E111JC Sn-Pb
SY10E111JCTR(2) J28-1 Commercial SY10E111JC Sn-Pb
SY100E111JC J28-1 Commercial SY100E111JC Sn-Pb
SY100E111JCTR(2) J28-1 Commercial SY100E111JC Sn-Pb
SY10E111JY(3) J28-1 Industrial SY10E111JY with Matte-Sn
Pb-Free bar-line indicator
SY10E111JYTR(2, 3) J28-1 Industrial SY10E111JY with Matte-Sn
Pb-Free bar-line indicator
SY100E111JY(3) J28-1 Industrial SY100E111JY with Matte-Sn
Pb-Free bar-line indicator
SY100E111JYTR(2, 3) J28-1 Industrial SY100E111JY with Matte-Sn
Pb-Free bar-line indicator
Notes:
1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only.
2. Tape and Reel.
3. Pb-Free package is recommended for new designs.
28-Pin PLCC (J28-1)
VCC
VEE
/EN
VBB
/IN
Q
2
26
27
28
1
2
3
4
18
17
16
15
14
13
12
25 24 23 22 21 20 19
567891011
NC
IN
Q
6
/Q
6
Q3
/Q
1
PLCC
TOP VIEW
J28-1
/Q
2
/Q
0
Q
0
V
CCO
Q
1
/Q3
Q4
VCCO
/Q4
Q5
/Q5
Q
7
V
CCO
/Q
7
Q
8
/Q
8
3
SY10E111
SY100E111
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = –40°CT
A = 0°CT
A = +25°CT
A = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
tPD Propagation Delay to ps
Output
IN (differential)(1) 430 630 430 630 430 630
IN (single-ended)(2) 330 730 330 730 330 730
Enable(3) 450 850 450 850 450 850
Disable(3) 450 850 450 850 450 850
tSKEW Within-Device Skew(4) 25 50 25 50 25 50 ps
tSSet-up Time
/EN to IN(5) 200 0 200 0 200 0 ps
tHHold Time
IN to /EN(6) 0200 0200 0200 ps
tRRelease Time
/EN to IN(7) 300 100 300 100 300 100 ps
VPP Minimum Input Swing(8) 250 ——250 ——250 ——mV
VCMR Common Mode Range(9) 1.6 —–0.4 1.6 —–0.4 1.6 —–0.4 V
trRise/Fall Times 275 375 600 275 375 600 275 375 600 ps
tf(20% to 80%)
Notes:
1. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential
output signals.
2. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
3. Enable is defined as the propagation delay from the 50% point of a negative transition on /EN to the 50% point of a positive transition on Q (or a negative
transition on /Q). Disable is defined as the propagation delay from the 50% point of a positive transition on /EN to the 50% point of a negative transition
on Q (or a positive transition on /Q).
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device.
5. The set-up time is the minimum time that /EN must be asserted prior to the next transition of /IN/IN to prevent an output response greater than ±75mV
to that /IN/IN transition (see Figure 1).
6. The hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response greater
than ±75mV to that IN, /IN transition (see Figure 2).
7. The release time is the minimum time that /EN must be de-asserted prior to the next IN, /IN transition to ensure an output response that meets the specified
IN to Q propagation delay and output transition times (see Figure 3).
8. VPP (min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP (min.) is AC limited for the
E111, as a differential input as low as 50mV will still produce full ECL levels at the output.
9. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be
such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP (min.).
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = VCCO = GND
TA = –40°CT
A = 0°CT
A = +25°CT
A = +85°C
Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
VBB Output Reference V
Voltage 10E 1.38 —–1.27 1.35 —–1.25 1.31 —–1.19
100E 1.38 —–1.26 1.38 —–1.26 1.38 —–1.26
IIH Input HIGH Current ——150 ——150 ——150 µA
IEE Power Supply mA
Current 10E 48 60 48 60 48 60
100E 48 60 48 60 55 69
DC ELECTRICAL CHARACTERISTICS
4
SY10E111
SY100E111
Micrel, Inc.
M9999-032006
hbwhelp@micrel.com or (408) 955-1690
28-PIN PLCC (J28-1)
Rev. 03
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB http://www.micrel.com
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Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
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© 2006 Micrel, Incorporated.