HMPP-389x Series
MiniPak Surface Mount RF PIN Switch Diodes
Data Sheet
Description/Applications
These ultra-miniature products represent the blending of
Avago Technologies’ proven semiconductor and the latest
in leadless packaging technology.
The HMPP-389x series is optimized for switching applications
where low resistance at low current and low capacitance
are required. The MiniPak package oers reduced parasitics
when compared to conventional leaded diodes, and lower
thermal resistance.
Low junction capacitance of the PIN diode chip, combined
with ultra low package parasitics, mean that these prod-
ucts may be used at frequencies which are higher than
the upper limit for conventional PIN diodes.
Note that Avago’s manufacturing techniques assure that
dice packaged in pairs are taken from adjacent sites on
the wafer, assuring the highest degree of match.
The HMPP-389T low inductance wide band shunt switch
is well suited for applications up to 6 GHz.
Minipak 1412 is a ceramic based package, while Minipak
QFN is a leadframe based package.
Package Lead Code Identication (Top View)
Features
• Surface mount MiniPak package
• Better thermal conductivity for higher power dissipa-
tion
• Single and dual versions
• Matched diodes for consistent performance
• Low capacitance
• Low resistance at low current
• Low FIT (Failure in Time) rate*
• Six-sigma quality level
* For more information, see the Surface Mount Schottky Reliability
Data Sheet.
Pin Connections and Package Marking
Notes:
1. Package marking provides orientation and
identication.
2. See “Electrical Specications” for appropri-
ate package marking.
3
2
Product code Date code
4
AA
1
Single
3
2
4
1
#0
Anti-parallel
3
2
4
1
#2
Parallel
3
2
4
1
#5
(Minipak 1412) (Minipak 1412) (Minipak 1412)
Shunt Switch
3
2
4
1
T
Anode Cathode
Cathode Anode
2
HMPP-389x Series Absolute Maximum Ratings[1], TC = 25°C
MiniPak 1412 /
Symbol Parameter Units MiniPak QFN
If Forward Current (1 µs pulse) Amp 1
PIV Peak Inverse Voltage V 100
Tj Junction Temperature °C 150
Tstg Storage Temperature °C -65 to +150
qjc Thermal Resistance[2] °C/W 150
Notes:
1. Operation in excess of any one of these conditions may result in permanent damage to the
device.
2. TC = +25°C, where TC is dened to be the temperature at the package pins where contact is
made to the circuit board.
MiniPak1412
Electrical Specications, TC = +25°C, each diode
Part Number Package Minimum Breakdown Maximum Series Maximum Total
HMPP- Marking Code Lead Code Conguration Voltage (V) Resistance (Ω) Capacitance (pF)
3890 D 0 Single 100 2.5 0.30
3892 C 2 Anti-parallel
3895 B 5 Parallel
389T T T Shunt Switch
Test Conditions VR = VBR IF = 5 mA VR = 5V
Measure IR ≤ 10 µA f = 100 MHz f = 1 MHz
ESD WARNING:
Handling Precautions Should Be Taken
To Avoid Static Discharge.
MiniPak1412
Typical Parameters, TC = +25°C
Part Number Series Resistance Carrier Lifetime Total Capacitance
HMPP- RS (Ω) τ (ns) CT (pF)
389x 3.8 200 0.20 @ 5 V
Test Conditions IF = 1 mA IF = 10 mA
f = 100 MHz IR = 6 mA
3
MiniPak 1412 HMPP-389x Series Typical Performance
TC = +25 °C (unless otherwise noted), each diode
120
115
110
105
100
95
90
85
1 10 30
IF – FORWARD BIAS CURRENT (mA)
Figure 3. 2nd Harmonic Input Intercept Point
vs. Forward Bias Current.
INPUT INTERCEPT POINT (dBm)
Diode Mounted as a
Series Attenuator in a
50 Ohm Microstrip and
Tested at 123 MHz
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15 0 4 8 12 16 20
VR – REVERSE VOLTAGE (V)
TOTAL CAPACITANCE (pF)
1 MHz
1 GHz
Figure 2. Capacitance vs. Reverse Voltage.
200
160
120
80
40
010 2015 25 30
Trr – REVERSE RECOVERY TIME (nS)
FORWARD CURRENT (mA)
Figure 4. Typical Reverse Recovery Time vs.
Reverse Voltage.
VR = –2V
VR = –5V
VR = –10V
100
10
1
0.1
0.01 0 0.2 0.4 0.6 0.8 1.0 1.2
IF – FORWARD CURRENT (mA)
VF – FORWARD VOLTAGE (V)
Figure 5. Forward Current vs. Forward Voltage.
125 C 25 C –50 C
Intercept point
will be higher
at higher
frequencies
Figure 1. Total RF Resistance at 25 C vs.
Forward Bias Current.
10
1
RF RESISTANCE (OHMS)
IF – FORWARD BIAS CURRENT (mA)
0.1 1 10 100
4
RF COMMON
RF 2
RF 1
BIAS
2
34
12
34
1
3
41
2
Figure 8. Very High Isolation SPDT Switch, Dual Bias.
Typical Applications
RF COMMON
RF 1
1
23
4
BIAS 1
RF 2
BIAS 2
RF COMMON
RF 2
BIAS
RF 1
2
3 4
12
34
1
Figure 6. Simple SPDT Switch Using Only Positive Bias. Figure 7. High Isolation SPDT Switch Using Dual Bias.
Bulk Attenuator Diode
Epi Switching Diode
P+ Diffusion
Bulk
I-Layer
N+ Diffusion
Metal Contact
Contact Over
P+ Diffusion
N+ Substrate
Epi
I-Layer
Figure 9. PIN Diode Construction.
Applications Information
PIN Diodes
In RF and microwave networks, mechanical switches and
attenuators are bulky, often unreliable, and dicult to
manufacture. Switch ICs, while convenient to use and
low in cost in small quantities, suer from poor distortion
performance and are not as cost eective as PIN diode
switches and attenuators in very large quantities. For over
30 years, designers have looked to the PIN diode for high
performance/low cost solutions to their switching and
level control needs.
In the RF and microwave ranges, the switch serves the
simple purpose which is implied by its name; it operates
between one of two modes, ON or OFF. In the ON state,
the switch is designed to have the least possible loss. In
the OFF state, the switch must exhibit a very high loss
(isolation) to the input signal, typically from 20 to 60 dB.
The attenuator, however, serves a more complex func-
tion. It provides for the “soft” or controlled variation in the
power level of a RF or microwave signal. At the same time
as it attenuates the input signal to some predetermined
value, it must also present a matched input impedance
(low VSWR) to the source. Every microwave network which
uses PIN diodes (phase shifter, modulator, etc.) is a varia-
tion on one of these two basic circuits.
One can see that the switch and the attenuator are quite
dierent in their function, and will therefore often require
dierent characteristics in their PIN diodes. These proper-
ties are easily controlled through the way in which a PIN
diode is fabricated. See Figure 14.
5
Diode Construction
At Avago Technologies, two basic methods of diode fabri-
cation are used. In the case of bulk diodes, a wafer of very
pure (intrinsic) silicon is heavily doped on the top and
bottom faces to form P and N regions. The result is a diode
with a very thick, very pure I region. The epitaxial layer (or
EPI) diode starts as a wafer of heavily doped silicon (the
P or N layer), onto which a thin I layer is grown. After the
epitaxial growth, diusion is used to add a heavily doped
(N or P) layer on the top of the epi, creating a diode with
a very thin I layer populated by a relatively large number
of imperfections.
These two different methods of design result in two
classes of diode with distinctly dierent characteristics,
as shown in Table 1.
Table 1. Bulk and EPI Diode Characteristics.
Characteristic EPI Diode Bulk Diode
Lifetime Short Long
Distortion High Low
Current Required Low High
I Region Thickness Very Thin Thick
As we shall see in the following paragraphs, the bulk diode
is almost always used for attenuator applications and
sometimes as a switch, while the epi diode (such as the
HMPP-3890) is generally used as a switching element.
Diode Lifetime and Its Implications
The resistance of a PIN diode is controlled by the conductiv-
ity (or resistivity) of the I layer. This conductivity is controlled
by the density of the cloud of carriers (charges) in the I layer
(which is, in turn, controlled by the DC bias). Minority car-
rier lifetime, indicated by the Greek symbol τ, is a measure
of the time it takes for the charge stored in the I layer to
decay, when forward bias is replaced with reverse bias, to
some predetermined value. This lifetime can be short (35
to 200 nsec. for epitaxial diodes) or it can be relatively long
(400 to 3000 nsec. for bulk diodes). Lifetime has a strong
inuence over a number of PIN diode parameters, among
which are distortion and basic diode behavior.
To study the eect of lifetime on diode behavior, we rst
dene a cutofrequency fC = 1/τ. For short lifetime diodes,
this cuto frequency can be as high as 30 MHz while for
our longer lifetime diodes fC ≅ 400 KHz. At frequencies
which are ten times fC (or more), a PIN diode does indeed
act like a current controlled variable resistor. At frequen-
cies which are one tenth (or less) of fC, a PIN diode acts
like an ordinary PN junction diode. Finally, at 0.1fC ≤ f ≤
10fC, the behavior of the diode is very complex. Suce it
to mention that in this frequency range, the diode can
exhibit very strong capacitive or inductive reactance — it
will not behave at all like a resistor. However, at zero bias
or under heavy forward bias, all PIN diodes demonstrate
very high or very low impedance (respectively) no matter
what their lifetime is.
Diode Resistance vs. Forward Bias
If we look at the typical curves for resistance vs. forward
current for bulk and epi diodes (see Figure 15), we see
that they are very dierent. Of course, these curves apply
only at frequencies > 10 fC. One can see that the curve
of resistance vs. bias current for the bulk diode is much
higher than that for the epi (switching) diode. Thus, for a
given current and junction capacitance, the epi diode will
always have a lower resistance than the bulk diode. The
thin epi diode, with its physically small I region, can easily
be saturated (taken to the point of minimum resistance)
with very little current compared to the much larger bulk
diode. While an epi diode is well saturated at currents
around 10 mA, the bulk diode may require upwards of
100 mA or more. Moreover, epi diodes can achieve rea-
sonable values of resistance at currents of 1 mA or less,
making them ideal for battery operated applications.
Having compared the two basic types of PIN diode, we
will now focus on the HMPP-3890 epi diode.
Given a thin epitaxial I region, the diode designer can
trade o the device’s total resistance (RS + Rj) and junction
capacitance (Cj) by varying the diameter of the contact
and I region. The HMPP-3890 was designed with the 930
MHz cellular and RFID, the 1.8 GHz PCS and 2.45 GHz RFID
markets in mind. Combining the low resistance shown
in Figure 15 with a typical total capacitance of 0.27 pF, it
forms the basis for high performance, low cost switching
networks.
Figure 10. Resistance vs. Forward Bias.
1000
100
10
1
RESISTANCE ( )
BIAS CURRENT (mA)
0.01 0.1 1 10 100
HMPP-389x
Epi PIN Diode
HSMP-3880 Bulk PIN Diode
Figure 10. Resistance vs, Forward Bias.
6
Linear Equivalent Circuit
In order to predict the performance of the HMPP-3890 as
a switch, it is necessary to construct a model which can
then be used in one of the several linear analysis programs
presently on the market. Such a model is given in Figure
16, where RS + Rj is given in Figure 1 and Cj is provided
in Figure 2. Careful examination of Figure 16 will reveal
the fact that the package parasitics (inductance and ca-
pacitance) are much lower for the MiniPak than they are
for leaded plastic packages such as the SOT-23, SOT-323
or others. This will permit the HMPP-389x family to be
used at higher frequencies than its conventional leaded
counterparts.
APLAC parameter can be obtained at http://www.
hp.woodshot.com/hprfhelp/design/SPICE/pins.
htm#HSMP389x website
Figure 11a. Linear Equivalent Circuit of the MiniPak 1412 PIN Diode.
7
Figure 13. Soldering details of connector ngers to upper ground plane.
Figure 14. Soldering details of connector ngers to lower ground plane.
Demo-board Preparation
Since the performance of the shunt switch is ultimately
limited by the demo-board, a short discussion of the
constructional aspects will be benecial. Edge-mounted
SMA connectors (Johnson #142-0701-881) were mounted
on both the reference and test lines. A special mounting
technique has been used to minimize reection at the pcb
to connector interface. Prior to mounting, the connector
pins were cut down to two pin diameters in length. Subse-
quently, the connector ngers were soldered to the upper
ground plane (Figure 18). Solder was lled between the
connector body and ngers on the lower ground plane
until the small crescent of exposed teon was completely
covered (Figure 19).
Test Results
Measurements of the reference line’s return and insertion
losses were used to gauge the eectiveness of the VSWR
mitigating steps. In our prototype, the worst case return
loss of the reference line was 20 dB at 5 GHz (Figure 20).
Figure 15. Swept Return Loss of Reference
Line.
FREQUENCY (GHz)
RETURN LOSS (dB)
1 62 4 53
-18
-22
-26
-30
-34
-38
Figure 12. Demo-board DEMO-HMPP-389T.
test line
reference line
Agilent
SK063A
HMPP-389T
Testing the HMPP-389T on the Demo-board
Introduction
The HMPP-389T PIN diode is a high frequency shunt switch.
It has been designed as a smaller and higher performance
version of the HSMP-389T (SC-70 package).
The DEMO-HMPP-389T demo-board allows customers
to evaluate the performance of the HMPP-389T without
having to fabricate their own PCB. Since a shunt switch’s
isolation is limited primarily by its parasitic inductance, the
product’s true potential cannot be shown if a conventional
microstrip pcb is used. In order to overcome this problem,
a coplanar waveguide over ground-plane structure is
used for the demo-board. The bottom ground-plane is
connected to the upper ground traces using multiple
via-holes.
A 50Ω reference line is provided at the top to calibrate the
board loss. The bottom line allows the HMPP-389T diode
to be tested as a shunt switch.
Figure 15. Swept return loss of reference line.
8
To evaluate the HMPP-389T as shunt switch, it was
mounted on the test line and then the appropriate bias-
ing voltage was applied. In our prototype, the worst case
return loss was 10 dB at 5 GHz (Figure 22). The return loss
varied very little when the bias was changed from zero
to -20V. Figure 19.
Insertion loss of HMPP-389T at -20V.
The PIN diode’s resistance is a function of the bias current.
So, at higher forward current, the isolation improved.
The combination of the HMPP-389T and the SK063A
demoboard exhibited more than 17 dB of isolation from
1 to 6 GHz at If ≥ 1mA (Figure 25).
Figure 17. Return Loss of HMPP-389T
Mounted on Test Line at 0V and -20V Bias.
FREQUENCY (GHz)
RETURN LOSS (dB)
-5
-15
-25
-35
-45
-55
1 62 4 53
Figure 18. Insertion Loss of HMPP-389T at
0V.
FREQUENCY (GHz)
INSERTION LOSS (dB)
0
-0.2
-0.4
-0.6
-0.8
-1.0
1 62 4 53
Figure 19. Insertion Loss of HMPP-389T at
-20V.
FREQUENCY (GHz)
INSERTION LOSS (dB)
1 62 4 53
0
-0.2
-0.4
-0.6
-0.8
-1.0
Figure 20. Isolation at Different Frequencies
with Forward Current as a Parameter.
FREQUENCY (GHz)
ISOLATION (dB)
-10
-14
-18
-22
-26
-30
1 62
0.15 mA
0.25 mA
0.5 mA
1 mA
1.5 mA
20 mA
4 53
Figure 18. Return loss of HMPP-389T mounted on test line at 0V and -20V
bias.
Normalization was used to remove the pcb’s and connec-
tors’ losses from the measurement of the shunt switch’s
loss. The active trace was divided by the memorized
trace (Data/Memory) to produce the normalized data.
At zero bias, the insertion loss was under 0.6 dB up to 6
GHz (Figure 23). Applying a reverse bias to the PIN diode
has the eect of reducing its parasitic capacitance. With a
reverse bias of -20V, the insertion loss improved to better
than 0.5 dB (Figure 24).
Figure 18. Insertion loss of HMPP-389T at 0V.
Figure 20. Isolation at dierent frequencies with forward current as a
parameter.
The combination of the HMPP-389T and the demo-board
allows a high performance shunt switch to be constructed
swiftly and economically. The extremely low parasitic
inductance of the package allows the switch to operate
over a very wide frequency range.
Figure 16. Insertion Loss of Reference
Line.
FREQUENCY (GHz)
INSERTION LOSS (dB)
0
-0.2
-0.4
-0.6
-0.8
-1.0
1 62 4 53
Figure 16. Insertion loss of reference line.
Insertion loss of the reference was very low and generally,
increased with frequency (Figure 21). If the demo-board
has been constructed carefully, there should not be any
evidence of resonance. The reference line’s insertion loss
trace can be stored in the VNA’s display memory and
used to correct for the insertion loss of the test line in the
subsequent measurements.
9
Assembly Information
The MiniPak diode is mounted to the PCB or microstrip
board using the pad pattern shown in Figure 26.
SMT Assembly
Reliable assembly of surface mount components is a com-
plex process that involves many material, process, and
equipment factors, including: method of heating (e.g., IR
or vapor phase reow, wave soldering, etc.) circuit board
material, conductor thickness and pattern, type of solder
alloy, and the thermal conductivity and thermal mass of
components. Components with a low mass, such as the
MiniPak package, will reach solder reow temperatures
faster than those with a greater mass.
After ramping up from room temperature, the circuit
board with components attached to it (held in place with
solder paste) passes through one or more preheat zones.
The preheat zones increase the temperature of the board
and components to prevent thermal shock and begin
evaporating solvents from the solder paste. The reow
zone briey elevates the temperature suciently to pro-
duce a reow of the solder.
The rates of change of temperature for the ramp-up and
cool-down zones are chosen to be low enough to not
cause deformation of the board or damage to compo-
nents due to thermal shock. The maximum temperature
in the reow zone (TMAX) should not exceed 260°C.
These parameters are typical for a surface mount assembly
process for Avago diodes. As a general guideline, the
circuit board and components should be exposed only
to the minimum temperatures and times necessary to
achieve a uniform reow of solder.
0.4 0.4
0.3
0.5
0.3
0.5
2.60
0.40
0.20
0.40 mm via hole
(4 places)
0.8 2.40
Figure 21. PCB Pad Layout, MiniPak (dimensions in mm).
This mounting pad pattern is satisfactory for most
applications. However, there are applications where a
high degree of isolation is required between one diode
and the other is required. For such applications, the
mounting pad pattern of Figure 27 is recommended.
Figure 22. PCB Pad Layout, High Isolation MiniPak (dimensions in mm).
This pattern uses four via holes, connecting the crossed
ground strip pattern to the ground plane of the board.
10
MiniPak 1412 Outline Drawing for HMPP-3890, -3892, and -3895
1.44 (0.057)
1.40 (0.055)
Top view
Side view
Dimensions are in millimeters (inches)
Bottom view
1.20 (0.047)
1.16 (0.046)
0.70 (0.028)
0.58 (0.023)
1.12 (0.044)
1.08 (0.043)
0.82 (0.032)
0.78 (0.031)
0.32 (0.013)
0.28 (0.011)
-0.07 (-0.003)
-0.03 (-0.001)
0.00
-0.07 (-0.003)
-0.03 (-0.001)
0.42 (0.017)
0.38 (0.015)
0.92 (0.036)
0.88 (0.035)
1.32 (0.052)
1.28 (0.050)
0.00
MiniPak 1412 Outline Drawing for HMPP-389T
Dimensions are in millimeters (inches)
Bottom view
1.12 (0.044)
1.08 (0.043)
0.82 (0.032)
0.78 (0.031)
0.32 (0.013)
0.28 (0.011)
-0.07 (-0.003)
-0.03 (-0.001)
0.00
-0.07 (-0.003)
-0.03 (-0.001)
0.42 (0.017)
0.38 (0.015)
0.92 (0.036)
0.88 (0.035)
1.32 (0.052)
1.28 (0.050)
0.00
11
Ordering Information
Part Number No. of Devices Container
HMPP-389x-TR2 10000 13” Reel
HMPP-389x-TR1 3000 7”Reel
HMPP-389x-BLK 100 antistatic bag
Device Orientation
USER
FEED
DIRECTION
COVER TAPE
CARRIER
TAPE
REEL
END VIEW
8 mm
4 mm
TOP VIEW
AA
AA
AA
AA
Note: “AA” represents package marking code. Package marking is
right side up with carrier tape perforations at top. Conforms to
Electronic Industries RS-481, “Taping of Surface Mounted
Components for Automated Placement.” Standard quantity is 3,000
devices per reel.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2009 Avago Technologies . All rights reserved. Obsoletes 5989-3630EN
AV02-0653EN - August 5, 2009
Tape Dimensions and Product Orientation
For Outline 4T (MiniPak 1412)
P
P0
P2
F
W
C
D1
D
E
A0
5°MAX.
t1(CARRIER TAPE THICKNESS) T t(COVER TAPE THICKNESS)
5°MAX.
B0
K0
DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)
LENGTH
WIDTH
DEPTH
PITCH
BOTTOM HOLE DIAMETER
A0
B0
K0
P
D1
1.40 ±0.05
1.63 ±0.05
0.80 ±0.05
4.00 ±0.10
0.80 ±0.05
0.055 ±0.002
0.064 ±0.002
0.031 ±0.002
0.157 ±0.004
0.031 ±0.002
CAVITY
DIAMETER
PITCH
POSITION
D
P0
E
1.50 ±0.10
4.00 ±0.10
1.75 ±0.10
0.060 ±0.004
0.157 ±0.004
0.069 ±0.004
PERFORATION
WIDTH
THICKNESS
W
t1
8.00 + 0.30 - 0.10
0.254 ±0.02
0.315 + 0.012 - 0.004
0.010 ±0.001
CARRIER TAPE
CAVITY TO PERFORATION
(WIDTH DIRECTION)
CAVITY TO PERFORATION
(LENGTH DIRECTION)
F
P2
3.50 ±0.05
2.00 ±0.05
0.138 ±0.002
0.079 ±0.002
DISTANCE
WIDTH
TAPE THICKNESS
C
Tt
5.40 ±0.10
0.062 ±0.001
0.213 ±0.004
0.002 ±0.00004
COVER TAPE