LM4985, LM4985TMEVAL
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LM4985 Boomer™ Audio Power Amplifier Series Stereo 135mW Low Noise Headphone
Amplifier with Selectable Capacitively Coupled or Output Capacitor-less (OCL) Output
and Digitally Controlled (I
2
C) Volume Control
Check for Samples: LM4985,LM4985TMEVAL
1FEATURES DESCRIPTION
The LM4985 is a stereo audio power amplifier with
23• OCL or Capacitively Coupled Outputs (Patent internal digitally controlled volume control. This
Pending) amplifier is capable of delivering 68mWRMS per
• I2C Digitally Controlled Volume Control channel into a 16Ωload or 38mWRMS per channel
• Available in Space-Saving 0.4mm Lead-Pitch into a 32Ωload at 1% THD when powered by a 3.6V
power supply and operating in the OCL mode.
DSBGA Package
• Volume Control Range: –76dB to +18dB Boomer audio power amplifiers were designed
specifically to provide high quality output power with a
• Ultra Low Current Shutdown Mode minimal amount of external components. To that end,
• 2.3V - 5.5V Operation the LM4985 features two functions that optimize
• Ultra Low Noise system cost and minimize PCB area: an integrated,
digitally controlled (I2C bus) volume control and an
APPLICATIONS operational mode that eliminates output signal
coupling capacitors (OCL mode). Since the LM4985
• Mobile Phones does not require bootstrap capacitors, snubber
• PDAs networks, or output coupling capacitors, it is optimally
suited for low-power, battery powered portable
• Portable Electronics Devices systems. For added design flexibility, the LM4985 can
• MP3 Players also be configured for single-ended capacitively
coupled outputs.
KEY SPECIFICATIONS (VDD = 3.6V) The LM4985 features a current shutdown mode for
• PSRR: 217Hz and 1kHzs micropower dissipation and thermal shutdown
– Output Capacitor-Less (OCL) protection.
– fRIPPLE = 217Hz, 77dB (Typ)
– fRIPPLE = 1kHz, 76dB (Typ)
– Capacitor Coupled (C-CUPL)
– fRIPPLE = 217Hz, 63dB (Typ)
– fRIPPLE = 1kHz, 62dB (Typ)
• Output Power Per Channel
(fIN = 1kHz, THD+N = 1%),
RL= 16Ω, OCL
– VDD = 2.5V, 31mW (Typ)
– VDD = 3.6V, 68mW (Typ)
– VDD = 5.0V, 135mW (Typ)
• THD+N (f = 1kHz)
– RLOAD = 16Ω, OCL, POUT = 60mW, 0.60
– RLOAD = 32Ω, OCL, POUT = 33mW, 0.031
• Shutdown Current, 0.1µA (Typ)
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Boomer is a trademark of Texas Instruments.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2006–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Controlled
Analog Volume
Control
Interface
Output
Transient
Suppression
and
Mode-Control
Logic
Bias
Generator
-
+
-
+
-
+
Volume
Control
Volume
Control
IN1
BYPASS
IN2
GND
0.47 PF
0.47 PF100 PF
100 PF
CNTGND
OUT2
OUT1
VDD
I2C Digitally
Mux
Mux
Digital
Control
System
Controlled
Analog Volume
Control
Interface
Output
Transient
Suppression
and
Mode-Control
Logic
Bias
Generator
-
+
-
+
-
+
Volume
Control
Volume
Control
I2C Digitally
Mux
Mux
IN1
BYPASS
IN2
SDA
SCL
I2CVDD
VDD
GND
OUT2
CNTGND
OUT1
ADR
LM4985, LM4985TMEVAL
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Block Diagram
Figure 1. Block Diagram
Typical Application
Figure 2. Typical Capacitively Coupled Output Configuration Circuit
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1
2
3
DCBA
Controlled
Analog Volume
Control
Interface
Output
Transient
Suppression
and
Mode-
Control Logic
Bias
Generator
-
+
-
+
-
+
Volume
Control
Volume
Control
IN1
BYPASS
IN2
GND
0.47 PF
0.47 PF
CNTGND
OUT2
OUT1
VDD
I2C Digitally
Mux
Mux
Digital
Control
System
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Figure 3. Typical OCL Output Configuration Circuit
Connection Diagram
Figure 4. DSBGA Package
Top View
See NS Package Number YFQ0012
PIN REFERENCE, NAME, AND FUNCTION
Reference Name Function
A1 ADR I2C serial interface address input.
A2 IN2 Analog signal input two.
A3 OUT2 Power amplifier two output.
B1 SDA I2C serial interface data input.
B2 BYPASS The internal VDD/2 ac bypass node.
B3 CNTGND In OCL mode, this is the ac ground return. It is biased to VDD/2. Leave unconnected for C-
CUPL mode.
C1 SCL I2C serial interface clock input.
C2 GND The LM4985’s power supply ground input.
C3 VDD The LM4985’s power supply voltage input.
D1 I2CVDD I2C serial interface power supply input. Can be connected to the same supply that is
connected to the VDD pin.
D2 IN1 Analog signal input one.
D3 OUT1 Power amplifier one output.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage (VDD, I2CVDD) 6.0V
Storage Temperature −65°C to +150°C
Input Voltage (IN1, IN2, OUT1, OUT2, BYPASS, CNTGND, GND
pins relative to the VDD pin) -0.3V to VDD + 0.3V
Input Voltage (ADR, SDA, SCL pins, relative to the I2CVDD pin) -0.3V to I2CVDD + 0.3V
Power Dissipation(3) Internally Limited
ESD Susceptibility(4) 2000V
ESD Susceptibility(5) 200V
Junction Temperature 150°C
Thermal Resistance θJA 109°C/W
(1) All voltages are measured with respect to the GND pin unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX,θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA)/ θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM4985, see power derating currents for more information.
(4) Human Body Model: 100pF discharged through a 1.5kΩresistor.
(5) Machine Model: 200pF ≤Cmm ≤220pF discharged through all pins.
Operating Ratings
Temperature Range TMIN ≤TA≤TMAX −40°C ≤TA≤85°C
VDD 2.3V ≤VCC ≤5.5V
Supply Voltage I2CVDD 1.7V ≤I2CVDD ≤5.5V
Electrical Characteristics VDD = 5V(1)(2)
The following specifications apply for RL= 16Ω, f = 1kHz, and CB= 4.7µF unless otherwise specified. Limits apply to TA=
25°C.Symbol Parameter Conditions LM4985 Units
(Limits)
Typ(3) Limit(4)(5)
VIN = 0V, IOUT = 0A
Single-Channel no load OCL 2
IDD Quiescent Power Supply Current Single-Channel no load C-CUPL 1.5 mA (max)
Dual-Channel no load OCL 3 4.9
Dual-Channel no load C-CUPL 2.3 3.8
ISD Shutdown Current VSHUTDOWN = GND 0.1 1.0 µA (max)
VSDIH Logic Voltage Input High 3.5 V (min)
VSDIL Logic Voltage Input Low 1.5 V (max)
(1) All voltages are measured with respect to the GND pin unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
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Electrical Characteristics VDD = 5V(1)(2) (continued)
The following specifications apply for RL= 16Ω, f = 1kHz, and CB= 4.7µF unless otherwise specified. Limits apply to TA=
25°C.Symbol Parameter Conditions LM4985 Units
(Limits)
Typ(3) Limit(4)(5)
THD ≤1%; fIN = 1kHz
RLOAD = 16ΩOCL 135 115
POOutput Power RLOAD = 16ΩC-CUPL 135 mW (min)
RLOAD = 32ΩOCL 79 70
RLOAD = 32ΩC-CUPL 80
RLOAD = 16ΩOCL, PO= 100mW 0.08
RLOAD = 16ΩC-CUPL, PO= 100mW 0.02
THD+N Total Harmonic Distortion + Noise %
RLOAD = 32ΩOCL, PO= 60mW 0.04
RLOAD = 32ΩC-CUPL, PO= 70mW 0.01
VON Output Noise Voltage VIN = AC GND, AV= 0dB, A-weighted 15 µV
VRIPPLE = 200mVp-p(6)
fIN = 217Hz sinewave 57
OCL 77
C-CUPL 65
PSRR Power Supply Rejection Ratio dB (min)
fIN = 1kHz sinewave
OCL 77 60
C-CUPL 65
Pout = 40mW. OCL
RLOAD = 16Ω51 dB
RLOAD= 32Ω56
Xtalk Channel-to-channel Crosstalk Pout = 50mW. C-CUPL
RLOAD = 16Ω58 dB
RLOAD= 32Ω68
CBYPASS= 4.7μF(7)
WT1 = 0, WT0 = 0
OCL 75
C-CUPL 285
WT1 = 0, WT0 = 1
OCL 110
TWU Wake Up Time form Shutdown C-CUPL 530 msec
WT1 = 1, WT0 = 0
OCL 180
C-CUPL 1030
WT1 = 1, WT0 = 1
OCL 320
C-CUPL 2050
Stereo mode 20
RIN Input Resistance kΩ
Mono mode 10
AVMIN Minimum Gain Code = 00000 –76 dB (min)
AVMAX Maximum Gain Code = 11111 18 dB (min)
18dB ≥AV≥–44dB ±0.5
ΔAVGain Accuracy per Step dB
–44dB ≥AV> –76dB ±1.0
OCL
VOS Output Offset Voltage RLOAD = 32Ω2.0 20 mV (max)
VIN = AC GND
(6) 10Ωterminated input.
(7) The wake-up time (TWU) is calculated using the following formula; TWU = [CBYPASS (VDD) / 2 (IBYPASS)] + 40ms.
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Electrical Characteristics VDD = 3.6V(1)(2)
The following specifications apply for RL= 16Ω, f = 1kHz, and CB= 4.7µF unless otherwise specified. Limits apply to TA=
25°C.Symbol Parameter Conditions LM4985 Units
(Limits)
Typ(3) Limit(4)(5)
VIN = 0V, IOUT = 0A
Single-Channel no load OCL 1.8 3.1
IDD Quiescent Power Supply Current Single-Channel no load C-CUPL 1.0 mA (max)
Dual-Channel no load OCL 2.1 4
Dual-Channel no load C-CUPL 2.3 3
ISD Shutdown Current VSHUTDOWN = GND 0.1 1.0 µA (max)
VSDIH Logic Voltage Input High 2.52 V (min)
VSDIL Logic Voltage Input Low 1.08 V (max)
THD+N < 1%, fIN = 1kHz
RLOAD = 16ΩOCL 68 60
POOutput Power RLOAD = 16ΩC-CUPL 70 mW (min)
RLOAD = 32ΩOCL 38 34
RLOAD = 32ΩC-CUPL 41
RLOAD = 16ΩOCL, PO= 60mW 0.06
RLOAD = 16ΩC-CUPL, PO= 60mW 0.03
THD+N Total Harmonic Distortion + Noise %
RLOAD = 32ΩOCL, PO= 33mW 0.03
RLOAD = 32ΩC-CUPL, PO= 38mW 0.03
VON Output Noise Voltage VIN = AC GND, AV= 0dB, A-weighted 15 µV
VRIPPLE = 200mVp-p(6)
fIN = 217Hz sinewave 55
OCL 77
C-CUPL 63
PSRR Power Supply Rejection Ratio dB (min)
fIN = 1kHz sinewave
OCL 76 57
C-CUPL 62
Pout = 40mW. OCL
RLOAD = 16Ω51 dB
RLOAD= 32Ω56
Xtalk Channel-to-Channel Crosstalk Pout = 50mW. C-CUPL
RLOAD = 16Ω58 dB
RLOAD= 32Ω69
(1) All voltages are measured with respect to the GND pin unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
(6) 10Ωterminated input.
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Electrical Characteristics VDD = 3.6V(1)(2) (continued)
The following specifications apply for RL= 16Ω, f = 1kHz, and CB= 4.7µF unless otherwise specified. Limits apply to TA=
25°C.Symbol Parameter Conditions LM4985 Units
(Limits)
Typ(3) Limit(4)(5)
CBYPASS= 4.7μF(7)
WT1 = 0, WT0 = 0
OCL 66 93
C-CUPL 222
WT1 = 0, WT0 = 1
OCL 92
TWU Wake Up Time from Shutdown C-CUPL 405 msec
WT1 = 1, WT0 = 0
OCL 143
C-CUPL 774
WT1 = 1, WT0 =1
OCL 246
C-CUPL 1532
Stereo mode 20
RIN Input Resistance kΩ
Mono mode 10
AVMIN Minimum Gain Code = 00000 –76 –72 dB (max)
AVMAX Maximum Gain Code = 11111 18 17 dB (min)
18dB ≥AV≥–44dB ± 0.5 ± 1.0
ΔAVGain Accuracy per Step dB
–44dB ≥AV> –76dB ± 1.0 ± 2.0
OCL
VOS Output Offset Voltage RLOAD = 32Ω2.0 20 mV (max)
VIN = AC GND
(7) The wake-up time (TWU) is calculated using the following formula; TWU = [CBYPASS (VDD) / 2 (IBYPASS)] + 40ms.
Electrical Characteristics VDD = 2.5V(1)(2)
The following specifications apply for RL= 16Ω, f = 1kHz, and CB= 4.7µF unless otherwise specified. Limits apply to TA=
25°C.Symbol Parameter Conditions LM4985 Units
(Limits)
Typ(3) Limit(4)(5)
VIN = 0V, IOUT = 0A
Single-Channel no load OCL 1.6
IDD Quiescent Power Supply Current Single-Channel no load C-CUPL 1 mA
Dual-Channel no load OCL 2.1
Dual-Channel no load C-CUPL 1.6
ISD Shutdown Current VSHUTDOWN = GND 0.1 µA
VSDIH Logic Voltage Input High 1.75 V (min)
VSDIL Logic Voltage Input Low 0.75 V (max)
THD+N < 1%, fIN = 1kHz
RLOAD = 16ΩOCL 31
POOutput Power RLOAD = 16ΩC-CUPL 33 mW
RLOAD = 32ΩOCL 19
RLOAD = 32ΩC-CUPL 19
(1) All voltages are measured with respect to the GND pin unless otherwise specified.
(2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
(3) Typicals are measured at 25°C and represent the parametric norm.
(4) Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
(5) Datasheet min/max specification limits are specified by design, test, or statistical analysis.
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Electrical Characteristics VDD = 2.5V(1)(2) (continued)
The following specifications apply for RL= 16Ω, f = 1kHz, and CB= 4.7µF unless otherwise specified. Limits apply to TA=
25°C.Symbol Parameter Conditions LM4985 Units
(Limits)
Typ(3) Limit(4)(5)
RLOAD = 16ΩOCL, PO= 26mW 0.07
RLOAD = 16ΩC-CUPL, PO= 20mW 0.05
THD+N Total Harmonic Distortion + Noise %
RLOAD = 32ΩOCL, PO= 16mW 0.06
RLOAD = 32ΩC-CUPL, PO= 15mW 0.04
VON Output Noise Voltage VIN = AC GND, AV= 0dB, A-weighted 10 µV
VRIPPLE = 200mVp-p(6)
fIN = 217Hz sinewave
OCL 75
C-CUPL 59
PSRR Power Supply Rejection Ratio dB
fIN = 1kHz sinewave
OCL 75
C-CUPL 59
Pout = 20mW, OCL
RLOAD = 16Ω50 dB
RLOAD= 32Ω55
Xtalk Channel-to-Channel Crosstalk Pout = 20mW. C-CUPL
RLOAD = 16Ω58 dB
RLOAD= 32Ω67
CBYPASS = 4.7µF(7)
WT1 = 0, WT0 = 0
OCL 66
C-CUPL 214
WT1 = 0, WT0 = 1
OCL 92
TWU Wake Up Time from Shutdown C-CUPL 544 msec
WT1 = 1, WT0 = 0
OCL 145
C-CUPL 1053
WT1 = 1, WT0 = 1
OCL 250
C-CUPL 2098
Stereo mode 20
RIN Input Resistance kΩ
Mono mode 10
AVMIN Minimum Gain Code = 00000 –76 dB
AVMAX Maximum Gain Code = 11111 18 dB
18dB ≥AV≥–44dB ± 0.5
ΔAVGain Accuracy per Step dB
–44dB ≥AV> –76dB ± 1.0
OCL
VOS Output Offset Voltage RLOAD = 32Ω2.0 mV
VIN = AC GND
(6) 10Ωterminated input.
(7) The wake-up time (TWU) is calculated using the following formula; TWU = [CBYPASS (VDD) / 2 (IBYPASS)] + 40ms.
External Components Description
(See Figure 2)
Components Functional Description
1. CIInput coupling capacitor which blocks the DC voltage at the amplifier's input terminals. Also creates a high-pass filter
with Riat fc= 1/(2πRiCi). Refer to the section Proper Selection of External Components, for an explanation of how to
determine the value of Ci.
2. CSSupply bypass capacitor which provides power supply filtering. Refer to the POWER SUPPLY BYPASSING section for
information concerning proper placement and selection of the supply bypass capacitor.
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Components Functional Description
3. CBBypass pin capacitor which provides half-supply filtering. Refer to the section, POWER SUPPLY BYPASSING, for
information concerning proper placement and selection of CB
6. CoOutput coupling capacitor which blocks the DC voltage at the amplifier's output. Forms a high pass filter with RLat fo=
1/(2πRLCo)
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20 100 1k 10k 20k
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
0.02
0.2
2
0.05
0.5
5
50 200 2k500 5k
20 100 1k 10k 20k
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
0.02
0.2
2
0.05
0.5
5
50 200 2k500 5k
20 100 1k 10k 20k
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
0.02
0.2
2
0.05
0.5
5
50 200 2k500 5k
20 100 1k 10k 20k
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
0.02
0.2
2
0.05
0.5
5
50 200 2k500 5k
20 100 1k 10k 20k
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
0.02
0.2
2
0.05
0.5
5
50 200 2k500 5k
20 100 1k 10k 20k
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
0.02
0.2
2
0.05
0.5
5
50 200 2k500 5k
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Typical Performance Characteristics
TA= 25°C, AV= 0dB, fIN = 1kHz unless otherwise stated.
THD+N vs Frequency THD+N vs Frequency
VDD = 2.5V, RL= 16ΩVDD = 3.6V, RL= 16Ω
POUT = 20mW, C-CUPL POUT = 50mW, C-CUPL
Figure 5. Figure 6.
THD+N vs Frequency THD+N vs Frequency
VDD = 5V, RL= 16ΩVDD = 2.5V, RL= 32Ω
POUT = 50mW, C-CUPL POUT = 15mW, C-CUPL
Figure 7. Figure 8.
THD+N vs Frequency THD+N vs Frequency
VDD = 3.6V, RL= 32ΩVDD = 5.0V, RL= 32Ω
POUT = 35mW, C-CUPL POUT = 60mW, C-CUPL
Figure 9. Figure 10.
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20 100 1k 10k 20k
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
0.02
0.2
2
0.05
0.5
5
50 200 2k500 5k
20 100 1k 10k 20k
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
0.02
0.2
2
0.05
0.5
5
50 200 2k500 5k
20 100 1k 10k 20k
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
0.02
0.2
2
0.05
0.5
5
50 200 2k500 5k
20 100 1k 10k 20k
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
0.02
0.2
2
0.05
0.5
5
50 200 2k500 5k
20 100 1k 10k 20k
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
0.02
0.2
2
0.05
0.5
5
50 200 2k500 5k
20 100 1k 10k 20k
0.01
0.1
1
10
THD+N (%)
FREQUENCY (Hz)
0.02
0.2
2
0.05
0.5
5
50 200 2k500 5k
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Typical Performance Characteristics (continued)
TA= 25°C, AV= 0dB, fIN = 1kHz unless otherwise stated.
THD+N vs Frequency THD+N vs Frequency
VDD = 2.5V, RL= 16ΩVDD = 3.6V, RL= 16Ω
POUT = 20mW, OCL POUT = 50mW, OCL
Figure 11. Figure 12.
THD+N vs Frequency THD+N vs Frequency
VDD = 5.0V, RL= 16ΩVDD = 2.5V, RL= 32Ω
POUT = 50mW, OCL POUT = 15mW, OCL
Figure 13. Figure 14.
THD+N vs Frequency THD+N vs Frequency
VDD = 3.6V, RL= 32ΩVDD = 5.0V, RL= 32Ω
POUT = 35mW, OCL POUT = 60mW, OCL
Figure 15. Figure 16.
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0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
THD+N (%)
10m 200m20m 30m 50m 100m
OUTPUT POWER (W)
OUTPUT POWER (W)
10m
100m
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10
THD+N (%)
20m
30m
40m
50m
60m
70m
80m
90m
10m
OUTPUT POWER (W)
0.01
0.1
1
10
THD+N (%)
0.02
0.2
2
0.05
0.5
5
200m
100m20m 30m40m
50m
60m
70m
7m 10m
OUTPUT POWER (W)
8m9m 20m
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10
THD+N (%)
30m 40m6m
OUTPUT POWER (W)
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
THD+N (%)
10m 100m20m 30m 50m
10m
OUTPUT POWER (W)
0.01
0.1
1
10
THD+N (%)
0.02
0.2
2
0.05
0.5
5
200m
100m20m 30m40m
50m
60m
70m
LM4985, LM4985TMEVAL
SNAS346C –MAY 2006–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (continued)
TA= 25°C, AV= 0dB, fIN = 1kHz unless otherwise stated.
THD+N vs Output Power THD+N vs Output Power
VDD = 2.5V, RL= 16ΩVDD = 3.6V, RL= 16Ω
C-CUPL C-CUPL
Figure 17. Figure 18.
THD+N vs Output Power THD+N vs Output Power
VDD = 5.0V, RL= 16ΩVDD = 2.5V, RL= 32Ω
C-CUPL C-CUPL
Figure 19. Figure 20.
THD+N vs Output Power THD+N vs Output Power
VDD = 3.6V, RL= 32ΩVDD = 5.0V, RL= 32Ω
C-CUPL C-CUPL
Figure 21. Figure 22.
12 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4985 LM4985TMEVAL
10m
OUTPUT POWER (W)
0.01
0.1
1
10
THD+N (%)
0.02
0.2
2
0.05
0.5
5
200m
100m20m 30m40m
50m
60m
70m
OUTPUT POWER (W)
10m
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10
THD+N (%)
20m
30m
40m
50m
60m
70m
80m
100m
10m
OUTPUT POWER (W)
0.01
0.1
1
10
THD+N (%)
0.02
0.2
2
0.05
0.5
5
200m
100m20m 30m40m
50m
60m
70m
OUTPUT POWER (W)
10m
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10
THD+N (%)
20m
30m
40m
50m
60m
70m
80m
100m
1m 10m 100m
OUTPUT POWER (W)
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10
THD+N (%)
2m 20m
5m 50m
1m 10m 100m
OUTPUT POWER (W)
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
10
THD+N (%)
2m 20m
5m 50m
LM4985, LM4985TMEVAL
www.ti.com
SNAS346C –MAY 2006–REVISED APRIL 2013
Typical Performance Characteristics (continued)
TA= 25°C, AV= 0dB, fIN = 1kHz unless otherwise stated.
THD+N vs Output Power THD+N vs Output Power
VDD = 2.5V, RL= 16ΩVDD = 3.6V, RL= 16Ω
OCL OCL
Figure 23. Figure 24.
THD+N vs Output Power THD+N vs Output Power
VDD = 5.0V, RL= 16ΩVDD = 2.5V, RL= 32Ω
OCL OCL
Figure 25. Figure 26.
THD+N vs Output Power THD+N vs Output Power
VDD = 3.6V, RL= 32ΩVDD = 5.0V, RL= 32Ω
OCL OCL
Figure 27. Figure 28.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LM4985 LM4985TMEVAL
20 20k
FREQUENCY (Hz)
-100
+0
PSRR (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
FREQUENCY (Hz)
-100
+0
PSRR (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
FREQUENCY (Hz)
-100
+0
PSRR (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
FREQUENCY (Hz)
-100
+0
PSRR (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
FREQUENCY (Hz)
-100
+0
PSRR (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
FREQUENCY (Hz)
-100
+0
PSRR (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
LM4985, LM4985TMEVAL
SNAS346C –MAY 2006–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (continued)
TA= 25°C, AV= 0dB, fIN = 1kHz unless otherwise stated.
PSRR vs Frequency PSRR vs Frequency
VDD = 2.5V, RL= 16ΩVDD = 3.6V, RL= 16Ω
VRIPPLE = 200mVpp, OCL VRIPPLE = 200mVpp, OCL
Figure 29. Figure 30.
PSRR vs Frequency PSRR vs Frequency
VDD = 5.0V, RL= 16ΩVDD = 2.5V, RL= 32Ω
VRIPPLE = 200mVpp, OCL VRIPPLE = 200mVpp, OCL
Figure 31. Figure 32.
PSRR vs Frequency PSRR vs Frequency
VDD = 3.6V, RL= 32ΩVDD = 5.0V, RL= 32Ω
VRIPPLE = 200mVpp, OCL VRIPPLE = 200mVpp, OCL
Figure 33. Figure 34.
14 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4985 LM4985TMEVAL
20 20k
FREQUENCY (Hz)
-100
+0
PSRR (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
FREQUENCY (Hz)
-100
+0
PSRR (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
FREQUENCY (Hz)
-100
+0
PSRR (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
FREQUENCY (Hz)
-100
+0
PSRR (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
FREQUENCY (Hz)
-100
+0
PSRR (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
FREQUENCY (Hz)
-100
+0
PSRR (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
LM4985, LM4985TMEVAL
www.ti.com
SNAS346C –MAY 2006–REVISED APRIL 2013
Typical Performance Characteristics (continued)
TA= 25°C, AV= 0dB, fIN = 1kHz unless otherwise stated.
PSRR vs Frequency PSRR vs Frequency
VDD = 2.5V, RL= 16ΩVDD = 3.6V, RL= 16Ω
VRIPPLE = 200mVpp, C-CUPL VRIPPLE = 200mVpp, C-CUPL
Figure 35. Figure 36.
PSRR vs Frequency PSRR vs Frequency
VDD = 5.0V, RL= 16ΩVDD = 2.5V, RL= 32Ω
VRIPPLE = 200mVpp, C-CUPL VRIPPLE = 200mVpp, C-CUPL
Figure 37. Figure 38.
PSRR vs Frequency PSRR vs Frequency
VDD = 3.6V, RL= 32ΩVDD = 5.0V, RL= 32Ω
VRIPPLE = 200mVpp, C-CUPL VRIPPLE = 200mVpp, C-CUPL
Figure 39. Figure 40.
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20 20k
FREQUENCY (Hz)
CROSSTALK (dB)
50 100 200 500 10k1k 2k 5k
+0
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
-70
20 20k
FREQUENCY (Hz)
CROSSTALK (dB)
50 100 200 500 10k1k 2k 5k
+0
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
-70
20 20k
FREQUENCY (Hz)
CROSSTALK (dB)
50 100 200 500 10k1k 2k 5k
+0
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
-70
20 20k
FREQUENCY (Hz)
CROSSTALK (dB)
50 100 200 500 10k1k 2k 5k
+0
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
-70
20 20k
FREQUENCY (Hz)
CROSSTALK (dB)
50 100 200 500 10k1k 2k 5k
+0
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
-70
20 20k
FREQUENCY (Hz)
CROSSTALK (dB)
50 100 200 500 10k1k 2k 5k
+0
-65
-60
-55
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
-70
LM4985, LM4985TMEVAL
SNAS346C –MAY 2006–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (continued)
TA= 25°C, AV= 0dB, fIN = 1kHz unless otherwise stated.
Crosstalk vs Frequency Crosstalk vs Frequency
VDD = 2.5V, RL= 16ΩVDD = 3.6V, RL= 16Ω
POUT = 20mW. OCL POUT = 40mW, OCL
Figure 41. Figure 42.
Crosstalk vs Frequency Crosstalk vs Frequency
VDD = 5.0V, RL= 16ΩVDD = 2.5V, RL= 32Ω
POUT = 40mW, OCL POUT = 20mW, OCL
Figure 43. Figure 44.
Crosstalk vs Frequency Crosstalk vs Frequency
VDD = 3.6V, RL= 32ΩVDD = 5.0V, RL= 32Ω
POUT = 40mW, OCL POUT = 50mW, OCL
Figure 45. Figure 46.
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Product Folder Links: LM4985 LM4985TMEVAL
20 20k
FREQUENCY (Hz)
-100
+0
CROSSTALK (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
FREQUENCY (Hz)
CROSSTALK (dB)
-80
-76
-72
-68
-64
-60
-56
-52
-48
-44
-40
30 100 1k 20k
10k
200 2k500 5k
50
20 20k
FREQUENCY (Hz)
-100
+0
CROSSTALK (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
FREQUENCY (Hz)
-100
+0
CROSSTALK (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
FREQUENCY (Hz)
-100
+0
CROSSTALK (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
20 20k
FREQUENCY (Hz)
-100
+0
CROSSTALK (dB)
10k1k 2k 5k50 100 200 500
-90
-80
-70
-60
-50
-40
-30
-20
-10
LM4985, LM4985TMEVAL
www.ti.com
SNAS346C –MAY 2006–REVISED APRIL 2013
Typical Performance Characteristics (continued)
TA= 25°C, AV= 0dB, fIN = 1kHz unless otherwise stated.
Crosstalk vs Frequency Crosstalk vs Frequency
VDD = 2.5V, RL= 16ΩVDD = 3.6V, RL= 16Ω
POUT = 20mW, C-CUPL POUT = 50mW, C-CUPL
Figure 47. Figure 48.
Crosstalk vs Frequency Crosstalk vs Frequency
VDD = 5.0V, RL= 16ΩVDD = 2.5V, RL= 32Ω
POUT = 50mW, C-CUPL POUT = 20mW, C-CUPL
Figure 49. Figure 50.
Crosstalk vs Frequency Crosstalk vs Frequency
VDD = 3.6V, RL= 32ΩVDD = 5.0V, RL= 32Ω
POUT = 50mW, C-CUPL POUT = 50mW, C-CUPL
Figure 51. Figure 52.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LM4985 LM4985TMEVAL
0.0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
LOAD DISSIPATION (W)
AMPLIFIER DISSIPATION (W)
0.01 0.03 0.05 0.07
RL = 16:
1% THD+N
RL = 32:
10% THD+N
0.0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
LOAD DISSIPATION (W)
AMPLIFIER DISSIPATION (W)
0.05 0.100
0.01 0.180
0.140
10% THD+N
RL = 32:
RL = 16:
1% THD+N
0.0
0.02
0.04
0.06
0.08
LOAD DISSIPATION (W)
AMPLIFIER DISSIPATION (W)
0.01 0.05 0.10 0.14 0.18
RL = 32:
1% THD+N
RL = 16:
10% THD+N
0.100
LOAD DISSIPATION (W)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
AMPLIFIER DISSIPATION (W)
0.01 0.02 0.03 0.04
1% THD+N
10% THD+N
RL = 16:
RL = 32:
0.0
0.1
0.2
0.3
0.4
0.5
LOAD DISSIPATION (W)
AMPLIFIER DISSIPATION (W)
0.01 0.03 0.05 0.07 0.09
RL = 32:
1% THD+N
RL = 16:
10% THD+N
0.0
0.05
0.10
0.15
0.20
0.25
LOAD DISSIPATION (W)
AMPLIFIER DISSIPATION (W)
0.01 0.02 0.03 0.04
RL = 16:
10% THD+N
RL = 32:
1% THD+N
LM4985, LM4985TMEVAL
SNAS346C –MAY 2006–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (continued)
TA= 25°C, AV= 0dB, fIN = 1kHz unless otherwise stated.
Load Dissipation vs Amplifier Dissipation Load Dissipation vs Amplifier Dissipation
VDD = 2.5V, C-CUPL VDD = 3.6V, C-CUPL
Figure 53. Figure 54.
Load Dissipation vs Amplifier Dissipation Load Dissipation vs Amplifier Dissipation
VDD = 5.0V, C-CUPL VDD = 2.5V, OCL
Figure 55. Figure 56.
Load Dissipation vs Amplifier Dissipation Load Dissipation vs Amplifier Dissipation
VDD = 3.6V, OCL VDD = 5.0V, OCL
Figure 57. Figure 58.
18 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM4985 LM4985TMEVAL
100
LOAD RESISTANCE (:)
OUTPUT POWER (W)
16 24 32 64 128 200 300
0
20
40
60
80
1% THD+N
10% THD+N
LOAD RESISTANCE (:)
OUTPUT POWER (W)
16 24 32 64 128 200 300
0
50
100
150
200
1% THD+N
10% THD+N
LOAD RESISTANCE (:)
OUTPUT POWER (W)
16 24 32 64 128 200 300
0
50
100
150
200
1% THD+N
10% THD+N
LOAD RESISTANCE (:)
OUTPUT POWER (W)
16 24 32 64 128 200 300
0
10
20
30
40
50
10% THD+N
1% THD+N
LOAD RESISTANCE (:)
OUTPUT POWER (W)
16 24 32 64 128 200 300
0
5
15
20
25
30
35
40
10 1% THD+N
10% THD+N
LOAD RESISTANCE (:)
OUTPUT POWER (W)
16 24 32 64 128 200 300
0
5
15
20
25
30
35
40
10 1% THD+N
10% THD+N
LM4985, LM4985TMEVAL
www.ti.com
SNAS346C –MAY 2006–REVISED APRIL 2013
Typical Performance Characteristics (continued)
TA= 25°C, AV= 0dB, fIN = 1kHz unless otherwise stated.
Output Power vs Load Resistance Output Power vs Load Resistance
VDD = 2.5V, C-CUPL VDD = 3.6V, C-CUPL
Figure 59. Figure 60.
Output Power vs Load Resistance Output Power vs Load Resistance
VDD = 5.0V, C-CUPL VDD = 2.5V, OCL
Figure 61. Figure 62.
Output Power vs Load Resistance Output Power vs Load Resistance
VDD = 3.6V, OCL VDD = 5.0V, OCL
Figure 63. Figure 64.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LM4985 LM4985TMEVAL
2.3 2.5 3.0 4.0 4.5 5.0 5.5
VOLTAGE SUPPLY (V)
SUPPLY CURRENT (mA)
2.5
3.5
1.0
1.5
0.0
3.5
0.5
2.0
3.0
2.3 2.5 3.0 4.0 4.5 5.0 5.5
VOLTAGE SUPPLY (V)
SUPPLY CURRENT (mA)
2.5
3.5
1.0
1.5
0.0
3.5
0.5
2.0
3.0
2.3 2.5 3.0 4.0 4.5 5.0 5.5
VOLTAGE SUPPLY (V)
OUTPUT POWER (mW)
250
3.5
50
100
150
200
0
1% THD+N
10% THD+N
2.3 2.5 3.0 4.0 4.5 5.0 5.5
VOLTAGE SUPPLY (V)
OUTPUT POWER (mW)
100
3.5
10
20
30
40
50
60
70
80
90
0
1% THD+N
10% THD+N
2.3 2.5 3.0 4.0 4.5 5.0 5.5
VOLTAGE SUPPLY (V)
OUTPUT POWER (mW)
250
3.5
50
100
150
200
0
1% THD+N
10% THD+N
2.3 2.5 3.0 4.0 4.5 5.0 5.5
VOLTAGE SUPPLY (V)
OUTPUT POWER (mW)
150
3.5
50
100
0
200
10% THD+N
1% THD+N
LM4985, LM4985TMEVAL
SNAS346C –MAY 2006–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (continued)
TA= 25°C, AV= 0dB, fIN = 1kHz unless otherwise stated.
Output Power vs Supply Voltage Output Power vs Supply Voltage
RL= 16Ω, C-CUPL RL= 32Ω, C-CUPL
Figure 65. Figure 66.
Output Power vs Supply Voltage Output Power vs Supply Voltage
RL= 16Ω, OCL RL= 32Ω, OCL
Figure 67. Figure 68.
Supply Current vs Supply Voltage Supply Current vs Supply Voltage
RL= 16Ω, C-CUPL RL= 32Ω, C-CUPL
Figure 69. Figure 70.
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Product Folder Links: LM4985 LM4985TMEVAL
Av (dB)
3 6 3012 24211815 2790
VOLUME STEPS
30
-80
-50
-60
-30
-10
10
20
0
-20
-40
-70
Av (dB)
3 6 3012 24211815 2790
VOLUME STEPS
30
-80
-50
-60
-30
-10
10
20
0
-20
-40
-70
Av (dB)
3 6 3012 24211815 2790
VOLUME STEPS
30
-80
-50
-60
-30
-10
10
20
0
-20
-40
-70
Av (dB)
3 6 3012 24211815 2790
VOLUME STEPS
30
-80
-50
-60
-30
-10
10
20
0
-20
-40
-70
2.3 3.0 3.5 4.0 4.5 5.0 5.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
2.3 3.0 3.5 4.0 4.5 5.0 5.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
LM4985, LM4985TMEVAL
www.ti.com
SNAS346C –MAY 2006–REVISED APRIL 2013
Typical Performance Characteristics (continued)
TA= 25°C, AV= 0dB, fIN = 1kHz unless otherwise stated.
Supply Current vs Supply Voltage Supply Current vs Supply Voltage
RL= 16Ω, OCL RL= 32Ω, OCL
Figure 71. Figure 72.
Gain vs Volume Steps Gain vs Volume Steps
VCC = 2.5V, RL= 16Ω, OCL VCC = 3.6V, RL= 16Ω, OCL
Figure 73. Figure 74.
Gain vs Volume Steps Gain vs Volume Steps
VCC = 5V, RL= 16Ω, OCL VCC = 2.5V, RL= 16Ω, C-CUPL
Figure 75. Figure 76.
Copyright © 2006–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LM4985 LM4985TMEVAL
Av (dB)
-100
-80
-60
-40
-20
0
20
40
3 6 3012 24211815 2790
VOLUME STEPS
Av (dB)
3 6 3012 24211815 2790
VOLUME STEPS
30
-80
-50
-60
-30
-10
10
20
0
-20
-40
-70
Av (dB)
3 6 3012 24211815 2790
VOLUME STEPS
30
-80
-50
-60
-30
-10
10
20
0
-20
-40
-70
Av (dB)
3 6 3012 24211815 2790
VOLUME STEPS
30
-80
-50
-60
-30
-10
10
20
0
-20
-40
-70
Av (dB)
-80
-40
-60
-20
0
20
40
3 6 3012 24211815 2790
VOLUME STEPS
VOLUME STEPS
Av (dB)
-80
-40
-60
-20
0
20
40
3 6 3012 24211815 2790
LM4985, LM4985TMEVAL
SNAS346C –MAY 2006–REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (continued)
TA= 25°C, AV= 0dB, fIN = 1kHz unless otherwise stated.
Gain vs Volume Steps Gain vs Volume Steps
VCC = 3.6V, RL= 16Ω, C-CUPL VCC = 5V, RL= 16Ω, C-CUPL
Figure 77. Figure 78.
Gain vs Volume Steps Gain vs Volume Steps
VCC = 2.5V, RL= 32Ω, OCL VCC = 3.6V, RL= 32Ω, OCL
Figure 79. Figure 80.
Gain vs Volume Steps Gain vs Volume Steps
VCC = 5V, RL= 32Ω, OCL VCC = 2.5V, RL= 32Ω, C-CUPL
Figure 81. Figure 82.
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Av (dB)
-80
-40
-60
-20
0
20
40
3 6 3012 24211815 2790
VOLUME STEPS
Av (dB)
-80
-40
-60
-20
0
20
40
3 6 3012 24211815 2790
VOLUME STEPS
LM4985, LM4985TMEVAL
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SNAS346C –MAY 2006–REVISED APRIL 2013
Typical Performance Characteristics (continued)
TA= 25°C, AV= 0dB, fIN = 1kHz unless otherwise stated.
Gain vs Volume Steps Gain vs Volume Steps
VCC = 3.6V, RL= 32Ω, C-CUPL VCC = 5V, RL= 32Ω, C-CUPL
Figure 83. Figure 84.
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APPLICATION INFORMATION
AMPLIFIER CONFIGURATION EXPLANATION
As shown in Figure 1, the LM4985 has three internal power amplifiers. Two of the amplifiers which amplify
signals applied to their inputs, have internally configurable gain. The remaining third amplifier provides both half-
supply output bias and AC ground return.
Loads, such as a headphone speaker, are connected between OUT1 and CNTGND or OUT2 and CNTGND.
This configuration does not require an output coupling capacitor. The classical single-ended amplifier
configuration, where one side of the load is connected to ground, requires large, expensive output coupling
capacitors.
A configuration such as the one used in the LM4985 has a major advantage over single supply, single-ended
amplifiers. Since the outputs OUT1, OUT2, and CNTGND are all biased at 1/2 VDD, no net DC voltage exists
across each load. This eliminates the need for output coupling capacitors which are required in a single-supply,
single-ended amplifier configuration. Without output coupling capacitors in a typical single-supply, single-ended
amplifier, the bias voltage is placed across the load resulting in both increased internal IC power dissipation and
possible loudspeaker damage.
The LM4985 eliminates these output coupling capacitors when operating in Output Capacitor-less (OCL) mode.
Unless shorted to ground, VoC is internally configured to apply a 1/2 VDD bias voltage to a stereo headphone
jack's sleeve. This voltage matches the bias voltage present on VoA and VoB outputs that drive the headphones.
The headphones operate in a manner similar to a bridge-tied load (BTL). Because the same DC voltage is
applied to both headphone speaker terminals this results in no net DC current flow through the speaker. AC
current flows through a headphone speaker as an audio signal's output amplitude increases on the speaker's
terminal.
The headphone jack's sleeve is not connected to circuit ground when used in OCL mode. Using the headphone
output jack as a line-level output will place the LM4985's 1/2 VDD bias voltage on a plug's sleeve connection. This
presents no difficulty when the external equipment uses capacitively coupled inputs. For the very small minority
of equipment that is DC coupled, the LM4985 monitors the current supplied by the amplifier that drives the
headphone jack's sleeve. If this current exceeds 500mAPEAK, the amplifier is shutdown, protecting the LM4985
and the external equipment.
POWER DISSIPATION
Power dissipation is a major concern when using any power amplifier. When operating in capacitor-coupled
mode (C-CUPL), Equation 1 states the maximum power dissipation point for a single-ended amplifier operating
at a given supply voltage and driving a specified output load.
PDMAX = 2(VDD)2/ (2π2RL) (1)
When operating in the OCL mode, the LM4985's three operational amplifiers produce a maximum power
dissipation given in Equation 2:
PDMAX = [2(VDD)2/ (2π2RL)] + [VDD2/ (4πRL)] (2)
The maximum power dissipation point obtained from Equation 1 or Equation 2 must not be greater than the
power dissipation that results from Equation 3:
PDMAX = (TJMAX - TA) / θJA (3)
For package YFQ0012, θJA = 190°C/W. TJMAX = 150°C for the LM4985. Depending on the ambient temperature,
TA, of the system surroundings, Equation 3 can be used to find the maximum internal power dissipation
supported by the IC packaging. If the result of Equation 2 is greater than that of Equation 3, then either the
supply voltage must be decreased, the load impedance increased or TAreduced.
For a typical application using a 3.6V power supply, with a 32Ωload, the maximum ambient temperature possible
without violating the maximum junction temperature is approximately 144°C provided that device operation is
around the maximum power dissipation point. Thus, for typical applications, power dissipation is not an issue.
Power dissipation is a function of output power and thus, if typical operation is not around the maximum power
dissipation point, the ambient temperature may be increased accordingly. Refer to the Typical Performance
Characteristics curves for power dissipation information for lower output powers.
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POWER SUPPLY BYPASSING
As with any amplifier, proper supply bypassing is important for low noise performance and high power supply
rejection. The capacitor location on the power supply pins should be as close to the device as possible.
Typical applications employ a regulator with 10µF tantalum or electrolytic capacitor and a ceramic bypass
capacitor which aid in supply stability. This does not eliminate the need for bypassing the supply nodes of the
LM4985. A bypass capacitor value in the range of 0.1µF to 1µF is recommended for CS.
MICRO POWER SHUTDOWN
The LM4985's micropower shutdown is activated or deactivated through its I2C digital interface . Please refer to
Table 1 for the I2C Address, Register Select, and Mode Control registers. Each amplifier within the LM4985 can
be shutdown individually.
Please observe the following protocol when placing an individual amplifier channel in shutdown while the other
channel remains active. The protocol requires activating both channels’ shutdown simultaneously, then
deactivating the shutdown of the channel whose output is desired (or leaving the desire channel in shutdown
mode). Also, when operating in the C-CUPL mode, a short delay time is required between activating one channel
after placing both channels in shutdown. If the user finds that both channels activate when only one was chosen,
increase the delay.
SELECTION OF INPUT CAPACITOR SIZE
Amplifying the lowest audio frequencies requires a high value input coupling capacitor, Ci. A high value capacitor
can be expensive and may compromise space efficiency in portable designs. In many cases, however, the
headphones used in portable systems have little ability to reproduce signals below 60Hz. Applications using
headphones with this limited frequency response reap little improvement by using a high value input capacitor.
In addition to system cost and size, turn on time is affected by the size of the input coupling capacitor Ci. A larger
input coupling capacitor requires more charge to reach its quiescent DC voltage. This charge comes from the
output via the feedback Thus, by minimizing the capacitor size based on necessary low frequency response,
turn-on time can be minimized. A small value of Ci(in the range of 0.22µF to 0.68µF), is recommended.
MAXIMIZING OCL MODE CHANNEL-to-CHANNEL SEPARATION
The OCL mode AC ground return (CNT_GND pin) is shared by both amplifiers. As such, any resistance between
the CNT_GND pin and the load will create a voltage divider with respect to the load resistance. In a typical
circuit, the amount of CNT_GND resistance can be very small, but still significant. It is significant because of the
relatively low load impedances for which the LM4985 was designed to drive: 16Ωto 32Ω. The ratio of this
voltage divider will determine the magnitude of any residual signal present at the CNT_GND pin. It is this residual
signal that leads to channel-to-channel separation (crosstalk) degradation.
For example, for a 60dB channel-to-channel separation while driving a 16Ωload, the resistance between the
LM4985’s CNT_GND pin and the load must be less than 16mΩ. This is achieved by ensuring that the trace that
connects the CNT_GND pin to the headphone jack sleeve should be as short and massive as possible, given the
physical constraints of any specific printed circuit board layout and design.
DEMONSTRATION BOARD AND PCB LAYOUT
Information concerning PCB layout considerations and demonstration board use and performance is found in
Application Note AN-1452 (Literature Number SNAA029).
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I2C Control Register
Table 1 shows the actions that are implemented by manipulating the bits within the two internal I2C control
registers.
Table 1. LM4985 I2C Control Register Addressing and Data Format Chart
LM4985 I2C Contorl Register Addressing and Data Chart
A6 A5 A4 A3 A2 A1 A0 Function
I2C Address 1 1 0 0 1 1 A0
D7 D6 D5 D4 D3 D2 RS1 RS0
0 0 0 0 0 0 0 0 Read and write the mode control
Register register
Select 0 0 0 0 0 0 0 1 Read and write the volume
control register
D7 D6 D5 D4 D3 D2 D1 D0
WT1 WT0 PHG SDCH1 SDCH2 CHSEL1 CHSEL2
0 X X X X X X X D7 must always be set to 0
– 0 0 X X X X X Wake-up time: 80ms (OCL),
250ms (C-CUPL)
– 0 1 X X X X X Wake-up time: 110ms (OCL),
450ms (C-CUPL)
– 1 0 X X X X X Wake-up time: 170ms (OCL),
850ms (C-CUPL)
– 1 1 X X X X X Wake-up time: 290ms (OCL),
1650ms (C-CUPL)
– X X 1 X X X X Output capacitor-less mode
active
Mode – X X 0 X X X X Output capacitor-less mode
Control inactive
Register – X X X 0 0 X X Amplifier's SHUTDOWN mode
active
– X X X 0 1 X X Illegal mode
– X X X 1 0 X X Illegal mode
– X X X 1 1 X X Amplifier's SHUTDOWN mode
inactive
– X X X X X 0 02 Amplifier's Chan. 1 is Input 1,
Chan 2. is Input 2
– X X X X X 0 1 Amplifier's Chan. 1 is Input 1,
Chan 2. is Input 1
– X X X X X 1 0 Amplifier's Chan. 1 is Input 2,
Chan 2. is Input 2
– X X X X X 1 1 Amplifier's Chan. 1 is Input 2,
Chan 2. is Input 1
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Volume Control Settings Binary Values
The minimum volume setting is set to –76dB when 00000 is loaded into the volume control register. Incrementing
the volume control register in binary fashion increases the volume control setting, reaching full scale at 11111.
Table 2 shows the value of the gain for each of the 32 binary volume control settings.
Table 2. Binary Values for the Different Volume Control Gain Settings
Gain B4 B3 B2 B1 B0
1811111
1711110
1611101
1511100
1411011
1311010
1211001
1011000
810111
610110
410101
210100
010011
–210010
–410001
–610000
–801111
–10 0 1 1 1 0
–12 0 1 1 0 1
–14 0 1 1 0 0
–16 0 1 0 1 1
–18 0 1 0 1 0
–21 0 1 0 0 1
–24 0 1 0 0 0
–27 0 0 1 1 1
–30 0 0 1 1 0
–34 0 0 1 0 1
–38 0 0 1 0 0
–44 0 0 0 1 1
–52 0 0 0 1 0
–62 0 0 0 0 1
–76 0 0 0 0 0
Revision History
Rev Date Description
1.0 05/17/06 Initial WEB release.
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 27
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PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
LM4985TM/NOPB ACTIVE DSBGA YFQ 12 250 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 G
H2
LM4985TMX/NOPB ACTIVE DSBGA YFQ 12 3000 Green (RoHS
& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 G
H2
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM4985TM/NOPB DSBGA YFQ 12 250 178.0 8.4 1.35 1.75 0.76 4.0 8.0 Q1
LM4985TMX/NOPB DSBGA YFQ 12 3000 178.0 8.4 1.35 1.75 0.76 4.0 8.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM4985TM/NOPB DSBGA YFQ 12 250 210.0 185.0 35.0
LM4985TMX/NOPB DSBGA YFQ 12 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 2
MECHANICAL DATA
YFQ0012xxx
www.ti.com
TMD12XXX (Rev B)
E
0.600
±0.075
D
A
. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
NOTES:
4215079/A 12/12
D: Max =
E: Max =
1.64 mm, Min =
1.24 mm, Min =
1.58 mm
1.18 mm
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