MB85R1001ANC-GE1 - FUJITSU - Datasheet.Directory

FUJITSU SEMICONDUCTOR

DATA SHEET

2011.7

Memory FRAM

1 M Bit (128 K × 8)

MB85R1001A

■DESCRIPTIONS

The MB85R1001A is an FRAM (Ferroelectric Random Access Memory) chip consisting of 131,072

words × 8 bits of nonvolatile memory cells fabricated using ferroelectric process and silicon gate CMOS

process technologies.

The MB85R1001A is able to retain data without using a back-up battery, as is needed for SRAM.

The memory cells used in the MB85R1001A can be used for 1010 read/write operations, which is a significant

improvement over the number of read and write operations supported by Flash memory and E2PROM.

The MB85R1001A uses a pseudo-SRAM interface that is compatible with conventional asynchronous SRAM.

■FEATURES

• Bit configuration : 131,072 words × 8 bits

• Read/write endurance : 1010 times

• Operating power supply voltage : 3.0 V to 3.6 V

• Operating temperature range : − 40 °C to + 85 °C

• Data retention : 10 years ( + 55 °C)

• Package : 48-pin plastic TSOP (1)

DS501-00003-1v0-E

MB85R1001A

2DS501-00003-1v0-E

■PIN ASSIGNMENTS

■PIN DESCRIPTIONS

Pin Number Pin Name Functional Description

1, 2, 4, 5, 8, 18 to 26, 28, 29, 45 A0 to A16 Address Input pins

33 to 35, 38 to 42 I/O1 to I/O8 Data Input/Output pins

44 CE1 Chip Enable 1 Input pin

7 CE2 Chip Enable 2 Input pin

6WE

Write Enable Input pin

48 OE Output Enable Input pin

10, 16, 37 VDD Supply Voltage pins

Connect all three pins to the power supply.

13, 27, 46 VSS Ground pins

Connect all three pins to ground.

3, 9, 11, 12, 14, 15, 17, 30 to

32, 36, 43, 47 NC No Connect pins

A11

A13

CE2

A15

VDD

VSS

VDD

A16

A14

A12

VSS

A10

CE1

I/O8

I/O7

I/O6

I/O5

I/O4

VDD

I/O3

I/O2

I/O1

VSS

(FPT-48P-M48)

(TOP VIEW)

MB85R1001A

DS501-00003-1v0-E 3

■BLOCK DIAGRAM

■FUNCTIONAL TRUTH TABLE

Note: L = VIL, H = VIH, X can be either VIL or VIH, Hi-Z = High Impedance

: Latch address and latch data at falling edge, : Latch address and latch data at rising edge

*1 : OE control of the Pseudo-SRAM means the valid address at the falling edge of OE to read.

*2 : WE control of the Pseudo-SRAM means the valid address and data at the falling edge of WE to write.

Operation Mode CE1CE2 WE OE I/O1 to I/O8Supply Current

Standby Precharge

HXXX

Hi-Z Standby

(ISB)

XLXX

XXHH

Read

Data Output

Operation

(ICC)

Read

(Pseudo-SRAM, OE control*1)LHH

Write

Data Input

Write

(Pseudo-SRAM, WE control*2)LH H

I/O8

I/O1

A16

Address Latch

Row Decoder

FRAM Array

131,072 x 8

Column Decoder

S/A

I/O1 to I/O8

CE2

CE1

intOE

intWE

MB85R1001A

4DS501-00003-1v0-E

■ABSOLUTE MAXIMUM RATINGS

* : All voltages are referenced to VSS = 0 V.

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

■RECOMMENDED OPERATING CONDITIONS

* : All voltages are referenced to VSS = 0 V.

WARNING: The recommended operating conditions are required in order to ensure the normal operation of

the semiconductor device. All of the device's electrical characteristics are warranted when the

device is operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges.

Operation outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented

on the data sheet. Users considering application outside the listed conditions are advised to contact

their representatives beforehand.

Parameter Symbol Rating Unit

Min Max

Power Supply Voltage* VCC − 0.5 + 4.0 V

Input Pin Voltage* VIN − 0.5 VCC + 0.5 ( ≤ 4.0) V

Output Pin Voltage* VOUT − 0.5 VCC + 0.5 ( ≤ 4.0) V

Operating Temperature TA − 40 + 85 °C

Storage Temperature TSTG − 40 + 125 °C

Parameter Symbol Value Unit

Min Typ Max

Power Supply Voltage* VCC 3.0 3.3 3.6 V

High Level Input Voltage* VIH VCC × 0.8 ⎯VCC + 0.5( ≤ 4.0) V

Low Level Input Voltage* VIL − 0.5 ⎯ + 0.6 V

Operating Temperature TA − 40 ⎯ + 85 °C

MB85R1001A

DS501-00003-1v0-E 5

■ELECTRICAL CHARACTERISTICS

1. DC Characteristics

(within recommended operating conditions)

*1 : During the measurement of ICC, the Address, Data In were taken to only change once per active cycle.

Iout: output current

*2 : All pins other than setting pins should be input at the CMOS level voltages such as H ≥ VCC − 0.2 V, L ≤ 0.2 V.

Parameter Symbol Condition Value Unit

Min Typ Max

Input Leakage Current |ILI|VIN = 0 V to VCC ⎯⎯10 μA

Output Leakage Current |ILO|VOUT = 0 V to VCC,

CE1 = VIH or OE = VIH ⎯⎯10 μA

Operating Power Supply

Current ICC CE1 = 0.2 V, CE2 = VCC−0.2 V,

Iout = 0 mA*1⎯10 15 mA

Standby Current ISB

CE1 ≥ VCC−0.2 V

⎯10 50 μACE2 ≤ 0.2 V*2

OE ≥ VCC−0.2 V, WE ≥ VCC−0.2 V*2

High Level Output Voltage VOH IOH = −1.0 mA VCC ×

0.8 ⎯⎯V

Low Level Output Voltage VOL IOL = 2.0 mA ⎯⎯0.4 V

MB85R1001A

6DS501-00003-1v0-E

2. AC Characteristics

• AC Test Conditions

Supply Voltage : 3.0 V to 3.6 V

Operating Temperature : −40 °C to +85 °C

Input Voltage Amplitude : 0.3 V to 2.7 V

Input Rising Time : 5 ns

Input Falling Time : 5 ns

Input Evaluation Level : 2.0 V / 0.8 V

Output Evaluation Level : 2.0 V / 0.8 V

Output Impedance : 50 pF

(1) Read Cycle

(within recommended operating conditions)

(2) Write Cycle

(within recommended operating conditions)

Parameter Symbol Value Unit

Min Max

Read Cycle Time tRC 150 ⎯ns

CE1 Active Time tCA1 120 ⎯ns

CE2 Active Time tCA2 120 ⎯ns

OE Active Time tRP 120 ⎯ns

Precharge Time tPC 20 ⎯ns

Address Setup Time tAS 0⎯ns

Address Hold Time tAH 50 ⎯ns

OE Setup Time tES 0⎯ns

Output Hold Time tOH 0⎯ns

Output Set Time tLZ 30 ⎯ns

CE1 Access Time tCE1 ⎯100 ns

CE2 Access Time tCE2 ⎯100 ns

OE Access Time tOE ⎯100 ns

Output Floating Time tOHZ ⎯20 ns

Parameter Symbol Value Unit

Min Max

Write Cycle Time tWC 150 ⎯ns

CE1 Active Time tCA1 120 ⎯ns

CE2 Active Time tCA2 120 ⎯ns

Precharge Time tPC 20 ⎯ns

Address Setup Time tAS 0⎯ns

Address Hold Time tAH 50 ⎯ns

Write Pulse Width tWP 120 ⎯ns

Data Setup Time tDS 0⎯ns

Data Hold Time tDH 50 ⎯ns

Write Setup Time tWS 0⎯ns

MB85R1001A

DS501-00003-1v0-E 7

3. Pin Capacitance

Parameter Symbol Condition Value Unit

Min Typ Max

Input Capacitance CIN VIN = VOUT = 0 V,

f = 1 MHz, TA = +25 °C

⎯⎯10 pF

Output Capacitance COUT ⎯⎯10 pF

MB85R1001A

8DS501-00003-1v0-E

■TIMING DIAGRAMS

1. Read Cycle Timing (CE1, CE2 Control)

2. Read Cycle Timing (OE Control)

tAS tAH

tES

Valid

tRP

H or L

CE1

CE2

tRC

tPC

A0 to A16

I/O1 to I/O8

tOHZ

Hi-Z

Valid

tOH

tLZ

Invalid Invalid

tCA1

tCA2

tCE1,

tCE2

A0 to A16

I/O1 to I/O8

tAS tAH

tRC

tOE tOHZ

Hi-Z

Valid

tOH

tLZ

Valid H or L

tRP

Invalid Invalid

tPC

CE1

CE2

tCA1

tCA2

MB85R1001A

DS501-00003-1v0-E 9

3. Write Cycle Timing (CE1, CE2 Control)

4. Write Cycle Timing (WE Control)

CE1

CE2 t

CA2

CA1

A0 to A16

Data In

Hi-Z

Valid H or L

A0 to A16

tWP

tWC

tDH

Hi-Z

tAH

tAS

tDS

Valid H or L

tPC

Data In

CE1

CE2

tCA1

tCA2

MB85R1001A

10 DS501-00003-1v0-E

■POWER ON/OFF SEQUENCE

(within recommended operating conditions)

■NOTES ON USE

After the IR reflow completed, it is not guaranteed to hold the data written prior to the IR reflow.

Parameter Symbol Value Unit

Min Typ Max

CE1 level hold time for Power OFF tPD 85 ⎯⎯ns

CE1 level hold time for Power ON tPU 85 ⎯⎯ns

Power supply rising time tR0.05 ⎯200 ms

CE1 > VCC × 0.8* CE1 : Don't Care CE1 > VCC × 0.8*

tPUtRtPD

VCC

CE2

3.0 V

1.0 V

VIH (Min)

VIL (Max)

0 V

CE1 CE1

VCC

CE2

3.0 V

1.0 V

VIH (Min)

VIL (Max)

0 V

* : CE1 (Max) < VCC + 0.5 V

Notes: • Use either of CE1 or CE2, or both for disable control of the device.

• Because turning the power-on from an intermediate level cause malfunction, when the

power is turned on, VCC is required to be started from 0 V.

• If the device does not operate within the specified conditions of read cycle, write cycle,

power on/off sequence, memory data can not be guaranteed.

• When turning the power on or off, it is recommended that CE2 is connected to ground to

prevent unexpected writing.

CE2 ≤ 0.2 V

MB85R1001A

DS501-00003-1v0-E 11

■ORDERING INFOMATION

Part Number Package

MB85R1001ANC-GE1 48-pin plastic TSOP(1)

(FPT-48P-M48)

MB85R1001A

12 DS501-00003-1v0-E

■PACKAGE DIMENSIONS

Please check the latest package dimension at the following URL.

http://edevice.fujitsu.com/package/en-search/

48-pin plastic TSOP Lead pitch 0.50 mm

Package width ×

package length 12.00 mm × 12.40 mm

Lead shape Gullwing

Sealing method Plastic mold

Mounting height 1.20 mm MAX

Weight 0.36 g

48-pin plastic TSOP

(FPT-48P-M48)

2010 FUJITSU SEMICONDUCTOR LIMITED F48048Sc-1-1

14.00±0.20(.551±.008)

#12.00±0.10

0.10±0.05 (.004±.002)

(.472±.004)

0.08(.003)

0.50(.020)

0.22

(.009 )

0.145

(.006 )

0.10(.004)

Details of A part

0~8

(.024±.006)

0.60±0.15

INDEX

(STAND OFF)

*12.40±0.10(.488±.004)

+0.05

–0.03

+.002

–.001

+.002

–.002

+0.05

–0.04

1.13±0.07 (.044±.003)

(MOUNTING HEIGHT)

0.25(.010)

Dimensions in mm (inches).

Note: The values in parentheses are reference values.

Note 1) # : Resin protrusion. (Each side : +0.15 (.006) Max).

Note 2) * : These dimensions do not include resin protrusion.

Note 3) Pins width and pins thickness include plating thickness.

Note 4) Pins width do not include tie bar cutting remainder.

MB85R1001A

DS501-00003-1v0-E 13

MEMO

MB85R1001A

14 DS501-00003-1v0-E

MEMO

MB85R1001A

DS501-00003-1v0-E 15

MEMO

MB85R1001A

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