TDA7498 100-watt + 100-watt dual BTL class-D audio amplifier Features 100-W + 100-W output power at THD = 10% with RL = 6 and VCC = 36 V 80-W + 80-W output power at THD = 10% with RL = 8 and VCC = 34 V Wide-range single-supply operation (14 - 39 V) High efficiency ( = 90%) Four selectable, fixed gain settings of nominally 25.6 dB, 31.6 dB, 35.1 dB and 37.6 dB Differential inputs minimize common-mode noise Standby and mute features Short-circuit protection Thermal overload protection Externally synchronizable PowerSSO36 with exposed pad up Description The TDA7498 is a dual BTL class-D audio amplifier with single power supply designed for home systems and active speaker applications. It comes in a 36-pin PowerSSO package with exposed pad up (EPU) to facilitate mounting a separate heatsink. Table 1. Device summary Order code Operating temp. range Package Packaging TDA7498 -40 to 85 C PowerSSO36 (EPU) Tube TDA7498TR -40 to 85 C PowerSSO36 (EPU) Tape and reel September 2011 Doc ID 16107 Rev 8 1/28 www.st.com 28 Contents TDA7498 Contents 1 2 3 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Characterizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2.1 For RL = 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.2.2 For RL = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5 Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.1 Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5.2 Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.6 Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7 Protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.8 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2/28 Doc ID 16107 Rev 8 TDA7498 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Internal block diagram (showing one channel only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin connections (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Test circuit for characterizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Output power (THD = 10%) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 THD vs. frequency (1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 THD vs. frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 FFT performance (0 dBFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 FFT performance (-60 dBFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Output power (THD = 10%) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 THD vs. frequency (1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 THD vs. frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 FFT performance (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 FFT performance (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Applications circuit for 6- or 8- speakers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Standby and mute circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Turn on/off sequence for minimizing speaker "pop" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Typical LC filter for a 8- speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Typical LC filter for a 6- speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Behavior of pin DIAG for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PowerSSO36 EPU outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Doc ID 16107 Rev 8 3/28 List of tables TDA7498 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. 4/28 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin description list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 How to set up SYNCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PowerSSO36 EPU dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Doc ID 16107 Rev 8 TDA7498 Device block diagram Device block diagram Figure 1 shows the block diagram of one of the two identical channels of the TDA7498. Figure 1. Internal block diagram (showing one channel only) Doc ID 16107 Rev 8 5/28 Pin description TDA7498 1 Pin description 1.1 Pinout Figure 2. Pin connections (top view, PCB view) SUB_GND 1 SVCC OUTPB 2 34 VREF OUTPB 3 33 INNB PGNDB 4 32 INPB PGNDB 5 31 GAIN1 PVCCB 6 30 GAIN0 PVCCB 7 29 SVR OUTNB 8 28 DIAG OUTNB 9 27 SGND OUTNA 10 26 VDDS OUTNA 11 25 SYNCLK PVCCA 12 24 ROSC PVCCA 13 23 INNA PGNDA 14 36 VSS 35 22 INPA EP, exposed pad Connect to ground 21 MUTE OUTPA 16 OUTPA 17 20 STBY 19 VDDPW 6/28 PGNDA 15 Doc ID 16107 Rev 8 PGND 18 TDA7498 1.2 Pin description Pin list Table 2. Pin description list Number Name Type Description 1 SUB_GND PWR Connect to the frame 2,3 OUTPB O Positive PWM for right channel 4,5 PGNDB PWR Power stage ground for right channel 6,7 PVCCB PWR Power supply for right channel 8,9 OUTNB O Negative PWM output for right channel 10,11 OUTNA O Negative PWM output for left channel 12,13 PVCCA PWR Power supply for left channel 14,15 PGNDA PWR Power stage ground for left channel 16,17 OUTPA O Positive PWM output for left channel 18 PGND PWR Power stage ground 19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power stage 20 STBY I Standby mode control 21 MUTE I Mute mode control 22 INPA I Positive differential input of left channel 23 INNA I Negative differential input of left channel 24 ROSC O Master oscillator frequency-setting pin 25 SYNCLK I/O Clock in/out for external oscillator 26 VDDS O 3.3-V (nominal) regulator output referred to ground for signal blocks 27 SGND PWR Signal ground 28 DIAG O Open-drain diagnostic output 29 SVR O Supply voltage rejection 30 GAIN0 I Gain setting input 1 31 GAIN1 I Gain setting input 2 32 INPB I Positive differential input of right channel 33 INNB I Negative differential input of right channel 34 VREF O Half VDDS (nominal) referred to ground 35 SVCC PWR Signal power supply 36 VSS O 3.3-V (nominal) regulator output referred to power supply - EP - Exposed pad for heatsink, to be connected to ground Doc ID 16107 Rev 8 7/28 Electrical specifications TDA7498 2 Electrical specifications 2.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol 2.2 Unit DC supply voltage for pins PVCCA, PVCCB, SVCC 44 V VI Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN0, GAIN1 -0.3 to 3.6 V Tj Operating junction temperature -40 to 150 C Tstg Storage temperature -40 to 150 C Thermal data Thermal data Symbol Parameter Rth j-case Thermal resistance, junction to case Min - Typ 2 Max 3 Unit C/W Recommended operating conditions Table 5. Recommended operating conditions Symbol 2.4 Value VCC Table 4. 2.3 Parameter Parameter Min Typ Max Unit VCC Supply voltage for pins PVCCA, PVCCB, SVCC 14 - 39 V Tamb Ambient operating temperature -40 - 85 C Electrical specifications Unless otherwise stated, the values in the table below are specified for the conditions: VCC = 36 V, RL = 6 , ROSC = R3 = 39 k, C8 = 100 nF, f = 1 kHz, GV = 25.6 dB Tamb = 25 C. Table 6. Symbol 8/28 Electrical specifications Parameter Condition Min Typ Max Unit Iq Total quiescent current No LC filter, no load - 40 60 mA IqSTBY Quiescent current in standby - - 1 10 A Play mode -100 - 100 VOS Output offset voltage Mute mode -60 - 60 IOCP Overcurrent protection threshold RL = 0 6 7 - mV Doc ID 16107 Rev 8 A TDA7498 Electrical specifications Table 6. Electrical specifications (continued) Symbol Parameter Condition Min Typ Max Unit Tj Junction temperature at thermal shutdown - - 150 - C Ri Input resistance Differential input 48 60 - k VOVP Overvoltage protection threshold - 42 43 - V VUVP Undervoltage protection threshold - - - 8 V High side - 0.2 - RdsON Power transistor on resistance Low side - 0.2 - THD = 10% - 100 - Po Output power THD = 1% - 78 - Po Output power RL = 8 , THD = 10% - 80 - W PD Dissipated power Po = 100 W + 100 W, THD = 10% - 20 - W Efficiency Po = 100 W + 100 W - 90 - % THD Total harmonic distortion Po = 1 W - 0.1 - % GAIN0 = L, GAIN1 = L 24.6 25.6 26.6 GAIN0 = L, GAIN1 = H 30.6 31.6 32.6 GAIN0 = H, GAIN1 = L 34.1 35.1 36.1 GAIN0 = H, GAIN1 = H 36.6 37.6 38.6 GV W Closed-loop gain dB GV Gain matching - -1 - 1 dB CT Crosstalk f = 1 kHz, Po = 1 W 50 70 - dB 15 - Total input noise A Curve, GV = 20 dB - eN f = 22 Hz to 22 kHz - 25 50 V SVRR Supply voltage rejection ratio fr = 100 Hz, Vr = 0.5 Vpp, CSVR = 10 F 70 - dB Tr, Tf Rise and fall times - - 50 - ns fSW Switching frequency Internal oscillator 290 310 330 kHz 250 - 400 250 - 400 2.3 - - - - 0.8 fSWR Output switching frequency range VinH Digital input high (H) VinL Digital input low (L) With internal oscillator With external oscillator (1) (2) kHz - Doc ID 16107 Rev 8 V 9/28 Electrical specifications Table 6. Symbol TDA7498 Electrical specifications (continued) Parameter Condition Pin STBY voltage high (H) VSTBY AMUTE Typ 2.7 - - Pin STBY voltage low (L) - - 0.5 2.5 - - - - 0.8 - 70 - Pin MUTE voltage low (L) Mute attenuation VMUTE = L, VSTBY = H 2. fSW = fSYNCLK / 2 with the external oscillator. Doc ID 16107 Rev 8 Unit V V 1. fSW = 106 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 k (see Figure 19.). 10/28 Max Pin MUTE voltage high (H) VMUTE Min dB Characterizations 3.1 Test circuit TDA7498 3 Figure 3 shows the test circuit with which the characterization curves, shown in the next sections, were measured. Figure 4 shows the PCB layout. Figure 3. Test circuit for characterizations 1 SUB_GND OUTPA 16 22 INPA OUTPA 17 C3 1nF 23 INNA PGNDA 14 PGNDA 15 C4 1nF 27 SGND VDDS 26 VDDS R1 DIAG C1 1uF C2 1uF J1 C5 INPUT 100nF Doc ID 16107 Rev 8 3 L- 4 L+ 1 R- 2 R+ For J7 Single-Ended Input 28 R3 24 39K J5 30 ROSC GAIN0 31 GAIN1 32 C13 1nF 3V3 C12 S2 120k R2 33k IN IC2 1 L4931CZ33 3 2 GND C9 100nF R8 VCC OUT C29 2.2uF C14 1nF R4 S1 STBY 1 2 3 6.8k D1 18V 11/28 3V3 POWER SUPPLY TDA7498 + + 220nF OUTPB 2 7 PVCCB 6 8R L3 33 C23+ 50V L1 R5 * VCC 2 GND 22uH * C18 220nF R17 8R C42 C20 C31 100nF PGNDB 5 PGNDB 4 OUTNB 9 OUTNB 1 J2 22R 8 VREF 34 SVR 29 21 MUTE 680nF 1uF * * C43 220nF 220nF R18 8R L2 * 220nF C22 C21 330pF INNB C15 2.2uF 20 STBY 16V J3 OUTPUT Load = 6 ohm L+ 1 L2 R3 R+ 4 2200uF 22uH 3 PVCCB C41 220nF R16 330pF * OUTPB * C24 IC1 SVCC INPB C40 22uH C17 C7 2.2uF 16V TDA7498 CLASS-D AMPLIFIER 10uF 10V C16 10uF 10V LC FILTER COMPONENTS Load L1,L2,L3,L4 6 ohm 22 uH 680 nF 220 nF 8 ohm 22 uH 470 nF 220 nF C20,C26 C18,C22,C24,C28 Characterizations 1uF MUTE 1 2 3 680nF OUTNA 11 C10 1uF J4 1uF C19 35 C11 FS 100nF J6 100nF 36 VSS 3V3 C26 C27 18 PGND For Single-Ended Input * C30 OUTNA 10 VDDS J8 220nF C25 19 VDDPW 25 SYNCLK 8R C28 22R PVCCA 12 C6 100nF R15 * PVCCA 13 DIAG FREQUENCY SHIFT R9 Q1 KTC3875(S) 180K 3 C8 R13 FS 100nF 1 47k 2 R14 100k * R6 220nF 100k R7 22R L4 22uH Characterizations Figure 4. 12/28 TDA7498 Test board Doc ID 16107 Rev 8 TDA7498 3.2 Characterizations Characterization curves Unless otherwise stated the measurements were made under the following conditions: VCC = 36 V, f = 1 kHz, GV = 25.6 dB, ROSC = 39 k, COSC = 100 nF, Tamb = 25 C 3.2.1 For RL = 6 Figure 5. Output power (THD = 10%) vs. supply voltage 120 110 Output power (W) 100 90 80 70 60 50 40 30 20 10 +10 +12 +14 +16 +18 +20 +22 +24 +26 +28 +30 +32 +34 +36 Supply voltage (V) Figure 6. THD vs. output power 10 5 THD+N (%) 2 1 0.5 0.2 f = 1 kHz 0.1 0.05 f = 100 Hz 0.02 0.01 0.005 100m 200m 500m 1 2 5 10 20 50 100 200 Output power (W) Doc ID 16107 Rev 8 13/28 Characterizations Figure 7. TDA7498 THD vs. frequency (1 W) 2 1 THD+N (%) 0.5 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 20k 2k 5k 10k 20k 10k 20k Frequency (Hz) Figure 8. THD vs. frequency (100 mW) 2 1 THD+N (%) 0.5 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1k Frequency (Hz) Figure 9. Frequency response +3 +2.5 Ampl (dB) +2 +1.5 +1 +0.5 +0 -0.5 -1 -1.5 -2 -2.5 -3 10 20 50 100 200 500 Frequency (Hz) 14/28 Doc ID 16107 Rev 8 1k 2k 5k TDA7498 Characterizations Figure 10. FFT performance (0 dBFS) +0 -10 -20 FFT (dB) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Figure 11. FFT performance (-60 dBFS) +0 -10 -20 FFT (dB) -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Doc ID 16107 Rev 8 15/28 Characterizations 3.2.2 TDA7498 For RL = 8 Figure 12. Output power (THD = 10%) vs. supply voltage 120 110 Output power (W) 100 90 80 70 60 50 40 30 20 10 +10 +12 +14 +16 +18 +20 +22 +24 +26 +28 +30 +32 +34 +36 Supply voltage (V) Figure 13. THD vs. output power 10 5 THD+N (%) 2 1 0.5 0.2 f = 1 kHz 0.1 0.05 0.02 f = 100 Hz 0.01 0.005 100m 200m 500m 1 2 5 Output power (W) 16/28 Doc ID 16107 Rev 8 10 20 50 100 200 TDA7498 Characterizations Figure 14. THD vs. frequency (1 W) 2 1 THD+N (%) 0.5 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1k 2k 5k 10k 20k 2k 5k 10k 20k Frequency (Hz) Figure 15. THD vs. frequency (100 mW) 2 1 THD+N (%) 0.5 0.2 0.1 0.05 0.02 0.01 20 50 100 200 500 1k Frequency (Hz) Figure 16. Frequency response +3 +2.5 Ampl (dB) +2 +1.5 +1 +0.5 +0 -0.5 -1 -1.5 -2 -2.5 -3 10 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Doc ID 16107 Rev 8 17/28 Characterizations TDA7498 Figure 17. FFT performance (0 dB) ))7 G% N N N N N )UHTXHQF\ +] Figure 18. FFT performance (-60 dB) +0 -10 FFT (dB) -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 1k Frequency (Hz) 18/28 Doc ID 16107 Rev 8 2k 5k 10k 20k Applications information 4.1 Applications circuit TDA7498 4 Figure 19. Applications circuit for 6- or 8- speakers 1 C1 22 1uF C3 1nF C2 1uF C4 1nF J1 C5 INPUT 100nF Doc ID 16107 Rev 8 3 L- 4 L+ 1 R- 2 R+ 23 For J7 Single-Ended Input 27 SUB_GND OUTPA 16 INPA OUTPA 17 INNA PGNDA 14 PGNDA 15 VDDS R1 DIAG DIAG R3 24 ROSC J5 30 GAIN0 VDDS J8 31 GAIN1 32 3V3 C12 S2 1uF MUTE 1 2 3 120k R2 33k IN IC2 1 L4931CZ33 3 2 GND C9 100nF R8 VCC OUT C29 2.2uF C14 1nF R4 S1 STBY 1 2 3 6.8k D1 18V 19/28 3V3 POWER SUPPLY 220nF TDA7498 2 PVCCB 7 PVCCB 6 + + 2200uF 22uH C23+ 50V L1 3 OUTPB 8R L3 * OUTPB R5 * 33 5 * C18 220nF C20 PGNDB 4 9 8 * * R17 8R C43 C22 220nF R18 8R L2 * 220nF 220nF C21 330pF 34 21 MUTE 680nF 1uF INNB C15 2.2uF 20 STBY 16V GND C42 PGNDB VREF VCC 2 22uH C31 OUTNB 1 J2 22R 100nF OUTNB C41 220nF R16 330pF IC1 SVCC INPB J3 OUTPUT Load = 6 ohm L+ 1 L2 R3 R+ 4 22uH C17 SVR 29 C7 2.2uF 16V TDA7498 CLASS-D AMPLIFIER 10uF 10V C16 10uF 10V LC FILTER COMPONENTS Load L1,L2,L3,L4 6 ohm 22 uH 680 nF 220 nF 8 ohm 22 uH 470 nF 220 nF C20,C26 C18,C22,C24,C28 Applications information C13 1nF C40 * C24 PVCCA 13 C10 1uF J4 680nF C19 35 C11 FS 1uF J6 For Single-Ended Input 100nF 36 VSS 3V3 100nF PVCCA 12 OUTNA 11 18 PGND 25 SYNCLK * C26 C27 C6 39K 220nF C30 19 VDDPW 100nF 8R C28 22R C25 OUTNA 10 FREQUENCY SHIFT R9 Q1 KTC3875(S) 180K 3 C8 R13 FS 100nF 1 47k 2 R14 100k R15 * 220nF 100k R7 22R * R6 SGND VDDS 26 28 L4 22uH Applications information 4.2 TDA7498 Mode selection The three operating modes of the TDA7498 are set by the two inputs, STBY (pin 20) and MUTE (pin 21). Standby mode: all circuits are turned off, very low current consumption. Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty cycle. Play mode: the amplifiers are active. The protection functions of the TDA7498 are enabled by pulling down the voltages of the STBY and MUTE inputs shown in Figure 20. The input current of the corresponding pins must be limited to 200 A. Table 7. Mode settings Mode STBY MUTE L (1) Standby Mute H Play H X (don't care) (1) L H 1. Drive levels defined in Table 6: Electrical specifications on page 8 Figure 20. Standby and mute circuits Standby 3.3 V 0V STBY R2 30 k C7 2.2 F R4 30 k C15 2.2 F Mute MUTE 3.3 V 0V TDA7498 Figure 21. Turn on/off sequence for minimizing speaker "pop" VCC 0 t STBY 0 t MUTE 0 Input t 0 t Output 0 t Standby Mute Play Mute Standby Iq 0 20/28 t Doc ID 16107 Rev 8 TDA7498 4.3 Applications information Gain setting The gain of the TDA7498 is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin31). Internally, the gain is set by changing the feedback resistors of the amplifier. Table 8. Gain settings GAIN0 4.4 GAIN1 Nominal gain, Gv (dB) L L 25.6 L H 31.6 H L 35.6 H H 37.6 Input resistance and capacitance The input impedance is set by an internal resistor Ri = 60 k (typical). An input capacitor (Ci) is required to couple the AC input signal. The equivalent circuit and frequency response of the input components are shown in Figure 22. For Ci = 470 nF the high-pass filter cutoff frequency is below 20 Hz: fC = 1 / (2 * * Ri * Ci) Figure 22. Input circuit and frequency response Rf Input signal Ci Input pin Ri Doc ID 16107 Rev 8 21/28 Applications information 4.5 TDA7498 Internal and external clocks The clock of the class-D amplifier can be generated internally or can be driven by an external source. If two or more class-D amplifiers are used in the same system, it is recommended that all devices operate at the same clock frequency. This can be implemented by using one TDA7498 as master clock, while the other devices are in slave mode, that is, externally clocked. The clock interconnect is via pin SYNCLK of each device. As explained below, SYNCLK is an output in master mode and an input in slave mode. 4.5.1 Master mode (internal clock) Using the internal oscillator, the output switching frequency, fSW, is controlled by the resistor, ROSC, connected to pin ROSC: fSW = 106 / ((ROSC * 16 + 182) * 4) kHz where ROSC is in k. In master mode, pin SYNCLK is used as a clock output pin whose frequency is: fSYNCLK = 2 * fSW For master mode to operate correctly then resistor ROSC must be less than 60 k as given below in Table 9. 4.5.2 Slave mode (external clock) In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin SYNCLK to be internally configured as an input as given in Table 9. The output switching frequency of the slave devices is: fSW = fSYNCLK / 2 Table 9. How to set up SYNCLK Mode ROSC SYNCLK Master ROSC < 60 k Output Slave Floating (not connected) Input Figure 23. Master and slave connection Master Slave TDA7498 TDA7498 ROSC SYNCLK Output Cosc 100 nF 22/28 Rosc 39 k Doc ID 16107 Rev 8 SYNCLK Input ROSC TDA7498 4.6 Applications information Output low-pass filter To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The cutoff frequency should be larger than 22 kHz and much lower than the output switching frequency. It is necessary to choose the L and C component values depending on the loud-speaker impedance. Some typical values, which give a cutoff frequency of 27 kHz, are shown in Figure 24 and Figure 25 below. Figure 24. Typical LC filter for a 8- speaker Figure 25. Typical LC filter for a 6- speaker Doc ID 16107 Rev 8 23/28 Applications information 4.7 TDA7498 Protection functions The TDA7498 is fully protected against overvoltages, undervoltages, overcurrents and thermal overloads as explained here. Overvoltage protection (OVP) If the supply voltage exceeds the value for VOVP given in Table 6: Electrical specifications on page 8 the overvoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage falls back to within the operating range the device restarts. Undervoltage protection (UVP) If the supply voltage drops below the value for VUVP given in Table 6: Electrical specifications on page 8 the undervoltage protection is activated which forces the outputs to the high-impedance state. When the supply voltage recovers to within the operating range the device restarts. Overcurrent protection (OCP) If the output current exceeds the value for IOCP given in Table 6: Electrical specifications on page 8 the overcurrent protection is activated which forces the outputs to the high-impedance state. Periodically, the device attempts to restart. If the overcurrent condition is still present then the OCP remains active. The restart time, TOC, is determined by the R-C components connected to pin STBY. Thermal protection (OTP) If the junction temperature, Tj, reaches 145 C (nominally), the device goes to mute mode and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction temperature reaches the value for Tj given in Table 6: Electrical specifications on page 8 the device shuts down and the output is forced to the high-impedance state. When the device cools sufficiently the device restarts. 4.8 Diagnostic output The output pin DIAG is an open drain transistor. When any protection is activated it switches to the high-impedance state. The pin can be connected to a power supply (< 39 V) by a pull-up resistor whose value is limited by the maximum sinking current (200 A) of the pin. Figure 26. Behavior of pin DIAG for various protection conditions VDD TDA7498 R1 DIAG Protection logic VDD Restart Restart Overcurrent protection 24/28 OV, UV, OT protection Doc ID 16107 Rev 8 TDA7498 5 Package mechanical data Package mechanical data The TDA7498 comes in a 36-pin PowerSSO package with exposed pad up. Figure 27 shows the package outline and Table 10 gives the dimensions. Table 10. PowerSSO36 EPU dimensions Dimensions in mm Dimensions in inches Symbol Min Typ Max Min Typ Max A 2.15 - 2.45 0.085 - 0.096 A2 2.15 - 2.35 0.085 - 0.093 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees - - 8 degrees L 0.60 - 1.00 0.024 - 0.039 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 4.90 - 7.10 0.193 - 0.280 In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Doc ID 16107 Rev 8 25/28 h x 45 Package mechanical data 26/28 Figure 27. PowerSSO36 EPU outline drawing Doc ID 16107 Rev 8 TDA7498 TDA7498 6 Revision history Revision history Table 11. Document revision history Date Revision 11-Aug-2009 1 Initial release. 27-Aug-2009 2 Updated supply voltage range on page 1 Updated package exposed pad dimension Y (Min) in Table 10 on page 25. 3 Updated first feature on page 1 Updated order code name in Table 1 on page 1 Updated Table 5: Electrical specifications on page 8 Updated Section 3.2: Characterization curves on page 13 Removed tables for standby, mute and gain after Figure 19 on page 19. 30-Jun-2010 4 Removed datasheet preliminary status, updated features list and updated Device summary table on page 1 Added Table 5: Recommended operating conditions on page 8 with updated minimum supply voltage. 27-Jan-2011 5 Updated applications circuit in Figure 19 on page 19. 11-Feb-2011 6 Updated test circuit for characterizations in Figure 3 on page 11. 29-Mar-2011 7 Updated IOCP in Table 6: Electrical specifications. 12-Sep-2011 8 Updated OUTNA in Table 2: Pin description list 23-Oct-2009 Changes Doc ID 16107 Rev 8 27/28 TDA7498 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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