September 2011 Doc ID 16107 Rev 8 1/28
28
TDA7498
100-watt + 100-watt dual BTL class-D audio amplifier
Features
■100-W + 100-W output power at
THD = 10% with RL = 6 Ω and VCC = 36 V
■80-W + 80-W output power at
THD = 10% with RL = 8 Ω and VCC = 34 V
■Wide-range single-supply operation (14 - 39 V)
■High efficiency (η = 90%)
■Four selectable, fixed gain settings of
nominally 25.6 dB, 31.6 dB, 35.1 dB and
37.6 dB
■Differential inputs minimize common-mode
noise
■Standby and mute features
■Short-circuit protection
■Thermal overload protection
■Externally synchronizable
Description
The TDA7498 is a dual BTL class-D audio
amplifier with single power supply designed for
home systems and active speaker applications.
It comes in a 36-pin PowerSSO package with
exposed pad up (EPU) to facilitate mounting a
separate heatsink.
PowerSSO36
with exposed pad up
Table 1. Device summary
Order code Operating temp. range Package Packaging
TDA7498 -40 to 85 °C PowerSSO36 (EPU) Tube
TDA7498TR -40 to 85 °C PowerSSO36 (EPU) Tape and reel
www.st.com
Contents TDA7498
2/28 Doc ID 16107 Rev 8
Contents
1 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Characterizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1 For RL = 6 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.2.2 For RL = 8 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 Applications circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.4 Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.5 Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5.1 Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.5.2 Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.6 Output low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7 Protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.8 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TDA7498 List of figures
Doc ID 16107 Rev 8 3/28
List of figures
Figure 1. Internal block diagram (showing one channel only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pin connections (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Test circuit for characterizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Output power (THD = 10%) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. THD vs. frequency (1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. THD vs. frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. FFT performance (0 dBFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. FFT performance (-60 dBFS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Output power (THD = 10%) vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. THD vs. frequency (1 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 15. THD vs. frequency (100 mW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. Frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17. FFT performance (0 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 18. FFT performance (-60 dB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 19. Applications circuit for 6- or 8-Ω speakers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. Standby and mute circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 21. Turn on/off sequence for minimizing speaker “pop” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22. Input circuit and frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 23. Master and slave connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 24. Typical LC filter for a 8-Ω speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 25. Typical LC filter for a 6-Ω speaker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 26. Behavior of pin DIAG for various protection conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 27. PowerSSO36 EPU outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
List of tables TDA7498
4/28 Doc ID 16107 Rev 8
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 7. Mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. Gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 9. How to set up SYNCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 10. PowerSSO36 EPU dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TDA7498 Device block diagram
Doc ID 16107 Rev 8 5/28
Device block diagram
Figure 1 shows the block diagram of one of the two identical channels of the TDA7498.
Figure 1. Internal block diagram (showing one channel only)
Pin description TDA7498
6/28 Doc ID 16107 Rev 8
1 Pin description
1.1 Pinout
Figure 2. Pin connections (top view, PCB view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
28
29
30
31
32
33
34
35
36
19
20
21
22
23
24
25
26
27
VSS SUB_GND
OUTPB
OUTPB
PGNDB
PGNDB
PVCCB
PVCCB
OUTNB
OUTNB
OUTNA
OUTNA
PVCCA
PVCCA
PGNDA
PGNDA
OUTPA
OUTPA
PGND
VDDPW
STBY
MUTE
INPA
INNA
ROSC
SYNCLK
VDDS
SGND
DIAG
SVR
GAIN0
GAIN1
INPB
INNB
VREF
SVCC
EP, exposed pad
Connect to ground
TDA7498 Pin description
Doc ID 16107 Rev 8 7/28
1.2 Pin list
Table 2. Pin description list
Number Name Type Description
1 SUB_GND PWR Connect to the frame
2,3 OUTPB O Positive PWM for right channel
4,5 PGNDB PWR Power stage ground for right channel
6,7 PVCCB PWR Power supply for right channel
8,9 OUTNB O Negative PWM output for right channel
10,11 OUTNA O Negative PWM output for left channel
12,13 PVCCA PWR Power supply for left channel
14,15 PGNDA PWR Power stage ground for left channel
16,17 OUTPA O Positive PWM output for left channel
18 PGND PWR Power stage ground
19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power
stage
20 STBY I Standby mode control
21 MUTE I Mute mode control
22 INPA I Positive differential input of left channel
23 INNA I Negative differential input of left channel
24 ROSC O Master oscillator frequency-setting pin
25 SYNCLK I/O Clock in/out for external oscillator
26 VDDS O 3.3-V (nominal) regulator output referred to ground for signal
blocks
27 SGND PWR Signal ground
28 DIAG O Open-drain diagnostic output
29 SVR O Supply voltage rejection
30 GAIN0 I Gain setting input 1
31 GAIN1 I Gain setting input 2
32 INPB I Positive differential input of right channel
33 INNB I Negative differential input of right channel
34 VREF O Half VDDS (nominal) referred to ground
35 SVCC PWR Signal power supply
36 VSS O 3.3-V (nominal) regulator output referred to power supply
- EP - Exposed pad for heatsink, to be connected to ground
Electrical specifications TDA7498
8/28 Doc ID 16107 Rev 8
2 Electrical specifications
2.1 Absolute maximum ratings
2.2 Thermal data
2.3 Recommended operating conditions
2.4 Electrical specifications
Unless otherwise stated, the values in the table below are specified for the conditions:
VCC =36V, R
L = 6 Ω, ROSC = R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 25.6 dB
Tamb = 25 °C.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage for pins PVCCA, PVCCB, SVCC 44 V
VIVoltage limits for input pins STBY, MUTE, INNA, INPA,
INNB, INPB, GAIN0, GAIN1 -0.3 to 3.6 V
TjOperating junction temperature -40 to 150 °C
Tstg Storage temperature -40 to 150 °C
Table 4. Thermal data
Symbol Parameter Min Typ Max Unit
Rth j-case Thermal resistance, junction to case - 2 3 °C/W
Table 5. Recommended operating conditions
Symbol Parameter Min Typ Max Unit
VCC Supply voltage for pins PVCCA, PVCCB, SVCC 14 - 39 V
Tamb Ambient operating temperature -40 - 85 °C
Table 6. Electrical specifications
Symbol Parameter Condition Min Typ Max Unit
IqTotal quiescent current No LC filter, no load - 40 60 mA
IqSTBY Quiescent current in standby - - 1 10 µA
VOS Output offset voltage Play mode -100 - 100 mV
Mute mode -60 - 60
IOCP Overcurrent protection threshold RL = 0 Ω67- A
TDA7498 Electrical specifications
Doc ID 16107 Rev 8 9/28
Tj
Junction temperature at thermal
shutdown - - 150 - °C
RiInput resistance Differential input 48 60 - kΩ
VOVP Overvoltage protection threshold - 42 43 - V
VUVP
Undervoltage protection
threshold - --8V
RdsON Power transistor on resistance High side - 0.2 -
Ω
Low side - 0.2 -
PoOutput power THD = 10% - 100 - W
THD = 1% - 78 -
PoOutput power RL = 8 Ω, THD = 10% - 80 - W
PDDissipated power Po = 100 W + 100 W,
THD = 10% -20-W
ηEfficiency Po = 100 W + 100 W - 90 - %
THD Total harmonic distortion Po = 1 W - 0.1 - %
GVClosed-loop gain
GAIN0 = L, GAIN1 = L 24.6 25.6 26.6
dB
GAIN0 = L, GAIN1 = H 30.6 31.6 32.6
GAIN0 = H, GAIN1 = L 34.1 35.1 36.1
GAIN0 = H, GAIN1 = H 36.6 37.6 38.6
ΔGVGain matching - -1 - 1 dB
CTCrosstalk f = 1 kHz, Po = 1 W 5070- dB
eN Total input noise A Curve, GV = 20 dB - 15 - µV
f = 22 Hz to 22 kHz - 25 50
SVRR Supply voltage rejection ratio fr = 100 Hz, Vr = 0.5 Vpp,
CSVR = 10 µF -70-dB
Tr, TfRise and fall times - - 50 - ns
fSW Switching frequency Internal oscillator 290 310 330 kHz
fSWR
Output switching frequency
range
With internal oscillator (1) 250 - 400 kHz
With external oscillator (2) 250 - 400
VinH Digital input high (H) -2.3 - - V
VinL Digital input low (L) - - 0.8
Table 6. Electrical specifications (continued)
Symbol Parameter Condition Min Typ Max Unit
Electrical specifications TDA7498
10/28 Doc ID 16107 Rev 8
VSTBY
Pin STBY voltage high (H) -2.7 - - V
Pin STBY voltage low (L) - - 0.5
VMUTE
Pin MUTE voltage high (H) -2.5 - - V
Pin MUTE voltage low (L) - - 0.8
AMUTE Mute attenuation VMUTE = L, VSTBY = H - 70 - dB
1. fSW = 106 / ((16 * ROSC + 182) * 4) kHz, fSYNCLK = 2 * fSW with R3 = 39 kΩ (see Figure 19.).
2. fSW = fSYNCLK / 2 with the external oscillator.
Table 6. Electrical specifications (continued)
Symbol Parameter Condition Min Typ Max Unit
TDA7498 Characterizations
Doc ID 16107 Rev 8 11/28
3 Characterizations
3.1 Test circuit
Figure 3 shows the test circuit with which the characterization curves, shown in the next sections, were measured. Figure 4 shows
the PCB layout.
Figure 3. Test circuit for characterizations
L+
R+
R-
VCC
GND
L+
L-
R+
R-
TDA7498
MUTE
STBY
3V3 POWER SUPPLY
Single-Ended
*
*
*
*
*
Input
CLASS-D AMPLIFIER
*
*
*
*
Single-Ended
Input
Load = 6 ohm
For
For
FREQUENCY SHIFT
OUTPUT
INPUT
L-
*
LC FILTER COMPONENTS
LoadL1,L2,L3,L4 C20,C26 C18,C22,C24,C28
6 ohm
8 ohm
22 uH
22 uH 470 nF
680 nF
220 nF
220 nF
C5
100nF
R3
39K
L4
22uH
C1
1uF
C2
1uF
C11
1uF
C12
1uF
C8
100nF
C25
100nF
C19
100nF
C27
330pF
R6
22R C40
220nF
C41
220nF
C21
330pF
R5
22R
C42
220nF
C43
220nF
C14
1nF
32INPB
36VSS
9
OUTNB
5
PGNDB
7
PVCCB
3
OUTPB
10
OUTNA
12
PVCCA
14
PGNDA
16
OUTPA
33 INNB
8
OUTNB
4
PGNDB
21 MUTE
6
PVCCB
2
OUTPB
29
SVR
11
OUTNA
1SUB_GND
22 INPA
23INNA
27 SGND
26 VDDS
28DIAG
19 VDDPW
18PGND
20 STBY
24 ROSC
31GAIN1
35SVCC
30GAIN0
25 SYNCLK
17
OUTPA
15
PGNDA
34
VREF
13
PVCCA
IC1
TDA7498
R1
100k
R7
22R
C6
100nF
R4
120k
R2
33k
R8
6.8k
C26
680nF
C10
100nF
C20
680nF
J6
J5
2
1
3
S1
2
1
3
S2
C29
2.2uF
2GND
1
OUT
3
IN
IC2
L4931CZ33
1
2
J2
J8
J7
+
C23
2200uF
50V
L3
22uH
L1
22uH
L2
22uH
J4
C30
1uF
C31
1uF
R14
100k
R15
8R
C28
220nF
R16
8R
C24
220nF
R17
8R
C18
220nF
R18
8R
C22
220nF
1
2
3
4
J3
2
4
1
3
J1
R13
47k
C13
1nF
+
C15
2.2uF
16V
+
C7
2.2uF
16V
D1
18V
C9
100nF
C4
1nF
C3
1nF
C16
10uF
10V
C17
10uF
10V
R9
180K
1
2
3
Q1
KTC3875(S)
DIAG
VCC
3V3
3V3FS
FS
VDDS
VDDS
Characterizations TDA7498
12/28 Doc ID 16107 Rev 8
Figure 4. Test board
TDA7498 Characterizations
Doc ID 16107 Rev 8 13/28
3.2 Characterization curves
Unless otherwise stated the measurements were made under the following conditions:
VCC = 36 V, f = 1 kHz, GV = 25.6 dB, ROSC = 39 kΩ, COSC = 100 nF, Tamb = 25 °C
3.2.1 For RL = 6 Ω
Figure 5. Output power (THD = 10%) vs. supply voltage
Figure 6. THD vs. output power
10
120
20
30
40
50
60
70
80
90
100
110
Output power (W)
+10 +36+12 +14 +16 +18+20 +22 +24 +26 +28+30+32+34
Supply voltage (V)
0.005
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
THD+N (%)
100m 200200m 500m 1 2 5 10 20 50 100
Output power (W)
f = 1 kHz
f = 100 Hz
Characterizations TDA7498
14/28 Doc ID 16107 Rev 8
Figure 7. THD vs. frequency (1 W)
Figure 8. THD vs. frequency (100 mW)
Figure 9. Frequency response
THD+N (%)
20 20k50 100 200 500 1k 2k 5k 10k
Frequency (Hz)
0.01
2
0.02
0.05
0.1
0.2
0.5
1
0.01
2
0.02
0.05
0.1
0.2
0.5
1
THD+N (%)
20 20k50 100 200 500 1k 2k 5k 10k
Frequency (Hz)
-3
+3
-2.5
-2
-1.5
-1
-0.5
+0
+0.5
+1
+1.5
+2
+2.5
Ampl (dB)
10 20k20 50 100 200 500 1k 2k 5k 10k
Frequency (Hz)
TDA7498 Characterizations
Doc ID 16107 Rev 8 15/28
Figure 10. FFT performance (0 dBFS)
Figure 11. FFT performance (-60 dBFS)
FFT (dB)
20 20k50 100 200 500 1k 2k 5k 10k
Frequency (Hz)
-180
+0
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
FFT (dB)
20 20k50 100 200 500 1k 2k 5k 10k
Frequency (Hz)
-180
+0
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
Characterizations TDA7498
16/28 Doc ID 16107 Rev 8
3.2.2 For RL = 8 Ω
Figure 12. Output power (THD = 10%) vs. supply voltage
Figure 13. THD vs. output power
10
120
20
30
40
50
60
70
80
90
100
110
Output power (W)
+10 +36+12 +14 +16 +18+20 +22 +24 +26 +28+30+32+34
Supply voltage (V)
0.005
10
0.01
0.02
0.05
0.1
0.2
0.5
1
2
5
THD+N (%)
100m 200200m 500m 1 2 5 10 20 50 100
Output power (W)
f = 1 kHz
f = 100 Hz
TDA7498 Characterizations
Doc ID 16107 Rev 8 17/28
Figure 14. THD vs. frequency (1 W)
Figure 15. THD vs. frequency (100 mW)
Figure 16. Frequency response
THD+N (%)
20 20k50 100 200 500 1k 2k 5k 10k
Frequency (Hz)
0.01
2
0.02
0.05
0.1
0.2
0.5
1
THD+N (%)
20 20k50 100 200 500 1k 2k 5k 10k
Frequency (Hz)
0.01
2
0.02
0.05
0.1
0.2
0.5
1
-3
+3
-2.5
-2
-1.5
-1
-0.5
+0
+0.5
+1
+1.5
+2
+2.5
Ampl (dB)
10 20k20 50 100 200 500 1k 2k 5k 10k
Frequency (Hz)
Characterizations TDA7498
18/28 Doc ID 16107 Rev 8
Figure 17. FFT performance (0 dB)
Figure 18. FFT performance (-60 dB)
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)UHTXHQF\+]

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
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












FFT (dB)
20 20k50 100 200 500 1k 2k 5k 10k
Frequency (Hz)
-180
+0
-170
-160
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
TDA7498 Applications information
Doc ID 16107 Rev 8 19/28
4 Applications information
4.1 Applications circuit
Figure 19. Applications circuit for 6- or 8-Ω speakers
L+
R+
R-
VCC
GND
L+
L-
R+
R-
TDA7498
MUTE
STBY
3V3 POWER SUPPLY
Single-Ended
*
*
*
*
*
Input
CLASS-D AMPLIFIER
*
*
*
*
Single-Ended
Input
Load = 6 ohm
For
For
FREQUENCY SHIFT
OUTPUT
INPUT
L-
*
LC FILTER COMPONENTS
LoadL1,L2,L3,L4 C20,C26 C18,C22,C24,C28
6 ohm
8 ohm
22 uH
22 uH 470 nF
680 nF
220 nF
220 nF
C5
100nF
R3
39K
L4
22uH
C1
1uF
C2
1uF
C11
1uF
C12
1uF
C8
100nF
C25
100nF
C19
100nF
C27
330pF
R6
22R C40
220nF
C41
220nF
C21
330pF
R5
22R
C42
220nF
C43
220nF
C14
1nF
32INPB
36VSS
9
OUTNB
5
PGNDB
7
PVCCB
3
OUTPB
10
OUTNA
12
PVCCA
14
PGNDA
16
OUTPA
33 INNB
8
OUTNB
4
PGNDB
21 MUTE
6
PVCCB
2
OUTPB
29
SVR
11
OUTNA
1SUB_GND
22 INPA
23INNA
27 SGND
26 VDDS
28DIAG
19 VDDPW
18PGND
20 STBY
24 ROSC
31GAIN1
35SVCC
30GAIN0
25 SYNCLK
17
OUTPA
15
PGNDA
34
VREF
13
PVCCA
IC1
TDA7498
R1
100k
R7
22R
C6
100nF
R4
120k
R2
33k
R8
6.8k
C26
680nF
C10
100nF
C20
680nF
J6
J5
2
1
3
S1
2
1
3
S2
C29
2.2uF
2GND
1
OUT
3
IN
IC2
L4931CZ33
1
2
J2
J8
J7
+
C23
2200uF
50V
L3
22uH
L1
22uH
L2
22uH
J4
C30
1uF
C31
1uF
R14
100k
R15
8R
C28
220nF
R16
8R
C24
220nF
R17
8R
C18
220nF
R18
8R
C22
220nF
1
2
3
4
J3
2
4
1
3
J1
R13
47k
C13
1nF
+
C15
2.2uF
16V
+
C7
2.2uF
16V
D1
18V
C9
100nF
C4
1nF
C3
1nF
C16
10uF
10V
C17
10uF
10V
R9
180K
1
2
3
Q1
KTC3875(S)
DIAG
VCC
3V3
3V3FS
FS
VDDS
VDDS
Applications information TDA7498
20/28 Doc ID 16107 Rev 8
4.2 Mode selection
The three operating modes of the TDA7498 are set by the two inputs, STBY (pin 20) and
MUTE (pin 21).
●Standby mode: all circuits are turned off, very low current consumption.
●Mute mode: inputs are connected to ground and the positive and negative PWM
outputs are at 50% duty cycle.
●Play mode: the amplifiers are active.
The protection functions of the TDA7498 are enabled by pulling down the voltages of the
STBY and MUTE inputs shown in Figure 20. The input current of the corresponding pins
must be limited to 200 µA.
Figure 20. Standby and mute circuits
Figure 21. Turn on/off sequence for minimizing speaker “pop”
Table 7. Mode settings
Mode STBY MUTE
Standby L (1)
1. Drive levels defined in Table 6: Electrical specifications on page 8
X (don’t care)
Mute H (1) L
Play H H
STBY
MUTE
0 V
3.3 V C7
2.2 µF
R2
30 kΩ
Standby
0 V
3.3 V C15
2.2 µF
R4
30 kΩ
Mute
TDA7498
VCC
STBY
MUTE
Input
Output
Iq
Standby Mute Play Mute Standby
t
t
t
t
t
t
0
0
0
0
0
0
TDA7498 Applications information
Doc ID 16107 Rev 8 21/28
4.3 Gain setting
The gain of the TDA7498 is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin31).
Internally, the gain is set by changing the feedback resistors of the amplifier.
4.4 Input resistance and capacitance
The input impedance is set by an internal resistor Ri = 60 kΩ (typical). An input capacitor
(Ci) is required to couple the AC input signal.
The equivalent circuit and frequency response of the input components are shown in
Figure 22. For Ci = 470 nF the high-pass filter cutoff frequency is below 20 Hz:
fC = 1 / (2 * π * Ri * Ci)
Figure 22. Input circuit and frequency response
Table 8. Gain settings
GAIN0 GAIN1 Nominal gain, Gv (dB)
LL25.6
LH31.6
HL 35.6
HH37.6
Ri
Input
Ci
Rf
Input
pin
signal
Applications information TDA7498
22/28 Doc ID 16107 Rev 8
4.5 Internal and external clocks
The clock of the class-D amplifier can be generated internally or can be driven by an
external source.
If two or more class-D amplifiers are used in the same system, it is recommended that all
devices operate at the same clock frequency. This can be implemented by using one
TDA7498 as master clock, while the other devices are in slave mode, that is, externally
clocked. The clock interconnect is via pin SYNCLK of each device. As explained below,
SYNCLK is an output in master mode and an input in slave mode.
4.5.1 Master mode (internal clock)
Using the internal oscillator, the output switching frequency, fSW, is controlled by the
resistor, ROSC, connected to pin ROSC:
fSW = 106 / ((ROSC * 16 + 182) * 4) kHz
where ROSC is in kΩ.
In master mode, pin SYNCLK is used as a clock output pin whose frequency is:
fSYNCLK = 2 * fSW
For master mode to operate correctly then resistor ROSC must be less than 60 kΩ as given
below in Ta bl e 9 .
4.5.2 Slave mode (external clock)
In order to accept an external clock input the pin ROSC must be left open, that is, floating.
This forces pin SYNCLK to be internally configured as an input as given in Ta bl e 9 .
The output switching frequency of the slave devices is:
fSW = fSYNCLK / 2
Figure 23. Master and slave connection
Table 9. How to set up SYNCLK
Mode ROSC SYNCLK
Master ROSC < 60 kΩOutput
Slave Floating (not connected) Input
SYNCLK ROSC
Rosc
Cosc
ROSC SYNCLK
39 kΩ
100 nF
Output Input
Master Slave
TDA7498 TDA7498
TDA7498 Applications information
Doc ID 16107 Rev 8 23/28
4.6 Output low-pass filter
To avoid EMI problems, it may be necessary to use a low-pass filter before the speaker. The
cutoff frequency should be larger than 22 kHz and much lower than the output switching
frequency. It is necessary to choose the L and C component values depending on the
loud-speaker impedance. Some typical values, which give a cutoff frequency of 27 kHz, are
shown in Figure 24 and Figure 25 below.
Figure 24. Typical LC filter for a 8-Ω speaker
Figure 25. Typical LC filter for a 6-Ω speaker
Applications information TDA7498
24/28 Doc ID 16107 Rev 8
4.7 Protection functions
The TDA7498 is fully protected against overvoltages, undervoltages, overcurrents and
thermal overloads as explained here.
Overvoltage protection (OVP)
If the supply voltage exceeds the value for VOVP given in Table 6: Electrical specifications on
page 8 the overvoltage protection is activated which forces the outputs to the
high-impedance state. When the supply voltage falls back to within the operating range the
device restarts.
Undervoltage protection (UVP)
If the supply voltage drops below the value for VUVP given in Table 6: Electrical
specifications on page 8 the undervoltage protection is activated which forces the outputs to
the high-impedance state. When the supply voltage recovers to within the operating range
the device restarts.
Overcurrent protection (OCP)
If the output current exceeds the value for IOCP given in Table 6: Electrical specifications on
page 8 the overcurrent protection is activated which forces the outputs to the
high-impedance state. Periodically, the device attempts to restart. If the overcurrent
condition is still present then the OCP remains active. The restart time, TOC, is determined
by the R-C components connected to pin STBY.
Thermal protection (OTP)
If the junction temperature, Tj, reaches 145 °C (nominally), the device goes to mute mode
and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction
temperature reaches the value for Tj given in Table 6: Electrical specifications on page 8 the
device shuts down and the output is forced to the high-impedance state. When the device
cools sufficiently the device restarts.
4.8 Diagnostic output
The output pin DIAG is an open drain transistor. When any protection is activated it switches
to the high-impedance state. The pin can be connected to a power supply (< 39 V) by a
pull-up resistor whose value is limited by the maximum sinking current (200 µA) of the pin.
Figure 26. Behavior of pin DIAG for various protection conditions
TDA7498
Protection logic
R1
DIAG
VDD
VDD
Overcurrent
protection
Restart Restart
OV, UV, OT
protection
TDA7498 Package mechanical data
Doc ID 16107 Rev 8 25/28
5 Package mechanical data
The TDA7498 comes in a 36-pin PowerSSO package with exposed pad up.
Figure 27 shows the package outline and Ta bl e 1 0 gives the dimensions.
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Table 10. PowerSSO36 EPU dimensions
Symbol
Dimensions in mm Dimensions in inches
Min Typ Max Min Typ Max
A 2.15 - 2.45 0.085 - 0.096
A2 2.15 - 2.35 0.085 - 0.093
a1 0 - 0.10 0 - 0.004
b 0.18 - 0.36 0.007 - 0.014
c 0.23 - 0.32 0.009 - 0.013
D 10.10 - 10.50 0.398 - 0.413
E 7.40 - 7.60 0.291 - 0.299
e - 0.5 - - 0.020 -
e3 - 8.5 - - 0.335 -
F - 2.3 - - 0.091 -
G- - 0.10 - - 0.004
H 10.10 - 10.50 0.398 - 0.413
h- - 0.40 - - 0.016
k 0 - 8 degrees - - 8 degrees
L 0.60 - 1.00 0.024 - 0.039
M - 4.30 - - 0.169 -
N - - 10 degrees - - 10 degrees
O - 1.20 - - 0.047 -
Q - 0.80 - - 0.031 -
S - 2.90 - - 0.114 -
T - 3.65 - - 0.144 -
U - 1.00 - - 0.039 -
X 4.10 - 4.70 0.161 - 0.185
Y 4.90 - 7.10 0.193 - 0.280
Package mechanical data TDA7498
26/28 Doc ID 16107 Rev 8
Figure 27. PowerSSO36 EPU outline drawing
h x 45°
TDA7498 Revision history
Doc ID 16107 Rev 8 27/28
6 Revision history
Table 11. Document revision history
Date Revision Changes
11-Aug-2009 1 Initial release.
27-Aug-2009 2
Updated supply voltage range on page 1
Updated package exposed pad dimension Y (Min) in Table 10 on
page 25.
23-Oct-2009 3
Updated first feature on page 1
Updated order code name in Table 1 on page 1
Updated Table 5: Electrical specifications on page 8
Updated Section 3.2: Characterization curves on page 13
Removed tables for standby, mute and gain after Figure 19 on
page 19.
30-Jun-2010 4
Removed datasheet preliminary status, updated features list and
updated Device summary table on page 1
Added Table 5: Recommended operating conditions on page 8 with
updated minimum supply voltage.
27-Jan-2011 5 Updated applications circuit in Figure 19 on page 19.
11-Feb-2011 6 Updated test circuit for characterizations in Figure 3 on page 11.
29-Mar-2011 7 Updated IOCP in Table 6: Electrical specifications.
12-Sep-2011 8 Updated OUTNA in Table 2: Pin description list
TDA7498
28/28 Doc ID 16107 Rev 8
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