DS91M125EVK/NOPB - NATIONAL SEMICONDUCTOR

October 3, 2008

DS91M125

125 MHz 1:4 M-LVDS Repeater with LVDS Input

General Description

The DS91M125 is a 1:4 M-LVDS repeater designed for driv-

ing and distributing clock or data signals to up to four multi-

point networks.

M-LVDS (Multipoint LVDS) is a new family of bus interface

devices based on LVDS technology specifically designed for

multipoint and multidrop cable and backplane applications. It

differs from standard LVDS in providing increased drive cur-

rent to handle double terminations that are required in multi-

point applications. Controlled transition times minimize re-

flections that are common in multipoint configurations due to

unterminated stubs.

A single DS91M125 channel is a 1:4 repeater that accepts

M-LVDS/LVDS/CML/LVPECL signals and converts them to

M-LVDS signal levels. Each output has an associated inde-

pendent driver enable pin. The DS91M125 input conforms to

the LVDS standard.

The DS91M125 has a flow-through pinout for easy PCB lay-

out. It provides a new alternative for high speed multipoint

interface applications. It is packaged in a space saving

SOIC-16 package.

Features

■DC - 125 MHz / 250 Mbps low jitter, low skew, low power

operation

■Independent Driver Enable pins

■Outputs Conform to TIA/EIA-899 M-LVDS Standard

■Controlled transition times minimize reflections

■Inputs Conform to TIA/EIA-644-A LVDS Standard

■8 kV ESD on M-LVDS output pins protects adjoining

components

■Flow-through pinout simplifies PCB layout

■Industrial operating temperature range (−40°C to +85°C)

■Available in a space saving SOIC-16 package

Applications

■Multidrop / Multipoint clock and data distribution

■High-Speed, Low Power, Short-Reach alternative to

TIA/EIA-485/422

■Clock distribution in AdvancedTCA (ATCA) and MicroTCA

(μTCA, uTCA) backplanes

Typical Application

30054202

DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input

Ordering Information

Order Number Function Package Type

DS91M125TMA 1:4 Repeater SOIC-16

Connection Diagram

30054201

Logic Diagram

30054203

Pin Descriptions

Number Name I/O, Type Description

1, 2, 3, 8 DE I, LVCMOS Driver enable pins: When DE is low, the driver is disabled. When

DE is high, the driver is enabled. There is a 300 kΩ pulldown

resistor on each pin.

6 DI+ I, LVDS Non-inverting receiver input pin.

7 DI- I, LVDS Inverting receiver input pin.

5 GND Power Ground pin.

10, 11, 14, 15 A O, M-LVDS Non-inverting driver output pin.

9, 12, 13, 16 B O, M-LVDS Inverting driver output pin.

4 VDD Power Power supply pin, +3.3V ± 0.3V

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DS91M125

Absolute Maximum Ratings (Note 4)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Supply Voltage −0.3V to +4V

LVCMOS Input Voltages −0.3V to (VDD + 0.3V)

M-LVDS Output Voltages −1.9V to +5.5V

LVDS Input Voltages −0.3V to (VDD + 0.3V)

Maximum Package Power Dissipation at +25°C

SOIC Package 2.21W

Derate SOIC Package 19.2 mW/°C above +25°C

Thermal Resistance (4-Layer, 2 oz. Cu, JEDEC)

θJA 52°C/W

θJC 19°C/W

Maximum Junction Temperature 140°C

Storage Temperature Range −65°C to +150°C

Lead Temperature

(Soldering, 4 seconds) 260°C

ESD Susceptibility

HBM (Note 1) ≥ 8 kV

MM (Note 2) ≥ 250V

CDM (Note 3) ≥ 1250V

Note 1: Human Body Model, applicable std. JESD22-A114C

Note 2: Machine Model, applicable std. JESD22-A115-A

Note 3: Field Induced Charge Device Model, applicable std.

JESD22-C101-C

Recommended Operating

Conditions

Min Typ Max Units

Supply Voltage, VDD 3.0 3.3 3.6 V

Voltage at M-LVDS Outputs −1.4 +3.8 V

Voltage at LVDS Inputs 0 VDD V

LVCMOS Input Voltage High VIH 2.0 VDD V

LVCMOS Input Voltage Low VIL 0 0.8 V

Operating Free Air

Temperature TA−40 +25 +85 °C

Electrical Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 5, 6, 7, 10)

Symbol Parameter Conditions Min Typ Max Units

LVCMOS DC Specifications

VIH High-Level Input Voltage 2.0 VDD V

VIL Low-Level Input Voltage GND 0.8 V

IIH High-Level Input Current VIH = 3.6V -15 ±1 15 μA

IIL Low-Level Input Current VIL = 0V -15 ±1 15 μA

VCL Input Clamp Voltage IIN = -18 mA -1.5 V

M-LVDS Driver DC Specifications

|VAB| Differential output voltage magnitude RL = 50Ω, CL = 5pF 480 650 mV

ΔVAB Change in differential output voltage magnitude

between logic states

Figures 1, 3−50 0 +50 mV

VOS(SS) Steady-state common-mode output voltage RL = 50Ω, CL = 5pF 0.3 1.6 2.1 V

|ΔVOS(SS)|Change in steady-state common-mode output

voltage between logic states

Figures 1, 20 +50 mV

VA(OC) Maximum steady-state open-circuit output voltage Figure 4 0 2.4 V

VB(OC) Maximum steady-state open-circuit output voltage 0 2.4 V

VP(H) Voltage overshoot, low-to-high level output RL = 50Ω, CL = 5pF, CD = 0.5pF

Figures 6, 7 (Note 8) 1.2VSS V

VP(L) Voltage overshoot, high-to-low level output −0.2VS

IOS Differential short-circuit output current Figure 5 (Note 9) -43 43 mA

IADriver output current VA = 3.8V, VB = 1.2V 32 µA

VA = 0V or 2.4V, VB = 1.2V −20 +20 µA

VA = −1.4V, VB = 1.2V −32 µA

IBDriver output current VB = 3.8V, VA = 1.2V 32 µA

VB = 0V or 2.4V, VA = 1.2V −20 +20 µA

VB = −1.4V, VA = 1.2V −32 µA

IAB Driver output differential current (IA − IB)VA = VB, −1.4V ≤ V ≤ 3.8V −4 +4 µA

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DS91M125

Symbol Parameter Conditions Min Typ Max Units

IA(OFF) Driver output power-off current VA = 3.8V, VB = 1.2V,

DE = 0V

0V ≤ VDD ≤ 1.5V

32 µA

VA = 0V or 2.4V, VB = 1.2V,

DE = 0V

0V ≤ VDD ≤ 1.5V

−20 +20 µA

VA = −1.4V, VB = 1.2V,

DE = 0V

0V ≤ VDD ≤ 1.5V

−32 µA

IB(OFF) Driver output power-off current VB = 3.8V, VA = 1.2V,

DE = 0V

0V ≤ VDD ≤ 1.5V

32 µA

VB = 0V or 2.4V, VA = 1.2V,

DE = 0V

0V ≤ VDD ≤ 1.5V

−20 +20 µA

VB = −1.4V, VA = 1.2V,

DE = 0V

0V ≤ VDD ≤ 1.5V

−32 µA

IAB(OFF) Driver output power-off differential current (IA(OFF) −

IB(OFF))

VA = VB, −1.4V ≤ V ≤ 3.8V,

DE = 0V

0V ≤ VDD ≤ 1.5V

−4 +4 µA

CADriver output capacitance VDD = OPEN 7.8 pF

CBDriver output capacitance 7.8 pF

CAB Driver output differential capacitance 3 pF

CA/B Driver output capacitance balance (CA/CB) 1

LVDS Receiver DC Specifications

VIT+ Positive-going differential input voltage threshold -5 100 mV

VIT− Negative-going differential input voltage threshold −100 -5 mV

VCMR Common mode voltage range VID = 100 mV 0.05 VDD-

0.05

IIN Input current VIN = 3.6V, VDD = 3.6V ±1 ±10 µA

VIN = 0V, VDD = 3.6V ±1 ±10 µA

CIN Input capacitance VDD = OPEN 5 pF

POWER SUPPLY CURRENT

ICCD Driver Supply Current RL = 50Ω, DE = VDD 67 78 mA

ICCZ TRI-STATE Supply Current DE = GND 21 26 mA

Note 4: “Absolute Maximum Ratings” indicate limits beyond which damage

to the device may occur, including inoperability and degradation of device

reliability and/or performance. Functional operation of the device and/or non-

degradation at the Absolute Maximum Ratings or other conditions beyond

those indicated in the Recommended Operating Conditions is not implied.

The Recommended Operating Conditions indicate conditions at which the

device is functional and the device should not be operated beyond such

conditions.

Note 5: The Electrical Characteristics tables list guaranteed specifications

under the listed Recommended Operating Conditions except as otherwise

modified or specified by the Electrical Characteristics Conditions and/or

Notes. Typical specifications are estimations only and are not guaranteed.

Note 6: Current into device pins is defined as positive. Current out of device

pins is defined as negative. All voltages are referenced to ground except

VOD and ΔVOD.

Note 7: Typical values represent most likely parametric norms for VDD =

+3.3V and TA = +25°C, and at the Recommended Operation Conditions at

the time of product characterization and are not guaranteed.

Note 8: Specification is guaranteed by characterization and is not tested in

production.

Note 9: Output short circuit current (IOS) is specified as magnitude only,

minus sign indicates direction only.

Note 10: CL includes fixture capacitance and CD includes probe

capacitance.

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DS91M125

Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified. (Notes 11, 12, 18)

Symbol Parameter Conditions Min Typ Max Units

DRIVER AC SPECIFICATION

tPLH Differential Propagation Delay Low to High RL = 50Ω, CL = 5 pF, 3.0 5.5 8.5 ns

tPHL Differential Propagation Delay High to Low CD = 0.5 pF 3.0 5.5 8.5 ns

tSKD1 (tsk(p)) Pulse Skew |tPLHD − tPHLD| (Notes 14, 19) Figures 6, 7 65 350 ps

tSKD2 Channel-to-Channel Skew (Notes 15, 19) 65 400 ps

tSKD3 Part-to-Part Skew (Notes 16, 19) 2.2 2.5 ns

tSKD4 Part-to-Part Skew (Note 17) 5.5 ns

tTLH (tr) Rise Time (Note 19) 1.1 2.0 3.0 ns

tTHL (tf) Fall Time (Note 19) 1.1 2.0 3.0 ns

tPZH Enable Time (Z to Active High) RL = 50Ω, CL = 5 pF, 6 11 ns

tPZL Enable Time (Z to Active Low ) CD = 0.5 pF 6 11 ns

tPLZ Disable Time (Active Low to Z) Figures 8, 9 6 11 ns

tPHZ Disable Time (Active High to Z) 6 11 ns

fMAX Maximum Operating Frequency (Note 19) 125 MHz

Note 11: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics Conditions and/or Notes.

Note 12: Typical values represent most likely parametric norms for VDD = +3.3V and TA = +25°C, and at the Recommended Operation Conditions at the time of

product characterization and are not guaranteed.

Note 13: Specification is guaranteed by characterization and is not tested in production.

Note 14: tSKD1, |tPLHD − tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of

the same channel.

Note 15: tSKD2, Channel-to-Channel Skew, is the difference in propagation delay (tPLHD or tPHLD) among all output channels.

Note 16: tSKD3, Part-to-Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification

applies to devices at the same VDD and within 5°C of each other within the operating temperature range.

Note 17: tSKD4, Part-to-Part Skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over

recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay.

Note 18: CL includes fixture capacitance and CD includes probe capacitance.

Note 19: Specification is guaranteed by characterization and is not tested in production.

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DS91M125

Test Circuits and Waveforms

30054214

FIGURE 1. Differential Driver Test Circuit

30054224

FIGURE 2. Differential Driver Waveforms

30054222

FIGURE 3. Differential Driver Full Load Test Circuit

30054212

FIGURE 4. Differential Driver DC Open Test Circuit

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DS91M125

30054225

FIGURE 5. Differential Driver Short-Circuit Test Circuit

30054216

FIGURE 6. Driver Propagation Delay and Transition Time Test Circuit

30054218

FIGURE 7. Driver Propagation Delays and Transition Time Waveforms

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DS91M125

30054219

FIGURE 8. Driver TRI-STATE Delay Test Circuit

30054221

FIGURE 9. Driver TRI-STATE Delay Waveforms

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DS91M125

Typical Performance Characteristics

30054250

Driver Rise Time as a Function of Temperature

30054251

Driver Fall Time as a Function of Temperature

30054258

Driver Output Signal Amplitude as a Function of Resistive

Load

30054252

Driver Propagation Delay (tPLHD) as a Function of

Temperature

30054253

Driver Propagation Delay (tPHLD) as a Function of

Temperature

30054254

Driver Power Supply Current as a Function of Frequency

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DS91M125

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead (0.150″ Wide) Molded Small Outline Package, JEDEC

Order Number DS91M125TMA

NS Package Number M16A

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DS91M125

Notes

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DS91M125

Notes

DS91M125 125 MHz 1:4 M-LVDS Repeater with LVDS Input

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