Vishay Siliconix
Si1865DL
Document Number: 71297
S10-1054-Rev. D, 03-May-10
www.vishay.com
1
Load Switch with Level-Shift
DESCRIPTION
The Si1865DL includes a p- and p-channel MOSFET in a
single SC70-6 package. The low on-resistance p-channel
TrenchFET is tailored for use as a load switch. The
n-channel, with an external resistor, can be used as a level-
shift to drive the p-channel load-switch. The n-channel
MOSFET has internal ESD protection and can be driven by
logic signals as low as 1.5 V. The Si1865DL operates on
supply lines from 1.8 V to 8 V, and can drive loads up to 1.2 A.
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• 215 mΩ Low RDS(on) TrenchFET®
• 1.8 V to 8 V Input
• 1.5 V to 8 V Logic Level Control
• Low Profile, Small Footprint SC70-6 Package
• 2000 V ESD Protection On Input Switch, VON/OFF
• Adjustable Slew-Rate
• 1.8 V Rated
• Compliant to RoHS Directive 2002/95/EC
APPLICATION CIRCUITS
The Si1865DL is ideally suited for high-side load switching in
portable applications. The integrated n-channel level-shift
devices saves space by reducing external components. The
slew rate is set externally so that rise-times can be tailored to
different load types.
* Minimum R1 value should be least 10 x R2 to ensure Q1 turn-on.
PRODUCT SUMMARY
VDS2 (V) RDS(on) (Ω)I
D (A)
1.8 to 8
0.215 at VIN = 4.5 V ± 1.2
0.300 at VIN = 2.5 V ± 1.0
0.440 at VIN = 1.8 V ± 0.7
Si1865DL
VOUT
GND
LOAD
VIN
ON/OFF
R2
R2
1
2, 3
C1
6
4
6
5
R1
Q1
Q2
Co
Ci
Switching Variation
R2 at VIN = 2.5 V, R1 = 20 kΩ
0
4
8
12
16
20
0246810
R2 (kΩ)
I
L
= 1 A
V
ON/OFF
= 3 V
C
i
= 10 µF
C
o
= 1 µF t
r
t
d(on)
t
d(off)
t
f
e (µs)mi
T
Note: For R2 switching variations with other V
IN
/R1
combinations see Typical Characteristics
COMPONENTS
R1 Pull-Up Resistor Typical 10 kΩ to 1 mΩ*
R2 Optional Slew-Rate Control Typical 0 kΩ to 100 kΩ*
C1 Optional Slew-Rate Control Typical 1000 pF
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Document Number: 71297
S10-1054-Rev. D, 03-May-10
Vishay Siliconix
Si1865DL
FUNCTIONAL BLOCK DIAGRAM
Notes:
a) Surface mounted on FR4 board.
b) VIN = 8 V, VON/OFF = 8 V, TA = 25 °C.
c) Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
D2
SC70-6
Top View
6
4
1
2
3
5
S2
ON/OFF
R1, C1
D2
D2
R2
S2
ON/OFF
R2
1
4
6
5 Q1
Q2
Si1865DL
R1, C1
2, 3
Marking Code
VA XX
Lot Traceability
and Date Code
Part # Code
Y Y
Ordering Information: Si1865DL-T1-E3 (Lead (Pb)-free)
Si1865DL-T1-GE3 (Lead (Pb)-free and Halogen-free)
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter Symbol Limit Unit
Input Voltage VIN 8V
ON/OFF Voltage VON/OFF 8
Load Current Continuousa, b
IL
± 1.2
APulsedb, c ± 3
Continuous Intrinsic Diode ConductionaIS- 0.4
Maximum Power DissipationaPD0.4 W
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150 °C
ESD Rating, MIL-STD-833D Human Body Model (100 pF, 1500 Ω)ESD 2kV
THERMAL RESISTANCE RATINGS
Parameter Symbol Typical Maximum Unit
Maximum Junction-to-Ambient (continuous current)aRthJA 260 320 °C/W
Maximum Junction-to-Foot (Q2) RthJC 180 220
SPECIFICATIONS TJ = 25 °C unless otherwise noted
Parameter Symbol Test Conditions Min. Typ. Max. Unit
OFF Characteristics
Reverse Leakage Current VIN VIN = 8 V, VON/OFF = 0 V 1 µA
Diode Forward Voltage IQlS = - 0.4 A 0.85 1.1 V
ON Characteristics
Input Volatge VIN 1.8 8 V
On-Resistance (P-Channel) at 1 A RDS(on)
VON/OFF = 1.5 , VIN = 4.5 V, ID = 1.2 A 0.180 0.215
Ω
VON/OFF = 1.5 , VIN = 2.5 V, ID = 1.0 A 0.250 0.300
VON/OFF = 1.5 , VIN = 1.8 V, ID = 0.7 A 0.367 0.440
On-State (P-Channel) Drain-Current ID(on)
VIN-OUT ≤ 0.2 V, VIN = 5 V, VON/OFF = 1.5 A 1
A
VIN-OUT ≤ 0.3 V, VIN = 3 V, VON/OFF = 1.5 A 1
Document Number: 71297
S10-1054-Rev. D, 03-May-10
www.vishay.com
3
Vishay Siliconix
Si1865DL
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
VDROP vs. IL at VIN = 4.5 V
VDROP vs. IL at VIN = 1.8 V
VDROP Variance vs. Junction Temperature
0.0
0.2
0.4
0.6
0
.
8
0.0 0.5 1.0 1.5 2.0 2.5 3.0
IL (A)
)
V
(
V PORD
V
ON/OFF
= 1.5 V to 8 V
T
J
= 125 °C
T
J
= 25 °C
0.0
0.2
0.4
0.6
0.8
1.0
0.0 0.2 0.4 0.6 0.81.0 1.2 1.4 1.6
IL (A)
)V
(V
PO
RD
VON/OFF = 1.5 V to 8 V
TJ = 125 °C
TJ = 25 °C
- 0.10
- 0.06
- 0.02
0.02
0.06
0.10
- 50 - 25 0 25 50 75 100 125 150
TJ- Junction Temperature (°C)
)V( ecnaira
V
VPO
RD
IL = 0.7 A
V
ON/OFF
= 1.5 V to 8 V
V
IN
= 4.5 V
VIN = 1.8 V
VDROP vs. IL at VIN = 2.5 V
VDROP vs. IL at IL = 0.7 V
On-Resistance vs. Input Voltage
IL (A)
) V ( V PORD
V
ON/OFF
= 1.5 V to 8 V
T
J
= 125 °C
T
J
= 25 °C
0.0
0.2
0.4
0.6
0.8
1.0
0.0 0.5 1.0 1.5 2.0 2.5
0.0
0.2
0.4
0.6
0.8
0123456
V
IN
(V)
) V
( V PO
RD
V
ON/OFF
= 1.5 V to 8 V
T
J
= 125 °C
T
J
= 25 °C
0.0
0.2
0.4
0.6
0.8
1.0
0123456
-(Ω)
ecna
ts
is
e
R
-
nO
R)no(SS
VIN (V)
I
L
= 0.7 A
VON/OFF = 1.5 V to 8 V
T
J
= 125 °C
TJ = 25 °C
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Document Number: 71297
S10-1054-Rev. D, 03-May-10
Vishay Siliconix
Si1865DL
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Normalized On-Resistance vs.
Junction Temperature
Switching Variation
R2 at VIN = 2.5 V, R1 = 20 kΩ
Switching Variation
R2 at VIN = 4.5 V, R1 = 300 kΩ
0.5
0.7
0.9
1.1
1.3
1
.5
- 50 - 25 0 25 50 75 100 125 150
- ecnatsiseR-nO R )no(SD
TJ- Junction Temperature (°C)
IL = 0.7 A
V
ON/OFF
= 1.5 V to 8 V
V
IN
= 1.8 V
V
IN
= 4.5 V
(Normalized)
0
4
8
12
16
20
0246810
R2 (kΩ)
I
L
= 1 A
V
ON/OFF
= 3 V
C
i
= 10 µF
C
o
= 1 µF
e (µs)
m
iT
t
r
td(on)
t
d(off)
t
f
0
40
80
120
160
200
0 20406080 100
R2 (kΩ)
I
L
= 1 A
V
ON/OFF
= 3 V
C
i
= 10 µF
C
o
= 1 µF
e (µs)
m
iT
td(on)
tr
td(off)
t
f
Switching Variation
R2 at VIN = 1.8 V, R1 = 20 kΩ
Switching Variation
R2 at VIN = 1.8 V, R1 = 20 kΩ
Switching Variation
R2 at VIN = 2.5 V, R1 = 300 kΩ
R2 (kΩ)
e (µs)miT
t
r
I
L
= 1 A
V
ON/OFF
= 3 V
C
i
= 10 µF
C
o
= 1 µF t
f
td(on)
td(off)
0
4
8
12
16
20
0246810
0
6
12
18
24
30
02468
R2 (kΩ)
e (µs)m
iT
I
L
= 1 A
V
ON/OFF
= 3 V
C
i
= 10 µF
C
o
= 1 µF
td(on)
t
r
t
f
td(off)
0
30
60
90
120
150
020406080 100
R2 (kΩ)
e (µs)mi
T
I
L
= 1 A
V
ON/OFF
= 3 V
C
i
= 10 µF
C
o
= 1 µF
t
f
t
d(off)
t
r
t
d(on)
Document Number: 71297
S10-1054-Rev. D, 03-May-10
www.vishay.com
5
Vishay Siliconix
Si1865DL
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?71297.
Switching Variation
R2 at VIN = 1.8 V, R1 = 300 kΩ
0
30
60
90
120
0 20406080
R2 (kΩ)
e (µs)miT
I
L
= 1 A
V
ON/OFF
= 3 V
C
i
= 10 µF
C
o
= 1 µF
t
f
t
d(off)
t
r t
d(on)
Normalized Thermal Transient Impedance, Junction-to-Ambient
10-3 10-2 1 10 60010-1
10-4 100
2
1
0.1
0.01
tneisnarT evitce
ffE
dez
i
la
m
roN
e
c
nadepmI la
m
rehT
0.2
0.1
0.05
0.02
Single Pulse
Duty Cycle = 0.5
1. Duty Cycle, D =
2. Per Unit Base = R
thJA
= 320 °C
3. T
JM - T
A = PDMZthJA(t)
t
1
t
2
t
1
t
2
Notes:
4. Surface Mounted
P
DM
Square Wave Pulse Dureation (s)
L
c
E
E1
e
D
e1
A2A
A1
1
-A-
b
-B-
23
654
Package Information
Vishay Siliconix
Document Number: 71154
06-Jul-01 www.vishay.com
1
SCĆ70: 6ĆLEADS
MILLIMETERS INCHES
Dim Min Nom Max Min Nom Max
A0.90 – 1.10 0.035 – 0.043
A1– – 0.10 – – 0.004
A20.80 – 1.00 0.031 – 0.039
b0.15 – 0.30 0.006 – 0.012
c0.10 – 0.25 0.004 – 0.010
D1.80 2.00 2.20 0.071 0.079 0.087
E1.80 2.10 2.40 0.071 0.083 0.094
E11.15 1.25 1.35 0.045 0.049 0.053
e0.65BSC 0.026BSC
e11.20 1.30 1.40 0.047 0.051 0.055
L0.10 0.20 0.30 0.004 0.008 0.012
7_Nom 7_Nom
ECN: S-03946—Rev. B, 09-Jul-01
DWG: 5550
AN814
Vishay Siliconix
Document Number: 71237
12-Dec-03
www.vishay.com
1
Dual-Channel LITTLE FOOTR SC-70 6-Pin MOSFET
Recommended Pad Pattern and Thermal Performance
INTRODUCTION
This technical note discusses the pin-outs, package outlines,
pad patterns, evaluation board layout, and thermal
performance for dual-channel LITTLE FOOT power
MOSFETs in the SC-70 package. These new Vishay Siliconix
devices are intended for small-signal applications where a
miniaturized package is needed and low levels of current
(around 250 mA) need to be switched, either directly or by
using a level shift configuration. Vishay provides these devices
with a range of on-resistance specifications in 6-pin versions.
The new 6-pin SC-70 package enables improved
on-resistance values and enhanced thermal performance.
PIN-OUT
Figure 1 shows the pin-out description and Pin 1 identification
for the dual-channel SC-70 device in the 6-pin configuration.
FIGURE 1.
SOT-363
SC-70 (6-LEADS)
6
4
1
2
3
5
Top View
S1
G1
D2
D1
G2
S2
For package dimensions see outline drawing SC-70 (6-Leads)
(http://www.vishay.com/doc?71154)
BASIC PAD PATTERNS
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286) for the 6-pin
SC-70. This basic pad pattern is sufficient for the low-power
applications for which this package is intended. For the 6-pin
device, increasing the pad patterns yields a reduction in
thermal resistance on the order of 20% when using a 1-inch
square with full copper on both sides of the printed circuit board
(PCB).
EVALUATION BOARDS FOR THE DUAL
SC70-6
The 6-pin SC-70 evaluation board (EVB) measures 0.6 inches
by 0.5 inches. The copper pad traces are the same as
described in the previous section, Basic Pad Patterns. The
board allows interrogation from the outer pins to 6-pin DIP
connections permitting test sockets to be used in evaluation
testing.
The thermal performance of the dual SC-70 has been
measured on the EVB with the results shown below. The
minimum recommended footprint on the evaluation board was
compared with the industry standard 1-inch square FR4 PCB
with copper on both sides of the board.
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance
(the Package Performance)
Thermal performance for the dual SC-70 6-pin package
measured as junction-to-foot thermal resistance is 300_C/W
typical, 350_C/W maximum. The “foot” is the drain lead of the
device as it connects with the body. Note that these numbers
are somewhat higher than other LITTLE FOOT devices due to
the limited thermal performance of the Alloy 42 lead-frame
compared with a standard copper lead-frame.
Junction-to-Ambient Thermal Resistance
(dependent on PCB size)
The typical RθJA for the dual 6-pin SC-70 is 400_C/W steady
state. Maximum ratings are 460_C/W for the dual. All figures
based on the 1-inch square FR4 test board. The following
example shows how the thermal resistance impacts power
dissipation for the dual 6-pin SC-70 package at two different
ambient temperatures.
AN814
Vishay Siliconix
www.vishay.com
2
Document Number: 71237
12-Dec-03
SC-70 (6-PIN)
Room Ambient 25 _CElevated Ambient 60 _C
PD+TJ(max) *TA
RqJA
PD+150oC*25oC
400oCńW
PD+312 mW
PD+TJ(max) *TA
RqJA
PD+150oC*60oC
400oCńW
PD+225 mW
NOTE: Although they are intended for low-power applications,
devices in the 6-pin SC-70 will handle power dissipation in
excess of 0.2 W.
Testing
To aid comparison further, Figure 2 illustrates the dual-channel
SC-70 thermal performance on two different board sizes and
two different pad patterns. The results display the thermal
performance out to steady state. The measured steady state
values of RθJA for the dual 6-pin SC-70 are as follows:
LITTLE FOOT SC-70 (6-PIN)
1) Minimum recommended pad pattern (see
Figure 2) on the EVB of 0.5 inches x
0.6 inches.
518_C/W
2) Industry standard 1” square PCB with
maximum copper both sides. 413_C/W
Time (Secs)
FIGURE 2. Comparison of Dual SC70-6 on EVB and 1”
Square FR4 PCB.
Thermal Resistance (C/W)
0
1
500
100
200
100 1000
300
1010-1
10-2
10-3
10-4
10-5
1” Square FR4 PCB
Dual EVB
400
The results show that if the board area can be increased and
maximum copper traces are added, the thermal resistance
reduction is limited to 20%. This fact confirms that the power
dissipation is restricted with the package size and the Alloy 42
leadframe.
ASSOCIATED DOCUMENT
Single-Channel LITTLE FOOT SC-70 6-Pin MOSFET Copper
Leadframe Version, REcommended Pad Pattern and Thermal
Performance, AN815, (http://www.vishay.com/doc?71334).
Application Note 826
Vishay Siliconix
www.vishay.com Document Number: 72602
18 Revision: 21-Jan-08
APPLICATION NOTE
RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead
0.096
(2.438)
Recommended Minimum Pads
Dimensions in Inches/(mm)
0.067
(1.702)
0.026
(0.648)
0.045
(1.143)
0.016
(0.406)
0.026
(0.648)
0.010
(0.241)
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Revision: 12-Mar-12 1Document Number: 91000
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
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