VNQ810P (R) QUAD CHANNEL HIGH SIDE DRIVER TARGET SPECIFICATION TYPE VNQ810P RDS(on) 160 m (*) IOUT 3.5 A (*) VCC 36 V (*) Per each channel CMOS COMPATIBLE INPUTS OPEN DRAIN STATUS OUTPUTS ON STATE OPEN LOAD DETECTION OFF STATE OPEN LOAD DETECTION SHORTED LOAD PROTECTION UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN PROTECTION AGAINST LOSS OF GROUND VERY LOW STAND-BY CURRENT REVERSE BATTERY PROTECTION (**) DESCRIPTION The VNQ810P is a quad HSD formed by assembling two VND810 chips in the same SO-28 package. The VND810 is a monolithic device made by using STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active VCC pin voltage clamp protects the device SO-28 (DOUBLE ISLAND) ORDER CODES PACKAGE SO-28 TUBE T&R VNQ810P VNQ810P13TR against low energy spikes (see ISO7637 transient compatibility table). Active current limitation combined with thermal shutdown and automatic restart protects the device against overload. The device detects open load condition both in on and off state . Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection. ABSOLUTE MAXIMUM RATING Symbol VCC - VCC - Ignd IOUT - IOUT IIN ISTAT VESD EMAX Ptot Tj Tstg Parameter DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current DC Status Current Electrostatic Discharge (Human Body Model: R=1.5K; C=100pF) Value 41 - 0.3 - 200 Internally Limited -6 +/- 10 +/- 10 Unit V V mA A A mA mA - INPUT 4000 V - STATUS 4000 V - OUTPUT 5000 V - VCC Maximum Switching Energy 5000 V 23 mJ 6.25 Internally Limited - 55 to 150 W C C (L=1.38mH; RL=0; Vbat=13.5V; Tjstart=150C; IL=5A) Power dissipation (per island) at Tlead=25C Junction Operating Temperature Storage Temperature (**) See application schematic at page 9 October 2003 - Revision 1.2 (Working document) 1/20 This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice. VNQ810P BLOCK DIAGRAM VCC1,2 Vcc OVERVOLTAGE CLAMP UNDERVOLTAGE GND1,2 CLAMP 1 OUTPUT1 INPUT1 DRIVER 1 CLAMP 2 STATUS1 CURRENT LIMITER 1 LOGIC DRIVER 2 OUTPUT2 OVERTEMP. 1 OPENLOAD ON 1 CURRENT LIMITER 2 INPUT2 OPENLOAD OFF 1 OPENLOAD ON 2 STATUS2 OPENLOAD OFF 2 OVERTEMP. 2 VCC3,4 Vcc CLAMP OVERVOLTAGE UNDERVOLTAGE GND3,4 CLAMP 3 OUTPUT3 INPUT3 DRIVER 3 CLAMP 4 STATUS3 CURRENT LIMITER 3 LOGIC DRIVER 4 OUTPUT4 OVERTEMP. 3 OPENLOAD ON 3 CURRENT LIMITER 4 INPUT4 OPENLOAD OFF 3 OPENLOAD ON 4 STATUS4 OPENLOAD OFF 4 OVERTEMP. 4 2/20 VNQ810P CURRENT AND VOLTAGE CONVENTIONS IS1,2 IS3,4 VCC1,2 VCC1,2 VCC3,4 VCC3,4 IIN1 INPUT1 ISTAT1 VIN1 IIN2 VSTAT1 VSTAT3 INPUT4 VIN4 ISTAT4 VOUT2 OUTPUT3 STATUS3 IIN4 VOUT1 OUTPUT2 IOUT3 INPUT3 ISTAT3 VIN3 IOUT2 STATUS2 IIN3 VSTAT2 OUTPUT1 INPUT2 ISTAT2 VIN2 IOUT1 STATUS1 IOUT4 OUTPUT4 STATUS4 VOUT3 VOUT4 VSTAT4 GND3,4 GND1,2 IGND1,2 IGND3,4 CONNECTION DIAGRAM (TOP VIEW) VCC1,2 1 28 VCC1,2 GND 1,2 OUTPUT1 INPUT1 OUTPUT1 STATUS1 OUTPUT1 STATUS2 OUTPUT2 INPUT2 OUTPUT2 VCC1,2 OUTPUT2 VCC3,4 OUTPUT3 GND 3,4 OUTPUT3 INPUT3 OUTPUT3 STATUS3 OUTPUT4 STATUS4 OUTPUT4 INPUT4 OUTPUT4 VCC3,4 14 15 VCC3,4 3/20 VNQ810P THERMAL DATA (Per island) Symbol Rthj-lead Parameter Thermal Resistance Junction-lead per chip Value 20 Unit C/W Rthj-amb Thermal resistance Junction-ambient (one chip ON) 60 (*) C/W Rthj-amb Thermal resistance Junction-ambient (two chips ON) 46 (*) C/W (*) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40C< Tj <150C, unless otherwise specified) POWER OUTPUTS (Per each channel) Symbol VCC (**) VUSD (**) VOV (**) RON Parameter Operating Supply Voltage Undervoltage Shut-down Overvoltage Shut-down On State Resistance Test Conditions Min 5.5 3 36 Supply Current Off State Output Current Off State Output Current Off State Output Current Off State Output Current 12 320 40 m A 12 25 A 5 7 50 0 5 3 mA A A A A Typ Max Unit IOUT=1A; VCC>8V Off State; VCC=13V; VIN=VOUT=0V; Tj =25C On State; VCC=13V; VIN=5V; IOUT=0A IL(off1) IL(off2) IL(off3) IL(off4) 160 Unit V V V m IOUT=1A; Tj=25C Off State; VCC=13V; VIN=VOUT=0V IS (**) Typ 13 4 VIN=VOUT=0V VIN=0V; VOUT=3.5V VIN=VOUT=0V; VCC=13V; Tj =125C VIN=VOUT=0V; VCC=13V; Tj =25C 0 -75 Max 36 5.5 SWITCHING (Per each Channel) (VCC=13V) Symbol Parameter td(on) Turn-on Delay Time td(off) Turn-off Delay Time Test Conditions RL=13 from VIN rising edge to VOUT=1.3V RL=13 from VIN falling edge to VOUT=11.7V dVOUT/dt(on) Turn-on Voltage Slope RL=13 from VOUT=1.3V to VOUT=10.4V dVOUT/dt(off) Turn-off Voltage Slope RL=13 from VOUT=11.7V to VOUT=1.3V Min 30 s 30 s See relative diagram See relative diagram V/s V/s LOGIC INPUT (Per each channel) Symbol VIL IIL VIH IIH VI(hyst) VICL (**) Per island 4/20 1 Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current Input Hysteresis Voltage Input Clamp Voltage Test Conditions VIN=1.25V Min Typ 1 3.25 VIN=3.25V IIN=1mA IIN=-1mA Max 1.25 10 0.5 6 6.8 -0.7 8 Unit V A V A V V V VNQ810P ELECTRICAL CHARACTERISTICS (continued) VCC - OUTPUT DIODE Symbol VF Parameter Forward on Voltage Test Conditions -IOUT=0.5A; Tj=150C Min Typ Max 0.6 Unit V STATUS PIN (Per each channel) Symbol VSTAT ILSTAT CSTAT VSCL Parameter Test Conditions Status Low Output Voltage ISTAT=1.6mA Status Leakage Current Normal Operation; VSTAT=5V Status Pin Input Normal Operation; VSTAT=5V Capacitance ISTAT=1mA Status Clamp Voltage ISTAT=-1mA Min 6 Typ 6.8 Max 0.5 10 Unit V A 100 pF 8 V -0.7 V PROTECTIONS (Per each channel) Symbol TTSD TR Thyst tsdl Parameter Shut-down Temperature Reset Temperature Thermal Hysteresis Status Delay in Overload Conditions Ilim Current limitation VDEMAG Turn-off Output Clamp Voltage Test Conditions Min 150 135 7 Typ 175 5 5.5V<VCC<36V IOUT=1A; L=6mH Unit C C C 20 s 7.5 A 7.5 A 15 Tj>TTSD 3.5 Max 200 VCC-41 VCC-48 VCC-55 V OPENLOAD DETECTION (Per each channel) Symbol IOL tDOL(on) VOL tDOL(off) Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Openload OFF State Voltage Detection Threshold Openload Detection Delay at Turn Off Test Conditions Typ Max Unit 20 40 80 mA 200 s 3.5 V 1000 s VIN=5V IOUT=0A VIN=0V 1.5 OPEN LOAD STATUS TIMING (with external pull-up) VOUT > VOL Min 2.5 OVER TEMP STATUS TIMING IOUT < IOL Tj > TTSD VINn VINn VSTATn VSTATn tSDL tDOL(off) tSDL tDOL(on) 5/20 2 VNQ810P Switching time Waveforms VOUTn 90% 80% dVOUT/dt(off) dVOUT/dt(on) 10% t VINn td(on) td(off) t TRUTH TABLE CONDITIONS Normal Operation Current Limitation Overtemperature Undervoltage Overvoltage Output Voltage > VOL Output Current < IOL 6/20 INPUT L H L H H L H L H L H L H L H OUTPUT L H L X X L L L L L L H H L H STATUS H H H (Tj < TTSD) H (Tj > TTSD) L H L X X H H L H H L VNQ810P ELECTRICAL TRANSIENT REQUIREMENTS ON VCC PIN ISO T/R 7637/1 Test Pulse I II TEST LEVELS III IV 1 2 3a 3b 4 5 -25 V +25 V -25 V +25 V -4 V +26.5 V -50 V +50 V -50 V +50 V -5 V +46.5 V -75 V +75 V -100 V +75 V -6 V +66.5 V -100 V +100 V -150 V +100 V -7 V +86.5 V ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I C C C C C C TEST LEVELS RESULTS II III C C C C C C C C C C E E Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2 IV C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure and cannot be returned to proper operation without replacing the device. 7/20 VNQ810P Figure 1: Waveforms NORMAL OPERATION INPUTn OUTPUT VOLTAGEn STATUSn UNDERVOLTAGE VUSDhyst VCC VUSD INPUTn OUTPUT VOLTAGEn STATUSn undefined OVERVOLTAGE VCC>VOV VCC<VOV VCC INPUTn OUTPUT VOLTAGEn STATUSn OPEN LOAD with external pull-up INPUTn VOUT>VOL OUTPUT VOLTAGEn VOL STATUSn OPEN LOAD without external pull-up INPUTn OUTPUT VOLTAGEn STATUSn OVERTEMPERATURE Tj TTSD TR INPUTn OUTPUT CURRENTn STATUSn 8/20 1 VNQ810P APPLICATION SCHEMATIC +5V +5V +5V VCC1,2 VCC3,4 Rprot STATUS1 Rprot INPUT1 Dld Rprot STATUS2 Rprot INPUT2 Rprot STATUS3 C OUTPUT1 OUTPUT2 OUTPUT3 Rprot INPUT3 Rprot STATUS4 OUTPUT4 Rprot INPUT4 GND1,2 GND3,4 RGND DGND VGND +5V +5V Note: Channels 3 & 4 have the same internal circuit as channel 1 & 2. GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / 2(IS(on)max). 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggest to utilize Solution 2. 9/20 VNQ810P Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The 10/20 same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. C I/Os PROTECTION: If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k. VNQ810P OPEN LOAD DETECTION IN OFF STATE 2) no misdetection when load is disconnected: in this case the VOUT has to be higher than VOLmax; this results in the following condition RPU<(VPU-VOLmax)/ IL(off2). Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pull-up resistor RPU should be connected to a supply that is switched OFF when the module is in standby. The values of VOLmin, VOLmax and IL(off2) are available in the Electrical Characteristics section. Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition VOUT=(VPU/(RL+RPU))RL<VOlmin. Open Load detection in off state V batt. VPU VCC RPU INPUT DRIVER + LOGIC IL(off2) OUT + R STATUS VOL RL GROUND 11/20 VNQ810P High Level Input Current Off State Output Current IL(off1) (uA) Iih (uA) 1.6 5 1.44 4.5 Off state Vcc=36V Vin=Vout=0V 1.28 1.12 Vin=3.25V 4 3.5 0.96 3 0.8 2.5 0.64 2 0.48 1.5 0.32 1 0.16 0.5 0 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 50 Tc (C) 75 100 125 150 175 Tc (C) Input Clamp Voltage Status Leakage Current Vicl (V) Ilstat (uA) 8 0.05 7.8 Iin=1mA 7.6 0.04 7.4 Vstat=5V 0.03 7.2 7 6.8 0.02 6.6 6.4 0.01 6.2 6 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 Tc (C) 50 75 100 125 150 175 Tc (C) Status Low Output Voltage Status Clamp Voltage Vscl (V) Vstat (V) 8 0.8 7.8 0.7 Istat=1mA Istat=1.6mA 7.6 0.6 7.4 0.5 7.2 7 0.4 6.8 0.3 6.6 0.2 6.4 0.1 6.2 6 0 -50 -25 0 25 50 75 Tc (C) 12/20 100 125 150 175 -50 -25 0 25 50 75 Tc (C) 100 125 150 175 VNQ810P On State Resistance Vs Tcase On State Resistance Vs VCC Ron (mOhm) Ron (mOhm) 400 300 275 350 Iout=0.5A 250 Iout=0.5A Vcc=8V; 13V & 36V 300 Tc= 150C 225 250 200 200 175 150 150 Tc= 25C 125 100 100 Tc= - 40C 50 75 0 50 -50 -25 0 25 50 75 100 125 150 175 5 10 15 20 Tc (C) 25 30 35 40 Vcc (V) Openload On State Detection Threshold Input High Level Iol (mA) Vih (V) 60 3.6 55 3.4 Vcc=13V Vin=5V 50 3.2 45 3 40 2.8 35 30 2.6 25 2.4 20 2.2 15 2 10 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 100 125 150 175 Tc (C) Tc (C) Input Low Level Input Hysteresis Voltage Vil (V) Vhyst (V) 2.6 1.5 1.4 2.4 1.3 2.2 1.2 2 1.1 1.8 1 0.9 1.6 0.8 1.4 0.7 1.2 0.6 1 0.5 -50 -25 0 25 50 75 Tc (C) 100 125 150 175 -50 -25 0 25 50 75 Tc (C) 13/20 VNQ810P Overvoltage Shutdown Openload Off State Voltage Detection Threshold Vov (V) Vol (V) 50 5 48 4.5 46 4 44 3.5 Vin=0V 42 3 40 2.5 38 2 36 1.5 34 1 32 0.5 30 0 -50 -25 0 25 50 75 100 125 150 175 -50 -25 0 25 Tc (C) 75 100 125 150 175 100 125 150 175 Tc (C) Turn-on Voltage Slope Turn-off Voltage Slope dVout/dt(on) (V/ms) dVout/dt(off) (V/ms) 1000 500 450 900 Rl=13Ohm Vcc=13V Rl=13Ohm 800 400 700 350 600 300 500 250 400 200 300 150 200 100 100 50 0 0 -50 -25 0 25 50 75 100 125 150 175 ILIM Vs Tcase Ilim (A) 10 9 Vcc=13V 8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 Tc (C) -50 -25 0 25 50 75 Tc (C) Tc (C) 14/20 50 100 125 150 175 VNQ810P Maximum turn off current versus load inductance ILMAX (A) 10 A B C 1 0.01 0.1 1 L(mH) 10 100 A = Single Pulse at TJstart=150C B= Repetitive pulse at TJstart=100C C= Repetitive Pulse at TJstart=125C Conditions: VCC=13.5V Values are generated with RL=0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization t 15/20 VNQ810P SO-28 DOUBLE ISLAND THERMAL DATA SO-28 Double island PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: 0.5cm2, 3cm2, 6cm2). Thermal calculation according to the PCB heatsink area Chip 1 ON OFF ON ON Chip 2 OFF ON ON ON Tjchip1 RthA x Pdchip1 + Tamb RthC x Pdchip2 + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb (RthA x Pdchip1) + RthC x Pdchip2 + Tamb Tjchip2 Note RthC x Pdchip1 + Tamb RthA x Pdchip2 + Tamb RthB x (Pdchip1 + Pdchip2) + Tamb Pdchip1=Pdchip2 (RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1Pdchip2 RthA = Thermal resistance Junction to Ambient with one chip ON RthB = Thermal resistance Junction to Ambient with both chips ON and Pdchip1=Pdchip2 RthC = Mutual thermal resistance Rthj-amb Vs. PCB copper area in open box free air condition RTHj_am b (C/W) 70 60 50 RthA 40 RthB 30 20 RthC 10 0 16/20 1 2 3 4 5 PCB Cu heatsink area (cm ^2)/island 6 7 VNQ810P SO-28 Thermal Impedance Junction Ambient Single Pulse Zth(C/W) 100 0,5 cm ^2/island 3 cm ^2/island 6 cm ^2/island 10 One channel ON Two channels ON on same chip 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 time(s) Thermal fitting model of a four channels HSD in SO-28 Tj_1 C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd1 Tj_2 C13 R13 C14 R14 Pd2 R17 Tj_3 R18 C7 C8 C9 R7 R8 R9 C10 C11 C12 Pd3 Tj_4 C15 R15 R10 C16 R16 Pd4 T_amb R11 R12 10 100 1000 Pulse calculation formula Z TH = R TH + Z THtp ( 1 - ) where = t p T Thermal Parameter Area/island (cm2) R1=R7=R13=R15 (C/W) R2=R8=R14=R16 (C/W) R3=R9 (C/W) R4=R10 (C/W) R5=R11 (C/W) R6=R12 (C/W) C1=C7=C13=C15 (W.s/C) C2=C8=C14=C16 (W.s/C) C3=C9 (W.s/C) C4=C10 (W.s/C) C5=C11 (W.s/C) C6=C12 (W.s/C) R17=R18 (C/W) 0.5 0.35 1.8 4.5 11 15 30 0.0001 7.00E-04 6.00E-03 0.2 1.5 5 150 6 13 8 17/20 VNQ810P SO-28 MECHANICAL DATA DIM. mm. MIN. TYP A inch MAX. TYP. MAX. 0.104 a1 0.10 0.30 0.004 0.012 b 0.35 0.49 0.013 0.019 b1 0.23 0.32 0.009 0.012 C 0.50 0.020 c1 45 (typ.) D 17.7 E 10.00 e 18.1 0.697 10.65 0.393 1.27 e3 0.713 0.419 0.050 16.51 0.650 F 7.40 7.60 0.291 0.299 L 0.40 1.27 0.016 0.050 S 18/20 MIN. 2.65 8 (max.) VNQ810P SO-28 TUBE SHIPMENT (no suffix) Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) C B 28 700 532 3.5 13.8 0.6 All dimensions are in mm. A TAPE AND REEL SHIPMENT (suffix "13TR") REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 1000 1000 330 1.5 13 20.2 16.4 60 22.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) All dimensions are in mm. 16 4 12 1.5 1.5 7.5 6.5 2 End Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed 19/20 VNQ810P Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 2003 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 20/20