®
Oc tober 200 3 - Revision 1.2 (W orking doc um ent) 1/20
This is preli minar y informa tion on a new product foreseen to be developed. Detail s are s ubject to change without notice.
VNQ810P
QUAD CHANNEL HIGH SIDE DRIVER
■ CMOS COMPATIBLE INPUTS
■ OPEN DRAIN STATUS OUTPUTS
■ ON STATE OPEN LOAD DETECTION
■ OFF STATE OPEN LOAD DETECTION
■ SHORTED LOAD PROT ECTION
■ UNDERVO LT AGE AND OVERVOLTAGE
SHUTDOWN
■ PROTECTION AGAINST LOSS OF GROUND
■ VERY LOW STAND-BY CURRENT
■ REVE RSE BATTERY PROTECTION (**)
DESCRIPTION
The VNQ810P is a quad HSD formed by
assembling two VND 810 chips in the sam e SO-2 8
package. The VND810 is a monolithic device
made by using STMicroelectronics VIPower M0-3
Techno logy, intende d for d riving any kin d of load
with one side connected to ground.
Active VCC p in voltag e clamp protects th e de vice
against low energy spikes (see ISO7637 transient
compatibility table). Active current limitation
combined with thermal shutdown and automatic
restart protects the device against overload. The
device detects open load condition both in on and
off state . Output shorted to VCC is detected in the
of f state. Dev ice auto matic ally tur ns off in case of
ground pin disconnection.
TYPE RDS(on) IOUT VCC
VN Q 810P 160 m Ω (*) 3.5 A (*) 36 V
SO-28 (DOUBLE ISLAND)
ORDE R CODES
PACKAGE TUBE T&R
SO-28 VNQ810P VNQ810P13TR
(* ) Per each channel
ABSOLUTE MAXIMUM RATING
(**) See application schematic at page 9
Symbol Parameter Value Unit
VCC DC Su pply Voltag e 41 V
- VCC Re verse DC Supply Vo ltage - 0.3 V
- Ignd DC Reverse Ground Pin Current - 200 mA
IOUT DC Output Curren t Internally Limite d A
- IOUT Reverse DC Output Current - 6 A
IIN DC Input Curren t +/- 10 mA
ISTAT DC Status Current +/- 10 mA
VESD
E lectr ostati c Discharge (Hu m an Body M odel: R=1.5KΩ; C=100pF)
- IN PUT
- STATUS
- OUTPUT
- VCC
4000
4000
5000
5000
V
V
V
V
EMAX Maximum Switching Energy
(L=1.38mH; RL=0Ω; Vbat=13.5V; Tjstart=15 0ºC; I L=5A) 23 mJ
Ptot Powe r dissipation (per island) at Tlead=25°C 6.25 W
TjJunction Op erating T em perature Internally Limited °C
Tstg Storage Temperature - 55 to 150 °C
TARGET SPE CIFICATION
2/20
VNQ810P
BLOCK DIAGRAM
OVERTEMP. 1
VCC1,2
GND1,2
INPUT1 OUTPUT1
OVERVOLTAGE
LOGIC
DRIVER 1
STATUS1
Vcc
CLAMP
UNDERVOLTAGE
CLAMP 1
OPENLOAD ON 1
CURRENT LIMITER 1
OPENLOAD OFF 1
OUTPUT2
DRIVER 2
CLAMP 2
OPENLOAD ON 2
OPENLOAD OFF 2
OVERTEMP. 2
INPUT2
STATUS2
CURRENT LIMITER 2
OVERTEMP. 3
VCC3,4
GND3,4
INPUT3 OUTPUT3
OVERVOLTAGE
LOGIC
DRIVER 3
STATUS3
Vcc
CLAMP
UNDERVOLTAGE
CLAMP 3
OPENLOAD ON 3
CURRENT LIMITER 3
OPENLOAD OFF 3
OUTPUT4
DRIVER 4
CLAMP 4
OPENLOAD ON 4
OPENLOAD OFF 4
OVERTEMP. 4
INPUT4
STATUS4
CURRENT LIMITER 4
3/20
VNQ810P
CO NN EC TI ON DIAG R A M (TO P VI E W)
CURRENT AND V OLTAGE CONVE N TIO NS
VCC1,2
G ND 1,2
INPUT1
STATUS1
STATUS2
VCC1,2
VCC3,4
GND 3,4
INPUT3
STATUS3
VCC3,4 VCC3,4
OUTPUT4
OUTPUT4
OUTPUT4
OUTPUT3
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
VCC1,2
OUTPUT3
OUTPUT3
OUTPUT1
OUTPUT1
INPUT2
STATUS4
INPU T4
1
14 15
28
IS3,4
IGND1,2
OUTPUT3
VCC3,4
GND1,2
INPUT2
IOUT3
VCC1,2
VOUT4
OUTPUT2 IOUT2
VOUT3
INPUT1
IIN1
STATUS1
ISTAT1 OUTPUT1 IOUT1
OUTPUT4
IOUT4
VOUT2
VOUT1
IIN2
ISTAT2
ISTAT3
IIN4
ISTAT4
STATUS2
STATUS3
STATUS4
INPUT3
INPUT4
VSTAT4
VIN4
VSTAT3
VIN3
VSTAT2 IIN3
VIN2
VSTAT1
VIN1
I
S1,2
VCC1,2
GND3,4 IGND3,4
VCC3,4
4/20
VNQ810P
THERMAL DATA (Per island)
(*) Wh en m ounted on a standard si ngle-sided F R- 4 board with 0.5cm2 of Cu (at least 35µm thick) connected to all V CC pins .
Horizontal mounting and no artificial air flow.
ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C< Tj <150°C, unless otherwise specified)
POWER OUTPUTS (Per each channel)
SWITCHING (Per each Channel) (VCC=13V)
LOGIC INPUT (Per each channel)
(**) Per island
Symbol Parameter Value Unit
Rthj-lead Thermal R esistance Junc tion-lead per chip 20 °C/W
Rthj-amb Thermal resistance Junction-ambient (one chip ON) 60 (*) °C/W
Rthj-amb Thermal resistan ce Jun ction-a mbient (t w o chi ps O N) 46 (*) ° C /W
S ymbol Parameter Test Conditions Min Typ M ax Un it
VCC (**) Operating Supply Voltage 5.5 13 36 V
VUS D (**) Undervo lt age Shut- down 3 4 5.5 V
VOV ( **) Ove rvolt age Shu t-down 36 V
RON On State Resistance IOUT=1A; Tj=25°C
IOUT=1A; VCC>8V 160
320 mΩ
mΩ
IS (**) Supply Current
Off State; VCC=13V; VIN=VOUT=0V
Off State; VCC=13V; VIN=VOUT=0V;
Tj =2 5° C
On State; VCC=13V; VIN=5V; IOUT=0A
12
12
5
40
25
7
µA
µA
mA
IL(off1) Off St ate Ou tput Current VIN=VOUT=0V 0 50 µA
IL(off2) Off State Output Current VIN=0V; VOUT=3.5V -75 0 µA
IL(off3) Off State Output Current VIN=VOUT=0V; VCC=1 3V; T j =125 °C 5 µA
IL(off4) Off State Output Current VIN=VOUT=0V; VCC=1 3V; Tj =25°C 3 µA
Symbol Parameter Test Conditions Min Typ Max Unit
td(on) Turn -on Delay Time RL=13Ω from VIN risin g ed ge to
VOUT=1.3V 30 µs
td(off) T urn-o ff Dela y T ime RL=13Ω from VIN fall ing e dge to
VOUT=11.7V 30 µs
dVOUT/dt(on) Turn-on Volt age Slope RL=13Ω from V OUT=1.3 V to VOUT=10.4V See
rel ative
diagram V/µs
dVOUT/dt(off) Turn-off V olta g e Slope RL=13Ω from VOUT=11.7V to VOUT=1.3V See
relative
diagram V/µs
S ymbol Parameter Test Conditions Min Typ Max Unit
VIL Input Low Level 1.25 V
IIL Low Level Input Current VIN=1.25V 1 µA
VIH Input High Level 3.25 V
IIH High Level Input Current V IN=3.25V 10 µA
VI(hyst) Input Hyst eres is Volt age 0.5 V
VICL Inpu t Cl amp Vol tag e IIN=1mA
IIN=-1mA 66.8
-0.7 8V
V
1
5/20
VNQ810P
2
ELECTRICAL CHARACTERISTICS (continued)
VCC - OUTPUT DIODE
STATUS PIN (Per each channel)
PROTECTIONS (Per each channel)
OPENLOAD DETECTION (Per each channel)
S ymbol Parameter Test Conditions Min Typ Max Un it
VFForward on Voltage -IOUT=0.5A; Tj=150°C 0.6 V
Symbol Parameter Test Conditions Min Typ Max Unit
VSTAT Status Low Output Voltage ISTAT=1.6mA 0.5 V
ILSTAT Status Leakage Current Normal Operation; VSTAT=5V 10 µA
CSTAT Status Pin Input
Capacitance Normal Operation; VSTAT=5V 100 pF
VSCL Status Clamp Voltage ISTAT=1mA
ISTAT=-1mA 66.8
-0.7 8V
V
S ymbol Parameter Test Conditi ons Min Typ Max Unit
TTSD Shut-down Temperature 150 175 200 °C
TRReset Temp erature 135 °C
Thyst T h erma l Hy steres is 7 15 °C
tsdl Status Delay in Overload
Conditions Tj>TTSD 20 µs
Ilim Current limitation 5.5V<VCC<36V 3.5 5 7.5
7.5 A
A
VDEMAG Turn-off Output Clamp
Voltage IOUT=1A; L= 6m H VCC-41 VCC-48 VCC-55 V
S ymbol Parameter Test Conditions Min Typ Max Unit
IOL Openload ON State
Detectio n Threshold VIN=5V 20 40 80 mA
tDOL(on)
Openload ON State
Detectio n Delay IOUT=0A 200 µs
VOL
Openload OFF State
Voltage Detection
Threshold VIN=0V 1.5 2.5 3.5 V
tDOL(off) Openload Detection Delay
at Turn Off 1000 µs
VINn
VSTATn
tDOL(off)
OP EN LO AD STAT US TIMING (with exte rnal pul l-up)
VINn
VSTATn
OVER TEMP STATUS TIMI NG
tSDL
tSDL
IOUT < IOL
VOUT > V OL
tDOL(on)
Tj > TTSD
6/20
VNQ810P
t
t
VOUTn
VINn
80%
10%
dVOUT/dt(on)
td(off)
90%
dVOUT/dt(off)
td(on)
Switching time Waveforms
TRUT H TABL E
CONDITIONS INPUT OUTPUT STATUS
Normal Operation L
HL
HH
H
Current Limitation L
H
H
L
X
X
H
(Tj < TTSD) H
(Tj > TTSD) L
Overtemperature L
HL
LH
L
Undervoltage L
HL
LX
X
Overvoltage L
HL
LH
H
Output Voltage > VOL L
HH
HL
H
Output Current < IOL L
HL
HH
L
7/20
VNQ810P
ELECTRICAL TRANSIENT REQUIREMENTS ON VCC PIN
ISO T/R 7637/1
Test Pulse TEST LEVELS
I II III IV Delays and
Impedance
1 -25 V -50 V -75 V -100 V 2 ms 10 Ω
2 +25 V +50 V +75 V +100 V 0.2 ms 10 Ω
3a -25 V -50 V -100 V -150 V 0.1 µs 50 Ω
3b +25 V +50 V +75 V +100 V 0.1 µs 50 Ω
4 -4 V -5 V -6 V - 7 V 100 m s, 0.01 Ω
5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2 Ω
IS O T/ R 76 37/1
Test Pulse TEST LEVELS RESULTS
I II III IV
1CCCC
2CCCC
3aCCCC
3bCCCC
4CCCC
5CEEE
CLASS CONTENTS
CAll functio ns of the dev ice are performed as de sign ed after exposure to disturbance.
EOn e or mor e functions of the device is not performed as desi gne d after exposur e and ca nnot be
returned to proper ope ration wit hout replacing the device.
8/20
VNQ810P
1
OPEN LOAD without external pull- up
STATUSn
INPUTn
N ORMAL OPER ATION
UNDERVOLTAGE
VCC VUSD
VUSDhyst
INPUTn
OVERVOLTAGE
VCC
STATUSn
INPUTn
STATUSn
STATUSn
INPUTn
STATUSn
INPUTn
OPEN LOAD with external pull-up
undefined
OVERTEMPERATURE
INPUTn
STATUSn
TTSD
TR
Figure 1: Waveforms
Tj
O UTPUT VOLTAGEn
VCC<VOV
OU TPUT VOLTAGEn
OUTPUT VOLTAG E n
OUTPUT VOLTAGEn
OUTP U T VO LTAGEn
OUTPUT CURRENTn
VCC>VOV
VOL
VOUT>VOL
9/20
VNQ810P
GND PROTECTION NETWORK AGAINST
REVERSE BATTERY
Solution 1: Resistor in the ground line (R
GND
only). This
can be us ed with any type of load.
The following is an indication on how to dimension the
R
GND
resistor.
1) R
GND
≤ 600m V / 2 (I S(on)max).
2) R
GND
≥ (−VCC) / (-IGND)
where -IGND is th e DC re vers e g roun d pin cu rr ent an d can
be f o un d i n the absolute m ax i m um rating section of the of
th e de vice’s da ta sheet.
Power Dissipation in R
GND
(whe n VCC<0: during reverse
battery situations) is:
PD= ( -VCC)2/R
GND
This resistor can be shared amongst several different
HSD. Please note that the value of this resi stor should be
calc ulated with formula (1) where IS(on)max becomes the
sum of the maximum on-state currents of the different
devices.
Please note that if the microprocessor ground is not
common with the device ground then the R
GND
will
produ ce a shi f t ( IS(on)max * R
GND
) in the input thresholds
and the status output values. This shift will vary
depending on many devices are ON in the case of several
high side drivers sharing the same R
GND
.
If the calculated power dissipation leads to a large resistor
or se vera l devices ha ve to sha re the same r esisto r then
the ST sugge st to utilize Solu tio n 2.
V
CC1,2
OUTPUT2
+5V
R
prot
OUTPUT1
STATUS1
INPUT1
+5V
STATUS2
INPUT2
+5V
D
GND
R
GND
V
GND
GND1,2 GND3,4
OUTPUT3
OUTPUT4
µ
C
V
CC3,4
STATUS3
INPUT3
STATUS4
INPUT4
+5V
+5V
R
prot
R
prot
R
prot
R
prot
R
prot
R
prot
R
prot
D
ld
Note: Channe ls 3 & 4 have the same internal ci rcuit as channe l 1 & 2.
APPLICATION SCHEMATIC
10/20
VNQ810P
So lu t ion 2: A diode (D
GND
) in the ground line.
A resistor (R
GND
=1kΩ) should be inserted in parallel to
D
GND
if th e device will be dri ving an induct ive load.
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
the ground network will produce a shift (
j
600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
share s the sam e diode/resistor network.
Series resistor in INPUT and STATUS lines are also
req uired t o prevent th at, duri ng batt ery volt age tra nsient ,
the cu rren t exce eds the Absolute Maximum R ating.
Safest co nfigu ration f or unused IN PUT and STATUS pin
is to leave them un conne cted .
LOAD DUMP PRO TECTION
Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating. The
same applies if the device will be subject to transients on
th e VCC l ine tha t are grea ter tha n th e ones show n in the
ISO T/R 7637/1 table.
µC I/Os PROTECTION:
If a ground protection network is used and negative
transient are present on the VCC line, the control pins will
be pul led negat ive. S T su ggest s to ins er t a re sistor (Rprot)
in li ne to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between
the leakage current of µC and the current requir ed by the
HS D I /Os (Inp ut leve ls compa tibilit y) wit h the lat ch-up li mit
of µC I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-V
GND
) / IIHmax
Calculation example:
For VCCpeak= - 100V an d Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommended Rprot value is 10kΩ.
11/20
VNQ810P
OPEN LOAD DETECTION IN OFF STATE
Off state open load detection requires an external pull-up
resistor (RPU) connected between OUTPUT pin and a
positive supply voltage (VPU) like the +5V line used to
supply the microprocessor.
The external resistor has to be selected according to the
following requirements:
1) no fal se op en l oad ind i cati on wh en l oad i s conne ct ed :
in this c ase we have to avo id VOUT t o be higher than
VOlmin; this results in the following condition
VOUT=(VPU/(RL+RPU))RL<VOlmin.
2) no misdetection when load is disconnected: in this
case the VOUT has to be higher than VOLmax; this
results in the following condition RPU<(VPU–VOLmax)/
IL(off2).
Because Is(OFF) may sign ifi c a ntly incr ea se if Vout is p ul led
high (up to several mA), the pull-up resistor RPU should
be co nne ct ed t o a su pply tha t is swi tch ed OFF whe n th e
module is in standby.
The va l ues of V OLmin, VOLmax an d IL(off2) are available in
the Electric al Cha racteristics secti on.
VOL
V batt. VPU
RPU
RL
R
DRIVER
+
LOGIC
+
-
INPU T
STAT US
VCC
OUT
GROUND
IL(off2)
Open Load detection in off state
12/20
VNQ810P
High Level Input Current
Input Clamp Voltage Status Leakage Current
Off State Output Current
Status Clamp VoltageStatus Low Output Voltage
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Iih (uA)
Vin=3.25V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
6
6.2
6.4
6.6
6.8
7
7.2
7.4
7.6
7.8
8
Vicl (V)
Iin=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (° C)
0
0.01
0.02
0.03
0.04
0.05
Ilstat (uA)
Vstat=5V
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
Vstat (V)
Istat=1.6mA
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
6
6.2
6.4
6.6
6.8
7
7.2
7.4
7.6
7.8
8
Vscl ( V)
Istat=1mA
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
0.16
0.32
0.48
0.64
0.8
0.96
1.12
1.28
1.44
1.6
IL(off1) (uA)
Off state
Vcc=36V
Vin=Vout=0V
13/20
VNQ810P
Input Hysteresis VoltageInput Low Level
On State Resistance Vs Tcase On State Resistance Vs VCC
Input High LevelOpenload On State Detection Threshold
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vi h (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (° C)
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
Vi l (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
Vhyst (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
50
100
150
200
250
300
350
400
Ron (mOhm)
Iout=0.5A
Vcc=8V; 13V & 36V
5 10152025303540
Vcc (V)
50
75
100
125
150
175
200
225
250
275
300
Ron (mOhm)
Iout=0.5A
Tc= - 40°C
Tc= 25°C
Tc= 150°C
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
10
15
20
25
30
35
40
45
50
55
60
Iol (mA)
Vcc=13V
Vin=5V
14/20
VNQ810P
Overvoltage Shutdown
Turn-on Voltage Slope Turn-off Voltage Slope
ILIM Vs Tcase
Openload Off State Voltage Detection Threshold
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
30
32
34
36
38
40
42
44
46
48
50
Vov (V)
-50 -25 0 25 50 75 100 125 150 175
Tc (° C)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Vol (V)
Vin=0V
-50 -25 0 25 50 75 100 125 150 175
Tc (ºC)
0
100
200
300
400
500
600
700
800
900
1000
dVout/dt(on) (V/ms)
Vcc=13V
Rl=13Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (° C)
0
50
100
150
200
250
300
350
400
450
500
dVout/dt(off) (V/ms)
Rl=13Ohm
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
0
1
2
3
4
5
6
7
8
9
10
Ilim (A)
Vcc=13V
15/20
VNQ810P
Maximum turn off current versus load inductance
A = Single Pulse at TJstart=150ºC
B= Repetitive pulse at TJstart=100ºC
C= Repetitive Pulse at TJstart=125ºC
Conditions:
VCC=13.5V
Values are generated with RL=0Ω
In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed
the temperature specified above for curves B and C.
VIN, IL
t
Demagnetization Demagnetization Demagnetization
1
10
0.01 0.1 1 10 100
L(mH)
ILMAX (A)
A
B
C
16/20
VNQ810P
SO-28 Double island PC Board
Thermal calculation according to the PCB heatsink area
RthA = Thermal resistance Junction to Ambient with one chip ON
RthB = Thermal resistance Junction to Ambient with both chips O N and Pdchip1=Pdchip2
RthC = Mutua l thermal resistance
Rthj-amb Vs. PCB copper area in open box free air condition
Chip 1 Chip 2 Tjchip1 Tjchip2 Note
ON OFF RthA x Pdchip1 + Tamb RthC x Pdchip1 + Tamb
OFF ON RthC x Pdchip2 + Tamb RthA x Pdchip2 + Tamb
ON ON RthB x (Pdchip1 + Pdchip2) + T amb RthB x ( Pdchip1 + Pdchip2) + Tamb Pdchip1=Pdchip2
ON ON (RthA x P dchip1) + RthC x P dchip2 + Tamb (RthA x Pdchip2) + RthC x Pdchip1 + Tamb Pdchip1≠Pdchip2
SO-28 DOUBLE ISLAND THERMAL DATA
Layout condi ti on of R th an d Zth measurem ents (PCB FR4 area= 58 m m x 58mm, PCB thickness =2mm,
Cu thickness=35µm, Copper areas: 0.5cm2, 3cm2, 6cm2).
10
20
30
40
50
60
70
01234567
PCB Cu heatsink area (cm^2)/island
RTHj_amb
(°C/W)
RthA
RthB
RthC
17/20
VNQ810P
Thermal fitting model of a four channels HSD
in SO-28 Pulse calculation formula
Therma l Paramete r
Area/island (cm2)0.56
R 1=R7= R13=R15 (°C/W) 0.35
R 2=R8= R14=R16 (°C/W) 1.8
R 3=R9 (°C/W) 4.5
R4=R10 (°C/W) 11
R5=R11 (°C/W) 15
R6=R12 (°C/W) 30 13
C 1=C7=C13=C15 (W .s/°C ) 0.0001
C2=C8=C14=C16 (W.s/°C) 7.00E-04
C3=C9 (W.s/°C) 6.00E-03
C4=C1 0 (W.s /° C ) 0.2
C5=C1 1 (W.s /° C ) 1.5
C6=C1 2 (W.s /° C ) 5 8
R17=R18 (°C/W) 150
ZTHδRTH δZTHtp 1δ–()+⋅=
where δtpT⁄=
SO-28 Thermal Impedance Junction Ambient Single Pulse
0.01
0.1
1
10
100
0.0001 0.001 0.01 0.1 1 10 100 1000
time(s)
Zth(°C/W)
6 cm^2/island
3 cm^2/island
0,5 cm^2/island
One channel ON
Two channels
ON on same chip
Pd1
C1
R4
C3 C4
R3R1 R6R5R2
C5 C6C2
Pd2 R14
C13 C14
R13
Tj_1
Tj_2
T_amb
Pd3
C7
R10
C9 C10
R9R7 R12R11R8
C11 C12
C8
Pd4 R16
C15 C16
R15
Tj_3
Tj_4
R17 R18
18/20
VNQ810P
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 2.65 0.104
a1 0.10 0.30 0.004 0.012
b 0.35 0.49 0.013 0.019
b1 0.23 0.32 0.009 0.012
C 0.50 0.020
c1 45 (typ.)
D 17.7 18.1 0.697 0.713
E 10.00 10.65 0.393 0.419
e 1.27 0.050
e3 16.51 0.650
F 7.40 7.60 0.291 0.299
L 0.40 1.27 0.016 0.050
S8 (max.)
SO-28 MECHANICAL DATA
19/20
VNQ810P
SO-28 TUBE SHIPMENT (no suffix)
A ll dimensions are in m m .
Base Q.ty 28
Bulk Q.ty 700
Tube length (± 0.5) 532
A3.5
B13.8
C (± 0.1) 0.6
TAPE AND REEL SHIPMENT (suffix “13TR”)
Base Q. ty 1000
Bulk Q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F20.2
G (+ 2 / -0) 16.4
N (min) 60
T (max) 22.4
TAPE DIMENSIONS
Accord ing to Electr onic Indu stries Association
(EIA ) S tandard 4 8 1 rev. A , Feb 1986
All dimensions ar e in mm.
Tape width W 16
Tap e Hole Spacing P 0 (± 0.1) 4
Component Spacing P 12
Hole Di am eter D (± 0.1/-0) 1.5
Hole Diameter D 1 (min) 1.5
Hole Position F (± 0.05) 7.5
Compartment Depth K (max) 6.5
Hole Spac ing P1 (± 0.1) 2
Top
cover
tape
End
Start
No componentsNo components Components
500mm min
500mm min
Empty components pockets
saled with cover tape.
User di rection of feed
A
CB
REEL DIMENSIONS
20/20
VNQ810P
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gran ted by implication or other wise unde r any p atent or p atent rights of STMicroelectroni c s . Specific ations m entioned in this publication are
subj ec t to change without notice. This public ation supersedes and rep lac es all infor m ati on previous ly s upplied. ST M icroelectroni c s pr oducts
are not authorize d for use as critical components in life support d evices or systems without express written approval of STMicroelectronics.
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