Rev. 3.3
October 2003 1/104
ST6208C/ST6209C
ST6210C/ST6220C
8-BIT MCUs WITH A/D CONVERTER,
TWO TIMERS, OSCILLATOR SAFEGUARD & SAFE RE SET
■Memories
– 1K, 2K or 4K bytes Program memory (OTP,
EPROM, FASTROM or ROM) with read-out
protection
– 64 bytes RAM
■Cl ock, Reset and Su pp ly Manag em e n t
– Enhanced reset system
– Low Voltage Detector (LVD) for Safe Reset
– Clock sources: crystal/ceramic resonator or
RC n etw ork, ex tern al cloc k, bac kup o scilla tor
(LFAO)
– Oscillator Safeguard (OS G)
– 2 Power Saving Modes: Wai t and Stop
■Interrupt Management
– 4 interrupt vectors plus NMI and RESET
– 12 ext ernal interrupt l i nes (on 2 vectors)
■12 I/O P o rts
– 12 m ultifunctional bidi rectional I/O lines
– 8 alternate function lines
– 4 hi gh sink outputs (20mA )
■2 Time rs
– Configurab le watchdog timer
– 8-bit timer/counter with a 7-bit prescaler
■Analo g Peripheral
– 8-bit ADC with 4 or 8 input channels (e xcept
on ST6208 C)
■Instruction S et
– 8-bit data manipulation
– 40 basic i ns tructio ns
– 9 address ing modes
– Bit manipulation
■Development Tools
– Full hardware/software development package
Device Summary
(See Section 11.5 for Ordering Information)
PDIP20
SO20
CDIP20W
SSOP20
Features ST62T08C(OTP)/
ST6208C(ROM)
ST62P08C(FASTROM)
ST62T09C(OTP)/
ST6209C (ROM)
ST62P09C(FASTROM)
ST62T10C(OTP)/
ST6210C (ROM)
ST62P10C(FASTROM)
ST62T20C(OTP)
ST6220C(ROM)
ST62P20C(FASTROM)
ST62E20C(EPROM)
Program memory
- by tes 1K 2K 4K
RAM - bytes 64
Operating Supply 3.0V t o 6V
Analog Inputs - 48
Cl ock Frequency 8MHz Max
Operating
Temperature -40°C to +125°C
Packages PDIP20/SO20/SSOP20 CDIP20W
1
Table of Conten ts
104
2/104
2
1 INTR ODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 MEMORY MAPS , PROGRAMMING MO DES AND OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . 9
3.1 MEMORY AND REG ISTER MAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.1 Introduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.2 Program Sp ace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.3 Re adout Protec tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.4 Data Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.5 Stack Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1.6 Data ROM Wind ow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 PROGRAMMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.1 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2.2 EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.3 CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5 CL OCKS, SUPPLY AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1 CLOCK SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.1 Main O scillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.2 Oscillator Safegua rd (OSG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1. 3 Low Frequenc y Au xi liary Osc illator (LFAO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.4 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.2 LOW VOL TAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.3 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.1 Introduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.2 RESET Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.3 RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3.4 Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3.5 LVD Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.5 INTERRUPT RULES AND PRIORITY MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.6 INTERRUPTS AND LO W POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.7 NON MASKABLE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.8 PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.9 EXTERNAL INTERRUPT S (I/O PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.9.1 Notes on using External Interrup ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.10 INTERRUPT HANDLING P ROCEDURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.10.1Interrupt Respon se Tim e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1 1 REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6 PO WER SAVIN G MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table of Conten ts
3/104
3
6.2 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.3 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4 NOTES RELATED TO WAIT AND STOP M ODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4.1 Exit from Wait and Stop Mode s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.4.2 Reco mmended M CU Conf iguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7
7.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.1 Digital Inp ut Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.2 Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.3 Out put Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.4 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.2.5 Instructions NOT to be used to access Port Data registers (SET, RES, INC and DEC) 39
7.2.6 Re comm enda tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.3 LOW POW ER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.4 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.5 REGISTER DESCRIPTIO N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8 O N-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2
8.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.1 Introduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.2 Main F eatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.1.3 Funct ional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.4 Re comm enda tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8.1.5 Low Powe r Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
8.1.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.2 8-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.1 Introduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.2 Main F eatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2.3 Counter/Prescaler Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8.2.4 Funct ional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.2.5 Low Powe r Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.2.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.2.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.3 A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.3.1 Introduc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.3.2 Main F eatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.3.3 Funct ional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.3.4 Re comm enda tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
8.3.5 Low Powe r Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
8.3.7 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9 INSTRUCT ION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.1 ST6 ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.2 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table of Conten ts
104
4/104
9.3 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
10 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1.1M ini mu m and Max imum Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1.2Typical Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1.3Typical Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1.4L oading Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.1.5P in Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
10.2 ABSO LUTE MAXIMUM RATING S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.2.1Voltage Cha racteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.2.2Cu rrent Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.2.3Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
10.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.3.1G eneral Operating Condit ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
10.3.2O perat ing Conditions with Low Voltage Detector (LVD) . . . . . . . . . . . . . . . . . . . . . 65
10.4 SUPPLY CURRENT CHARACTE RISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.4.1RU N Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
10.4.2WAIT Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
10.4.3STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
10.4.4Supply and Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.4.5On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
10.5 CLOC K AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.5.1G eneral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.5.2External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
10.5.3Cryst al and Ceramic Resonator Oscillato rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
10.5.4RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
10.5.5Osc illator Safeguard (OSG) and Low Frequency Auxiliary Oscillator (LFAO) . . . . . 75
10.6 MEM ORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.6.1RAM and Hardware Regist ers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.6.2EPROM Program M emory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10.7 EMC CHARACTERISTIC S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.7.1F unc tional EMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.7.2Absolute Electrical Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
10.7.3ESD Pin Protection Strate gy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
10.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.8.1G eneral Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
10.8.2Output Driving Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.9.1As ynchronous RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.9.2NMI Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.10 TIMER PERIPHERAL CH ARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.10.1Watchdo g Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.10.28-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7
10.11 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
1
Table of Conten ts
5/104
11.2 THERM AL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.3 SOLDERING AN D GLUEABILITY INFO RM ATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.4 PACKAGE/SOCKET FOO TPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.6 TRANSFER OF CUSTOMER CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.6.1FASTROM version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.6.2ROM VERSIO N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
12 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
13 ST6 APPLICAT ION NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
14 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
15 TO GET MORE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
1
ST6208C/ST6209C/ST6210C/ST6220C
6/104
1 INTRO DU CTION
The ST 6208C, 09C, 10C and 20C devices are low
cost members o f the ST62xx 8-bit HCM OS family
of microcontrollers, which is targeted at low to me-
dium complexity applications. All ST62xx devices
are based on a building block approach: a com-
mon core is surrounded by a number of on-chip
peripherals.
The ST62E20C is the erasable EPROM version of
the ST62T08C, T09C, T10C and T20C devices,
which may be used during the development phase
for the ST62T08C, T09C, T10C and T20C target
devices, as well as the resp ective ST 6208C, 09C,
10C and 20C ROM devices.
OTP and EPROM devices are functionally identi-
cal. OTP d evices offer all the adva ntag es of user
programmability at low cost, which make them t he
ideal choice in a wide range of application s wh ere
frequent c ode changes , multipl e code v ersions or
last minute program mability are required.
The ROM based versions offer the same function-
ality, selecting the opt i ons defined in the program-
mable option bytes of the OTP/EPROM versions
in the ROM option list (See Section 11.6 on page
96).
The ST62P08C/P09C/P10C/P20C are the Factory
Advanced Service Technique ROM (FASTROM)
versions of ST62T08C, T09C, T10C and T20C
OTP devices.
They offer the same functionali ty as OTP devic es,
but they do not have to be programmed by the
customer (See Sec tion 11 on page 90).
These compact low-cost devices feature a Timer
comprising an 8-bit counter with a 7-bit program-
mable pres caler, an 8-bit A/D Converter with up to
8 analog inputs (d epending on dev ice) and a Dig-
ital Watchdog timer, making them well suited for a
wide range of automotive, appliance and industr ial
applications.
For easy reference, all parametric data are located
in Sect ion 11 on page 90.
Figu re 1. Blo ck D ia gra m
NMI INTERRUPTS
PROGRAM
PC
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
STACK LEVEL 4
STACK LEVEL 5
STACK LEVEL 6
POWER
SUPPLY OSCILLATOR RESET
DAT A ROM
USER
SELECTABLE
DATA RAM
64 Bytes
PORT A
PORT B
TIMER
8-BIT CORE
8- BI T *
A /D CONVERT E R PA0..PA3 (20mA Sink)
PB0..PB7 / Ain*
TIMER
VDDVSS OSCin OSCout RESET
WATCHDOG
:
MEMORY
TIMER
(1 K, 2K
* D ependin g on device. Pleas e refer t o I/ O P ort secti on.
or 4K Bytes)
VPP
4
ST6208C/ST6209C/ST6210C/ST6220C
7/104
2 PI N DESCRIPTI O N
Figure 2. 20-Pin Package Pi nout
Table 1. Device Pin Description
VDD
TIMER
Ain*/PB5
Ain*/PB6
Ain*/PB7
RESET
VPP
NMI
OSCout
OSCin
VSS
PA0/20mA Sink
PB4/Ain*
PB3/Ain*
PB2/Ain*
PB1/Ain*
PB0/Ain*
PA3/20mA Sink
PA2/20mA Sink
PA1/20mA Sink
itX associated interrupt vector
1
2
3
4
5
6
7
8
9
10 11
12
20
19
18
17
16
15
14
13
* De pending on device. Ple ase refer to I/O Port se ct i on.
it2
it1
it2
Pin n° Pin Name
Type
Main Function
(after Reset) Alternate Function
1 VDD S Main power supply
2 TIMER I/O Timer input or output
3 OSCin I External clock input or resonator oscillator inverter input
4 OSCout O Resonator oscillator inverter output or resistor input for RC oscillator
5 NMI I Non maskable interrupt (falling edge sensitive)
6V
PP Must be held at Vss for normal operation, if a 12.5V level is applied to the pin
during the reset phase, the device enters EPROM programming mode.
7 RESET I/O Top priority non maskable interrupt (active low)
8 PB7/Ain* I/O Pin B7 (IPU) Analog input
9 PB6/Ain* I/O Pin B6 (IPU) Analog input
10 PB5/Ain* I/O Pin B5 (IPU) Analog input
11 PB4/Ain* I/O Pin B4 (IPU) Analog input
12 PB3/Ain* I/O Pin B3 (IPU) Analog input
13 PB2/Ain* I/O Pin B2 (IPU) Analog input
14 PB1/Ain* I/O Pin B1 (IPU) Analog input
15 PB0/Ain* I/O Pin B0 (IPU) Analog input
16 PA3/ 20mA Sink I/O Pin A3 (IPU)
17 PA2/ 20mA Sink I/O Pin A2 (IPU)
18 PA1/ 20mA Sink I/O Pin A1 (IPU)
5
ST6208C/ST6209C/ST6210C/ST6220C
8/104
Legend / Abbreviations for Ta ble 1:
* Depending on device. Please refer to Section 7 "I/ O PORTS" on page 37.
I = input, O = output, S = supply, IPU = input w ith pull-up
The input with pull-up configuration (reset state) is val id as long as the user software does not c ha nge it.
Refer to Section 7 "I/O PORTS" on page 37 for more details on the software configuration of the I/O ports.
19 PA0/ 20mA Sink I/O Pin A0 (IPU)
20 VSS S Ground
Pin n° Pin Name
Type
Main Function
(after Reset) Alternate Function
6
ST6208C/ST6209C/ST6210C/ST6220C
9/104
3 MEMORY MAPS, PROGRAMMING MODES AND OPTION BYTES
3.1 MEMORY AND REGISTER MAPS
3.1 .1 Int roducti on
The MCU operates in three separate memory
spaces: Program space, Data space, and Stack
space. Operation in these three m emory spaces is
described in the following paragraph s.
Briefly, Program space contains user program
code in OTP and user vectors; Data space con-
tains user data in RAM and in OTP, and Stack
space accommodates six levels of stack for sub-
routine and interrupt service routine nesting.
Figu re 3. Me m ory A ddres sin g Diagram
PROGRAM SPACE
PROGRAM
INTERRUPT &
RESET VECTORS ACCUMULATOR
RAM
X REGISTER
Y REGISTER
V REGISTER
W REGISTER
000h
03Fh
040h
07Fh
080h
081h
082h
083h
084h
0C0h
0FFh
DATA SPAC E
000h
0FF0h
0FFFh
MEMORY WINDOW
DATA ROM
RESERVED
HARDWARE
CONTROL
REGISTERS
0BFh
(see Table 2)
(see Figure 4
on page 10)
1
ST6208C/ST6209C/ST6210C/ST6220C
10/104
MEMORY MA P (Cont’d)
Figu re 4. P rog ra m Mem ory Ma p
(*) Reserved areas should be filled with 0FFh
0000h
0AFFh
0B00h
0B9Fh
NOT IMPLEMENTED
RESERVED*
USER
PROGRAM MEMORY
1024 BYTES
0BA0h
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED*
RESERVED*
INTERRUPT VECTORS
NMI VECTOR
USER RESET VECTOR
0000h
07Fh
USER
PROGRAM MEMORY
3872 BYTES
080h
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED*
RESERVED*
INTERRUPT VECTORS
NMI VECTOR
USER RESET VECTOR
RESERVED*
0000h
07FFh
0800h
087Fh
NOT IMPLEMENTED
RESERVED*
USER
PROGRAM MEMORY
1824 BYTE S
0880h
0F9Fh
0FA0h
0FEFh
0FF0h
0FF7h
0FF8h
0FFBh
0FFCh
0FFDh
0FFEh
0FFFh
RESERVED*
RESERVED*
INTERRUPT VECTORS
NMI VECTOR
USER RESET VECTOR
ST6208C, 09C ST621 0C ST6220C
1
ST6208C/ST6209C/ST6210C/ST6220C
11/104
MEMORY MA P (Cont’d)
3.1.2 Program Sp ace
Program Space comprises the instructions to be
executed, the data required for immediate ad-
dressing mode instructions, the reserved factory
test area and the us er vectors. Program Space is
addressed v ia the 12-bit Program Counter register
(PC register). Thus, the MCU is capable of ad-
dressing 4K bytes of memory directly.
3.1.3 Readout Protection
The Program Memory in OTP, EPROM or ROM
devices can be protected against external readout
of memory by set ting the Readout Prot ection bit in
the option bytes (S ection 3.3 on page 16).
In the EPROM parts, Readout Protection option
can be desactivated only by U.V. erasure that also
results in the whole EPROM context being erased.
Note: Once the Readout Protection is activated, it
is no longer possible, even for STMicroelec tronics,
to gain access to the OTP or ROM contents. Re-
turned parts can therefore not be accepted if the
Readout Protect ion bit is set.
3.1.4 Data Space
Data Space accommodates all t he data necessary
for processi ng the user program. This space com-
prises the RAM resource, the proc essor core an d
peripheral registers, as well as read-only data
such as constants and look-up tables in OTP/
EPROM.
3.1.4.1 Data ROM
All read-only data is physically stored in program
memory, which also accommodates the Program
Space. The program memory consequently con-
tains the program cod e to be executed, as well as
the constants and look-up tables required by the
application.
The Data Space locations in which the different
constants and look-up tabl es are addressed by the
processor core may be thought of as a 64-byte
window through which it is possibl e to access t he
read-only data stored i n OTP/EPROM.
3.1.4.2 Data RAM
The data space includes the user RAM area, the
accumulator (A), the indirect registers (X), (Y), the
short direct registers (V), (W), the I/O port regis-
ters, the peripheral data and c ontrol registers, the
interrupt option register and the Data ROM Win-
dow register (DRWR regi st er).
3.1.5 Stack Space
Stack space consists of six 12-bit registers which
are used to stack subroutine and interrupt return
addresses, as well as the current program counter
contents.
1
ST6208C/ST6209C/ST6210C/ST6220C
12/104
MEMORY MA P (Cont’d)
Table 2. Hardware Regi ster M ap
Legend:
x = undefined, R/W = Read/Write, Ro = Read-only Bit(s) in the register, Wo = Write-only Bit(s)
in the regis ter.
Notes:
1. The conte nts o f the I/O p ort D R registers are read able only in output conf iguration. I n i nput conf igura-
tion, the values of t he I/O pins are returned instead of t he DR regi ster contents.
2. The bits associated with unavailable pins must always be kept at their reset value.
3. Do not use single-bit instructions (SET, RES...) on Port Dat a Registers if any pin of the port is configured
in input mode (refer to Section 7 "I/O PORTS" on page 37 for mor e details)
4. Depending on device. See device sum mary on page 1.
Address Block Register
Label Register Name Reset
Status Remarks
080h
to 083h CPU X,Y,V,W X,Y index registers
V,W short direct registers xxh R/W
0C0h
0C1h I/O Ports DRA 1) 2) 3)
DRB 1) 2) 3) Port A Data Register
Port B Data Register 00h
00h R/W
R/W
0C2h
0C3h Reserved (2 Bytes)
0C4h
0C5h I/O Ports DDRA 2)
DDRB 2) Port A Direction Register
Port B Direction Register 00h
00h R/W
R/W
0C6h
0C7h Reserved (2 Bytes)
0C8h CPU IOR Interrupt Option Register xxh Write-only
0C9h ROM DRWR Data ROM Window register xxh Write-only
0CAh
0CBh Reserved (2 Bytes)
0CCh
0CDh I/O Ports ORA 2)
ORB 2) Port A Option Register
Port B Option Register 00h
00h R/W
R/W
0CEh
0CFh Reserved (2 bytes)
0D0h
0D1h ADC 4) ADR
ADCR A/D Converter Data Register
A/D Converter Control Register xxh
40h Read-only
Ro/Wo
0D2h
0D3h
0D4h Timer1 PSCR
TCR
TSCR
Timer 1 Prescaler Register
Timer 1 Downcounter Register
Timer 1 Status Control Register
7Fh
0FFh
00h
R/W
R/W
R/W
0D5h
to 0D7h Reserved (3 Bytes)
0D8h Watchdog
Timer WDGR Watchdog Register 0FEh R/W
0D9h
to 0FEh Reserved (38 Bytes)
0FFh CPU A Accumulator xxh R/W
1
ST6208C/ST6209C/ST6210C/ST6220C
13/104
MEMORY MA P (Cont’d)
3.1.6 Data ROM Window
The Data read-only memory window is located
from address 0040h to address 007Fh in Data
space. It allows direct reading of 64 consecutive
bytes located anywhere in program memory, be-
tween address 0000h and 0FF Fh.
There are 64 blocks of 64 bytes in a 4K device:
– Block 0 is related to the address range 0000h t o
003Fh.
– Block 1 is related to the address range 0040h t o
007Fh.
and so on...
All the program m emory can therefore be used to
store either instructions or read-only data. The
Data ROM window can be moved in steps of 64
bytes along the program memory by writing the
appropriate code in the Data ROM Window Regis-
ter (DRWR).
Figu re 5. Dat a R OM W in do w
3.1.6.1 Data ROM Window Register (DRWR)
The DRWR ca n be a ddres sed li ke any RA M loca-
tion in the Data Space.
This regist er is used t o sele ct t he 64-byt e blo ck of
program mem ory to be read in the Data ROM win-
dow (from address 40h to address 7Fh in Data
space). The DRWR register is not cleared on re-
set, therefore it must be written to before access-
ing the Data read-only memory window area for
the first time.
Address: 0C9h — Write Onl y
Reset Value = xxh (undefined)
Bits 7:6 = Reserved, must be cleared.
Bit 5:0 = DRWR[5:0]
Data read-only memory Win-
dow Register Bits.
These are the Data read-only
memory Window bits that correspond to the upper
bits of the data read-only memo ry space.
Caution:
This register is undefined on reset, it is
write-only, therefore do not read it nor access it us-
ing Read-Modify-Write instructions (SET, RES,
INC and DEC).
0000h
0FFFh
000h
040h
07Fh
0FFh
DATA ROM
WINDOW
DATA SPACE
64-BYTE
ROM
PROGRAM
SPACE
70
- - DRWR5 DRWR4 DRWR3 DRWR2 DRWR1 DRWR0
1
ST6208C/ST6209C/ST6210C/ST6220C
14/104
MEMORY MA P (Cont’d)
3.1.6.2 Data ROM Window memory addressi ng
In cases where some data (look-up tables for ex-
ample) are stored in program memory, reading
these dat a requi res the use of the Data ROM win-
dow mechanism. To do this:
1. The DRWR register has to be loaded with the
64-byte block number where the data are located
(in program memo ry). This nu mber also gives the
start address of the block.
2. Then, the of fset addres s of the by te in th e Data
ROM Window (corresponding to the offset in the
64-byte block in program memory) has to be load-
ed in a regi ster (A, X,...).
When the above two steps are completed, the
data can be read.
To understand how to determine the DRWR and
the content of th e register, p lease refer t o the ex -
ample shown in F igure 6. I n any c ase t he calcul a-
tion is automatically hand led by the ST6 deve lop-
ment tools.
Please refer to th e user manual of the c orrespod-
ing tool .
3.1.6.3 Recomm endatio ns
Care is required when ha ndling the DRWR regis-
ter as it is write only. For this reason, the DRWR
contents should not be changed while executing
an interrupt serv ice routine, as the service rout ine
cannot save and then restore the register’s previ-
ous contents. If it is imp ossible to avoi d writing to
the DRWR during the interrupt service routine, an
image of the register mu st be saved in a RA M lo-
cation, and each time the program writes to the
DRWR, it must also write to the image register.
The image register must be written first so that, if
an interrupt occurs between the two instructions,
the DRWR is not affected.
Figure 6. Data ROM Window Memo ry Addressi ng
DATA
PROGRAM SPACE
DATA SPACE
0000h
0400h
0421h
07FFh
64 bytes
OFFSET
000h
040h
061h
07Fh
OFFSET
21h
0FFh
DRWR
DATA address in Program memory : 421h
DRWR content : 421h / 3Fh (64) = 10H data is located in 64-bytes window number 10h
64-byte window start address : 10h x 3Fh = 400h
Register (A, X,...)content : Offset = (421h - 400h) + 40h ( Data ROM Window start address in data space) = 61h
10h
DATA
1
ST6208C/ST6209C/ST6210C/ST6220C
15/104
3.2 PROGRAM MING MODES
3.2.1 Program Me mory
EPROM/OTP programming mode is set by a
+12.5V v oltage a pplied to the T EST/VPP pin. The
programming flow of the ST62T08C,T09C,T10C,
T20C and E20C is des cribed in the User Manual of
the EPROM Programming Board.
Table 3. ST6208C/09C P rogram Memo ry M ap
Table 4. ST6210C Prog ram Memo ry Map
Table 5. ST6220C Prog ram Memo ry Map
Note: OTP/EPROM devices can be programmed
with the development tools available from
STMicroele ctronics (please refer to Section 12 on
page 99).
3.2.2 EPROM Erasi ng
The EPROM devices can be erased by exposure
to Ultra Violet light. The characteristics of the MCU
are such that erasure begins when th e memory is
exposed to light with a wave lengths sho rter than
approximately 4000Å . It should be noted that sun-
light and some types of fluorescent lamps have
wavelength s in the range 3000-4000Å.
It is thus recommended that the window of the
MCU packages be c overed by an opaque label to
prevent unint entional er as ure problems when test-
ing the application in such an environment.
The recommended er asur e procedure is exposure
to short wave u ltraviolet li ght which ha ve a wave-
length 2537Å. The integrated dose (i.e. U.V. inten-
sity x exposure time) for erasure should be a mini-
mum of 30W-sec/cm2. The erasure time with this
dosage is approximately 30 to 40 minutes using an
ultraviolet lamp with 12000µW/cm2 power rating.
The EPROM device should be placed within
2.5cm (1inch) of the lamp tubes during erasure.
Device Addr ess Descri ption
0000h-0B9Fh
0BA0h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vecto rs
Reserved
NMI Interrupt Vector
Reset Vector
Device Addr ess Descri ption
0000h-087Fh
0880h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vecto rs
Reserved
NMI Interrupt Vector
Reset Vector
Device Addr ess Descri ption
0000h-007Fh
0080h-0F9Fh
0FA0h-0FEFh
0FF0h-0FF7h
0FF8h-0FFBh
0FFCh-0FFDh
0FFEh-0FFFh
Reserved
User ROM
Reserved
Interrupt Vecto rs
Reserved
NMI Interrupt Vector
Reset Vector
1
ST6208C/ST6209C/ST6210C/ST6220C
16/104
3.3 OPTION BYTE S
Each device is available for product ion in user pro-
grammable versions (OTP) as well as in factory
coded versions (ROM). O TP devices are shippe d
to customers with a default content (00h), while
ROM factory coded parts contain the code sup-
plied by the customer. This implies that OTP de-
vices have to be configured by the customer using
the Option Bytes while the ROM devices are facto-
ry-configured.
The t wo option b ytes allow t he hardware configu-
ration of t he microcontrol le r to be selected.
The option bytes have no addre ss in th e mem ory
map and can be accessed only in programming
mode (for example using a standard ST6 program-
ming tool) .
In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see Section
11.6.2 "ROM VERSION" on page 98). It is there-
fore impossible to read the option bytes.
The option bytes can be only programmed once. It
is not possible to change the selected options after
they have been programm ed.
In order to reach the power consum pt ion value in-
dicated in Section 10.4, the option byte must be
programmed to its default value. Otherwise, an
over-consumption will occur.
MSB OP TI ON BY TE
Bits 15:10 = Reserved, must be always cleared.
Bi t 9 = EXTCNTL
Ext e r n al STO P MO DE control.
0: EXTCNTL mode not available. STOP mode is
not av ailable with the watchdog active.
1: EXTCNTL mode available. STOP mode is avail-
able with the watc hdog active by setting NMI pin
to one.
Bi t 8 = LVD
Low Vol tage Detector
on/off
.
This option bit enable o r disable the Low Voltage
De tect o r (LVD ) feature.
0: Low Voltage Detector disabled
1: Low Voltage Detector enabled
LSB OPTION BYTE
Bit 7 = PROTECT
Readout Protection.
This opti on bit enables or disables external access
to the internal program memory.
0: Program memory not read-ou t protected
1: Program memory read-out protected
Bit 6 = OSC
Osc illator se lec t io n
.
This opti on bit selects the main oscillator type.
0: Quart z crystal, ceramic resonator or external
clock
1: RC network
Bit 5 = Reserved, must be always cleared.
Bit 4 = Reserved, must be always set.
Bit 3 = NMI P ULL
NMI Pull-Up
on/off.
This option bit enables or disables the internal pull-
up on the NMI pin.
0: Pull-up disabled
1: Pull-up enabled
Bit 2 = TIM PULL
TIMER Pull-Up
on/off.
This option bit enables or disables the internal pull-
up on the TIMER pin.
0: Pull-up disabled
1: Pull-up enabled
Bit 1 = WDACT
Hardware or software watchdog.
This opti on bit selects the watchdog type.
0: Softwar e (watchdog to be enabled by software)
1: Hardware (watchdog always enabled)
Bit 0 = OSGEN
Oscillator Safeguard
on/off.
This option bit enables or disables the oscillator
Safeguard (OS G) feature.
0: Osc illator Safeguar d disabled
1: Osc illator Safeguar d enabled
MSB OPTION BYTE
15 8 LSB OPTION BYTE
70
Reserved EXT
CTL LVD PRO-
TECT OSC Res. Res. NMI
PULL TIM
PULL WD
ACT OSG
EN
Default
Value XXXXXXXXXXXXX X XX
1
ST6208C/ST6209C/ST6210C/ST6220C
17/104
4 CE NTRAL PROCE SSI NG U NIT
4.1 INTRODUCTION
The CPU Core of ST6 devices is independent of the
I/O or Memory configuration. As such, it may be
thought of as an independent central processor
communi cating with on-chip I/O, Memory and Pe-
ripherals via internal address, data, and control
buses.
4.2 MAIN FE ATURES
■40 basic instructions
■9 main addressing modes
■Two 8-bit index registers
■Two 8-bit short direct registers
■Low pow er modes
■Maskabl e hardware interrupts
■6-level hardware stack
4.3 CPU RE GISTERS
The ST6 Family CPU core features six registers and
three pairs of flags available to the programmer.
These are described in the following paragrap hs.
Accumulator (A). The accumulator is an 8-bit
general purpose register used in all arithmetic c al-
culations, logical operations, and data manipula-
tions. The accumulator can be addressed i n Data
Space as a RAM location at address FFh. Thus
the ST 6 can manip ulate the accumulator just like
any other register in Data Space.
Index Registers (X, Y). These two registers are
used in Indirect addressing mode as pointers to
memory locations in Data Space. They can also
be accessed in Direct, Short Direct, or Bit Direct
addressing modes. They are mapped in Data
Space at add resses 80 h (X) and 81h (Y) an d can
be accessed like any other memory location.
Short Direct Re gisters (V, W). These two regis-
ters are used in Short Direct addressing mode.
This mea ns t hat the data stored in V or W can be
accessed with a one-byte inst ruction (four CPU cy-
cles). V and W c an also be ac cessed using Di rect
and Bit Direct addressing modes. They are
mapped in Data Space at addresses 8 2h (V) and
83h (W) and can be accessed like any other mem-
ory location.
Note: The X and Y registers can also be u sed as
Short Direct registers in the same way as V and W.
Program Counter (PC). The program counter is a
12-bit register which contains the address of the
next instruction to be executed by the core. This
ROM location may be an opcode, an operand, or
the address of an operand.
Figure 7. CPU Registers
ACCUMULATOR
X INDEX REGISTER
Y INDEX REGISTER
PROGRAM COUNTER
RESET VALUE = RESET VECTOR @ 0FFEh-0FFFh
70
70
70
0
11
RESET VALU E = xxh
RESET VALUE = xxh
RESET VALU E = xxh
x = Undefined value
V SHORT INDIRECT
70
RESET VALU E = xxh
W SHORT INDIRECT
70
RESET VALU E = xxh
NORMAL FLAGS CN ZN
CI ZI
CNMI ZNMI
INTERRUPT FLAGS
NMI FLAGS
SIX LEVEL
STACK
REGISTER
REGISTER
1
ST6208C/ST6209C/ST6210C/ST6220C
18/104
CPU REGISTERS (Cont’d)
The 12-bit length allows the direct addressing of
4096 bytes in Program Space.
However, if the program space contains more than
4096 bytes, the additional memory in program
space can be addressed by using the Program
ROM Page register.
The PC value is incremented after reading the ad-
dress of the current instruction. To execute relative
jumps, the PC and the offset are shifted through
the ALU, where th ey are added; the result is then
shifted back into t he PC. The program counter c an
be changed in the following ways:
– JP (Jump) instruction PC = Jump address
– CALL instruction PC = Call address
– Relative Branch InstructionPC = PC +/- offset
– Interrupt PC = Interru pt vector
– Reset PC = Reset vector
– RET & RETI in structions PC = Pop (stack)
– Norm al instruction PC = PC + 1
Flags (C, Z). The ST6 CPU includes three pairs of
flags (Carry and Zero), eac h pair being ass oc iated
with one of the three norm al modes of o peration:
Normal mode, Interrupt mode and Non Maskable
Interrupt mode. Each pair consists of a CARRY
flag and a ZERO flag. One pair (CN, ZN) is used
during Normal operation, another pair is used dur-
ing Interrupt mode (CI, ZI), and a third pair is us ed
in the Non Maskable Interrupt mode (CNMI, ZN-
MI).
The ST6 CPU uses the pair of flags associated
with the current mode: as soon as an interrupt (or
a Non Maskable Interrupt) is generated, the ST6
CPU uses the Interrupt f lags (or the NM I flag s) in-
stead of the Normal flags. When the RET I instruc-
tion is executed, the previ ously used set of flags is
restored. It shou ld be n oted tha t ea ch flag s et ca n
only be addressed in its own context (Non Maska-
ble Interrupt, Normal Interrupt or Main routine).
The flags are no t cleared during cont ext switchin g
and thus retain their status.
C : Carry flag.
This bit is set when a carry or a borrow occurs dur-
ing arithmetic operations; otherwise it is cleared.
The Carry flag is also set to the value of the bit
tested in a bit t est instruction; it al so participates in
the rotate left instruction.
0: No carry has oc cured
1: A carry has occured
Z : Zero flag
This flag is s et if the result of the last arithmetic or
logical operation was equal to zero; otherwise it is
cleared.
0: The result of the last operation is different from
zero
1: The result of the last operat ion is zero
Switching between the three sets of flags is per-
formed autom atically when an NMI, an inte rrupt or
a RETI instruction occurs. As NMI mode is auto-
matically selected after the reset of the MCU, the
ST6 core uses the NMI flags first.
Stack. The ST6 CPU i ncludes a true LIFO (Last In
First Out) hardware stack which eliminates the
need for a stack pointer. The stack consists of six
separate 12-bit RAM locations that do not belong
to the data space RAM area. When a subroutine
call (or interrupt request) occurs, the contents of
each level are shifted into the next level down,
while the content of the PC i s shifted into the f irst
level (the original contents of the sixth stack level
are lost). When a subroutine or interrupt return oc-
curs (RET or RET I instructions), the first level reg-
ister is shifted back into the PC and the value of
each level is popped back into the previous level.
Figure 8. Stack manip ulation
Since the accumulator, in common with all other
data space registers, is not stored in this stack,
management of these registers should be per-
formed within the subroutine.
Caution: The stack will remain in its “deepest” po-
sition if more than 6 nested calls or interrupts are
executed, and consequently the last return ad-
dress will be lost.
It will also remain in its highest posi tion if the st ack
is empty and a RET or RETI is executed. In this
cas e the ne x t ins tru c t ion w ill be ex e cu t e d.
LEVEL 1
LEVEL 2
LEVEL 3
LEVEL 4
LEVEL 5
LEVEL 6
ON
INTERRUPT,
OR
SUBROUTINE
CALL
ON RETURN
FROM
INTERRUPT,
OR
SUBROUTINE
PROGRAM
COUNTER
1
ST6208C/ST6209C/ST6210C/ST6220C
19/104
5 CLOCKS, SUPPLY AND RESET
5.1 CLOCK SYSTEM
The main oscillator of the MCU can be driven by
any of these clock sources :
– external clock signal
– external AT-cut parallel-reson ant crystal
– external ceramic resonator
– external RC network (RNET).
In addition, an on-chip Low Frequency Auxiliary
Oscillator (LFAO) is available as a back-up clock
system or to reduce power consumption.
An optional Oscillator Safeguard (OSG) filters
spikes from the oscillator lines, and switches to the
LFAO backup os cill ator in the ev ent of m ain os cil-
lator failure. It also automatically limits the internal
clock frequency (fINT) as a funct ion of VDD, in order
to guarantee correct operation. These functions
are illustrated in Figure 10, and Figure 11.
Table 6 illustrates various possibl e oscilla tor con-
figurations using an external crystal or ceramic
resonator, an external clock input, an external re-
sist or (RNET), or the lowest cost solution using only
the LFAO.
For mo re details o n configuring the c lock optio ns,
refer to the Option Bytes section of this document.
The internal MCU c lock freque ncy (fINT) is divided
by 1 2 to drive th e Timer, the Watchdog timer and
the A/D converter, by 13 to drive the CPU core and
the SPI and by 1 or 3 to drive the ARTIMER, as
shown in Figure 9.
Wi th an 8 M H z os c illa t or , the fast es t C P U cycle is
therefore 1.625µs.
A CPU cycle is the smallest unit of time needed to
execute any operation (for in stance, to increment
the Program Counter). An instru ction may req uire
two, four, or five CPU cycles for execution.
Figure 9. Clock Circuit Block Diagram
MAIN
OSCILLATOR
OSG
LFAO
CORE
: 13
: 12
8-BIT TIMER
WATCHDOG
fINT
OSCOFF BIT
ADC
0
1
filtering
OSC ILLATO R SAFEGUA RD (OSG)
OSG ENABL E OPTION BIT (Se e OPTION BYTE SECTION)
(ADCR REGIST ER)
fOSC
* De pending on device. See de vice summ ary on page 1.
*
*
Oscillator
Divider
SPI
: 1
: 3
8-BIT ARTIMER
8-BIT ARTIMER
1
ST6208C/ST6209C/ST6210C/ST6220C
20/104
CLOCK SYSTEM (Cont’ d)
5.1.1 Mai n Oscil lator
The oscillator config uration is specified by select-
ing the appropriate opt ion in the option byt es (refer
to the Option Bytes section of this document).
When the CRYSTAL/RESONATOR option is se-
lected, it must be us ed wi th a quartz crystal, a ce-
ramic resonator or an external signal provided on
the OSCin pin. When the RC NETWORK option is
selected, the system clock is generated by an ex-
ternal resistor (the c apa citor is im ple men ted inter-
nally).
The main oscillator can be turned off (when the
OSG ENABLED option is selected) by setting the
OSCOFF bit of the ADC Control Register (not
available on some devices). This wil l autom at ically
start the Low Frequency Auxiliary Oscillator
(LFAO).
The main oscillator can be turned off by resetting
the OSCOFF bit of the A/D Converter Control Reg-
ister or by resetting the MCU. When the main os-
cillator starts there is a delay made up of the oscil-
lator start-up delay period pl us the duration of the
software instruction at a clock frequency fLFAO.
Caution: It should be noted th at when the RC net-
work option is selected, the accuracy of the fre-
quency is about 20% s o it may not be suitable for
some applicati ons (For more details, please refer
to the E le ctrical Characteristics Section).
Table 6. Oscillator Configurations
Notes:
1. To sele ct the option s shown in c olumn 1 of th e above
table, refer to the Option Byte section.
2.This schematic are given for guidance only and are sub-
ject to the schematics given by the crystal or ceramic res-
onator manufacturer.
3. For more deta ils, plea se refer to the Electric al Char ac-
teristics Section.
Hardware Configuration
Crystal/Resonator Option1)
Crystal/Resonator Option1)
RC Network Option1)
OSG Enabled Option1)
OSCin OSCout
EXTERNAL
ST6
CLOCK
NC
External Clock
OSCin OSCout
LOAD
CAPACITORS 3)
ST6
CL2
CL1
Crystal/Resonator Clock 2)
OSCin OSCout
ST6
RNET
NC
RC Network
OSCin OSCout
ST6
LFAO
NC
1
ST6208C/ST6209C/ST6210C/ST6220C
21/104
CLOCK SYSTEM (Cont’ d)
5.1.2 Oscillator Safegua rd (OSG)
The Oscillator Safeguard (OSG) feature is a
means of dramatically improving the operational
integrity of the MCU. It is available when the OSG
ENABLED option is selected in the option byte (re-
fer to the Option Bytes se ction of this document).
The OSG acts as a filter whose cross-over fre-
quency is device dependent and provides three
basic functions:
– Filt er ing s pik es o n the os c illator lines which
would result in driving the CPU at excessive fre-
quencies
– Management of the Low Frequency Auxiliary
Oscillator (LFAO), (useable as low cost internal
clock source, backup clock in case of mai n o scil-
lator failure or for low power consumption)
– Automatically limiting the fINT clock frequency as
a function of supply voltage, to ensure correct
operation even if the power supply drops.
5.1.2.1 Spike Filtering
Spikes on the oscillator lines result in an ef fectively
increased internal clock frequency. In the absence
of an OSG circuit, this may lead to an over fre-
quency for a given power supply voltage. The
OSG filters out such spikes (as illustrated in Figure
10). In all cases, when t he OSG is active, the max-
imum internal clock frequency, fINT, is limited to
fOSG, whi ch is supply voltage dependent.
5.1.2.2 Management of Supply Voltage
Variations
Over-frequency, at a given po wer supply level, is
seen by the OS G as spikes; it t herefore filters out
some cycles in order that the internal clock fre-
quency of the device is kept within the range the
particular device can stand (depending on VDD),
and below fOSG: the maximum authorised frequen-
cy with OSG enab led.
5.1.2.3 LFAO M anag emen t
When the OSG is enabled, the Low Frequency
Auxiliary Oscillator can be used (see Section
5.1.3).
Note: The OSG should be used wherever pos sible
as it provides maximum security for the applica-
tion. It should be noted however, that it can in-
crease power consumption and reduce the maxi-
mum operating frequency to fOSG (see Electrical
Characteristics section).
Caution: Care has to be taken when using the
OSG, as the internal frequency is defined between
a minimum and a maximum value and may vary
depending on both VDD and t emperature. For pre-
cise tim ing meas urem ents , it is not recom men ded
to use the OSG.
Figure 10. OSG Filtering Function
Figu re 11. LF A O Oscillato r Function
fOSC
fOSG
fINT
fOSC<fOSG
fOSC>fOSG
MAIN OSCILLATOR
STOPS MAIN OSCILLATOR
RESTARTS
INTERNAL CLOCK DR IVEN BY LFAO
fOSC
fINT
fLFAO
1
ST6208C/ST6209C/ST6210C/ST6220C
22/104
CLOCK SYSTEM (Cont’ d)
5.1.3 Low Frequency Auxiliary Oscillator
(LFAO)
The Low Frequency Auxili ary Oscillator has three
main purposes. Firstly, it can be used to reduce
power consum ption in non timin g critical routines.
Secondly, i t offers a full y i nteg ra ted syste m clock,
without any external c omponents. Lastly, it acts as
a backup oscillator in case of main oscillator fail-
ure.
This oscillator is available when the OSG ENA-
BLED option is selected in the option byte (refer to
the Option By tes section of this document ). In this
case, it automat ically starts one of i ts periods after
the first missin g edg e of the main oscillator, what -
ever the reason f or the failure (m ain oscillator de-
fective, n o c l ock circuitr y prov i ded, m ain oscillator
switched off. .. ). See Fi gure 11.
User code, normal interrupts, WA IT and S TO P in-
structions, are processed as normal, at the re-
duced fLFAO frequenc y. The A/D converter accura-
cy is decreased, since the int ernal frequenc y is be-
low 1 .2 MH z .
At power on, until the main oscillator starts, the re-
set delay counter is driven by the LFAO. If the
main oscillator starts before the 2048 cycle delay
has elapsed, it takes over.
The Low Frequency Auxiliary Oscillator is auto-
matically switched off as s oon as the main oscilla-
tor star ts.
5.1.4 Regi ster Description
ADC CONTROL REGISTER (ADCR)
Address: 0D1h — Re ad/Write
Reset value: 0100 0000 (40h)
Bit 7:3, 1:0 = ADCR[7:3], ADCR[1:0]
ADC Control
Register
.
These bits are used to control the A/D conv erter (if
available on the device) otherwise they are not
used.
Bit 2 = OSCOFF
Ma in Os c ill a tor Of f.
0: Mai n oscillator enabled
1: Mai n oscillator disabled
Note: The OSG must be enabled using the OS-
GEN o ption in the Opt ion Byte, otherw ise the OS -
COFF setting has no effect.
70
ADCR
7ADCR
6ADCR
5ADCR
4ADCR
3OSC
OFF ADCR
1ADCR
0
1
ST6208C/ST6209C/ST6210C/ST6220C
23/104
5.2 LOW VOLTAGE DETECTOR (LVD)
The on-chip Low Voltage Detector is enabled by
setting a bit in the option bytes (refer to the Option
Bytes section of this document).
The LVD al lows the dev ice to be used without any
ext e r n al RESET cir cu i try. In this case , th e RESET
pin should be left unconnected .
If the LVD is not used, an external circuit is manda-
tory to ensure correct Power On R eset operation,
see figure in th e Reset section. For more details,
please refer to the application note AN669.
The LVD generates a static Reset when the supply
voltage is below a reference value. This means
that it secures the power-up as well as the power-
down keeping the ST6 in reset.
The VIT- ref erence value for a vol tage drop is l ower
than the VIT+ reference value for power-on in order
to avoid a parasitic reset when the MCU starts run-
ning and sinks current on t he supply (hy steresis).
The LVD Reset circuitry generates a reset when
VDD is below:
– VIT+ when VDD is rising
– VIT- when VDD is falling
The LVD function is illustrated i n F igure 12 .
If the LV D is enabled, t he MCU can be in only one
of two states:
– Over the input thr eshol d voltage, i t is running un-
der full software control
– Below the input threshold voltage, it is i n static
safe rese t
In these conditions, secure operation is guaran-
teed without the need for external reset hardware.
During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devi ces.
Figure 12. Low Voltage Detector Reset
VDD
VIT+
RESET
VIT-
Vhyst
1
ST6208C/ST6209C/ST6210C/ST6220C
24/104
5.3 RESET
5.3 .1 Int roducti on
The MCU can be reset in three ways:
■A low pulse input on the RESET pin
■Internal Watchdog res et
■Internal Low Voltage Detector (LVD) reset
5.3.2 RESET Sequence
The basic RESET sequence consists of 3 main
phases:
■Internal (watchdog or LVD) or external Reset
event
■A delay of 2048 clock (fINT) cycles
■RESET vector fe tch
The reset delay allows the oscillator to stabilise
and ensures that recovery has taken place from
th e Reset sta te.
The RESET vector fetch phas e durat ion is 2 clock
cycles.
When a reset occurs:
– The stack is cleared
– The PC is loaded with the address of the Reset
vector. I t is located in program ROM starting at
address 0FF Eh.
A jump t o the beginning of the user program m ust
be coded at this address.
– The interrupt flag is automatically set, so t hat the
CPU is i n Non Maskable Interrupt mode. This
prevents the initialization routine from being i n-
terrupted. The initialization routine should there-
fore be terminated by a RETI instruction, in order
to go back to normal mode.
Fig ur e 13. RESET Sequence
VDD
RESET PIN
WATCHDOG
VIT+
VIT-
WATCHDOG UNDERFLOW
RESET
2048 CLOCK CYCLE (fINT) DEL AY
LVD
RESET
INTERNAL RUN
RESET
RUN RUN RUN
RESET RESET
RESET
1
ST6208C/ST6209C/ST6210C/ST6220C
25/104
RESET (Cont’d)
5.3.3 RESET Pin
The RESET pin m ay be connected t o a dev ice o n
the application board in order to reset the MCU if
required. The RESET pin may be pulled low in
RUN, WAIT or STOP mode. This input can be
used to reset the internal state of the MCU and en-
sure it starts-up correctly. The pin, which is con-
nected to an internal pull-up, i s active low and fea-
tures a Schmitt trigger input. A delay (2048 clock
cycles) added to the external signal ensures that
even short pulses on the RESET pin are accepted
as valid, provided VDD has completed its rising
phase and that the oscillator is running correctly
(normal RUN or WAIT modes). The MCU is kept in
the Reset s tate as l ong as the RESET p in is hel d
low.
If the RESET pin is grounded whil e the MCU is in
RUN or WAIT modes, processing of the user pro-
gram is stopped (RUN mode only), the I/O ports
are configured as input s with p ull-up resistors and
the main oscillator is restarted. When the level on
the RESET pin then goes high, the initialization se-
quence is executed at the end of the internal delay
period.
If the RESET pin is grounded while the M CU is in
STOP mode, the oscillator starts up and all the I/O
ports are configured as inputs with pull-up resis-
tors. When the RESET pin level then goes high,
the initialization sequence is executed at the end
of the internal delay period.
A simple external RESET circuitry is shown in Fig-
ure 15. For m ore det ails, plea se refer to the appli-
cation note AN669 .
Figure 14. Reset Block Diagram
f
INT
COUNTER
RESET
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
RESD1)
1) Resistive ESD protection.
VDD
RPU
2048
clock cycles
1
ST6208C/ST6209C/ST6210C/ST6220C
26/104
RESET (Cont’d)
5.3.4 Watchdog Reset
The MCU provides a Watchdog timer function in
order to be able to recover from software hang-
ups. If the Watchdo g register is not refreshed be-
fore an end-of-count condition is reached, a
Watchdog reset is generated.
After a Watchdog reset, the MCU restarts in the
same way as if a Reset was generated by the RE-
SET pin.
Note: When a watchdog reset occurs, the RESET
pin is t ied low for very s hort time period, to flag t he
reset phase. Th is t ime is not long enoug h t o reset
external circuits.
For more details refer to the Watchdog Timer
chapter.
5.3.5 LVD Reset
Two diff erent RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
■Power-On RESET
■Voltage Drop RESE T
During an LVD reset, the RESET pin is pul led lo w
when VDD<VIT+ (rising edge) or VDD<VIT- (falling
edge).
For more details, refer to the LVD chapter.
Caution: Do not externally connect directly the
RESET pin to VDD, t his may cause damage to the
component in case of internal RESET (Watchdog
or LVD).
Figure 15. Simple External Reset Circuitry
Figure 16. Reset Processing
ST62xx
RESET
VDD
VDD
R
C
Typical: R = 10K
C = 10nF R > 4.7 K
INT LATCH CLEARED
NMI MASK SET
(IF PRESENT)
SELECT
NMI MO DE F LAG S
IS RESET STILL
PRESENT?
YES
PUT FFEh
ON ADDRESS BUS
FROM RESET LOCATIONS
FFEh/FFFh
NO
FETCH INSTR UCTI ON
LOAD PC
INTERNAL
RESET
RESET
2048
CLO CK CYCLE
DELAY
1
ST6208C/ST6209C/ST6210C/ST6220C
27/104
5.4 INTERRUPTS
The ST6 core may be interrupted by four maska-
ble interrupt sources, in addi tio n to a Non M aska-
ble Interrupt (NMI) source. The interrupt process-
ing flowchart is shown in Figure 18.
Maskable interrupts must be enabled by setting
the GEN bit in the IOR register. However, even if
they are disabled (GEN bit = 0), interrupt events
are latched and may be proc ess ed as soon as the
GEN bit is set.
Each source i s associated wi th a specific Interrupt
Vector, located in P rogram s pace (see T able 8). In
the vector l ocation, the user must writ e a Jump in-
struction to the associated interrupt service rou-
tine.
When an interrupt source generates an interrupt
request, the PC register is loaded with the address
of the interrupt vector, which then causes a Jum p
to the relevant interrupt service routine, th us serv-
icing the int e rr up t.
Interrupt are triggered by events either on external
pins, or from the on-chip peripherals. Several
events can be ORed on the same interrupt vector.
On-chip peripherals have flag registers to deter-
mine which event triggered the interrupt.
Figu re 17. I nterrupts Bl oc k D i agram
NMI
ESB BIT
VDD
LATCH
CLEARED BY H/W
AT START OF VECTOR #0 ROU TINE
VECTOR #0
LES BIT
1
0
LATCH
CLEARED BY H/W
AT START OF
VECTOR #1
VECTOR #2
VECTOR #3
VECTOR #4
LATCH
CLEARED
BY H/W AT START OF
VECTOR #2 ROUTINE
I/O PORT REGISTER
CONFIGURATION
“INPUT W ITH INTE R RUP T”
I/O PORT REGISTER
CONFIGURATION
“INPUT W ITH INTE R RUP T”
EXIT FROM
STOP/WAIT
VEC TOR #1 ROUTINE
TIMER
A/D CONV ERT ER *
TMZ BIT
ETI BIT
EAI BIT
EOC BIT
GEN BIT
PB0...PB7
PA0...PA3
(TSCR REGISTER)
(A DC R RE G I ST ER)
(IOR REGISTER)
(IOR REGISTER)
(IOR REGISTER)
* Depending on device. See device summ ary on page 1.
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5.5 INTERRUPT RULES AND PRIORITY
MANAGEMENT
■A Reset can interrupt the NMI and peripheral
inte rrupt routines
■The Non Maskable Interrupt request has the
highest priority and can i nte rrupt any peripheral
interrupt routine at any time but cannot interrupt
another NMI interrupt.
■No perip heral interru pt can interrupt another. If
more than one interrupt request is pending,
these are processed by the processor core
according t o their priority level: vector #1 has the
highest priority while vector #4 the lowest. The
priority of each interrupt source is fixed by
hardware (see Interrupt Mapping table).
5.6 INTERRUPTS AND LOW POWER MODES
All interrupts cause the processor to exit from
WAIT mode. O nly the external and some specific
interrupts from the on-chip peripherals cause the
processor to exit from STOP mode (refer to the
“Exit from S TOP“ col umn in the Interrupt Mappin g
Table).
5.7 NON MASKABLE INTERRUPT
This interrupt is triggered when a falling edge oc-
curs on the NMI pin regardless of the state of the
GEN bit in the IOR register. An interrupt request
on NMI vector #0 is latched by a fl ip flop which is
automatically reset by the core at the beginning of
the NMI service routine.
5.8 PERIPHERAL INTERRUPTS
Different peripheral interrupt flags in the peripheral
control registers are able to cause an interrupt
when they are active if both:
– The GEN bit of the IOR register is set
– The corresponding enable bit is set in the periph-
eral control register.
Peripheral interrupts are linked to vectors #3 and
#4. Interrupt requests a re flagged by a bit in their
corresponding control register. This means that a
request cann ot be lost, because the flag b it must
be cleared by user software.
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5.9 EXTERNAL INTERRUPTS (I /O Ports)
External interrupt vectors can be loaded into the
PC register if the co rre spo nding external interrupt
occurred and if the GEN bit is set . These int errupts
allow the processor to exit from STOP mod e.
The external interrupt polarity is selected through
the IOR regi ster.
External interrupts are linked to vectors #1 and #
2.
Interrupt requests on v ector #1 can be conf igured
either as edge or level-sens itive using the LES bit
in the IOR Register.
Interrupt request s from v ector #2 ar e always edge
sensitive. The edge polarity can be configured us-
ing th e ESB bit in the IOR Register.
In edge-sensitive mode, a l atch is set when a edge
occurs on the interrupt source line an d is cleared
when the associated interrupt routine is started.
So, an interrupt request can be stored until com-
pletion of th e currently executing interrupt routine,
before being processed. If several interrupt re-
quests oc curs b efo re comp letion of the curren t in-
terrupt routine, only the first request is st ored.
Storing of i nterr upt r equests is not possible i n level
sensitive m ode. T o be t ak en i nto ac count , th e lo w
level must be present on the i nterrupt pin when t he
MCU samples the line after i nstruction exec ution.
5.9.1 Notes on using External Interrupts
ESB bi t Sp uri ous Inter rupt on Ve ct or #2
If a pin associated with interrupt vector #2 is con-
figured as interrupt with pull-up, whenever vector
#2 is configured to be rising edge sensitive (by set-
ting the ESB bit in t he IOR register), a n interrup t is
latched although a rising edge may not have oc-
cured on the associat ed pin.
This is due to the vector #2 circuitry.The worka-
round is to discard t his first interrupt request in the
routine (using a flag for example).
Masking of One Interrupt by Another on Vect or
#2.
When two or more port pins (associ ated with inter-
rupt vector #2) are configured together as input
with interrupt (falling edge sensitive), as long as
one pin is stuck at '0', the other pin can never gen-
erate an i nterrup t even if an act ive edge occurs at
this pin. The same thing occurs when one pin is
stuck at '1' and interrupt vector #2 is configured as
rising edge sensitive.
To avoid th is the first pin must input a signal that
goes back up to '1' right after the falling edge. Oth-
erwise, in the interrupt rou tine for t he first pin, de-
activate the “input with interrupt” mode using the
port control registers (DDR, OR, DR). An active
edge on another pin can then be latched.
I/O port Configuration Spurious Interrupt on
Vector #2
If a pin associated with interrupt vector #2 is in ‘in-
put with pull-up’ state, a ‘0’ l evel is p r esent on the
pi n and the ESB bit = 0, when the I/O pin is config-
ured as interrupt with pull-up by writing to the
DDRx, ORx a nd DRx register bits, an inte rrupt is
latched although a falling edge may not have oc-
curred on the associated pin.
In the opposite case, if the pin is in interrupt with
pull-up state , a 0 level is present on the pin and
the ES B bit =1, when the I/O po rt is con figured as
input with pull-up by wri ting t o the DDRx, ORx and
DRx bits, an interrupt is latched although a ri sing
edge may not have occurred on the associated
pin.
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5.10 INTERRUPT HANDLING PROCEDURE
The interrupt procedure is very similar to a call pro-
cedure, in fact the us er can cons ider the interrupt
as an asynchronous call procedure. As this is an
asynchronous event, the user cannot know the
context and the tim e at which i t occurred. A s a re-
sult, the user should save all Data space registers
which may be used within the interrupt routines.
The following list summarize s the interrupt proce-
dure:
When an interrupt request occurs, the following
actions are performed by the MCU automatically:
– The core switches from the normal fl ags to the
interrupt flags (or the NMI flags).
– The PC content s are s tored in the top level of the
stack.
– The normal interrupt lines are i nhi bited (NMI still
active).
– The internal latch (if any) is cleared.
– The associated interrupt vector is loaded in the PC.
When an interrupt request occurs, the following
actions must be performed by t he user sof tware:
– User select ed registers have to be saved within
the interrupt service routine (normally on a soft-
ware stack).
– The source of the interrupt must be determined
by polling the interrupt flags (if more than one
source is associated with the sam e vector).
– The RETI (RETurn fr om Interrupt) instruction
must end the interrupt service routine.
After the RETI instruction is executed, the MCU re-
turns to the main routine.
Caution: When a maskable interrupt occ urs while
the ST6 core is in NORMA L mode and du ri ng the
execution of an “ldi I OR, 00h” instruction (disabling
all maskable interrupts): if the interrupt request oc-
curs during the first 3 cycles of the “ldi” instruction
(which is a 4-cycl e instruction) the core wil l switch
to interrupt mode BUT the flags CN and ZN will
NOT switch to the interrupt pair CI and ZI.
5.10.1 Interrupt Resp ons e Time
This is defined as the time between the moment
when the Program Counter is loaded with the in-
terrupt vector and when the program has jump to
the interrupt subroutine and is ready to execute
the code. It depe nds on wh en t he in terrupt occurs
while the core is processing an instruction.
Figure 18. Interrupt Processing Fl ow Chart
Table 7. Interrupt Response Time
One CPU cycl e i s 1 3 e xtern a l cl o ck cycles thu s 11
CPU cycles = 11 x (13 /8M) = 17.875 µs with an 8
MHz external quartz.
Minimum 6 CPU cycles
Maximum 11 CPU cycles
INSTRUCTION
FETCH
INSTRUCTION
EXECUTE
INSTRUCTION
WAS
THE INST RUCT ION
A R ETI?
ENABLE
MASKABLE INTERRUPT S
SELECT
NORMAL FLA GS
“POP”
THE STAC K ED PC
IS THE R E AN
AN INTERRUPT REQUE ST
AND INTERRUP T MASK ?
SELECT
INTERRUPT FLAGS
PUSH TH E
PC IN T O TH E STAC K
LOAD PC FROM
INTERRUPT VEC TOR
DISABLE
MASKABL E INTE RRUPT
NO
NO
YES IS THE CORE
ALREADY IN
NORMAL MODE?
YES
NO
YES
CLEAR
INTERNAL LATCH *)
*) I f a latch is present on the interrupt source line
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5.11 RE G ISTER DESCRIPTION
INTERRUPT OPTION REGISTER (IOR)
Address: 0C8h — Write Only
Reset status: 00 h
Caution: This register is write-only and can not be
accessed by single-bit operations (SET, RES,
DEC,...).
Bit 7 =Reserved, must be cleared.
Bi t 6 = LES
Level/Edge S elect ion bit
.
0: Fal ling edge sensitive mode is s elected for in ter-
rupt vector #1
1: Low level sensitive mode is selected for int e r-
rupt vector #1
Bit 5 = ESB
Edge Select ion bit
.
0: Falling edge mode on interrupt vector #2
1: Rising edge mode on interrupt vector #2
Bit 4 = GEN
Global Enable Interrupt
.
0: Disable all maskable interrupts
1: Ena ble all maskab le int e r ru pts
Note: Whe n the GEN bit is cleared, the NMI inter-
rupt is active but cannot be used to exit from STOP
or WAIT modes.
Bits 3:0 = Rese rved, must be cleared.
Tabl e 8. Interrupt Mapping
* Depending on device. See device summary on page 1.
70
- LES ESB GEN - - - -
Vector
number Source
Block Description Register
Label Flag Exit
from
STOP
Vector
Address Priority
Order
RESET Reset N/A N/A yes FFEh-FFFh
Vector #0 NMI Non Maskable Interrupt N/A N/A yes FFCh-FFDh
NOT USED FFAh-FFBh
FF8h-FF9h
Vector #1 Port A Ext. Interrupt Port A N/A N/A yes FF6h-FF7h
Vector #2 Port B Ext. Interrupt Port B N/A N/A yes FF4h-FF5h
Vector #3 TIMER Timer underflow TSCR TMZ yes FF2h-FF3h
Vector #4 ADC* End Of Conversion ADCR EOC no FF0h-FF1h Priority
Lowest
Highest
Priority
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6 POW ER SAVING MODES
6.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, two main pow-
er saving m odes are implemented in the ST6 (see
Figure 19).
In addition, the Low Frequency Auxiliary Os cillator
(LFAO) can be us ed inste ad of the main oscillator
to reduce power consumption in RUN and WAIT
modes.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency.
From Run mode, the different power saving
modes may be sel ec ted by calling t he specif ic ST6
software instruction or for the LFAO by setting th e
relevant register bit. For more information on the
LFAO, please refer to the Clock chapter.
Figure 19. Power S aving Mod e Tran sitions
POWER CONSUMPTION
WAIT
LFAO
RUN
STOP
High
Low
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6.2 WAIT MODE
The MCU goes into WAIT mode as soon as the
WAIT instruction is execu ted. This has the follow-
ing effects:
– Program execution i s stopped, the microcontrol-
ler software can be considered as being in a “fro-
zen” state.
– RAM contents and peripheral registers are pre-
served as long as the power supply voltage is
higher than the RAM retention voltage.
– The oscillator is kept running to provide a clock
to the peripherals; they are st ill active.
WAIT mode can be used when the user wants to
reduce the MCU power consumption during idle
perio ds , while not los in g tra c k of ti me or the ab ilit y
to monitor external events. WAIT mode places the
MCU in a low power consumption mode by stop-
ping the CPU. The acti ve oscillator (main os cillator
or LFAO) is kept running in order to provide a clock
signal to the peripherals.
If the power consumption has to be further re-
duced, the Low Frequency Auxiliary Oscillator
(LFAO) can be used in place of the main oscillator,
if its operating frequen cy is lower. If requ ired, the
LFAO must be s witche d on before ent ering WAIT
mode.
Exit from Wait mode
The MCU remains in WAIT mode unti l one of th e
following event s occurs:
– RESET (Wa tchdog, LVD or R ESET pin)
– A peripheral interrupt (timer, ADC,...) ,
– An exte rnal interrupt (I/O port, NMI)
The Program Counter then branches to the start-
ing address of the i nterrupt or RESET servic e rou-
tine. R e fer to Figure 20.
See also Section 6.4.1 .
Figure 20. WAIT Mode Flowchart
WAIT INSTRUCTION
RESET
INTERRUPT Y
N
N
Y
Clock to CPU
OSCILLATOR
Clock to PE RIPH E RALS On
Yes
No
FETCH RESET VECTOR
OR SERVICE INTERRUPT
2048
Clock to CPU
OSCILLATOR
Clock to PERIPHERALS
Restart
Yes
Yes
DELAY
CLOCK CYCLE
OSCILLATOR
Clock to PERIPHERALS
Clock to CPU Yes
Yes
On
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6.3 STOP MODE
STOP mode is the lowest power consumption
m ode of th e M CU (s ee F igure 22).
The MCU goes into STOP mode as soon as the
STOP instruction is execute d. This has the follow-
ing effects:
– Program execution i s stopped, the microcontrol-
ler can be considered as being “frozen”.
– The conte nts of RAM and the peripheral regis-
ters are kept saf ely as long as the power supply
voltage is higher than the RAM retention vol tage.
– The oscillator is stopped, so peripherals cannot
work except the those that can be driven by an
external c lock.
Ex it from STOP Mode
The MCU remains in STO P mode until one of the
following event s occurs:
– RESET (Wa tchdog, LVD or R ESET pin)
– A peripheral interrupt (ass uming this peripheral
can be driven by an external clock)
– An exte rnal interrupt (I/O port, NMI)
In all cases a delay of 2048 clock cycles (fINT) is
generated to make sure the oscillator has started
properly.
The Program Counter then points to the starting
address of the interru pt or RESET service routine
(see Figure 21).
STOP Mode and Watchdog
When the Watchdog is active (hardware or soft-
ware activation), the STOP instruction is disabled
and a WAIT instruction will be executed in its place
unless t he EXCTNL option bit is set to 1 in the op-
tion bytes and a a high lev el is present on the NMI
pin. In this case, the ST OP instruction wi ll be exe-
cuted and the Watchdog will be frozen.
Figure 21. STOP Mode Tim ing Over vie w
STOPRUN RUN
2048
RESET
OR
INTERRUPT
STOP
INSTRUCTION
FETCH
VECTOR
CYCLECLOCK
DELAY
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ST OP MO D E (Cont’ d)
Fi gure 22 . STOP Mo de Flow char t
Notes:
1. EXCTNL is an option bit . See option byte section for more detail s.
2. Peripheral clocked with an external clock source can still be active.
3. Only some specific interrupts can exit the MCU from STOP mode (such as ext ernal interrupt). Refer to
the Interrupt Mapping table for more details.
STOP INSTRUCTION
RESET
INTERRUPT 3) Y
N
N
Y
FETCH RESET VECTOR
OR SERVICE INTERRUPT
WATCHDOG
ENABLE
DISABLE
EXCTNL 1
1
LEVEL
ON
NMI PIN
0
0
RESET
INTERRUPT
N
N
Y
Y
VALUE 1)
Clock to CPU
OSCILLATOR
Clock to PE RIPH E RALS2) Off
No
No
2048 DELAY
Clock to CPU
OSCILLATOR
Clock to PERIPHERALS
Restart
Yes
Yes
Clock to CPU
OSCILLATOR
Clock to PERIPHERALS On
Yes
Yes
Clock to CPU
OSCILLATOR
Clock to PERIPHERALS On
Yes
No
CLOCK CYCLE
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6.4 NOTES RELATED TO WAIT AND ST OP MODES
6.4 .1 E xit f rom Wa i t a nd S top Modes
6.4.1.1 NMI Interrupt
It should be noted that when the GEN bit in the
IOR register is low (interrupts disabled), the NMI
interrupt is active but cannot cause a wake up from
STOP/WAIT modes.
6.4.1.2 Restart Sequence
When the MCU exi t s from WAIT or STOP mode, it
should be noted that the restart sequence de-
pends on the or iginal st ate of the M CU (norm al, in-
terrupt or non-maskable interrupt mode) prior to
entering WAIT or STOP mode, as well as on the
interrupt typ e.
Normal Mode. If the MCU was in the main routine
when the WAIT or STOP instruction was execut-
ed, exit from Stop or Wait mode will occur as soon
as an interrupt occurs; the related interrupt routine
is executed and, on completion, the instruction
which follows the STOP or WAIT instruction is
then executed, providing no other interrupts are
pending.
Non Maskable Interrupt Mode. If the STOP or
WAIT instruction has been executed during execu-
tion of the non-maskable interrupt routine, the
MCU exits from Stop or W ait mo de as s oon a s a n
interrupt occurs: the instruction which follows the
STOP or WAIT instruction is executed, and the
MCU remains in non-maskable interrupt mode,
even if another interrupt has been generated.
Norma l Inte rrup t Mod e. If the MCU was in inter-
rupt mode before the STOP or WAIT instruction
was executed, it exits from STOP or WAIT mod e
as soon as an interrupt occ urs. Nevert heless, two
cases must be consid er ed:
– If the interrupt is a norm al one, t he interrupt rou-
tine in which the WAIT or ST OP mode was en-
te re d w ill b e c o mplete d , starting w ith th e
execution of the instruction which follows the
STOP or the WAIT instruction, and the MCU is
still in interrupt mode. At the end of this ro utine
pending interrupts will be serviced according to
their priority.
– In the eve nt of a non-maskable interrupt, the
non-maskabl e interrupt service routine is proc-
essed first, then the routine in which the WAIT or
STOP mode was entered will be completed by
executing the inst ruction following the STOP or
WAIT instruction. The MCU remains in normal in-
terrupt mode.
6.4.2 Recommended MCU Configuration
For lowest power consumption during RUN or
WAIT modes, the user software must configure
the MCU as follows:
– Configure unused I/Os as output push-pull low
mode
– Place all peripherals in t heir power down modes
before entering STOP mo de
– Selec t the Low Frequency Auxiliary Os cillator
(provided this runs at a lower frequenc y than the
ma in o s c illator).
The WAIT and STOP instructions are not execut-
ed if an enabl ed interrupt request is pending.
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7 I/O PORTS
7.1 INTRODUCTION
Each I/O po r t contains up to 8 p ins. Each pin can
be programmed independently as digital input
(with or without pull-up and interrupt generation),
digital output (open drain, push-pull) or analog in-
put (when available).
The I/O pins can b e used in eithe r s tandard o r a l-
ternate function mode.
Standard I/ O mode is used for:
– Transfer of data through digit al inputs and out-
puts (on specific pins):
– External int errupt generation
Alternate function mode is used for:
– Alternate signal input/output for the on-chip
peripherals
The generic I/O block diagram is shown in Figure
23.
7.2 FUNCTIONAL DESCRIPTION
Each port is associated wi th 3 registers located i n
Data space:
– Data Register (DR)
– Data Direction Register (DDR)
– Option Register (OR)
Each I/ O pin may be progr am med using the corre-
sponding register bits in t he DDR, DR and OR reg-
isters: bit x corresponding t o pin x of the port. Table
9 illustrates the various port configurations which
can be selected by user software.
During MCU initialization, all I/O registers are
cleared and the input mode with pull -up and no in-
terrupt generation is selected for all the pins, thus
avoiding pin conflicts.
7.2.1 Digital Input Modes
The input c onfigurat ion is sele cted by clearing th e
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the DR and OR registers, see Table 9.
E xternal Interrupt Function
All input lines can be individually connected by
software to the interrupt system by programming
the OR and DR registers accordingly. The inter-
rupt trigger modes (falling edge, rising edge and
low level) can be configured by software for each
port as described in the Interrupt section.
7.2.2 Analog Inputs
Som e pins can be co nfigured as analog in puts by
programm ing the OR and DR registers according-
ly, see Tabl e 9. T hese analog in puts are connect-
ed to the on-chip 8-bit Analog to Digital Converter.
Caution: ONLY ONE
pin sho uld be programmed
as an analog inpu t at any time, since by s electing
more than o ne input simultaneously their pins will
be effectively shorted .
7.2.3 Output Modes
The out put configu ration is s elected by setting the
corresponding DDR re gister bit. In this case, w rit-
ing to the DR register applies this digital value to
the I/O pin through the latch. Then, r eading the DR
register returns the previously stored value.
Two different output modes can be selected by
software through the OR register: push-pull and
open-drain.
DR register value and output pin status:
Note: The open drain setting is not a true open
drain. This means it has the same structure as the
push-pull setting but the P-buffer is deactivated.
To avoid damaging the dev ice, please respect the
VOUT absolute maximum rating described in the
Electrical Characteristics section.
7.2.4 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function (timer input/output...) is
not systematically selected but has to be config-
ured through the DDR, OR and D R registers. Re-
fer to the chapter describing the peripheral for
more details.
DR Push-pull Open-drain
0V
SS VSS
1V
DD Floating
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I/O POR T S (Cont ’d)
Figu re 23. I /O Por t Bloc k D i agram
Table 9. I/ O Port Configurations
Note: x = Don’t care
DDR OR DR Mode Option
0 0 0 Input With pull-up, no interrupt
0 0 1 Input No pull-up, no interrupt
0 1 0 Input With pull-up and with interrupt
0 1 1 Input Analog input (when available)
1 0 x Output Open-drain output (20mA sink when available)
1 1 x Output Push-pull output (20mA sink when available)
VDD
RESET
ST6
INTERNAL
DATA
DATA
DIRECTION
REGISTER
REGISTER
OPTION
REGISTER
TO INTERRUPT
VDD
TO ADC
VDD
N-BUFFER
P-BUFFER
PULL-UP
CMOS
SCHMITT
TRIGGER
Pxx I/O Pin
BUS
CLAMPING
DIODES
*
* Depending on device. See device summary on page 1
.
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I/O POR T S (Cont ’d)
7.2.5 Instructions NOT to be used to access
Port Data registers (SE T , RES, INC and DEC)
DO NOT USE READ-MODIFY-WRITE INSTRUC-
TIONS (SET, RES, INC and DEC) ON PORT
DA TA REGI STERS IF ANY P IN OF T HE PORT IS
CONFIGURED IN INPUT MO DE.
These instructions make an implicit read and write
back of the entire register. In port input mode,
however, the data register reads from the input
pins directly, and not from the data register latch-
es. Since dat a register information in input mode is
used to set the charac teristics of the inp ut pin (in-
terrupt, pull-up, analog inpu t), these may be uni n-
tentionally reprogrammed depending o n the state
of the input pins.
As a general rule, it i s better to only use single bit
instructions on data registers when the whole (8-
bit) port is in output mode. In the case of input s or
of mixed inputs and out puts, it is advisable to keep
a copy of the data register in RAM. Single bit in-
structions may then be used on the RAM copy, af-
ter which the whole copy register can be written to
the port dat a register:
SET bit, datacopy
LD a, datacopy
LD DRA, a
7.2.6 Recommend ations
1. Safe I/O State Switchi ng Sequen ce
Switching the I/O ports from one state to another
should be done in a sequenc e which ensures that
no unwanted side effects can occur. The recom-
mended safe transitions ar e illustrated in Figure 24
The Interrupt Pull-up to Input Analog transition
(and vice-vesra) is potentially risky and should b e
avoided when changing the I/O operating mode.
2. Handling Unused Port Bits
On ports that have less tha n 8 external pins con-
nected:
– Leave the unbonded pin s in reset state and do
not change thei r configuration.
– Do not use instruc tions th at act on a whole port
register (INC, DEC, or read operations). Unavail-
able bit s must be masked by software (AND in-
struction). Thus, when a read operation
performed on an incomplete port is followed by a
comparison, use a mask.
3. High Impedance Input
On any CMOS device, it is not recommended to
connect high impedance on input pins. The choice
of these impedance has to be done with respect to
the maximum leakage current defined in the da-
tasheet . The risk is t o be close or out of specifica-
tion on the input levels applied to the device.
7.3 LOW POWER MODES
The WAIT and STOP instructions allow the
ST62xx to be used in situations where low power
consumption is needed. The lowest power con-
sumption is achieved by configuri ng I/Os in output
push-pull low mode.
7.4 INTE RRUPTS
The exter nal interrupt event generates an int errupt
if the correspondi ng configuration is selected with
DDR, DR and OR registers (see Table 9) and the
GEN-bit in the IOR register is set .
Figure 24. Diagram showing S afe I/O State Transitions
Note *. xxx = DDR, OR, DR Bits respecti vely
Mode Description
WAIT No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.
STOP No effect on I/O ports. External interrupts
cause the device to exit from STOP mode.
Interrupt
pull-up
Output
Open Drai n
Output
Push-pull
Input
pull-up (Reset
state)
Input
Analog
Output
Open Drain
Output
Push-pull
Input
010*
000
100
110
011
001
101
111
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I/O PORTS (Cont’d)
Table 10. I/O Port Option Selections
Note 1. Provided the correct configuration has been selected (see Table 9).
MODE AVAILABLE ON(1) SCHEMATIC
Digital Input
Input PA0-PA3
PB0-PB7
DDRx
0ORx
0DRx
1
Reset state
Input
with pull up PA0-PA3
PB0-PB7
DDRx
0ORx
0DRx
0
Input
with pull up
with interrupt PA0-PA3
PB0-PB7
DDRx
0ORx
1DRx
0
Analog Input
Analog Input PB0-PB3
(ST6210C/20C
only)
PB4-PB7
(All devices,
except ST6208C)
DDRx
0ORx
1DRx
1
Digital output
Open drain outpu t (5mA)
Open drain output (20 mA)
PB0-PB7
PA0-PA3
DDRx
1ORx
0DRx
0/1
Push-pull output (5mA)
Push-pull output (20 mA)
PB0-PB7
PA0-PA3
DDRx
1ORx
1DRx
0/1
Data in
Interrupt
VDD
VDD
Data in
Interrupt
VDD
VDD
Data in
Interrupt
VDD
VDD
ADC
VDD
Data out
P-buffer disconnected
VDD
Data out
VDD
1
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I/O POR T S (Cont ’d)
7.5 REGISTER DESCRIPTION
DATA REGISTER (DR)
Port x Data Register
DRx with x = A o r B.
Address DRA: 0C0h - Read/Write
Address DRB: 0C1h - Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = D[7:0]
Data register bits.
Reading the DR regis ter returns either the DR reg-
ister l atch content (pin configured as output) or the
digital value applied to the I/O pin (pin conf igured
as input).
Caution: In input mode, modifying this regis ter will
modify the I/O port configuration (see Table 9).
Do not use the Single bit instructions on I/O port
data regist ers. See (Section 7.2.5).
DATA DIRECTION REGISTER (DDR)
Port x Data Direction Register
DDRx with x = A or B.
Address DDRA: 0C4h - Read/Write
Address DDRB: 0C5h - Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = DD[7:0]
Data direction register bits.
The D DR register gives th e input/output direction
configuration of the pins. Each bit is set and
cleared by software.
0: Input mode
1: Out put mode
OPTION REGISTER (OR)
Port x Option Register
ORx with x = A or B.
Address ORA : 0CCh - Read/Write
Address ORB : 0CDh - Read/Write
Reset Value: 0000 0000 (00h)
Bits 7:0 = O[7:0]
Option re gister bits.
The OR register allows to distinguish in output
mode if the push-pull or open drain configuration is
sele cted.
Output mod e :
0: Open drain output(with P-Buffer deactivated)
1: Push-pull Output
Input mode: See Table 9.
Each bit is set and cleared by software.
Caution: Modifying this register, will also modify
the I/O port configuration in input mode . (see Ta-
ble 9).
Table 11. I/ O Port Register Ma p and Reset Values
70
D7 D6 D5 D4 D3 D2 D1 D0
70
DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
70
O7 O6 O5 O4 O3 O2 O1 O0
Address
(Hex.) Regist er
Label 76543210
Reset Value
of all I/O port registers 00000000
0C0h DRA MSB LSB
0C1h DRB
0C4h DDRA MSB LSB
0C5h DDRB
0CCh ORA MSB LSB
0CDh ORB
1
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8 ON-CHIP PERIPHERALS
8.1 WATCHDOG TIMER (WDG)
8.1 .1 Int roducti on
The Watchdog timer is used to detect the occur-
rence of a software fault, usual ly generated by ex-
ternal interference o r by unfores een logi cal cond i-
tions, which causes the application program to
abandon it s normal seque nce. The W atchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed t ime peri od, unless the program refresh-
es the counter’s contents before the SR bit be-
comes cleared.
8.1.2 Main Featu res
■Programmable timer (64 steps of 3072 clock
cycles)
■Software reset
■Reset (if watchdog activated) when the SR bit
reaches zero
■Hardware or software watchdog activation
selectable by option bit (Refer to the option
bytes secti on)
Fi gure 25 . Watchdog Block Diagram
RESET
C
7-BIT DOWNCOUNTER
fint /12
SRT0
CLOCK DIVIDER
WATCHDOG REGISTER (WDGR)
÷ 256
T1 T2 T3 T4 T5 bit 0bit 7
1
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WATCHDOG TI MER (Cont’d)
8.1.3 Functional Desc ription
The watchdog activation is selected through an
option in the option bytes:
– HARDWARE Wat chdog option
After reset, the watchdog is permanently active,
the C bit in the WDG R is forced high an d the us er
can not change it. However, this bit can be read
equally as 0 or 1.
– SOFTWARE Watchdog option
After reset, the wat chdog is deactivated. The func-
tion is activated by s etting C bit in the WDGR reg-
ister. Once activated, it cannot be deactivated.
The counter value stored in the WDGR register
(bits SR:T0 ), is decremented every 3072 clock c y-
cles. The length of the t imeout period c an be pro-
grammed by the user in 64 steps of 3072 clock cy-
cles.
If the watchdog is activated (by setting the C bit)
and when the SR bit is cleared, the watchdog initi-
at es a reset cycl e pulling the reset pin low for typi-
cally 500ns.
The applica tio n program m ust write in the WDG R
register at regular intervals during normal opera-
tion to prevent an MCU reset. The value to be
stored in the WDGR register must be between
FEh and 02h (see T able 12). To run t he watchdo g
function the following conditions must be true:
– The C bi t is set (watchdog activated)
– The SR bit is set to pr ev ent generating an imme-
diate reset
– The T[5:0] bits contain the number of decre-
ments which r epresent the time delay before the
watchdog pr oduces a reset.
Tabl e 12. Watchdog Ti ming (fOSC = 8 MHz)
8.1.3.1 Software Rese t
The SR bit can be used to generate a soft ware re-
set by clearing the SR bit while the C bit is set.
8.1.4 Recommend ations
1. The Watchdog plays an important supporting
role in t he high noise immunity of ST62xx devices,
and should be used wherever possible. Watchdog
related option s sh ould b e select ed on the basis of
a trade-off between application security and STOP
mode availability (refer to the description of the
WDACT and EXTCNTL bits on the Option Bytes).
When S T OP m ode is not requ ired, ha rd ware a cti-
vation without EXTERNAL STOP MODE CON-
TROL should be preferred, as it provides maxi-
mum security, especiall y during power-on.
When STOP mode is required, hardware activa-
tion and EXTERNAL STOP MODE CONTROL
should be chosen. NMI shoul d be high by d efa ult,
to allow STOP mode to be entered when the MCU
is idle .
The NMI pin can be c onnected to an I/O line (see
Figure 26) to allow its st ate to be controlled by soft-
ware. The I/O line can then be used to ke ep NMI
low while Watchdog protection is required, or to
avoid noise or key bounce. When no more
processing is required, the I /O line is rel eased and
the device placed in STOP mode for lowest power
consumption.
Figure 26. A typical circuit making use of the
EXERNAL STOP MODE CONTROL feature
2. When software activation is selected (WDACT
bit in Opti on byte) and the Watchdog is not activat-
ed, the downcounter may be used as a simple 7-
bit timer (remember that the bits are in reverse or-
der).
The software activation option should be chosen
only when the Watc hdog counter is to be used as
a timer. To ensure the Watchdog has not been un-
expectedly activated, the following instructions
should be executed:
jrr 0, WDGR, #+3 ; If C=0,jump to next
ldi WDGR, 0FDH ; SR=0 -> reset
next :
WDGR Register
initial value WDG timeout period
(ms)
Max. FEh 24.576
Min. 02h 0.384
NMI
SWITCH
I/O
VR02002
1
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WATCHDOG TI MER (Cont’d)
These instructions test the C bit and reset the
MCU (i.e. disable the Watchdog) if the bit is set
(i.e. if the Watchdog is active), thus disabling the
Watchdog.
For more information on the use of the watch dog,
please read application note AN1015 .
Note: This note applies only when the watchdog is
used as a standard timer. It is recommended to
read the counter twic e, as it may somet imes return
an invali d value if the read is performed while the
counter is decremented (counter bits in transient
state). To validate the return value, both values
read must be equal. The counter decrements eve-
ry 384 µs at 8 MHz fOSC.
8.1.5 Low Power Mod es
8.1.6 Interrupts
None.
Mode Description
WAIT No effect on Watchdog.
STOP Behaviour depends on the EXTCNTL option in the Option bytes:
1. Watchdog disabled:
The MCU will enter Stop mode if a STOP instruction is executed.
2. Watchdog enabled and EXTCNTL option disabled:
If a STOP instruction is encountered, it is interpreted as a WAIT.
3. Watchdog and EXTCNTL option enabled:
If a STOP instruction is encountered when the NMI pin is low, it is interpreted as a WAIT. If, however, the
STOP instruction is encountered when the NMI pin is high, the Watchdog counter is frozen and the CPU en-
ters STOP mode.
When the MCU exits STOP mode (i.e. when an interrupt is generated), the Watchdog resumes its activity.
1
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WATCHDOG TI MER (Cont’d)
8.1.7 Register Descript ion
WATCHDOG REGISTER (WDGR)
Address: 0D8h - Read/Write
Reset Value: 1111 1110 (FEh)
Bits 7:2 = T[5:0]
Downcounter bits
Caution: These bits are reversed and shifted with
respect to the physical counter: bit-7 (T0) is the
LSB of the Watchdog downcounter and bit-2 (T5)
is the MSB.
Bi t 1 = SR:
Software Reset bit
Software can generate a reset by clearing this bit
while the C bit is set. Whe n C = 0 (Watc hdog de-
activated) the SR bit is th e MSB of the 7-bit t imer.
0: Generate (write)
1: No software reset generated, MSB of 7-bit timer
Bit 0 = C
W atchdog Contro l bit
.
If the hardware option is selected (WDACT bit in
Optio n byte), this bit is forced hi gh and ca nnot be
change d by the user (the Wa tchdog is always ac-
tive). When the software option is selected
(WDACT bit in Option byte), the Watchdog func-
tion is activated by setting the C bit, and cannot
then be deactivated (except by resetting the
MCU).
When C is kept cleared the counter can be used
as a 7-bit timer.
0: Wat chdog deactivated
1: Wat chdog activated
70
T0 T1 T2 T3 T4 T5 SR C
1
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8.2 8-BIT T IMER
8.2 .1 Int roducti on
The 8-Bit Timer on-chip peripheral is a free run-
ning downcounter ba se d o n an 8-bit do wnc ounter
with a 7-bit programmable prescaler, giving a max-
imum count of 2 15. The peripheral may be c onfig-
ured in three different ope rating modes.
8.2.2 Main Featu res
■Time-out downcounting mod e with up to 15-bit
accuracy
■External counter clock source (valid also in
STOP mo de)
■Interrupt capabil ity on counter under flow
■Output si gnal generation
■External puls e length measurement
■Event counter
The timer can be us ed i n WAIT and STOP m odes
to wake up the MCU.
Figure 27. Timer Block Diagram
INTERRUPT
TMZ ETI TOUT DOUT PSI PS2 PS1 PS0 TSCR
PROGRAMMABLE PRESCALER
PSCR6 PSCR5 PSCR4 PSCR3 PSCR2 PSCR1 PSCR0
PSCR REGISTER 0
70
TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
TCR
70
RELOAD
8-BIT DOWN COUN T E R
TIMER
fPRESCALER
fCOUNTER
fEXT
fINT/12
LATCH
PIN
PSCR7
7
/2 /1
/4/8/16/32/64/128
REGISTER
REGISTER
1
ST6208C/ST6209C/ST6210C/ST6220C
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8- B IT TI ME R (Cont’d)
8.2.3 Counter/Prescaler Descrip tion
Prescaler
The prescaler input can be the internal frequency
fINT divided by 12 or an external clock applied to
the TIMER pin. The prescaler decre men ts on the
rising edge, depending on the division factor pro-
grammed by the P S[2:0] bits in the TSCR register.
The state of the 7-b it prescaler ca n be read in th e
PSCR register.
When the prescaler reaches 0, it is automatically
reloaded wit h 7Fh.
Counter
The free running 8-bit downcounter is fed by the
output of the programm able prescaler, and is dec-
remented on every rising edge of the fCOUNTER
clock signal coming from the prescaler.
It is possible to read or write the contents of the
counter on the fly, by reading or writing the timer
counter register (TCR).
When the downcounter reaches 0, it is automati-
cally reloaded with the val ue 0FFh.
Counter Clock and Prescal er
The counter clock frequency is given by:
fCOUNTER = fPRESCALER / 2PS[2:0]
where fPRESCALER can be:
–f
INT/12
–f
EXT (input on TIMER pin)
–f
INT/12 gated by TIMER pin
The timer input clock feeds the 7-bit programma-
ble prescaler. The prescaler output can be pro-
grammed by selecting one of the 8 avai lable pres-
caler taps using the PS[2: 0] bit s in the Status/Con-
trol Register (TSCR). Thus the division factor of
the prescaler can be set to 2n (where n equals 0, to
7). See Figure 27.
The clock input is enabled by the PSI (Prescaler
Initialize) bit in the TSCR register. When PSI is re-
set, the counter is frozen and the prescaler is load-
ed with the value 7Fh. When PSI is set, the pres -
caler and t he counter run at the rat e of t he sel ec t-
ed clock source.
Counter and Prescaler I nitialization
After RESET, the counter and t he presc aler are in-
itialized to 0FFh and 7Fh respectiv ely.
The 7-bit prescaler can be initialized to 7Fh by
clearing the PSI bit. Direct write access to the
prescaler is also possible when PSI =1. Then, any
value between 0 and 7Fh can be loaded int o it.
The 8-bit counter can be initialized separately by
writing to the TCR register.
8.2.3.1 8-bit Counting and Interrupt Capability
on Counter Underflow
Whatever the division factor defined for the pres-
caler, the Timer Counter works as an 8-bit down-
counter. T he input clock frequency is user selec ta-
ble using the PS[2:0] bits.
When the downcounter decrements to zero, the
TMZ (Timer Zero) bit in the TSCR is set. If the ETI
(Enable Timer Interrupt) bit in the TSCR is also
set, an interrupt request is generated.
The Timer interrupt can be used to exit the MCU
from WAIT or STOP mode.
The TCR can be writ ten at any time by software to
define a time period ending with an underflow
event, and the re fore manage delay or timer func-
tions.
TMZ is set when the downcounter reaches zero;
however, it may also be set by writing 00h in the
TCR register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts when leaving the interrupt service
routine.
Note: A write to the TCR register will predominate
over the 8-bit counter decrement to 00h function,
i.e. if a write and a TCR register decrem ent to 00h
occur simultaneously, the write will take prece-
dence, and the TMZ bit is not set until the 8-bit
counter underflows again.
1
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8- B IT TI ME R (Cont’d)
8.2.4 Functional Desc ription
There are three operating modes, which are se-
lected by the TOUT and DOUT bits (see TSCR
register). These three modes correspond to the
two clocks which can be connected to the 7-bit
prescaler (fINT ÷ 12 or TIMER pin signal), and to
the output mode.
The settings for the different operating modes are
summarized Table 13.
Table 13. Timer Oper ating Modes
8.2.4.1 Gated Mode
(TOUT = “0”, DOUT = “1”)
In this m ode, t he pres caler i s decrem ent ed by the
Timer clock input, but onl y when the signa l on th e
TIMER pin is held high (fINT/12 gated by TIMER
pin). See Figure 28 and Figure 29.
This mode is selected by clearing the TOUT bit in
the TSCR register (i.e. as input) and setting the
DOUT bit.
Note: In this mode, if the TIMER pin is multi-
plexed, the corresponding port control bits have to
be set in input with pull-up configuration through
the DDR, OR and DR registers. For more details,
please refer to the I/O Ports section.
Figu re 28. fTIMER Clock in Ga te d Mo de
Figu re 29 . Gat ed Mode Operation
TOUT DOUT Timer
Function Application
00
Event Coun ter
(input) External counter clock
source
01Gated input
(input) External Pulse length
measurement
10Output “0”
(output) Output signal
11Output “1”
(output) generation
fPRESCALER
TIMER
fINT/12
fEXT
xx1
1
CO UNTER VALUE
TIMER PIN
TIMER CLOCK
VALUE 1
VALUE 2
PULSE LENGTH
xx2
1
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8- B IT TI ME R (Cont’d)
8.2.4.2 Event Counter Mode
(TOUT = “0”, DOUT = “0”)
In this mode, the TIMER pin is the input clock of
the Timer prescaler which is decremented on eve-
ry rising edge of the input clock (allowing event
count). See Figure 30 and Figure 31.
This mode is selected by clearing the TOUT bit in
the TSCR register (i.e. as input) and clearing the
DOUT bit.
Note: In this mode, if the TIMER pin is multi-
plexed, the corresponding port control bits have to
be set in input with pull-up configuration.
Figure 30. fTIMER Clock in Event Cou nter Mode
Figure 31. Event Counter Mode Operation
8.2.4.3 Output Mode
(TOUT = “1”, DOUT = “data out”)
In Output mode, the TIMER pin is connected to the
DOUT lat ch, hence the Timer prescaler is c locked
by the prescaler clock input (fINT/12). See Figure 32.
The user can select the prescaler division ratio us-
ing the PS[2:0] bits in the TSCR register. When TCR
decrements to zero, it sets the TMZ bit in the TSCR.
The TMZ bit can be tested under program control to
perform a t imer function whenever it goes high and
has to be cleared by the user. The low-to-high TMZ
bit transition is used to latch the DOUT bit in the
TSCR and, if the TOUT bit is set, DO UT is trans-
ferred to the TIMER pin. This operating mode allows
external signa l generation on the TIMER pin. See
Figure 33.
This mode is selected by setting the TOUT bit in
the TSCR register (i.e. as output) and setting the
DOUT bit to output a high level or clearing the
DOUT bit to o utput a low level.
Note: As soon as the TOUT bit is set, The timer
pin is configured as output push-pull regardl ess of
the corresponding I/O port control registers setting
(if the TIMER pin is multiplexed).
Figu re 32. Out pu t Mo de Control
Figure 33. Ou tput Mode Operation
fPRESCALERTIMER
XX1
COUNTER VAL UE
TIMER PIN
VALUE 1
VALUE 2
XX2
TMZ
TIMER
TOUT DOUT
LATCH
FFh
1
Counter
TIMER PI N
1st downcount:
Defa ult output value is 0
A t each zero event
DOUT has to be
copie d to the TIMER
pin
1
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8- B IT TI ME R (Cont’d)
8.2.5 Low Power Mod es 8.2.6 Interr up ts
Mode Description
WAIT No effect on timer.
Timer interrupt events cause the device to
exit from WAIT mode.
STOP Timer registers are frozen except in Event
Counter mode (with external clock on TIM-
ER pin).
Interrupt Event Event
Flag Enable
Bit
Exit
from
Wait
Exit
from
Stop
Timer Zero
Event TMZ ETI Yes Yes
1
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8- B IT TI ME R (Cont’d)
8.2.7 Register Descript ion
PRESCALER COUNTER REGISTER (PSCR)
Address: 0D2h - Read/ Write
Reset Value: 0111 1111 (7Fh)
Bi t 7 = PSCR7: Not used, always read as “0”.
Bits 6:0 = PSCR[6:0]
Prescaler LSB.
TIMER COUNTER REGISTER (TCR)
Address: 0D3h - Read / Write
Reset Value: 1111 1111 (FFh)
Bits 7:0 = TCR[7:0]
Time r counter bits.
TIMER STATUS CONT ROL REGISTER (TSCR)
Address: 0D4h - Read/ Write
Reset Value: 0000 0000 (00h)
Bi t 7 = TMZ
Time r Ze ro bit .
A low-to-high transition indicates that the timer
count register has underflowed. It means that the
TCR value has changed from 00h to FFh.
This bit must be cleared by user software.
0: Counter has not underflowe d
1: Counter underflow occurred
Bi t 6 = ETI
Enable Time r Interrupt.
When set, enables the timer interrupt request. If
ETI=0 the timer interrupt i s di sabled. If ETI=1 and
TMZ=1 an interrupt request is generated.
0: Interrupt disabled (rese t state)
1: Interrupt enabled
Bit 5 = TOUT Timer Out put Control
.
When low, this bit selects the input mode for the
TIMER pin. When high t he output mode i s select-
ed.
0: Input mode (reset state)
1: Output mode, the TIMER pin is configured as
push-pull outp ut
Bit 4 = DOUT
Data Output.
Data sent to the timer output when TMZ is set high
(output mode only). Input mode selection (input
mode only).
Bit 3 = PSI:
Pr es c a ler Ini tialize bit.
Used to initialize the prescaler and inhibit its count-
ing. W hen PS I =“0” t he prescaler is set to 7Fh and
the counter is inhibited. When PSI =“1” the prescal-
er is enabled to count downwards. As long as
PSE=“1” both counter and prescaler are not run-
ning
0: Count ing disabled
1: Count ing enabled
Bits 1:0 = PS[2:0]
Prescaler Mux. Select.
These bits s elect the division rati o of the prescaler
register.
Table 14. Prescaler Division Facto rs
Table 15. 8-B it Timer Register Map and Reset Values
70
PSCR
7PSCR
6PSCR
5PSCR
4PSCR
3PSCR
2PSCR
1PSCR
0
70
TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
70
TMZ ETI TOUT DOUT PSI PS2 PS1 PS0
PS2 PS1 PS0 Divided by
0 0 0 1
0 0 1 2
0 1 0 4
0118
10016
10132
11064
111128
Address
(Hex.) Reg ister Label 7 6543210
0D2h PSCR
Reset Value PSCR7
0PSCR6
1PSCR5
1PSCR4
1PSCR3
1PSCR2
1PSCR1
1PSCR0
1
0D3h TCR
Reset Value TCR7
1TCR6
1TCR5
1TCR4
1TCR3
1TCR2
1TCR1
1TCR0
1
0D4h TSCR
Reset Value TMZ
0ETI
0TOUT
0DOUT
0PSI
0PS2
0PS1
0PS0
0
1
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8.3 A/D CONVERT ER (ADC)
8.3 .1 Int roducti on
The on-chip An alog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter. This peripheral has multiplexed analog in-
put channels (refer to device pin out description)
that allow the peripheral to convert the analog volt-
age levels from different sources.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control Register.
8.3.2 Main Featu res
■8-bit conversion
■Multiplexed anal og input channels
■Linear successive approximat ion
■Data regist er (DR) which contains the results
■End of Conversion flag
■On/Off bit (to reduce consump tion)
■Typical conversion time 70 µs (with an 8 MHz
crystal)
The block diagram is shown in Figure 34.
Figure 3 4. ADC Block Diagram
Note: ADC not present on some devices . See device summ ary on page 1.
OSC
AD
EAI EOC STA PDS ADCR
AIN0
AIN1 ANALOG TO DIGITAL
CONVERTER
AINx
PORT
MUX
ADR2 ADR1ADR3ADR7 ADR6 ADR5 ADR4 ADR0
ADR
DIV 12 fADC
fINT
DDRx
ORx
DRx
I/O PORT
OFF
CR3 AD
CR1 AD
CR0
1
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A/D CONVERTER (Cont’d)
8.3.3 Functional Desc ription
8.3.3.1 Analog Power S up ply
The high and low level reference voltage pi ns are
internally connected to the VDD and VSS pins.
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
8.3.3.2 Digital A/D Con versi on Result
The conversion is monotonic, meaning that the re-
sult never decreases if the analo g input does not
and never increases if the analog input does not.
If the input voltage (VAIN) is greater than o r equal
to VDDA (high-level voltage reference) then the
conversion result in the DR register is FFh (full
scale) without overflow indication.
If input voltage (VAIN) is lower than or equal to
VSSA (low-level voltage reference) then the con-
version result in the DR register is 00h.
The A/D converter is l inear and the digital result of
the conversion is stored in the ADR register. The
accuracy of t he conversion is described in the par-
ametric section.
RAIN is the maximum recommended impedance
for an analog input sig nal. If the impe dance is too
high, this will result in a loss of accuracy due to
leakage and sampling no t being completed in the
allocated time. Refer to the electrica l characteris-
tics chapter for more detail s.
With an oscillator clock frequency less than
1.2MHz, conversi on accuracy is decreased.
8.3.3.3 Analog Input Selection
Selection of the input pin is done by configuring
the related I/O line as an analog input via the Data
Direction, Option and Data registers (refer to I/O
ports description for additional information).
Caution: On ly one I /O li ne m us t be configured as
an analog input at any time. T he us er must av oid
any situati on in which more than one I/O pi n is se-
lected as an analog input simul taneously, because
they will be shorted internally.
8.3.3.4 Softwar e Proced ure
Refer to the Control register (ADCR) and Data reg-
ister (ADR) in Section 8.3.7 for the bit definitions.
Analog Input Confi guration
The an alog inpu t must be configured through the
Port Control registers (DDRx, ORx and DRx). Re-
fer to the I/O port chapter.
ADC Configuration
In the ADCR regist er:
– Reset the PDS bit to power on the ADC. This bit
must be set at least one instruction before the
beginning of the conversion to allow stabilisation
of the A/D converter .
– Set the EAI bit to enable the ADC interrup t if
needed.
ADC Conversion
In the ADCR regist er:
– Set the STA bit to start a conv ersion. This auto-
matically clears (resets to “0”) the End Of Con-
version Bit (EOC).
When a conversion is compl ete
– The EOC bit is set by hardware to flag th at con-
version is complete and that t he dat a in the ADC
data conversion re gister is valid.
– An interrupt i s generated if the EAI bit was set
Setting the STA bit will start a new count and will
clear the EOC b it (thus clearing the interrupt con-
dition)
Note:
Setting the STA bit must be don e by a different in-
struction from the instruction that powers-on the
ADC (setting the PDS bit) in order to make sure
the voltage to be converted is present on the pin.
Each conversion has to be separately initiated by
writing to the STA bit.
The STA bit is continuously s canned so that, if the
user sets it to “1” while a previous conversion is in
progress, a new conversion is started before com-
pleting the previous one. The start bit (STA) is a
write only bit, any attempt to read it will show a log-
ical “0”.
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A/D CONVERTER (Cont’d)
8.3.4 Recommend ations
The following six notes provi de additi onal informa-
tion on usi ng the A/D converter.
1.The A/D converter does not feature a sample
and hold circuit. The analog voltage to be meas-
ured should therefore be stable during the entire
conversion cycle. V oltage variation sh ould not ex-
ceed ±1/2 LSB for optimum conversion accuracy.
A low pass filter may be used at the analog input
pins to reduce input voltage variation during con-
version.
2. When select ed as an analo g channel, the i nput
pin is internally connected to a capacitor Cad of
typ i ca lly 9 p F. For maxi mum accura cy, this capaci-
tor must be fully cha rged at the beginning of con-
version. In the worst case, conversion starts one
instruction (6.5 µs) after the channel has b een se-
lected. The impedance of the analog voltage
source (ASI) in worst case conditions, is calculat-
ed using the following formula:
6.5µs = 9 x Cad x ASI
(capacitor charged to over 99.9%), i.e. 30 kΩ in-
cluding a 50% guardband.
The AS I can be higher i f Cad has been charged for
a longer period by adding instructions before the
start of convers ion (add ing more t han 26 CP U cy -
cles is poi ntless).
3. Since the ADC is on the same chip as the micro-
processor, the user should not switch heavily load-
ed output signals during conversion, if high preci-
sion is requir ed. Such switching wil l aff ec t the sup-
ply voltages used as analog references.
4. Conversion accuracy depends on the quality of
the po wer supp lies (VDD and VSS). The user must
take special care t o ensure a well regulated refer-
ence voltage is present on the VDD and VSS pins
(power supply voltage variations must be less t han
0.1V/ms). This impl ies, in particular, that a suitable
decoupling capac itor is used at the VDD pin.
The converter resolution is given by:
The Input voltage (Ain) which is to be converted
must be constant for 1µs before conversion and
remain cons tant during conversion.
5. Conversion resolution can be improved if the
power supply voltage (VDD) to the mi crocon troller
is lowered.
6. In order to optimize the conversion resolution,
the user can confi gure the microcontroller in WAIT
mode, becau se this mode minimises noise distur-
bances and power s upply variations due to output
switching. Nevertheless, the WAIT instruction
should be execut ed as s oon as possible after the
beginning of the conv er sion, because execut ion of
the WAIT instruction may cause a small variation
of the VDD voltage. T he negat i ve effect of this var-
iation is m inimized at the beginn ing of t he c onver-
sion when the converter is less sensitive, rather
than at the en d of conversion, when the leas t sig-
nificant bits are determined.
The best configuration, from an accuracy stand-
point, is WAIT mode with the Timer stopped. In
this case only the ADC peripheral and the osci lla-
tor are then still working. The MCU must be woken
up from WAIT mode by the ADC interrupt at the
end of the conversion. The microcontroller can
also be woken up by the Timer interrupt, but this
means the Timer must be running an d the result-
ing noise could affect conversion acc uracy.
Caution: When an I/O pin is used as an analog in-
put, A/D conversion accuracy will be impaired if
negative c urrent injecti ons (VINJ < VSS) occur f rom
adjac ent I /O pi ns w ith analog i nput c apa bilit y . R e-
fer to Figure 35. To avoid this:
– Use another I/O port located further away from
the analog pi n, preferably not multi plexed on the
A/D converter
– Increase the input resistance RIN J (to reduce the
current inject ions) and reduce RADC (to preserve
conversion accurac y).
Figure 35. Leakag e from Digital Inputs
VDD VSS
–
256
--------------------------------
PBy/AINy
PBx/AINx
RADC
Leakage Current
if VINJ < VSS
A/D
I/O Port
(Digital I/O)
RINJ
Converter
Digital
Input
Analog
Input
VAIN
VINJ
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A/D CONVERTER (Cont’d)
8.3.5 Low Power Mod es
Note: The A/D converter may be disabled by clear-
ing the PDS bit. This feature allows reduc ed power
consumption when no conversion is needed.
8.3.6 Interrupts
Note: The EOC bit is cleared only when a new
conversion is started (it cannot be c leared by writ-
ing 0). To avoi d generati ng further EOC interrup t,
the EAI bit has to be cleared within the ADC inter-
rupt subroutine.
8.3.7 Register Descript ion
A/D CONVERTER CONTROL REGISTER (AD-
CR)
Address: 0D1h - Read/Write (Bit 6 Read Only, Bit
5 Write Only)
Reset value: 0100 0000 (40h)
Bi t 7 = EAI
Enable A/D Interrupt.
0: ADC int errupt disabled
1: ADC interrupt enabled
Bi t 6 = EOC
End of conversion.
Read Only
When a conversion has been completed, this bit is
set by hardware and an interr upt request is gener-
ated if the EAI bit is set. The EOC bit is autom ati-
cally cleared whe n the STA bit is set. Data in the
data conversion register are valid only when this
bit is set to “1”.
0: Convers ion is not complete
1: Convers ion can be read fr om the ADR register
Bit 5 = STA
: Start of Conversion. Write Only
.
0: No eff ect
1: Start conversion
Note: Setting this bit automatically clears t he EOC
bit. If the bit is set again when a conversion is in
progress, the present conversion is stopped and a
new one will take pl ace. This bit is write only, any
attempt to read i t will show a logical zer o.
Bit 4 = PDS
Power Down Selection.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 3 = ADCR3 Reserved, must be clear ed.
Bit 2 = OSCOFF
Main Oscill ator off.
0: Mai n Osci llator enabled
1: Mai n Osci llator disabled
Note: This bit does not apply to the ADC peripher-
al b ut to the main clock system. Refer to the Clo ck
System section.
Bits 1:0 = ADCR[1:0] Reserved, must be cleared.
A/D CONVERTER DATA REGISTER (ADR)
Address: 0D0h - Read only
Reset value: xxxx xxxx (xxh)
Bits 7:0 = ADR[7:0]
: 8 Bit A/D Conversion Result.
Table 16. A DC Register Map and Reset Values
Mode Description
WAIT No effect on A/D Converter. ADC interrupts
cause the device to exit from Wait mode.
STOP A/D Converter disabl ed.
Interrupt Event Event
Flag Enable
Bit
Exit
from
Wait
Exit
from
Stop
End of Conver-
sion EOC EAI Yes No
70
EAI EOC STA PDS ADCR
3OSC
OFF ADCR
1ADCR
0
70
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
Address
(Hex.) Register
Label 76543210
0D0h ADR
Reset Value ADR7
0ADR6
0ADR5
0ADR4
0ADR3
0ADR2
0ADR1
0ADR0
0
0D1h ADCR
Reset Value EAI
0EOC
1STA
0PDS
0ADCR3
0OSCOFF
0ADCR1
0ADCR0
0
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9 INSTRUCTIO N SET
9.1 ST6 ARCHITECTURE
The ST6 arch itecture has been designed for max -
imum efficiency while keeping byte usage to a
minimum; in short, to provide byte-efficient pro-
gramming. The ST6 core has the ability to set or
clear any register or RAM location bit in Data
space using a s ingle instruction. Furthermore, pro-
grams can branch to a selected address depend-
ing on the status of any bit in Dat a space.
9. 2 ADDRESSI NG MODES
The ST6 has nine addressing modes, which are
described in the following paragraphs. Three dif-
ferent address spaces are available: Program
space, Data space, and Stack space. Program
space contains t he inst ructions which are to be ex-
ecuted, plus t he data for immedi ate mo de in struc-
tions. Data space contains t he Accumulator, the X,
Y, V and W registers, peripheral and Input/Output
registers, the RA M lo cations and Data ROM l oca-
tions (for storage of tables and constants). Stack
space cont ains six 12-bi t RA M c ells used t o st ack
the return addresses for subroutines and inter-
rupts.
Immediate. In immediate addressing mode, the
operand of t he instruc tion fol lows the opcode loca-
tion. As the operand i s a ROM byte, the immediate
addressing mode is used to access constants
which do not change during program execution
(e.g., a constant used to initialize a loop counter).
Direct. In direct addres sing mode , the address of
the byte which is processed by the instruction is
stored in t he location which follows the opcode. Di-
rect addressing allows the user to directly address
the 256 bytes in Data Space mem ory with a single
two-byte instruction.
Short Direct. The core can address the four RAM
registers X, Y, V, W (locations 80h, 81h, 82h, 83h)
in short-direct addressing mode. In this case, the
instruction is only one byte and the sel ection of t he
location to be processed is contained in the op-
code. Short direct addressing is a su bset of direct
addressing mode. (Note that 80h and 81h are also
indi re ct registers).
Extended. I n extended addressin g mode, the 12-
bit address needed to d efine the instruction is ob-
tained by concatenating the four least significant
bits of the opcode with the byte following the op-
code. The instructions (JP, CALL) which use ex-
tended addressing mode are able to branch to any
address in the 4 Kbyte Program space.
Extended addressing mode instructions are two
bytes long.
Program Counter Relative. Relative addressing
mode is only used in conditional branch instruc-
tions. The instruction is used to perform a test and,
if the condition is true, a branc h with a span of -15
to +16 locations next to the address of the relative
instruction. If the condition is not true, the instruc-
ti o n w h ic h fo l lo ws t h e r el a ti ve i n st r uc t i on is exec ut -
ed. Relative addressing mode instructions are one
byte long. The opcode is obtained by adding the
three most significant bits which characterize the
test condi tion, one bit which determines whether it
is a forward branch (when it is 0) or backward
branch (wh en it is 1) and the fo ur least significant
bits which give the span of the branch (0h to Fh)
which must be added or subtracted from the ad-
dress of the relative instruction to obtain the
branch destinat ion address.
Bit Direct. I n bit direct addressing mode, the bit to
be set or cleared is part of the opcode, and the
byte fo llowing the opc od e points to the add ress of
the byte in which the specified bit must be set or
cleared. T hus, a ny bit in t he 25 6 locat ions of Dat a
space memory can be set or cleared.
Bit Test & Branch. Bit t est and branch addressing
mode is a combination of direct addressing and
relative addressing. Bit test and branch instruc-
tions are three bytes long. The bit identification
and the test condition are included in the opcode
byte. The address of the byte to be tes ted is given
in the next byte. The third byte is the jump dis-
placemen t, w hich is in the range of -127 to +128.
This displacement can be determined using a la-
bel, which is converted by the assembler.
Indirect. In indirect addressing mode, the byte
processed by the register-indirect instruction is at
the address pointed to by t he content of one of the
indirect registers, X or Y (80h, 81h). The indirect
register is selected by bit 4 of the opcode. Regis ter
indirect instructions are one byte long.
Inherent. I n inherent address ing mode, all the in-
formation necessary for executing the instruction
is contained in the opc ode. These i ns tructions are
one byte long.
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9.3 INSTRUCTION SET
The ST6 offers a set of 40 basic instructions
which, when combined with nine addressing
modes, yield 244 usable opcodes. They can be di-
vided into six different types: load/store, arithme-
tic/logic, conditional branch, control instructions,
jump/call, and bit manipu lation. The following par-
agraphs describe the different types.
All the instructions belonging to a given type are
presented in individual tables.
Loa d & S tore. These inst ructions u se one, two or
three bytes depending on the addressing mode.
For LOAD, one operand is the Accumulator and
the other operand is obtained from data memory
using one of the addressing modes.
For Load Immediate, one operand can be any of
the 256 data space bytes while the ot her i s always
immediat e data.
Table 17. Loa d & Store Instructions
Legend:
X, Y Index Reg i st ers,
V, W Short Direct Registe rs
# I m m ediate data (stored in R OM memory)
rr Data spac e regis te r
∆Affected
* Not Affected
Instruction Addressing Mode Bytes Cycles Flags
ZC
LD A, X Short Direct 1 4 ∆ *
LD A, Y Short Direct 1 4 ∆ *
LD A, V Short Direct 1 4 ∆ *
LD A, W Short Direct 1 4 ∆ *
LD X, A Short Direct 1 4 ∆ *
LD Y, A Short Direct 1 4 ∆ *
LD V, A Short Direct 1 4 ∆ *
LD W, A Short Direct 1 4 ∆ *
LD A, rr Direct 2 4 ∆ *
LD rr, A Direct 2 4 ∆ *
LD A, (X) Indirect 1 4 ∆ *
LD A, (Y) Indirect 1 4 ∆ *
LD (X), A Indirect 1 4 ∆ *
LD (Y), A Indirect 1 4 ∆ *
LDI A, #N Immediate 2 4 ∆ *
LDI rr, #N Immediate 3 4 * *
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INSTRUCTION SET (Cont’d)
Arithmetic and Logic. These instructions are
used to perform arithmetic calculations and logic
operations. In AND, ADD, CP, SUB instructions
one operand is always the accumulator while, de-
pending on the addressing mode, the other can be
either a data spa ce m emory locat ion or an i mme-
diate value. In CLR, DEC, INC inst ructions the op-
erand can be any of the 256 data space add ress-
es. In CO M, RLC, SLA the operan d is always the
accumulator.
Table 18. A rithmetic & Logic Instructions
Notes:
X,Y Index Registers
V, W Short Di rect Registers
∆ Affected
# Immediate data (s tored in ROM memory)
* Not Affected
rr Da t a space register
Instruction Addressing Mode Bytes Cycles Flags
ZC
ADD A, (X) Indirect 1 4 ∆∆
ADD A, (Y) Indirect 1 4 ∆∆
ADD A, rr Direct 2 4 ∆∆
ADDI A, #N Immediate 2 4 ∆∆
AND A, (X) Indirect 1 4 ∆∆
AND A, (Y) Indirect 1 4 ∆∆
AND A, rr Direct 2 4 ∆∆
ANDI A, #N Immediate 2 4 ∆∆
CLR A Short Direct 2 4 ∆∆
CLR r Direct 3 4 * *
COM A Inherent 1 4 ∆∆
CP A, (X) Indirect 1 4 ∆∆
CP A, (Y) Indirect 1 4 ∆∆
CP A, rr Direct 2 4 ∆∆
CPI A, #N Immediate 2 4 ∆∆
DEC X Short Direct 1 4 ∆*
DEC Y Short Direct 1 4 ∆*
DEC V Short Direct 1 4 ∆*
DEC W Short Direct 1 4 ∆*
DEC A Direct 2 4 ∆*
DEC rr Direct 2 4 ∆*
DEC (X) Indirect 1 4 ∆*
DEC (Y) Indirect 1 4 ∆*
INC X Short Direct 1 4 ∆*
INC Y Short Direct 1 4 ∆*
INC V Short Direct 1 4 ∆*
INC W Short Direct 1 4 ∆*
INC A Direct 2 4 ∆*
INC rr Direct 2 4 ∆*
INC (X) Indirect 1 4 ∆*
INC (Y) Indirect 1 4 ∆*
RLC A Inherent 1 4 ∆∆
SLA A Inherent 2 4 ∆∆
SUB A, (X) Indirect 1 4 ∆∆
SUB A, (Y) Indirect 1 4 ∆∆
SUB A, rr Direct 2 4 ∆∆
SUBI A, #N Immediate 2 4 ∆∆
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INSTRUCTION SET (Cont’d)
Conditional Branch. Branch i ns tructions pe rform
a branch in t he program wh en t he select ed condi-
tion is met.
Bit Manipulation Instructions. These instruc-
tions can handle any bit in Data space memory.
One group either sets or clears. The other group
(see Conditional Branch) performs the bit test
branch operations.
Co ntrol Instru ctions. Control instructions cont rol
microcontroller operations during program execu-
tion.
Jump and Call. These two instructions are used
to perform long (12-bit) jumps or subroutine calls
to any location in the whole program space.
Table 19. C ond itional Branch Instructions
Notes:
b 3-bit address rr Data space register
e 5 bi t s i gned displ aceme nt in the range -15 t o +16 ∆ Affected . The tested bit is shifted into ca rry.
ee 8 bit signed displ aceme nt in the range -126 to +129 * Not Affect ed
Table 20. B it Manipulation Instructions
Notes:
b 3 -bit address * No t A ffected
rr Data spac e register
Bit M anipulation Instr uctions should no t be used on Port Data Registers and any registers with read on l y and/or write o nl y bits (see I/ O port
chapter)
Table 21. Control Instructions
Notes:
1. T hi s i nstru ct i on i s deact i vated and a WAIT is aut omat ical l y exec ut ed i nstead of a STOP i f the wat chdog fu nction i s s el ected.
∆ Affected *Not Affecte d
Table 22. Jump & Cal l Instructions
Notes:
abc 12-bit address
* N ot Affected
Instruction Branch If Bytes Cycles Flags
ZC
JRC e C = 1 1 2 * *
JRNC e C = 0 1 2 * *
JRZ e Z = 1 1 2 * *
JRNZ e Z = 0 1 2 * *
JRR b, rr, ee Bit = 0 3 5 * ∆
JRS b, rr, ee Bit = 1 3 5 * ∆
Instruction Addressing Mode Bytes Cycles Flags
ZC
SET b,rr Bit Direct 2 4 * *
RES b,rr Bit Direct 2 4 * *
Instruction Addressing Mode Bytes Cycles Flags
ZC
NOP Inherent 1 2 * *
RET Inherent 1 2 * *
RETI Inherent 1 2 ∆∆
STOP (1) Inherent 1 2 * *
WAIT Inherent 1 2 * *
Instru ction Addres sing Mode B ytes Cycles Flags
ZC
CALL abc Extended 2 4 * *
JP abc Extended 2 4 * *
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Opcode Map Summary. The following table contains an opcode map for the instructions used by the ST6
LOW 0
0000 1
0001 2
0010 3
0011 4
0100 5
0101 6
0110 7
0111
LOW
HI HI
0
0000
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD 0
0000
e abc e b0,rr,ee e NOP # e a,(x)
1pcr2ext1pcr3 bt1pcr 1prc1ind
1
0001
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 LDI 1
0001
e abc e b0,rr,ee e x e a,nn
1pcr2ext1pcr3 bt1pcr1 sd1prc2imm
2
0010
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 CP 2
0010
e abc e b4,rr,ee e # e a,(x)
1pcr2ext1pcr3 bt1pcr 1prc1ind
3
0011
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 CPI 3
0011
e abc e b4,rr,ee e a,x e a,nn
1pcr2ext1pcr3 bt1pcr1 sd1prc2imm
4
0100
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 ADD 4
0100
e abc e b2,rr,ee e # e a,(x)
1pcr2ext1pcr3 bt1pcr 1prc1ind
5
0101
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 ADDI 5
0101
e abc e b2,rr,ee e y e a,nn
1pcr2ext1pcr3 bt1pcr1 sd1prc2imm
6
0110
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 INC 6
0110
e abc e b6,rr,ee e # e (x)
1pcr2ext1pcr3 bt1pcr 1prc1ind
7
0111
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 7
0111
e abc e b6,rr,ee e a,y e #
1pcr2ext1pcr3 bt1pcr1 sd1prc
8
1000
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 LD 8
1000
e abc e b1,rr,ee e # e (x),a
1pcr2ext1pcr3 bt1pcr 1prc1ind
9
1001
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 9
1001
e abc e b1,rr,ee e v e #
1pcr2ext1pcr3 bt1pcr1 sd1prc
A
1010
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 AND A
1010
e abc e b5,rr,ee e # e a,(x)
1pcr2ext1pcr3 bt1pcr 1prc1ind
B
1011
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC 4 ANDI B
1011
e abc e b5,rr,ee e a,v e a,nn
1pcr2ext1pcr3 bt1pcr1 sd1prc2imm
C
1100
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 SUB C
1100
e abc e b3,rr,ee e # e a,(x)
1pcr2ext1pcr3 bt1pcr 1prc1ind
D
1101
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 INC 2 JRC 4 SUBI D
1101
e abc e b3,rr,ee e w e a,nn
1pcr2ext1pcr3 bt1pcr1 sd1prc2imm
E
1110
2 JRNZ 4 CALL 2 JRNC 5 JRR 2 JRZ 2 JRC 4 DEC E
1110
e abc e b7,rr,ee e # e (x)
1pcr2ext1pcr3 bt1pcr 1prc1ind
F
1111
2 JRNZ 4 CALL 2 JRNC 5 JRS 2 JRZ 4 LD 2 JRC F
1111
e abc e b7,rr,ee e a,w e #
1pcr2ext1pcr3 bt1pcr1 sd1prc
Abbreviations for Addressing Modes: Legend:
dir Direct # Indicates Illegal Instructions
sd Short Direc t e 5-bit Displacement
imm Immediate b 3-bit Address
inh Inhe rent rr 1-byte Dat a space addres s
ext Extended nn 1-byte immediate data
b.d Bit Direct abc 12-bit address
bt Bit Test ee 8-bit displacement
pcr Program Counter Relat ive
ind Indirect
2JRC
e
1prc
Mnemonic
Addressing Mode
Bytes
Cycles
Operands
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Opcode Map Summ ar y (Continued)
LOW 8
1000 9
1001 A
1010 B
1011 C
1100 D
1101 E
1110 F
1111
LOW
HI HI
0
0000
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 LDI 2 JRC 4 LD 0
0000
e abc e b0,rr e rr,nn e a,(y)
1pcr2ext1pcr2b.d1pcr3imm1prc1ind
1
0001
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD 1
0001
e abc e b0,rr e x e a,rr
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
2
0010
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 COM 2 JRC 4 CP 2
0010
e abc e b4,rr e a e a,(y)
1pcr2ext1pcr2b.d1pcr 1prc1ind
3
0011
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 CP 3
0011
e abc e b4,rr e x,a e a,rr
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
4
0100
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RETI 2 JRC 4 ADD 4
0100
e abc e b2,rr e e a,(y)
1pcr2ext1pcr2b.d1pcr1inh1prc1ind
5
0101
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 ADD 5
0101
e abc e b2,rr e y e a,rr
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
6
0110
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 STOP 2 JRC 4 INC 6
0110
e abc e b6,rr e e (y)
1pcr2ext1pcr2b.d1pcr1inh1prc1ind
7
0111
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 INC 7
0111
e abc e b6,rr e y,a e rr
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
8
1000
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 JRC 4 LD 8
1000
e abc e b1,rr e # e (y),a
1pcr2ext1pcr2b.d1pcr 1prc1ind
9
1001
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 LD 9
1001
e abc e b1,rr e v e rr,a
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
A
1010
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 4 RCL 2 JRC 4 AND A
1010
e abc e b5,rr e a e a,(y)
1pcr2ext1pcr2b.d1pcr1inh1prc1ind
B
1011
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 AND B
1011
e abc e b5,rr e v,a e a,rr
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
C
1100
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 RET 2 JRC 4 SUB C
1100
e abc e b3,rr e e a,(y)
1pcr2ext1pcr2b.d1pcr1inh1prc1ind
D
1101
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 DEC 2 JRC 4 SUB D
1101
e abc e b3,rr e w e a,rr
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
E
1110
2 JRNZ 4 JP 2 JRNC 4 RES 2 JRZ 2 WAIT 2 JRC 4 DEC E
1110
e abc e b7,rr e e (y)
1pcr2ext1pcr2b.d1pcr1inh1prc1ind
F
1111
2 JRNZ 4 JP 2 JRNC 4 SET 2 JRZ 4 LD 2 JRC 4 DEC F
1111
e abc e b7,rr e w,a e rr
1pcr2ext1pcr2b.d1pcr1 sd1prc2 dir
Abbreviations for Addressing Modes: Legend:
dir Direct # Indicates Illegal Instructions
sd Short Direc t e 5-bit Displacement
imm Immediate b 3-bit Address
inh Inhe rent rr 1-byte Dat a space addres s
ext Extended nn 1-byte immediate data
b.d Bit Direct abc 12-bit address
bt Bit Test ee 8-bit Displacement
pcr Program Counter Relat ive
ind Indirect
2JRC
e
1prc
Mnemonic
Addressing Mode
Bytes
Cycles
Operands
1
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10 ELECTRICAL CHARACTERISTICS
10.1 PARAMETER CONDITIO NS
Unless otherwise specified, all voltages are re-
ferred to VSS.
10.1.1 Mi nimum and Maximum Val ues
Unless otherwise specified t he m inimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage an d
frequencies by tests in production on 100% of th e
devices with an ambient temperature at TA=25°C
and TA=TAmax (given by the selected temperature
range).
Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the ta ble foo tnotes a nd are not tes ted
in production. Bas ed on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean±3Σ).
10.1.2 Typical Values
Unless otherwise specified, typical data are based
on TA=25°C, VDD=5V (for the 4.5V≤VDD≤6.0V
voltage range) and VDD=3.3V (for the
3V≤VDD≤3.6V vol tage range). They are given only
as des ign guideli nes and are not tested.
10.1.3 Typical Curves
Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.
10.1.4 Loading Capac itor
The loading conditions used for pin parameter
m eas urement is s hown i n Figure 36.
Figu re 36 . Pin Loading Co ndition s
10.1.5 Pin Input Vo ltage
The input voltage measurement on a pin of the de-
vice i s described in Figure 37.
Figu re 37 . Pin In put Volt age
CL
ST6 PIN
VIN
ST6 PIN
1
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10.2 ABSOLUTE MAXIMUM RATI NGS
Stresses above those listed as “absolute maxi-
mum ratings” may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-
tions is not implied. Exposure to maximum rating
conditio ns for extended periods may affect device
reliability.
10.2.1 Voltage Characteri sti cs
10.2.2 Curren t Characteristics
10.2.3 Thermal Characteristics
Notes:
1. Directly conn ectin g the RES ET and I/O pins to VDD or V SS coul d damag e the dev ice if an uni ntenti onal int ernal re set
is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program coun-
ter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ
for RESE T, 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset con-
figuration.
2. When the cu rrent lim itation is not po ssible, th e VIN absolut e maxim um rating must be respe cted, oth erwise re fer to
IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS.
3. Power (VDD) and ground (VSS) lines must always be connected to the external supply.
4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 1mA (assuming that the impedance of the analog voltage
is lower than the specified limits).
- Pure digital pins must have a negative injection less than 1mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
Symbol Ratings Maximum value Unit
VDD - VSS Supply voltage 7
V
VIN Input voltage on any pin 1) & 2) VSS-0.3 to VDD+0.3
VOUT Output voltage on any pin 1) & 2) VSS-0.3 to VDD+0.3
VESD(HBM) Electro-static discharge voltage (Human Body Model) 3500
Symbol Ratings Maximum value Unit
IVDD Total current into VDD power lines (source) 3) 80
mA
IVSS Total current out of VSS ground lines (sink) 3) 100
IIO
Output current sunk by any standard I/O and control pin 20
Output current sunk by any high sink I/O pin 40
Output current source by any I/Os and control pin 15
IINJ(PIN) 2) & 4) Injected current on RESET pin ±5
Injected current on any other pin ±5
Symbol Ratings Value Unit
TSTG Storage temperature range -60 to +150 °C
TJMaximum junction temperature
(see THERMAL CHARACTERISTICS section)
1
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10.3 OPERATING CONDITIONS
10.3.1 General Operating Conditio ns
Notes:
1. An oscillator frequency above 1.2MHz is recommended for reliable A/D results.
2. Operating conditions with TA=-40 to +125° C.
Figure 38. fOSC Maximum Operating Frequency Versus VDD Supply Voltage for OTP & ROM devices
Symbol Parameter Conditions Min Max Unit
VDD Supply voltage see F igure 38 3.0 6 V
fOSC Oscillator frequency
VDD=3.0V, 1 & 6 Suffix 0 1) 4
MHz
VDD=3.0V, 3 Suffix 0 1) 4
VDD=3.6V, 1 & 6Suffix 0 1) 8
VDD=3.6V, 3 Suffix 0 1) 4
VDD Operating Supply Voltage
fOSC=4MHz, 1 & 6 Suffix 3.0 6.0
V
fOSC=4MHz, 3 Suffix 3.0 6.0
fOSC=8MHz, 1 & 6 Suffix 3.6 6.0
fOSC=8MHz, 3 Suffix 4.5 6.0
TAAmbient tempe ratur e range 1 Suffix Version 0 70 °C
6 Suffix Version -40 85
3 Suffix Version -40 125
12.5 3.644.555.56
8
7
6
5
4
3
2
SUPPLY
3
fOSG
fOSG Min
fOSC [MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
3
VOLTAGE (VDD)
2
1
1. In this area, operation is guaranteed at the quartz crystal frequency.
2. When the OSG is disabled, operation in this area is guaranteed at the crystal frequency. When the
3. When the OSG is disabled, operation in this area is guaranteed at the quartz crystal frequency. When
OSG is enabled, operation in this area is guaranteed at a frequency of at least fOSG Min.
the OSG is enabled, access to this area is prevented. The internal frequency is kept at fOSG.
1 & 6 su ffi x vers ion
3 su ffi x vers ion
1
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OPERATING CONDITIONS (Cont’d)
10.3.2 Operating Conditions with Low Voltage Detecto r (LVD)
Subject to general operati ng conditions for VDD, fOSC, and TA.
Notes:
1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.
2. The minimum VDD rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.
3. Data based on characterization results, not tested in production.
Figure 39. LVD Threshold Versus VDD and fOSC3)
Figure 40. Typical LVD Thresholds Versus
Temperature for OTP devices Figure 41. Typical LVD thresholds vs.
Tem pera ture for ROM devices
Symbol Parameter Conditions Min Typ 1) Max Unit
VIT+ R eset relea se threshol d
(VDD rise) 3.9 4.1 4.3 V
VIT- R eset gene ration threshold
(VDD fall) 3.6 3.8 4
Vhys LVD voltage threshold hysteresis VIT+-VIT- 50 300 700 mV
VtPOR VDD rise time rate 2) mV/s
tg(VDD) Filtered glitch delay on VDD 3) Not detected by the LVD 30 ns
fOSC [MHz]
SUPPLY
8
4
02.5 3 3.5 4 4.5 5 5.5
FUNCTION AL AREA
RESET
FUNCTIONALITY
NOT GUARANT EED
IN THIS AREA
VIT-≥3.6
000000000000000000000000000000000000000000000000000000000000
0
000000000000000000000000000000000000000000000000000000
00000
0
000000000000000000000000000000000000000000000000000000
00000
000000000000000000000000000000000000000000000000000000000000
DEVICE UNDER
IN THIS AREA
6VOLTAGE [V]
-40°C 25°C 95°C 125°C
T [°C]
3.6
3.8
4
4.2
Thresholds [V]
Vdd up
Vdd down
VIT+
VIT-
-40°C 25°C 95°C 125°C
T [°C]
3.6
3.8
4
4.2
Thresholds [V]
Vdd up
Vdd down
VIT+
VIT-
1
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10.4 SUPPLY CURRENT CHARACTERISTICS
The following current consumption specified for
the ST6 funct ional operat ing modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consump tion, th e two current values mus t be
added (except for STOP mo de for which the clock
is stopped).
10.4.1 RUN Mode s
Notes:
1. Typical data are based on TA=25° C, VDD=5V (4.5V≤VDD≤6.0V range) and VDD=3.3V (3V≤VDD≤3.6V range).
2. Data based on characterization results, tested in production at VDD max. and fOSC max.
3. CPU running with memory access, all I/O pins in input with pull-up mode (no load), all peripherals in reset state; clock
input (OSCIN) driven by external square wave, OSG and LVD disabled, option bytes not programmed.
Figure 42. Typical IDD in RUN vs. fCPU Figure 43. Typical IDD in RUN vs. Temperature
(VDD = 5V)
Symbol Parameter Conditions Typ 1) Max 2) Unit
IDD
Supply current in RUN mode 3)
(see Figure 42 & F igure 43)
4.5V≤VDD≤6.0V
fOSC=32kHz
fOSC=1MHz
fOSC=2MHz
fOSC=4MHz
fOSC=8MHz
0.5
1.3
1.6
2.2
3.3
0.7
1.7
2.4
3.3
4.8 mA
Supply current in RUN mode 3)
(see Figure 42 & F igure 43)
3V≤VDD≤3.6V
fOSC=32kHz
fOSC=1MHz
fOSC=2MHz
fOSC=4MHz
fOSC=8MHz
0.3
0.6
0.9
1.0
1.8
0.4
0.8
1.2
1.5
2.3
3456
VDD [V]
0
1
2
3
4
5
IDD [mA]
8MHz
4MHz
2MHz
1MHz
32KHz
-40 25 95 125
T[°C]
0
0.5
1
1.5
2
2.5
3
3.5
IDD [mA]
8MHz
4MHz
2MHz
1MHz
32KHz
1
ST6208C/ST6209C/ST6210C/ST6220C
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SUPPLY CURRENT CHARACTERISTICS (Cont’d)
10.4.2 WAIT Modes
Notes:
1. Typical data are based on TA=25° C, VDD=5V (4.5V≤VDD≤6.0V range) and VDD=3.3V (3V≤VDD≤3.6V range).
2. Data based on characterization results, tested in production at VDD max. and fOSC max.
3. All I/O pins in input wit h pu ll-up mode (no load) , al l peripherals in r eset state; clock inpu t (O SCIN) driv en by external
square wave, OSG and LVD disabled.
Symbol Parameter Conditions Typ 1) Max 2) Unit
IDD
Supply current in WAIT mode 3)
Option bytes not programmed
(see Figure 44)
4.5V≤VDD≤6.0V
OTP devices
fOSC=32kHz
fOSC=1MHz
fOSC=2MHz
fOSC=4MHz
fOSC=8MHz
330
350
370
410
480
550
600
650
700
800
µA
Supply current in WAIT mode 3)
Option bytes programmed to 00H
(see Figure 45)
fOSC=32kHz
fOSC=1MHz
fOSC=2MHz
fOSC=4MHz
fOSC=8MHz
18
26
41
57
70
60
80
120
180
200
Supply current in WAIT mode3)
(see Figure 46)
ROM devices
fOSC=32kHz
fOSC=1MHz
fOSC=2MHz
fOSC=4MHz
fOSC=8MHz
190
210
240
280
350
300
350
400
500
600
Supply current in WAIT mode 3)
Option bytes not programmed
(see Figure 44)
3V≤VDD≤3.6V
OTP devices
fOSC=32kHz
fOSC=1MHz
fOSC=2MHz
fOSC=4MHz
fOSC=8MHz
80
90
100
120
150
120
140
150
200
250
Supply current in WAIT mode 3)
Option bytes programmed to 00H
(see Figure 45)
fOSC=32kHz
fOSC=1MHz
fOSC=2MHz
fOSC=4MHz
fOSC=8MHz
5
8
16
18
20
30
40
50
60
100
Supply current in WAIT mode 3)
Option bytes not programmed
(see Figure 46)
ROM devices
fOSC=32kHz
fOSC=1MHz
fOSC=2MHz
fOSC=4MHz
fOSC=8MHz
60
65
80
100
130
100
110
120
150
210
1
ST6208C/ST6209C/ST6210C/ST6220C
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SUPPLY CURRENT CHARACTERISTICS (Cont’d)
Figure 44. Typical IDD in WAIT vs fCPU and Temperature for OTP devices with option bytes not
programmed
Figure 45. Typical IDD in WAIT vs f
CPU and Temperature for OTP devices with option bytes
programm ed t o 00H
3456
VDD [V]
0
100
200
300
400
500
600
700
800
IDD [µ A]
8MHz
4MHz
2MHz
1M
32KHz
-40 25 95 125
T[°C]
200
300
400
500
600
700
IDD [µ A]
8MHz
4MHz
2MHz
1MHz
32KHz
3456
VDD [V]
0
20
40
60
80
100
120
IDD [µ A]
8MHz
4MHz
2MHz
1M
32KHz
-20 25 95
T[°C]
10
20
30
40
50
60
70
80
90
IDD [µ A]
8MHz
4MHz
2MHz
1MHz
32KHz
1
ST6208C/ST6209C/ST6210C/ST6220C
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SUPPLY CURRENT CHARACTERISTICS (Cont’d)
Figure 46. Typical IDD in WAIT vs fCPU and Temper ature for ROM dev ices
3456
VDD [V]
0
100
200
300
400
500
600
IDD [µ A]
8MHz
4MHz
2MHz
1M
32KHz
-20 25 95 125
T[°C]
100
150
200
250
300
350
400
450
IDD [µ A]
8MHz
4MHz
2MHz
1MHz
32KHz
1
ST6208C/ST6209C/ST6210C/ST6220C
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SUPPLY CURRENT CHARACTERISTICS (Cont’d)
10.4.3 STOP Mod e
Notes:
1. Typical data are based on VDD=5.0V at TA=25°C.
2. All I/O pins in input with pull- up mode (no load) , all perip herals in reset stat e, OSG a nd LVD disabled, option by tes
programmed to 00H. Data based on characterization results, tested in production at VDD max. and fCPU max.
3. Maximum STOP consumption for -40°C<Ta<90°C
4. Maximum STOP consumption for -40°C<Ta<125°C
Figu re 47 . T ypi c al IDD in STOP vs Temperature
for OTP device s Figu re 48 . Typical IDD in STOP vs Temp eratu re
for ROM devices
Symbol Parameter Conditions Typ 1) Max Unit
IDD Supply current in STOP mode 2)
(see Figure 47 & Figure 48)
OTP devices 0.3 10 3)
20 4) µA
ROM devices 0.1 2 3)
20 4)
3456
VDD [V]
0
200
400
600
800
1000
1200
IDD [nA]
Ta=-40°C
Ta=25°C Ta=95°C
Ta=125°C
3456
VDD [V]
0
500
1000
1500
IDD [nA]
Ta=-40°C
Ta=25°C Ta=95°C
Ta=125°C
1
ST6208C/ST6209C/ST6210C/ST6220C
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SUPPLY CURRENT CHARACTERISTICS (Cont’d)
10.4.4 Supply and Clock System
The previous current consumption specified for
the ST6 funct ional operat ing modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-
vice consump tion, th e two current values mus t be
added (except for STOP m ode).
10.4.5 On-Chip P eriphe ral s
Notes:
1. Typical data are based on TA=25°C.
2. Data based on characterization results, not tested in production.
3. Data based on a differential IDD measurement between reset configuration (OSG and LFAO disabled) and LFAO run-
ning (also includes the OSG stand alone consumption).
4. Data based on a differential IDD measurement between reset configuration with OSG disabled and OSG enabled.
5. Data based on a differential IDD measurement between reset configuration with LVD disabled and LVD enabled.
6. Data based on a differential IDD measurement between reset configuration (timer disabled) and timer running.
7. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions.
Symbol Parameter Conditions Typ 1) Max 2) Unit
IDD(CK)
Supply current of RC oscillator
fOSC=32 kHz,
fOSC=1 MHz
fOSC=2 MHz
fOSC=4 MHz
fOSC=8 MHz
VDD=5.0 V 230
260
340
480
µA
fOSC=32 kHz,
fOSC=1 MHz
fOSC=2 MHz
fOSC=4 MHz
fOSC=8 MHz
VDD=3.3 V 80
110
180
320
Supply current of resonator oscillator
fOSC=32 kHz,
fOSC=1 MHz
fOSC=2 MHz
fOSC=4 MHz
fOSC=8MHz
VDD=5.0 V
900
280
240
140
40
fOSC=32 kHz,
fOSC=1 MHz
fOSC=2 MHz
fOSC=4 MHz
fOSC=8 MHz
VDD=3.3 V
120
70
50
20
10
IDD(LFAO) LFAO suppl y current 3) VDD=5.0 V 102
IDD(OSG) OSG supply current 4) VDD=5.0 V 40
IDD(LVD) LVD supply current 5) VDD=5.0 V 170
Symbol Parameter Conditions Typ 1) Unit
IDD(TIM) 8-bit Timer supply current 6) fOSC=8 MHz VDD=5.0 V 170
µA
VDD=3.3 V 100
IDD(ADC) ADC supply current when converting 7) fOSC=8 MHz VDD=5.0 V 80
VDD=3.3 V 50
1
ST6208C/ST6209C/ST6210C/ST6220C
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10.5 CLOCK AND TI MING CHARACTERISTICS
Subject to general operati ng conditions for VDD, fOSC, and TA.
10.5.1 General Timings
10.5.2 External Clock Sou rce
Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to finish
the current instruction execution.
Figure 49. Typical Application with an External Clock Source
Symbol Parameter Conditions Min Typ 1) Max Unit
tc(INST) Instruction cycle time 245t
CPU
fCPU=8 MHz 3.25 6.5 8.125 µs
tv(IT) Interrupt reaction time 2)
tv(IT) = ∆tc(INST) + 6 611t
CPU
fCPU=8 MHz 9.75 17.875 µs
Symbol Parameter Conditions Min Typ Max Unit
VOSCINH OSCIN input pin high level voltage See Figure 49 0.7xVDD VDD V
VOSCINL OSCIN input pin low level voltage VSS 0.3xVDD
ILOSCx Input leakage current VSS≤VIN≤VDD ± 2 µA
OSCIN
OSCOUT
fOSC
EXTERNAL
ST62XX
CLOCK SOURCE
VOSCINL
VOSCINH
IL
90%
10%
Not conne ct ed
1
ST6208C/ST6209C/ST6210C/ST6220C
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CLOCK AND T IMI NG CHARACTERISTICS (Cont’d)
10.5.3 Crystal and Ceram ic Reson ator Osc illators
The ST6 internal clock can be s upplied with sever-
al different Crystal/Ceramic resonator oscillators.
Only parallel resonant crystals can be used. All the
information given in this paragraph are based on
characterization results with specified typical ex-
ternal components. Refer to the crystal/ceramic
resonator m anufacturer for more details (frequen-
cy, package, accuracy...).
Notes:
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. tSU(OSC) is the typical oscillator start-up time measured between VDD=2.8V and the fetch of the first instruction (with a
quick VDD ramp-up from 0 to 5V (<50µs).
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value.
Refer to crystal/ceramic resonator manufacturer for more details.
Figure 50. Typical Application wi th a Cryst al or Ceramic Resonator
Symbol Parameter Conditions Typ Unit
RFFeedback resistor 3 MΩ
CL1
CL2
Recommended load capacitances versus equiva-
lent crystal or ceramic resonator frequency
fOSC=32 kHz,
fOSC=1 MHz
fOSC=2 MHz
fOSC=4 MHz
fOSC=8 MHz
120
47
33
33
22
pF
Oscillator Typical Crystal or Ceramic Resonators CL1
[pF] CL2
[pF] tSU(osc)
[ms] 1)
Reference Freq. Characteristic 1)
Ceramic
MURATA
CSB455E 455KHz ∆fOSC=[±0.5KHztolerance,±0.3%∆Ta,±0.5%aging] 220 220
CSB1000J 1MHz ∆fOSC=[±0.5KHztolerance,±0.3%∆Ta,±0.5%aging] 100 100
CSTCC2.00MG0H6 2MHz ∆fOSC=[±0.5%tolerance,±0.5%∆Ta,±0.3%aging]4747
CSTCC4.00MG0H6 4MHz ∆fOSC=[±0.5%tolerance,±0.3%∆Ta,±0.3%aging]4747
CSTCC8.00MG 8MHz ∆fOSC=[±0.5%tolerance,±0.3%∆Ta,±0.3%aging]1515
OSCOUT
OSCIN
CL1
CL2
RF
ST62XX
RESONATOR
VDD
FOSC
1
ST6208C/ST6209C/ST6210C/ST6220C
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CLOCK AND T IMI NG CHARACTERISTICS (Cont’d)
10.5.4 RC Oscillator
The ST6 internal clock can be supplied with an external RC oscillator. De pendin g on the RNET value, the
accuracy of the frequency is about 20%, so it may not be suitable for some applications.
Notes:
1. Data based on characterization results, not tested in production. These measurements were done with the OSCin pin
unconnected (only soldered on the PCB).
2. RNET must have a positive temperature coefficient (ppm/°C), carbon resistors should therefore not be used.
Figure 51. Typical Appli cation with RC Oscill ator
Symbol Parameter Conditions Min Typ Max Unit
fOSC RC oscillator frequency 1)
4.5V≤VDD≤6.0V
RNET=22 kΩ
RNET=47 kΩ
RNET=100 kΩ
RNET=220 kΩ
RNET=470 kΩ
7.2
5.1
3.2
1.8
0.9
8.6
5.7
3.4
1.9
0.95
10
6.5
3.8
2
1.1 MHz
3V≤VDD≤3.6V
RNET=22 kΩ
RNET=47 kΩ
RNET=100 kΩ
RNET=220 kΩ
RNET=470 kΩ
3.7
2.8
1.8
1
0.5
4.3
3
1.9
1.1
0.55
4.9
3.3
2
1.2
0.6
RNET RC Oscillator external resistor 2) see Figure 52 & F igure 53 22 870 kΩ
OSCIN
OSCOUT
RNET
EXTERNAL RC
C
EX
~9pF DISCHARGE
ST62XX
VDD VDD
fOSC
VDD
NC
MIRROR
CURRENT
1
ST6208C/ST6209C/ST6210C/ST6220C
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CLOCK AND T IMI NG CHARACTERISTICS (Cont’d)
Figure 5 2. Typic al RC Osci llator freque ncy vs.
VDD Figure 53. Typical RC Oscillator frequency vs.
Tem pera ture (VDD = 5V)
10.5.5 Oscillator Sa fegu ard (OSG) and Low Freq uency A uxiliary Os cillator (LFA O)
Figu re 54 . Ty pi ca l LF A O Freque nci e s
Note:
1. Data based on characterization results.
3456
VDD [V]
0
2
4
6
8
10
12
fosc [MHz] Rnet=22KOhm
Rnet=47KOhm
Rnet=100KOhm
Rnet=220KOhm
Rnet=470KOhm
-40 25 95 125
Ta [°C]
0
2
4
6
8
10
fosc [MHz] Rnet=22KOhm
Rnet=47KOhm
Rnet=100KOhm
Rnet=220KOhm
Rnet=470KOhm
Symbol Parameter Conditions Min Typ Max Unit
fLFAO Low Frequency Auxiliary Oscillator
Frequency 1) TA=25° C, VDD=5.0 V 200 350 800 kHz
TA=25° C, VDD=3.3 V 86 150 340
fOSG Internal Frequency with OSG ena-
bled TA=25° C, VDD=4.5 V 4 MHz
TA=25° C, VDD=3.3 V 2
3456
VDD [V]
0
100
200
300
400
500
600
fosc [kHz]
Ta=-40°C
Ta=25°C
Ta=125°C
1
ST6208C/ST6209C/ST6210C/ST6220C
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10.6 MEMORY CHARACTERISTI CS
Subject to general operati ng conditions for VDD, fOSC, and TA unless otherwis e specified.
10.6.1 RAM and Hardware Registers
10.6.2 EPROM Program Memory
Figure 55. EPROM Retention Time vs. Temperature
Notes:
1. Minimum VDD supply voltage without losing data stored in RAM (in STOP mode or under RESET) or in hardware reg-
isters (only in STOP mode). Guaranteed by construction, not tested in production.
2. Data based on reliability test results and monitored in production. For OTP devices, data retention and programmability
must be guaranteed by a screening procedure. Refer to Application Note AN886.
3. The data retention time increases when the TA decreases, see Figure 55.
Symbol Parameter Conditions Min Typ Max Unit
VRM Data retention1) 0.7 V
Symbol Parameter Conditions Min Typ Max Unit
tret Data retention 2) TA=+55°C 3) 10 years
-40-30-20-100 102030405060708090100110120
T emp erature [°C]
0.1
1
10
100
1000
10000
100000
Retention time [Years]
1
ST6208C/ST6209C/ST6210C/ST6220C
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10.7 EMC CHARACTERIS TI CS
Sus ceptibility tests are performed on a sample ba-
sis during product charact erization.
10.7.1 Fun ctional EMS
(Electro Magnetic Susceptibility)
Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnet ic events
until a f ailure occurs (indicated by the LEDs).
■ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of t he device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
■FTB: A Burst of Fast Transi ent voltage (positive
and negative) is applied to VDD and VSS through
a 100pF capacit or, until a functional disturbance
occurs. This test conform s with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed.
Notes:
1. Data based on characterization results, not tested in production.
2. The suggeste d 10 µF an d 0.1 µF decoupling capa citors on the power sup ply lines are propos ed as a good pri ce vs.
EMC performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC rec-
ommendations are given in other sections (I/Os, RESET, OSCx pin characteristics).
Figure 56. EMC Recommen ded Star Network Power S up ply Con nection 2)
Symbol Parameter Conditions Neg 1) Pos 1) Unit
VFESD Voltage limits to be applied on any I/O pin
to induce a functional disturbance VDD=5V, TA=+25°C, fOSC=8MHz
conforms to IEC 1000-4-2 -2 2
kV
VFFTB
Fast transient voltage burst limits to be ap-
plied through 100pF on VDD and VDD pins
to induce a functional disturbance
VDD=5V, TA=+25°C, fOSC=8MHz
conforms to IEC 1000-4-4 -2.5 3
VDD
VSS
0.1 µF10 µF
VDD ST62XX
POWER
SUPPLY
SOURCE
ST6
DIGITAL NOISE
FILTERING
(close to the MCU)
1
ST6208C/ST6209C/ST6210C/ST6220C
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EMC CHARACTERISTICS (Cont’d)
10.7.2 Absolute Electrical Sensi tivity
Based on th ree different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its per formance in
terms of electrical sensitivity. For more details, re-
fer to the AN1181 appli cation note.
10.7.2.1 Electro-Static Dischar ge (ESD)
Electro-Static Discharges (3 positive then 3 nega-
tive pulses separat ed by 1 second ) are applied t o
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms t o the JES D22-A114A/ A115A standard.
Se e Figure 57 and the following test sequences.
Human Body Mode l Test Sequence
– CL i s loaded through S1 by the HV pulse gener-
ator.
– S1 switches position from generator to R.
– A discharge from CL through R (body resistance)
to the ST6 occurs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST6 is not left in
charge state. S2 mus t be opened at least 10ms
prior to the delivery of the nex t pulse.
Machine Model Test Sequence
– CL is loaded through S1 by the HV pulse gene r-
ator.
– S 1 switches position f rom generator to ST6.
– A discharge from CL to t he ST6 occ urs.
– S2 must be closed 10 to 100ms after the pulse
delivery period to ensure the ST6 is not left in
charge state. S2 mus t be opened at least 10ms
prior to the delivery of the nex t pulse.
– R (machine resistance), in series with S2, en-
sures a slow discharge of the ST6.
Absolute Maximum Ratings
Notes:
1. Data based on characterization results, not tested in production.
Figure 57. Typical Equivalent ESD Circuits
Symbol Ratings Conditions Maximum value 1) Unit
VESD(HBM) Electro-static discharge voltage
(Human Body Model) TA=+25°C 2000 V
VESD(MM) Electro-static discharge voltage
(Machine Model) TA=+25°C 200
ST6 S2
R=1500Ω
S1
HIGH VOLTAGE CL=100pF
PULSE
GENERATOR ST6
S2
HIGH VOLTAGE
CL=200pF
PULSE
GENERATOR
R=10k~10MΩ
S1
HUMAN BODY MODEL MACHINE MODEL
1
ST6208C/ST6209C/ST6210C/ST6220C
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EMC CHARACTERISTICS (Cont’d)
10.7.2.2 Static and Dynamic Latch-U p
■LU: 3 complementary static tests are required
on 10 parts t o asses s t he l atch-up performance.
A supply overvoltage (applied to each power
sup ply pin), a current inje ction (appli ed to eac h
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on eac h sample. This test confo rm s to the EIA/
JESD 78 I C latch-up standard. For more details,
refer t o the AN1181 appli cation note.
■DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 58. For
more details, refer to the AN1181 application
note.
Electrical Sensi tivities
Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.
Figu re 58. S imp lifie d D iagram of t he ESD Generato r for DLU
Symbol Parameter Conditions Class 1)
LU S tatic latch- up class TA=+25°C
TA=+85°C A
A
DLU Dynamic latch-up class VDD=5V, fOSC=4MHz, TA=+25°C A
RCH=50MΩRD=330Ω
CS=150pF
ESD
HV RELAY
DISCHARGE TIP
DISCHARGE
RETURN CONNECTION
GENERATOR 2)
ST6
VDD
VSS
1
ST6208C/ST6209C/ST6210C/ST6220C
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EMC CHARACTERISTICS (Cont’d)
10.7.3 ESD Pin Protecti on Strateg y
To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradat ion or destruction of the circuit el -
ements. The stress g enerally affec ts the circuit el-
ements which are conn ected to the pads bu t ca n
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
te cte d must not recei ve e xce ssive curren t, voltage
or heating with in their st ructure.
An ESD network c ombines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pi ns subjected
to ESD stress. Two critical ESD stress cases are
presented in F igure 59 and Figure 60 for st and ard
pins.
Stand ard Pin Pro tection
To protect the output structure the following ele-
ment s are added:
– A diode to VDD (3a) and a diode from VSS (3b)
– A protection device bet ween VDD and V SS (4)
To protect the input structure the following ele-
ment s are added:
– A resistor in series with t he pad (1)
– A diode to VDD (2a) and a diode from VSS (2b)
– A protection device bet ween VDD and V SS (4)
Figure 59. Positi ve Stress on a Standard Pad vs. VSS
Figure 60. Negative Stress on a Standard Pad vs. VDD
IN
VDD
VSS
(1)
(2a)
(2b)
(4)
OUT
VDD
VSS
(3a)
(3b)
Main path
Path to avoid
IN
VDD
VSS
(1)
(2a)
(2b)
(4)
OUT
VDD
VSS
(3a)
(3b)
Main path
1
ST6208C/ST6209C/ST6210C/ST6220C
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10.8 I/O PORT P IN CHARACTERISTICS
10.8.1 Genera l Characteri stics
Subject to general operati ng conditions for VDD, fOSC, and TA unless otherwis e specified.
Figure 61. Typical RPU vs. VDD with VIN = VSS
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The RPU pull-up equiva lent resistor is based on a resisti ve t ransistor. This data is based on charac terization resu lts,
not tested in production.
5. Data based on characterization results, not tested in production.
6. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.
Figure 62. Two typical Applications with unused I/O Pin
Symbol Parameter Conditions Min Typ 1) Max Unit
VIL Input low level voltage 2) 0.3xVDD V
VIH Input high level voltage 2) 0.7xVDD
Vhys Schmitt trigger voltage hysteresis 3) VDD=5V 200 400 mV
VDD=3.3V 200 400
ILInput leakage current VSS≤VIN≤VDD
(no pull-up configured) 0.1 1 µA
RPU Weak pull-up equivalent resistor 4) VIN=VSS VDD=5V 40 110 350 kΩ
VDD=3.3V 80 230 700
CIN I/O input pin capacitance 5 10 pF
COUT I/O output pin capacitance 5 10 pF
tf(IO)out Output high to low level fall time 5) CL=50pF
Between 10% and 90% 30 ns
tr(IO)out Output low to high level rise time 5) 35
tw(IT)in External interrupt pulse time 6) 1t
CPU
3456
VDD [V]
50
100
150
200
250
300
350
Rpu [Khom]
Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
10kΩUNUSED I/O PORT
ST62XX
10kΩUNUSED I/O PORT
ST62XX
VDD
1
ST6208C/ST6209C/ST6210C/ST6220C
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I/O PORT P IN CHARACTERISTICS (Cont’d)
10.8.2 Output Driving Curren t
Subject to general operati ng conditions for VDD, fOSC, and TA unless otherwis e specified.
Notes:
1. The IIO current sunk must always respect the absolute maximum rating specified in Section 10.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
2. The IIO current s ource mus t alwa ys res pect the a bsolu te ma ximum rati ng sp ecifie d in Sectio n 10.2 .2 an d the sum of
IIO (I/O ports and control pins) must not exceed IVDD. True open drain I/O pins does not have VOH.
Figure 63. Typical VOL at V DD = 5V (standard) Figure 64. Typical VOL at VDD = 5V (high-sink)
Symbol Parameter Conditions Min Max Unit
VOL 1)
Output low level voltage for a standard I/O pin
(see Figure 63 and Figure 66)
VDD=5V
IIO=+10µA, TA≤125°C 0.1
V
IIO=+3 mA, TA≤125°C 0.8
IIO=+5 mA, TA≤85°C 0.8
IIO=+10mA, TA≤85°C 1.2
Output low level voltage for a high sink I/O pin
(see Figure 64 and Figure 67)
IIO=+10µA, TA≤125°C 0.1
IIO=+7 mA, TA≤125°C 0.8
IIO=+10mA, TA≤85°C 0.8
IIO=+15mA, TA≤125°C 1.3
IIO=+20mA, TA≤85°C 1.3
IIO=+30mA, TA≤85°C 2
VOH 2) Output high level voltage for an I/O pin
(see Figure 65 and Figure 68)
IIO=-10µA, TA≤125°C VDD-0.1
IIO=-3mA, TA≤125°C VDD-1.5
IIO=-5mA, TA≤85°C VDD-1.5
0246810
Iio [mA]
0
200
400
600
800
1000
Vol [mV] at Vdd=5V
Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
048121620
Iio [mA]
0
0.2
0.4
0.6
0.8
1
Vol [V] at Vdd=5V
Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
1
ST6208C/ST6209C/ST6210C/ST6220C
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I/O PORT P IN CHARACTERISTICS (Cont’d)
Figure 65. Typical VOH at V DD = 5V
Figure 66. Typical VOL vs VDD (standard I/Os)
Figure 67. Typical VOL vs VDD (high-sink I/Os)
-8 -6 -4 -2 0
Iio [mA]
3.5
4
4.5
5
Voh [V] at Vdd=5V
Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
3456
VDD [V]
150
200
250
300
350
Vol [mV] at Iio=2mA Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
3456
VDD [V]
300
400
500
600
700
Vol [mV] at Iio=5mA Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
3456
VDD [V]
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
Vol [V] at Iio=8mA Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
3456
VDD [V]
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Vol [V] at Iio=20mA
Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
1
ST6208C/ST6209C/ST6210C/ST6220C
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I/O PORT P IN CHARACTERISTICS (Cont’d)
Figure 68. Typical VOH vs V DD
3456
VDD [V]
2
3
4
5
6
Voh [V] at Iio=-2mA
Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
3456
VDD [V]
1
2
3
4
5
6
Voh [V] at Iio=-5mA
Ta=-40°C
Ta=25°C
Ta=95°C
Ta=125°C
1
ST6208C/ST6209C/ST6210C/ST6220C
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10.9 CONTROL PIN CHARACTERISTICS
10.9.1 Asynchronous RESET Pin
Subject to general operati ng conditions for VDD, fOSC, and TA unless otherwis e specified.
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The R ON pull-up equ ivalen t res istor is ba sed on a resi stive trans istor. This data is b ased on chara cteriz ation resu lts,
not tested in production.
5. All short pulse applied on RESET pin with a duration below th(RSTL)in can be ignored.
6. The reset network protects the device against parasitic resets, especially in a noisy environment.
7. The output of the external reset circuit must have an open-drain output to drive the ST6 reset pad. Otherwise the device
can be damaged when the ST6 generates an internal reset (LVD or watchdog).
Figure 69. Typical RON vs VDD with VIN=VSS
Symbol Parameter Conditions Min Typ 1) Max Unit
VIL Input low level voltage 2) 0.3xVDD V
VIH Input high level voltage 2) 0.7xVDD
Vhys Schmitt trigger voltage hysteresis 3) 200 400 mV
RON Weak pull-up equivalent resistor 4) VIN=VSS VDD=5V 150 350 900 kΩ
VDD=3.3V 300 730 1900
RESD ESD resistor protection VIN=VSS VDD=5V 2.8 kΩ
VDD=3.3V
tw(RSTL)out Generated reset pulse duration External pin or
internal reset sources tCPU
µs
th(RSTL)in External reset pulse hold time 5) µs
tg(RSTL)in Filtered glitch duration 6) ns
3456
VDD [V]
100
200
300
400
500
600
700
800
900
1000
Ron [Kohm]
Ta=-40°C
Ta=25°C Ta=95°C
Ta=125°C
1
ST6208C/ST6209C/ST6210C/ST6220C
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CONTROL PIN CHARACTERI STICS (Cont’d)
Fig ur e 70. T yp ic a l App lication with RESET pin 8)
10.9.2 NMI Pin
Subject to general operati ng conditions for VDD, fOSC, and TA unless otherwis e specified.
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The Rpull-up equivalent resistor is b ased on a resistive tra nsistor. Th is data is ba sed on cha racterizatio n results, n ot
tested in production.
Figure 71. Typical Rpull-up vs. VDD with VIN=VSS
0.1µF
VDD
0.1µF
VDD
4.7kΩ
EXTERNAL
RESET
CIRCUIT 7)
OPTIONAL
fINT
COUNTER
RESET
WATCHDOG RESET
LVD RESET
INTERNAL
RESET
RESD1)
VDD
RPU STOP MO DE
2048 external clock cycles
Symbol Parameter Conditions Min Typ 1) Max Unit
VIL Input low level voltage 2) 0.3xVDD V
VIH Input high level voltage 2) 0.7xVDD
Vhys Schmitt trigger voltage hysteresis 3) 200 400 mV
Rpull-up Weak pull-up equivalent resistor 4) VIN=VSS VDD=5V 40 100 350 kΩ
VDD=3.3V 80 200 700
3456
VDD [V]
50
100
150
200
250
300
Rpull-up [ Kohm]
Ta=-40°C
Ta=25°C Ta=95°C
Ta=125°C
1
ST6208C/ST6209C/ST6210C/ST6220C
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CONTROL PIN CHARACTERI STICS (Cont’d)
10.10 TIM E R PERIPHERAL CHARACTERISTICS
Subject to general operating conditions for VDD,
fOSC, and TA unless otherwise specified. Refer to I/O port characteristics for more detai ls on
the input/output alternate function characteristics
(TIMER).
10. 10.1 Wa tc hdog Tim er
10.10.2 8-Bit Ti mer
Symbol Parameter Conditions Min Typ Max Unit
tw(WDG) Watchdog time-out duration
3,072 196,608 tINT
fCPU=4MHz 0.768 49.152 ms
fCPU=8MHz 0.384 24.576 ms
Symbol Parameter Conditions Min Typ Max Unit
fEXT Timer external clock frequency 0 fINT/4 MHz
twPulse width at TIMER pin VDD>4.5V 125 ns
VDD=3V 1 µs
1
ST6208C/ST6209C/ST6210C/ST6220C
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10.11 8-BIT ADC CHARACTERISTICS
Subject to general operati ng conditions for VDD, fOSC, and TA unless otherwis e specified.
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.
2. The ADC refers to VDD and VSS.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data
based on characterization results, not tested in production.
4. As a stabilization time for the AD converter is required, the first conversion after the enable can be wrong.
Figure 72. Typical Application with ADC
Note: ADC not present on some devices. See device summary on page 1.
Symbol Parameter Conditions Min Typ 1) Max Unit
fOSC Clock frequency 1.2 fOSC MHz
VAIN Conversion range voltage 2) VSS VDD V
RAIN External input resistor 10 3) kΩ
tADC Total conve rtion time fOSC=8MHz
fOSC=4MHz 70
140 µs
tSTAB Stabilization time 4) 24t
CPU
fOSC=8MHz 3.25 6.5 µs
ADIAnalog input current during conver-
sion 1.0 µA
ACIN Analog input capacitance 2 5 pF
AINx
ST62XX
VAIN
RAIN
10pF ADC
10MΩ
r≈150Ω
1
ST6208C/ST6209C/ST6210C/ST6220C
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8-BIT ADC CHARACTERI STICS (Cont’d)
ADC Accuracy
Notes:
1. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 1mA (assuming that the impedance of the analog voltage
is lower than the specified limits).
- Pure digital pins must have a negative injection less than 1mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
2. Data based on characterization results over the whole temperature range, monitored in production.
Figure 73. ADC Accuracy Characteristics
Note: ADC not present on some devices. See device summary on page 1.
Symbol Parameter Conditions Min Typ. Max Unit
|ET| Total unadjusted error 1)
VDD=5V 2)
fOSC=8MHz
1.2 ±2, fosc>1.2MHz
±4, fosc>32KHz
LSB
EOOffset error 1) 0.72
EGGain Error 1) -0.31
|ED| Differential linearity error 1) 0.54
|EL| Integral linearity error 1)
EO
EG
1LSB
IDEAL
1LSBIDEAL VDDA VSSA
–
256
-----------------------------------------=
Vin (LSBIDEAL)
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3 ) E nd point correl at ion line
ET=Total Unadjusted Error: maximum deviation
between th e actual and the ideal transfer curves.
EO=Offset Er ror: deviation bet ween the f i rst actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the la st actual one.
ED=Differential Line arity E rror: maximum deviation
between ac tual steps and the i deal one .
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
Digital Resu lt ADCDR
255
254
253
5
4
3
2
1
0
7
6
1234567 253 254 255 256
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
1
ST6208C/ST6209C/ST6210C/ST6220C
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11 G ENERAL INFORM ATI ON
11.1 PACKAGE MECHANICAL DATA
Figure 74. 20-Pin Plastic Dual In-Line Packag e, 300-mil Width
Figure 75. 20-Pin Ceramic Side-Br azed Dual In-Line Package
Dim. mm inches
Min Typ Max Min Typ Max
A5.33 0.210
A1 0.38 0.015
A2 2.92 3.30 4.95 0.115 0.130 0.195
b0.36 0.46 0.56 0.014 0.018 0.022
b2 1.14 1.52 1.78 0.045 0.060 0.070
c0.20 0.25 0.36 0.008 0.010 0.014
D24.89 26.16 26.92 0.980 1.030 1.060
D1 0.13 0.005
e2.54 0.100
eB 10.92 0.430
E1 6.10 6.35 7.11 0.240 0.250 0.280
L2.92 3.30 3.81 0.115 0.130 0.150
Number of Pins
N20
E1
D
D1 be
A
A1 L
A2
c
eB
11
10
1
20
b2
Dim. mm inches
Min Typ Max Min Typ Max
A3.63 0.143
A1 0.38 0.015
B3.56 0.46 0.56 0.140 0.018 0.022
B1 1.14 12.70 1.78 0.045 0.500 0.070
C0.20 0.25 0.36 0.008 0.010 0.014
D24.89 25.40 25.91 0.980 1.000 1.020
D1 22.86 0.900
E1 6.99 7.49 8.00 0.275 0.295 0.315
e2.54 0.100
G6.35 6.60 6.86 0.250 0.260 0.270
G1 9.47 9.73 9.98 0.373 0.383 0.393
G2 1.14 0.045
L2.92 3.30 3.81 0.115 0.130 0.150
S12.70 0.500
Ø4.22 0.166
Number of Pins
N20
CDIP20W
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PACKAGE MECHANICAL DATA (Cont’d)
Figure 76. 20-Pin Plastic Small Outline Package, 300-mil Wi dth
Figure 77. 20-Pin Plastic Shri nk Small Outline Package
Dim. mm inches
Min Typ Max Min Typ Max
A2.35 2.65 0.093 0.104
A1 0.10 0.30 0.004 0.012
B0.33 0.51 0.013 0.020
C0.23 0.32 0.009 0.013
D12.60 13.00 0.496 0.512
E7.40 7.60 0.291 0.299
e1.27 0.050
H10.00 10.65 0.394 0.419
h0.25 0.75 0.010 0.030
α0° 8° 0° 8°
L0.40 1.27 0.016 0.050
Number of Pins
N20
EH
A
A1
Be
D
c
h x 45×
L
a
Dim. mm inches
Min Typ Max Min Typ Max
A2.00 0.079
A1 0.05 0.002
A2 1.65 1.75 1.85 0.065 0.069 0.073
b0.22 0.38 0.009 0.015
c0.09 0.25 0.004 0.010
D6.90 7.20 7.50 0.272 0.283 0.295
E7.40 7.80 8.20 0.291 0.307 0.323
E1 5.00 5.30 5.60 0.197 0.209 0.220
e0.65 0.026
θ0° 4° 8° 0° 4° 8°
L0.55 0.75 0.95 0.022 0.030 0.037
Number of Pins
N20
c
L
h
D
A
A1
e
b
A2
E
E1
1
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11.2 THERMAL CHARACTERIS TI CS
Notes:
1. The power dissipation is obtained from the formula PD = PINT + PPORT where PINT is the chip internal power (IDDxVDD)
and PPORT is the port power dissipation determined by the user.
2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA.
Symbol Ratings Value Unit
RthJA
Package thermal resistance (junction to ambient)
DIP20
SO20
SSOP20
60
80
115
°C/W
PDPower dissipation 1) 500 mW
TJmax Maximum junction temperature 2) 150 °C
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11.3 SOLDERING AND GLUEABILITY INFORMATION
Recommended soldering information given only
as des ign guideli nes in Fi gure 78 and Fi gure 79.Recommended gl ue for SMD plastic packages:
■Heraeus: PD945, PD955
■Loctite: 3615, 3298
Figure 78. Recom mend ed Wa ve Sold ering Profil e (with 37% Sn and 63% Pb)
Figu re 79. Re co m m e nd ed R ef l ow Sol de r ing Ov en Profile (MI D JEDEC)
250
200
150
100
50
040 80 120 160Time [sec]
Temp. [°C]
20 60 100 140
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
5 sec COOLING PHASE
(ROOM TEMPERATURE)
PREHEATING
80°C
PHASE
SOLDERING
PHASE
250
200
150
100
50
0100 200 300 400 Time [sec]
Temp. [°C]
ramp up
2°C/sec fo r 50sec
9 0 sec at 125 °C 150 sec above 183°C
ramp down natural
2°C/sec max
Tmax=220+/-5°C
for 2 5 sec
1
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11.4 PACKAGE/SOCKET FOOTPRINT PROP OSAL
Table 23. Su gg ested List of DIP20 Socket Ty pes
Table 24. Su gg ested List of SO20 So cket Types
Table 25. Su ggested List of SSOP20 Socket Types
Package / Probe Adaptor / Socket Reference Same
Footprint So cket Type
DIP20 TEXTOOL 220-33-42 X Textool
Package / Probe Adaptor / Socket Reference Same
Footprint So cket Type
SO20 ENPLAS OTS-20-1.27-04 Open Top
YAMAICHI IC51-0202-714 Clamshell
EMU PROBE Adapter from SO20 to DIP20 footprint
(delivered with emulator) X SMD to DIP
Programming
Adapter Logical Systems PA20SO1-08H-6 X Open Top
Package / Probe Adaptor / Socket Reference Same
Footprint So cket Type
SSOP20 ENPLAS OTS-20-0.65-01 X Open Top
Programming
Adapter Logical Systems PA20SS-OT-6 X Open Top
1
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11.5 ORDERING INFORMATIO N
The following s ection deals with the proce dure for
transfer of customer codes to STMicroelectronics and also details the ST6 factory coded device
type.
Figu re 80 . ST6 Factory C od e d De vi c e Types
ROM code
Temperature code:
1: Standard 0 to +70 °C
3: Automotive -40 to +125 °C
6: Industrial -40 to +85 °C
Package type:
B: Plastic DIP
D: Ceramic DIP
M: Plastic SOP
N: Plastic SSOP
T: Plastic TQFP
Revision index:
B,C: Product Definition change
L: Low Voltage Device
ST6 Sub family
Version Code:
No char: ROM
E: EPROM
P: FASTROM
T: OTP
Family
ST62T20CB6/CCC
1
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11.6 TRANSFER OF CUSTOMER CODE
Customer code is made up of the ROM contents
and the list of the selected FASTROM options.
The ROM contents are to be sent on diskette, or
by electronic means, with the hexadecimal file
generated by the development tool. All unused
bytes must be set to FFh.
The selected options are communicated to
STMicroelectronics using the correctly filled OP-
TION LIST appended. See page 97.
The STMicroelectronics Sales Organization wi ll be
pleased to provide detailed information on con-
tractual points.
Listing Generation and Verification. When
STMicroelect ronics rec eives the user’s ROM con-
tents, a computer listing is generated from it. This
listing re fers exa ctly to the ROM contents and op-
tions which will be used to produce the specified
MCU. The listing is then returne d to the cust omer
who must thoroughly check, complete, sign and
return it to STMicroelectronics. The signed listing
forms a part of the contractual agreement for the
production of the specific customer MCU .
11.6.1 FASTROM version
The ST62P08C/P09C/P10C and P20C are the
Factory Advanced Service Technique ROM (FAS-
TROM) versions of ST62T08C, T09C, T10C and
T20C OTP devices.
They offer the same functionali ty as OTP devic es,
but they do not have to be programmed by the
customer. The customer code must be sent to
STMicroelectronics in the same way as for ROM
devices. Th e FASTR OM option list has the same
options as defined in the programmable option
byte of the OTP version. It also of fers an identif ier
option. If this option is enabled, each FASTROM
device is programmed with a unique 5-byte
number which is mapped at addresses 0F9Bh-
0F9Fh. The user must therefore leave t hese bytes
blanked.
The identification num ber is st ructured as follows:
with T0, T1, T2, T3 = time i n seconds si nce 01/01/
1970 and Test ID = Tester Identifier.
0F9Bh T0
0F9Ch T1
0F9Dh T2
0F9Eh T3
0F9Fh Test ID
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TRANSFER OF CUSTOMER CODE (Cont’d)
ST6208C/09C/10C/20C/P08C/P09C/P10C/P20C MICROCONTROLLER OPTION LIST
Customer: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Address: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phone: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STMicroelectronics references:
Device: [ ] ST6208C (1 KB) [ ] ST6209C (1 KB)
[ ] ST6210C (2 KB) [ ] ST6220C (4 KB)
[ ] ST62P08C (1 KB) [ ] ST62P09C (1 KB)
[ ] ST62P10C (2 KB) [ ] ST62P20C (4 KB)
Package: [ ] Dual in Line Plastic
[ ] Small Outline Plastic with conditioning
[ ] Shrink Small Outline Plastic with conditioning
Conditioning option: [ ] Standard (Tube) [ ] Tape & Reel
Temperature Range: [ ] 0°C to + 70°C [ ] - 40°C to + 85°C
[ ] - 40°C to + 125°C
Marking: [ ] Standard marking
[ ] Special marking (ROM only):
PDIP20 (10 char. max): _ _ _ _ _ _ _ _ _ _
SO20 (8 char. max): _ _ _ _ _ _ _ _
SSOP20 (11 char. max): _ _ _ _ _ _ _ _ _ _ _
Authorized characters are letters, digits, '.', '-', '/' and spaces only.
Oscillator Safeguard: [ ] Enabled [ ] Disabled
Watchdog Selection: [ ] Software Activation [ ] Hardware Activation
Timer pull-up: [ ] Enabled [ ] Disabled
NMI pull-up: [ ] Enabled [ ] Disabled
Oscillator Selection: [ ] Quartz crystal / Ceramic resonator
[ ] RC network
Readout Prote ction: FASTR OM:
[ ] Enabled [ ] Disabled
ROM: [ ] Enabled:
[ ] Fuse is blown by STMicroelectronics
[ ] Fuse can be blown by the customer
[ ] Disabled
Low Voltage Detector: [ ] Enabled [ ] Disabled
External STOP Mode Control: [ ] Enabled [ ] Disabled
Identifier (FASTROM only): [ ] Enabled [ ] Disabled
Comments:
Oscillator Frequency in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Date: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Signature: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
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11.6.2 ROM VERSION
The ST6208C, 09C, 10C and 20C are mask pro-
grammed ROM version of ST62T08C, T09C,
T10C and T20C OTP devices.
They offer the same functionality as OTP devices ,
selecting as ROM options the options defined in
the programm able option byte of t he OTP version.
Figure 81. Programming Circui t
Note: ZPD15 is used for overvoltage protection
ROM Readout Protection. If t he RO M READOUT
PROTECTION option is selected, a protection
fuse can be blown to prevent any access to the
program memory co ntent.
In case the user wants to blow this fuse, high volt-
age must be applied on the VPP pin.
Figure 82. Progra m min g wave form
VR02003
VPP
5V
100nF
4.7µF
PROTECT
100nF
VDD
VSS
ZPD15
15V
14V
100 µs max
0.5s min
VPP
15
14V typ
10
5
VPP
400mA
4mA typ
VR02001
max
150 µs typ
t
1
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12 DEVELOPMENT TOOLS
STMicroelectronics offers a range of hardware
and software development tools for t he ST6 mi cro-
controller family. Full details of tools available for
the ST6 from third party manufacturers can be ob-
tain from the STMicroele ctronics Internet site:
➟ http://mcu.st.com .
Table 26. D edicated T hird Parties Developmen t Tools
Note 1: F or latest information on third party tools, please visit our Internet site: ➟ http://mcu.st.com.
Third Party 1) Designation ST Sales Type Web site address
ACTUM ST-REALIZER II: Graphical Schematic
based Development available from
STMicroelectronics. STREALIZER-II http://www.actum.com/
CEIBO Low cost emulator available from CEI-
BO. http://www.ceibo.com/
RAISONANCE
This tool includes in the same environ-
ment: an assembler, linker, C compiler,
debugger and simulator. The assembler
package (plus limited C compiler) is free
and can be downloaded from raisonance
web site. The full version is available
both from STMicroelectronics and Raiso-
nance.
ST6RAIS-SWC/
PC http://www.raisonance.com/
SOFTEC
High end emulator available from
SOFTEC. http://www.softecmicro.com/
Gang programmer available from
SOFTEC.
ADVANCED EQUIPMENT
Single and gang programmers
http://www.aec.com.tw/
ADVANCED TRANSDATA http://www.adv-transdata.com/
BP MICROSYSTEMS http://www.bpmicro.com/
DATA I/O http://www.data-io.com/
DATAMAN http://www.dataman.com/
EE TOOLS http://www.eetools.com/
ELNEC http://www.elnec.com/
HI-LO SYSTEMS http://www.hilosystems.com.tw/
ICE TECHNOLOGY http://www.icetech.com/
LEAP http://www.leap.com.tw/
LLOYD RESEARCH http://www.lloyd-research.com/
LOGICAL DEVI CES http://www.chipprogram-
mers.com/
MQP ELECTRON ICS http://www.mqp.com/
NEEDH AMS
ELECTRONICS http://www.needhams.com/
STAG PROGRAMMERS http://www.stag.co.uk/
SYSTEM GENERAL CORP http://www.sg.com.tw
TRIBAL MICROSYSTEMS http://www.tribalmicro.com/
XELTEK http://www.xeltek.com/
1
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DE VELOPMENT TOOLS (Cont’d)
STMicroelectronics Tools
Four types of development t ool are offered by ST, all of them c onnect to a PC via a parallel or serial port:
see Table 27 and Ta ble 28 for more details.
Table 27. ST Micro ele ctron ics Too l Features
Table 28. D edicated S TMi croe lectro nics Develop m ent Tool s
Emulation Type Programming Capability Software Included
ST6 Starter Kit Device simulation (limited
emulation as interrupts are
not supported) Yes (DIP packages only) MCU CD ROM with:
– Rkit-ST6 from Raisonance
– ST6 Assembly toolchain
– WGDB6 powerful Source Level
Debugger for Win 3.1, Win 95
and NT
– Various software demo ver-
sions.
– Windows Programming Tools
for Win 3.1, Win 95 and NT
ST6 HDS2 Emulator In-circuit powerful emula-
tion features including
trace/ logic analyzer No
ST6 EPROM
Programmer Board No Yes
Supported Products ST6 Starter Kit ST6 HDS2 Emulator ST6 Programming Board
ST6208C, ST6209C, ST6210C
and ST6220C ST622XC-KIT
Complete:
ST62GP-EMU2
Dedication board:
ST62GP-DBE
ST62E2XC-EPB
1
ST6208C/ST6209C/ST6210C/ST6220C
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13 ST6 APPLICATION NOTES
IDENTIFICATION DESCRIPTION
MOTOR CONTROL
AN392 MICROCONTROLLER AND TRIACS ON THE 110/240V MAINS
AN414 CONTROLLING A BRUSH DC MOTOR WITH AN ST6265 MCU
AN416 SENSORLESS MOTOR DRIVE WITH THE ST62 MCU + TRIAC
AN422 IMPROVES UNIVERSAL MOTOR DRIVE
AN863 IMPROVED SENSORLESS CONTROL WITH THE ST62 MCU FOR UNIVERSAL MOTOR
BATTERY MANAGEMENT
AN417 FROM NICD TO NIMH FAST BATTERY CHARGING
AN433 ULTRA FAST BATTERY CHARGER USING ST6210 MICROCONTROLLER
AN859 AN INTELLIGENT ONE HOUR MULTICHARGER FOR Li-Ion, NiMH and NiCd BATTERIES
HOME APPLIANCE
AN674 MICROCONTROLLERS IN HOME APPLIANCES: A SOFT REVOLUTION
AN885 ST62 MICROCONTROLLERS DRIVE HOME APPLIANCE MOTOR TECHNOLOGY
GRAPHICAL DESIGN
AN676 BATTERY CHARGER USING THE ST6-REALIZER
AN677 PAINLESS MICROCONTROLLER CODE BY GRAPHICAL APPLICATION DESCRIPTION
AN839 ANALOG MULTIPLE KEY DECODING USING THE ST6-REALIZER
AN840 CODED LOCK USING THE ST6-REALIZER
AN841 A CLOCK DESIGN USING THE ST6-REALIZER
AN842 7 SEGMENT DISPLAY DRIVE USING THE ST6-REALIZER
COST REDUCTION
AN431 USING ST6 ANALOG INPUTS FOR MULTIPLE KEY DECODING
AN594 DIRECT SOFTWARE LCD DRIVE WITH ST621X AND ST626X
AN672 OPTIMIZING THE ST6 A/D CONVERTER ACCURACY
AN673 REDUCING CURRENT CONSUMPTION AT 32KHZ WITH ST62
DESIGN IMPROVEMENTS
AN420 EXPANDING A/D RESOLUTION OF THE ST6 A/D CONVERTER
AN432 USING ST62XX I/O PORTS SAFELY
AN434 MOVEMENT DETECTOR CONCEPTS FOR NOISY ENVIRONMENTS
AN435 DESIGNING WITH MICROCONTROLLERS IN NOISY ENVIRONMENTS
AN669 SIMPLE RESET CIRCUITS FOR THE ST6
AN670 OSCILLATOR SELECTION FOR ST62
AN671 PREVENTION OF DATA CORRUPTION IN ST6 ON-CHIP EEPROM
AN911 ST6 MICRO IS EMC CHAMPION
AN975 UPGRADING FROM ST625X/6XB TO ST625X/6XC
AN1015 SOFTWARE TECHNIQUES FOR IMPROVING ST6 EMC PERFORMANCE
PERIPHERAL OPERATIONS
AN590 PWM GENERATION WITH ST62 AUTO-RELOAD TIMER
AN591 INPUT CAPTURE WITH ST62 AUTO-RELOAD TIMER
AN592 PLL GENERATION USING THE ST62 AUTO-RELOAD TIMER
AN593 ST62 IN-CIRCUIT PROGRAMMING
AN678 LCD DRIVING WITH ST6240
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102/104
AN913 PWM GENERATION WITH ST62 16-BIT AUTO-RELOAD TIMER
AN914 USING ST626X SPI AS UART
AN1016 ST6 USING THE ST623XB/ST628XB UART
AN1050 ST6 INPUT CAPTURE WITH ST62 16-BIT AUTO-RELOAD TIMER
AN1127 USING THE ST62T6XC/5XC SPI IN MASTER MODE
GENERAL
AN683 MCUS - 8/16-BIT MICROCONTROLLERS (MCUS) APPLICATION NOTES ABSTRACTS BY
TOPICS
AN886 SELECTING BETWEEN ROM AND OTP FOR A MICROCONTROLLER
AN887 MAKING IT EASY WITH MICROCONTROLLERS
AN898 EMC GENERAL INFORMATION
AN899 SOLDERING RECOMMENDATIONS AND PACKAGING INFORMATION
AN900 INTRODUCTION TO SEMICONDUCTOR TECHNOLOGY
AN901 EMC GUIDE-LINES FOR MICROCONTROLLER - BASED APPLICATIONS
AN902 QUALITY AND RELIABILITY INFORMATION
AN912 A SIMPLE GUIDE TO DEVELOPMENT TOOLS
AN1181 ELECTROSTATIC DISHARGE SENSITIVITY MEASUREMENT
IDENTIFICATION DESCRIPTION
1
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14 SUMMARY OF CHANGES
Description of the changes betwee n the current release of the specification and the previous one.
15 TO GET MORE I NFO RM ATI ON
To get the latest i nformation on this product please use the STMicroelectr onics web server.
➟ http://mcu.st.com/
Revision Main Changes Date
3.3 Removed references to 32768 clock cycle delay in Section 5 and Section 6
Changed note 2 in Section 10.6.2 on page 76: added text on data retention and program-
mability. Oct ober 03
1
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Notes:
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no r esponsibility for the c onsequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by i m pl i cation or oth erwise unde r any pat ent or paten t rights of STMi croelectronics. Specific ation s mentioned in this p ublicat i on are subject
to change without notice. This publication supersedes and repl aces all information previously supplied. STMicroel ectronics produ ct s are not
authorized for use as c ri tical com pone nt s i n l i f e support d evices or systems wi t hout express wri t ten approval of S T M i croel ectronics.
Th e ST logo is a registered tra dem ark of ST M i croelectronic s.
All o th er names are the property of thei r respec ti ve owners
© 2003 STMi croelect ronic s - Al l ri ghts reserved
STMicr oelectronics GROUP OF COMPANIES
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1
