AT17LV256-10PU - MICROCHIP TECHNOLOGY

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

Features

EE Programmable Serial Memories Designed to Store Configuration Programs

for Field Programmable Gate Arrays (FPGAs)

Supports both 3.3V and 5.0V Operating Voltage Applications

In-System Programmable (ISP) via 2-wire Bus

Simple Interface to SRAM FPGAs

Compatible with the Atmel® AT6000, AT40K and AT94K Devices, Altera®

FLEX®, APEX™ Devices, ORCA®, Xilinx® XC3000, XC4000, XC5200,

Spartan®, Virtex® FPGAs

Cascadable Read-back to Support Additional Configurations or Higher-density

Arrays

Very Low-power CMOS EEPROM Process

Programmable Reset Polarity

Available in 6mm x 6mm x 1mm 8-lead LAP (Pin-compatible with 8-lead SOIC

Package), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC and

44-lead TQFP Packages

Emulation of the Atmel AT24CXXX Serial EEPROMs

Low-power Standby Mode

High-reliability

Endurance: 100,000 Write Cycles

Data Retention: 90 Years for Industrial Parts (at 85C)

Green (Pb/Halide-free/RoHS Compliant) Package Options Available

Description

The AT17LV FPGA Configuration EEPROMs (Configurators) provide an easy-to-

use, cost-effective configuration memory solution for Field Programmable Gate

Arrays. The AT17LV devices are packaged in the 8-lead LAP, 8-lead PDIP, 8-lead

SOIC, 20-lead PLCC, 20-lead SOIC and 44-lead TQFP options(Table 1). The

AT17LV Configurators use a simple serial-access procedure to configure one or

more FPGA devices. The user can select the polarity of the reset function during

programming. These devices also support a write protection mechanism within its

programming mode.

65,536 x 1-bit(1)

131,072 x 1-bit(1)

262,144 x 1-bit

524,288 x 1-bit

1,048,576 x 1-bit

2,097,152 x 1-bit

4,194,304 x 1-bit

AT17LV65(1), AT17LV128(1), AT17LV256,

AT17LV512, AT17LV010, AT17LV002, AT17LV040

FPGA Configuration EEPROM Memory

3.3V and 5.0V System Support

DATASHEET

Note 1.

AT17LV65 and AT17LV128

are Not Recommended for

New Designs (NRND) and

are Replaced by AT17LV256.

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

The AT17LV configurators can be programmed with industry-standard programmers, the Atmel ATDH2200E

Programming Kit, or the Atmel ATDH2225 ISP Cable.

Table 1. AT17LV Packages

Notes: 1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-lead SOIC package is not

available for the AT17LV512/010/002 devices, it is possible to use an 8-lead LAP package instead.

2. The pinout for the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256 is not pin-for-pin compatible with

the AT17LV512/010/002 devices.

3. Refer to the AT17F datasheet which is available on the Atmel website.

4. The AT17LV65 and AT17LV128 are not recommended for new designs (NRND).

Package AT17LV65/128/256(4) AT17LV512/010 AT17LV002 AT17LV040

8-lead LAP Yes Yes Yes (3)

8-lead PDIP Yes Yes – —

8-lead SOIC Yes Use 8-lead LAP(1) Use 8-lead LAP(1) (3)

20-lead PLCC Yes Yes Yes —

20-lead SOIC Yes(2) —Yes(2) —

44-lead TQFP — — Yes Yes

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

1. Pin Configuration and Descriptions

Table 1-1. Pin Descriptions

Pin Description

DATA Three-state Data Output for Configuration. Open-collector bi-directional pin for

programming.

CLK Clock Input. Used to increment the internal address and bit counter for reading and

programming.

WP1

Write Protect (1). Used to protect portions of memory during programming. Disabled

by default due to internal pull-down resistor. This input pin is not used during FPGA loading

operations. This pin is only available on AT17LV512/010/002 devices.

RESET/OE

RESET (Active Low) / Output Enable (Active High) when SER_EN is High. A Low level on

RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the

data output driver. The logic polarity of this input is programmable as either RESET/OE or

RESET/OE. For most applications, RESET should be programmed active Low. This document

describes the pin as RESET/OE.

Write Protect Input (when CE is Low) during programming only (SER_EN Low). When WP is

Low, the entire memory can be written. When WP is enabled (High), the lowest block of the

memory cannot be written. This pin is only available on the AT17LV65 (NRND),

AT17LV128 (NRND), and the AT17LV256.

WP2

Write Protect (2). Used to protect portions of memory during programming. Disabled

by default due to internal pull-down resistor. This input pin is not used during FPGA loading

operations. This pin is only available on the AT17LV512/010.

Chip Enable Input (Active Low). A Low level (with OE High) allows CLK to increment the

address counter and enables the data output driver. A High level on CE disables both the

address and bit counters and forces the device into a low-power standby mode. Note that this

pin will not enable/disable the device in the Two-Wire Serial Programming mode (SER_EN

Low).

GND Ground. A 0.2μF decoupling capacitor between VCC and GND is recommended.

CEO

Chip Enable Output (Active Low). This output goes Low when the address counter has

reached its maximum value. In a daisy chain of AT17LV devices, the CEO pin of one device

must be connected to the CE input of the next device in the chain. It will stay Low as long as

CE is Low and OE is High. It will then follow CE until OE goes Low; thereafter, CEO will stay

High until the entire EEPROM is read again. This CEO feature is not available on the

AT17LV65 (NRND).

A2 Device Selection Input, A2. This is used to enable (or select) the device during programming

(i.e., when SER_EN is Low). A2 has an internal pull-down resistor.

READY Open Collector Reset State Indicator. Driven Low during power-up reset, released when

power-up is complete. It is recommended to use a 4.7k pull-up resistor when this pin is used.

SER_EN

Serial Enable must be held High during FPGA loading operations. Bringing SER_EN Low

enables the 2-wire Serial Programming Mode. For non-ISP applications, SER_EN should be

tied to VCC.

VCC Power Supply. 3.3V (±10%) and 5.0V (±10%) power supply pin.

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

Table 1-2. Pin Configurations

Notes: 1. The CEO feature is not available on the AT17LV65 (NRND).

2. The AT17LV65 and AT17LV128 are not recommended for new designs.

Name I/O

AT17LV65/128/256(2) AT17LV512/010 AT17LV002 AT17LV040

8-lead

DIP/LAP/

SOIC

20-lead

PLCC

20-lead

SOIC

8-lead

DIP/

LAP

20-lead

PLCC

8-lead

LAP

20-lead

PLCC

20-lead

SOIC

44-lead

TQFP

44-lead

TQFP

DATA I/O 1 2 2 1 2 1 2 1 40 40

CLK I 2 4 4 2 4 2 4 3 43 43

WP1 I – – – – 5 – 5 – 7 –

RESET/OE I 3 6 6 3 6 3 6 8 13 13

WP2 I – – – – 7 – 7 – – –

CE I 4 8 8 4 8 4 8 10 15 15

GND 5 10 10 5 10 5 10 11 18 18

CEO(1) O

6 14 14 6 14 6 14

21 21

A2 I –

READY O – – – – 15 – 15 – 23 23

SER_EN I 7 17 17 7 17 7 17 18 35 35

VCC 8 20 20 8 20 8 20 20 38 38

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

Figure 1-1. Pinouts(1)

Notes: 1. Drawings are not to scale.

2. This pin is only available on the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256.

3. This pin is only available on the AT17LV512/010/002.

4. This pin is not available on the AT17LV65 (NRND).

5. The AT17LV65 and AT17LV128 are not recommended for new designs.

8-lead PDIP

(Top View)

DATA

CLK

(WP(2)) RESET/OE

VCC

SER_EN

CEO (A2)

GND

DATA

CLK

(WP(2)) RESET/OE

VCC

SER_EN

CEO (A2)

GND

8-lead JEDEC SOIC

(Top View)

8-lead LAP

(Top View)

DATA

CLK

(WP(2)) RESET/OE

VCC

SER_EN

CEO (A2)

GND

20-lead PLCC

(Top View)

DATA

VCC

SER_EN

NC (READY(3))

CEO(4) (A2)

CLK

(WP1(3)) NC

(WP1(2)) RESET/OE

(WP2(3)) NC

GND

44-lead TQFP

(Top View)

AT17LV002 Only

CLK

DATA

VCC

SER_EN

RESET/OE

GND

CEO (A2)

READY

(WP1(1)) NC

20-lead SOIC

(Top View)

AT17LV65/128/256 Only(5)

VCC

SER_EN

CEO (A2)

DATA

CLK

RESET/OE

GND

20-lead SOIC

(Top View)

AT17LV002 Only

VCC

SER_EN

CEO(4)

GND

DATA

CLK

RESET/OE

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

2. Block Diagram

Figure 2-1. Block Diagram

Notes: 1. This pin is only available on the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256.

2. This pin is only available on AT17LV512, AT17LV010, and AT17LV002.

3. The CEO feature is not available on the AT17LV65 (NRND).

Power On

Reset

SER_EN

WP1(2)

WP2(2)

CLK READY(2) REST/OE (WP(1))CE CEO(3) (A2) DATA

Programming

Mode Logic

Programming

Data Shift

EEPROM

Cell Matrix

Column Decoder

Row Decoder

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

3. Device Description

The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) interface directly with the FPGA

device control signals. All FPGA devices can control the entire configuration process and retrieve data from the

configuration EEPROM without requiring an external intelligent controller.

The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the DATA output pin and

enable the address counter. When RESET/OE is driven High, the configuration EEPROM resets its address

counter and tri-states its DATA pin. The CE pin also controls the output of the AT17LV configurator. If CE is held

High after the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is

subsequently driven Low, the counter and the DATA output pin are enabled. When RESET/OE is driven High

again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of CE.

When the configurator has driven out all of its data and CEO is driven Low, the device tri-states the DATA pin to

avoid contention with other configurators. Upon power-up, the address counter is automatically reset.

This is the default setting for the device. Since almost all FPGAs use RESET Low and OE High, this document

will describe RESET/OE.

4. FPGA Master Serial Mode Summary

The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The

program is loaded either automatically upon power-up, or on command, depending on the state of the FPGA

mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory.

The AT17LV Serial Configuration EEPROM has been designed for compatibility with the Master Serial mode.

This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Xilinx applications.

5. Control of Configuration

Most connections between the FPGA device and the AT17LV Serial EEPROM are simple and self-explanatory.

The DATA output of the AT17LV configurator drives DIN of the FPGA devices.

The master FPGA CCLK output drives the CLK input of the AT17LV configurator.

The CEO output of any AT17LV configurator drives the CE input of the next configurator in a cascaded

chain of EEPROMs.

SER_EN must be connected to VCC (except during ISP).

The READY(1) pin is available as an open-collector indicator of the device’s reset status; it is driven Low

while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete.

Note: 1. This pin is not available for the AT17LV65 (NRND), AT17LV128 (NRND), and AT17LV256.

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

6. Cascading Serial Configuration EEPROMs

For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configuration memories,

cascaded configurators provide additional memory.

After the last bit from the first configurator is read, the clock signal to the configurator asserts its CEO output

Low and disables its DATA line driver. The second configurator recognizes the Low level on its CE input and

enables its DATA output.

After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE

on each configurator is driven to its active (Low) level.

If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive

(High) level.

The AT17LV65 (NRND) devices do not have the CEO feature to perform cascaded configurations.

7. AT17LV Reset Polarity

The AT17LV configurator allows the user to program the reset polarity as either RESET/OE or RESET/OE. This

feature is supported by industry-standard programmer algorithms.

8. Programming Mode

The programming mode is entered by bringing SER_EN Low. In this mode the chip can be programmed by the

2-wire serial bus. The programming is done at VCC supply only. Programming super voltages are generated

inside the chip.

9. Standby Mode

The AT17LV configurators enter a low-power standby mode whenever CE is asserted High. In this mode, the

AT17LV65 (NRND), AT17LV128 (NRND), or the AT17LV256 configurator consumes less than 50μA of current

at 3.3V (100μA for the AT17LV512/010 and 200μA for the AT17LV002/040). The output remains in a high-

impedance state regardless of the state of the OE input.

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

10. Electrical Specifications

10.1 Absolute Maximum Ratings*

10.2 Operating Conditions

Table 10-1. Operating Conditions

10.3 DC Characteristics

Table 10-2. DC Characteristics for VCC = 3.3V ± 10%

Note: 1. The AT17LV65 and AT17LV128 are not recommended for new designs.

Operating Temperature . . . . . . . . . . . . . . . . .-40C to +85C

Storage Temperature . . . . . . . . . . . . . . . . . .-65C to +150C

Voltage on Any Pin

with Respect to Ground . . . . . . . . . . . . . . -0.1V to VCC +0.5V

Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . -0.5V to +7.0V

Maximum Soldering Temp. (10s @ 1/16 in.) . . . . . . . . 260C

ESD (RZAP = 1.5K, CZAP = 100pF) . . . . . . . . . . . . . . . .2000V

*Notice: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent

damage to the device. This is a stress rating

only and functional operation of the device at

these or any other conditions beyond those

listed under operating conditions is not

implied. Exposure to Absolute Maximum

Rating conditions for extended periods of

time may affect device reliability.

Symbol Description

3.3V 5.0V

UnitsMin Max Min Max

VCC Industrial Supply voltage relative to GND

-40C to +85C3.0 3.6 4.5 5.5 V

Symbol Description

AT17LV65/128/256(1) AT17LV512/010 AT17LV002/40

UnitsMin Max Min Max Min Max

VIH High-level Input Voltage 2.0 VCC 2.0 VCC 2.0 VCC V

VIL Low-level Input Voltage 0 0.8 0 0.8 0 0.8 V

VOH

High-level Output Voltage

(IOH = -2mA) 2.4 2.4 2.4 V

VOL

Low-level Output Voltage

(IOL = +3mA) 0.4 0.4 0.4 V

ICCA Supply Current, Active Mode 5 5 5 mA

Input or Output Leakage Current

(VIN = VCC or GND) -10 10 -10 10 -10 10 μA

ICCS Supply Current, Standby Mode 100 100 150 μA

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

Table 10-3. DC Characteristics for VCC = 5.0V ± 10%

Note: 1. The AT17LV65 and AT17LV128 are not recommended for new designs.

10.4 AC Characteristics

Table 10-4. AC Characteristics for VCC = 3.3V ± 10%

Notes: 1. AC test lead = 50pF.

2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.

3. The AT17LV65 and AT17LV128 are not recommended for new designs.

Symbol Description

AT17LV65/128/256(1) AT17LV512/010 AT17LV002/040

UnitsMin Max Min Max Min Max

VIH High-level Input Voltage 2.0 VCC 2.0 VCC 2.0 VCC V

VIL Low-level Input Voltage 0 0.8 0 0.8 0 0.8 V

VOH

High-level Output Voltage

(IOH = -2mA) 3.60 3.76 3.76 V

VOL

Low-level Output Voltage

(IOL = +3mA) 0.37 0.37 0.37 V

ICCA Supply Current, Active Mode 10 10 10 mA

Input or Output Leakage Current

(VIN = VCC or GND) -10 10 -10 10 -10 10 μA

ICCS Supply Current, Standby Mode 150 200 350 μA

Symbol Description

AT17LV65/128/256(3) AT17LV512/010/002/040

UnitsMin Max Min Max

TOE(1) OE to Data Delay 55 55 ns

TCE(1) CE to Data Delay 60 60 ns

TCAC(1) CLK to Data Delay 80 60 ns

TOH Data Hold from CE, OE, or CLK 0 0 ns

TDF(2) CE or OE to Data Float Delay 55 50 ns

TLC CLK Low Time 25 25 ns

THC CLK High Time 25 25 ns

TSCE

CE Setup Time to CLK

(to guarantee proper counting) 60 35 ns

THCE

CE Hold Time from CLK

(to guarantee proper counting) 0 0 ns

THOE

OE High Time

(guarantees counter is reset) 25 25 ns

FMAX Maximum Clock Frequency 10 10 MHz

 11
AT17LV65/128/256/512/010/002/040 [DATASHEET]
Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014
Table 10-5. AC Characteristics when Cascading for VCC = 3.3V ± 10%
Notes: 1. AC test lead = 50pF.
2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
3. The AT17LV65 and AT17LV128 are not recommended for new designs.
Table 10-6. AC Characteristics for VCC = 5V ± 10% 
Notes: 1. AC test lead = 50pF.
2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.
3. The AT17LV65 and AT17LV128 are not recommended for new designs.
Symbol Description
AT17LV65/128/256(3) AT17LV512/010/002/040
UnitsMin Max Min Max
TCDF(2) CLK to Data Float Delay 60 50 ns
TOCK(1) CLK to CEO Delay 60 55 ns
TOCE(1) CE to CEO Delay 60 40 ns
TOOE(1) RESET/OE to CEO Delay 45 35 ns
FMAX Maximum Clock Frequency 8 10 MHz
Symbol Description
AT17LV65/128/256(3) AT17LV512/010/002/040
UnitsMin Max Min Max
TOE(1) OE to Data Delay 35 35 ns
TCE(1) CE to Data Delay 45 45 ns
TCAC(1) CLK to Data Delay 55 50 ns
TOH Data Hold from CE, OE, or CLK 0 0 ns
TDF(2) CE or OE to Data Float Delay 50 50 ns
TLC CLK Low Time 20 20 ns
THC CLK High Time 20 20 ns
TSCE
CE Setup Time to CLK 
(To Guarantee Proper Counting) 40 25 ns
THCE
CE Hold Time from CLK 
(To Guarantee Proper Counting) 0 0 ns
THOE
OE High Time 
(Guarantees Counter is Reset) 20 20 ns
FMAX Maximum Clock Frequency 12.5 15 MHz

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

Table 10-7. AC Characteristics When Cascading for VCC = 5V ± 10%

Notes: 1. AC test lead = 50pF.

2. Float delays are measured with 5pF AC loads. Transition is measured ± 200mV from steady-state active levels.

3. The AT17LV65 and AT17LV128 are not recommended for new designs.

Figure 10-1. AC Waveforms

Figure 10-2. AC Waveforms when Cascading

Symbol Description

AT17LV65/128/256(3) AT17LV512/010/002/040

UnitsMin Max Min Max

TCDF(2) CLK to Data Float Delay 50 50 ns

TOCK(1) CLK to CEO Delay 40 40 ns

TOCE(1) CE to CEO Delay 35 35 ns

TOOE(1) RESET/OE to CEO Delay 35 30 ns

FMAX Maximum Clock Frequency 10 12.5 MHz

RESET/OE

CLK

DATA

TSCE

TLC THC

TCAC

TOE

TCE

TOH

THOE

TSCE THCE

TDF

TOH

RESET/OE

CLK

DATA

CEO

TCDF

TOCK TOCE

TOCE

TOOE

LAST BIT FIRST BIT

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

10.5 Thermal Resistance Coefficients

Table 10-8. Thermal Resistance Coefficients

Notes: 1. Airflow = 0ft/min.

2. The AT17LV65 and AT17LV128 are not recommended for new designs.

Package Type AT17LV65/128/256(2) AT17LV512/010 AT17LV002 AT17LV040

8CN4 Leadless Array

Package (LAP)

JC [C/W] 45 45 45 —

JA [C/W](1) 115.71 135.71 159.60 —

8P3 Plastic Dual Inline

Package (PDIP)

JC [C/W] 37 37 — —

JA [C/W](1) 107 107 — —

8S1 Plastic Gull Wing

Small Outline (SOIC)

JC [C/W] 45 — — —

JA [C/W](1) 150 — — —

20J Plastic Leaded Chip

Carrier (PLCC)

JC [C/W] 35 35 35 —

JA [C/W](1) 90 90 90 —

20S2 Plastic Gull Wing

Small Outline (SOIC)

JC [C/W] —

JA [C/W](1) —

44A Thin Plastic Quad

Flat Package (TQFP)

JC [C/W] — — 17 17

JA [C/W](1) — — 62 62

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

11. Ordering Information

11.1 Ordering Code Detail

AT17LV256A-10PU

Atmel Designator

Product Family

Device Density

Special Pinouts Product Variation

65 = 64 kilobit

128 = 128 kilobit

256 = 256 kilobit

512 = 512 kilobit

010 = 1 Mbit

002 = 2 Mbit

040 = 4 Mbit

A = Altera

Blank = Xilinx/Atmel/Other

17LV = FPGA EEPROM

Configuration Memory

Package Device Grade

U = Green, Industrial

Temperature Range

(-40°C to +85°C)

10 = Default Value

Package Option

C = 8CN4, 8-lead LAP

P = 8P3, 8-lead PDIP

N = 8S1, 8-lead JEDEC SOIC

J = 20J, 20-lead PLCC

S = 20S2, 20-lead JEDEC SOIC

TQ = 44A, 44-lead TQFP

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

11.2 Ordering Information

Memory Size Atmel Ordering Code Lead Finish Package Voltage Operation Range

256-Kbit

AT17LV256-10CU CuNiAu

(Lead-free/Halogen-free) 8CN4

3.0V to 5.5V Industrial

(-40C to 85C)

AT17LV256-10JU

(Lead-free/Halogen-free)

20J

AT17LV256-10NU 8S1

AT17LV256-10PU 8P3

AT17LV256-10SU 20S2

512-Kbit

AT17LV512-10CU CuNiAu

(Lead-free/Halogen-free) 8CN4

3.0V to 5.5V Industrial

(-40C to 85C)

AT17LV512-10JU Sn

(Lead-free/Halogen-free) 20J

1-Mbit

AT17LV010-10CU CuNiAu

(Lead-free/Halogen-free) 8CN4

3.0V to 5.5V Industrial

(-40C to 85C)

AT17LV010-10JU Sn

(Lead-free/Halogen-free)

20J

AT17LV010-10PU 8P3

2-Mbit

AT17LV002-10CU CuNiAu

(Lead-free/Halogen-free) 8CN4

3.0V to 5.5V Industrial

(-40C to 85C)

AT17LV002-10JU

(Lead-free/Halogen-free)

20J

AT17LV002-10SU 20S2

AT17LV002-10TQU 44A

4-Mbit AT17LV040-10TQU Sn

(Lead-free/Halogen-free) 44A 3.0V to 5.5V Industrial

(-40C to 85C)

Package Type

8CN4 8-lead, 6mm x 6mm x 1mm, Leadless Array Package (LAP) (Pin-compatible with 8-lead SOIC Packages)

8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)

20J 20-lead, Plastic J-leaded Chip Carrier (PLCC)

20S2 20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)

44A 44-lead, Thin (1.0mm) Plastic Quad Flat Package Carrier (TQFP)

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

12. Packaging Information

12.1 8CN4 – LAP

TITLE DRAWING NO. GPC REV.

Package Drawing Contact:

packagedrawings@atmel.com

8CN4 DMH

8CN4, 8-lead (6 x 6 x 1.04 mm Body),

Lead Pitch 1.27mm,

Leadless Array Package (LAP)

2/15/08

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.94 1.04 1.14

A1 0.30 0.34 0.38

b 0.45 0.50 0.55 1

D 5.89 5.99 6.09

E 5.89 5.99 6.09

e 1.27 BSC

e1 1.10 REF

L 0.95 1.00 1.05 1

L1 1.25 1.30 1.35 1

Note: 1. Metal Pad Dimensions.

2. All exposed metal area shall have the following finished platings.

Ni: 0.0005 to 0.015 mm

Au: 0.0005 to 0.001 mm

Pin1 Corner

Marked Pin1 Indentifier

0.10 mm

TYP

Top View

Side View

Bottom View

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

12.2 8P3 – PDIP

DRAWING NO. REV. TITLE GPC

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A2 A

4 PLCS

A - - 5.334 2

A1 0.381 - -

A2 2.921 3.302 4.953

b 0.356 0.457 0.559 5

b2 1.143 1.524 1.778 6

b3 0.762 0.991 1.143 6

c 0.203 0.254 0.356

D 9.017 9.271 10.160 3

D1 0.127 0.000 0.000 3

E 7.620 7.874 8.255 4

E1 6.096 6.350 7.112 3

e 2.540 BSC

eA 7.620 BSC 4

L 2.921 3.302 3.810 2

Top View

Side View

End View

Package Drawing Contact:

packagedrawings@atmel.com

Gage Plane

.381

8P3 E

07/31/14

8P3, 8-lead, 0.300” Wide Body, Plastic Dual

In-line Package (PDIP) PTC

v0.254

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

12.3 8S1 – SOIC

DRAWING NO. REV. TITLE GPC

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1 0.10 – 0.25

A 1.35 – 1.75

b 0.31 – 0.51

C 0.17 – 0.25

D 4.80 – 5.05

E1 3.81 – 3.99

E 5.79 – 6.20

e 1.27 BSC

L 0.40 – 1.27

0° – 8°

TOP VIEW

END VIEW

SIDE VIEW

Package Drawing Contact:

packagedrawings@atmel.com

8S1 G

6/22/11

Notes: This drawing is for general information only.

Refer to JEDEC Drawing MS-012, Variation AA

for proper dimensions, tolerances, datums, etc.

8S1, 8-lead (0.150” Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC) SWB

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

12.4 20J – PLCC

TITLE DRAWING NO. REV.

Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA

2. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is .010"(0.254mm) per side. Dimension D1

and E1 include mold mismatch and are measured at the extreme

material condition at the upper or lower parting line.

3. Lead coplanarity is 0.004" (0.102mm) maximum

A 4.191 – 4.572

A1 2.286 – 3.048

A2 0.508 – –

D 9.779 – 10.033

D1 8.890 – 9.042 Note 2

E 9.779 – 10.033

E1 8.890 – 9.042 Note 2

D2/E2 7.366 – 8.382

B 0.660 – 0.813

B1 0.330 – 0.533

e 1.270 TYP

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

1.14(0.045) X 45° PIN NO. 1

IDENTIFIER

1.14(0.045) X 45°

0.51(0.020)MAX

0.318(0.0125)

0.191(0.0075)

45° MAX (3X)

D2/E2

E1 E

20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) B

20J

10/04/01

Package Drawing Contact:

packagedrawings@atmel.com

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

12.5 20S2 – SOIC

DRAWING NO. REV. TITLE GPC

20S2, 20-lead, 0.300” Wide Body, Plastic

Gull Wing Small Outline Package (SOIC) 20S2 E

7/1/14

SRJ

Package Drawing Contact:

packagedrawings@atmel.com

1. This drawing is for general information only. Refer to JEDEC Drawing

MS-013, Variation AC, for proper dimensions, tolerances, datums, etc.

2. Dimension D does not include mold flash, protrusions or gate burrs. Mold

flash, protrustions or gate burrs shall not exceed 0.15 mm per end.

Diminsion E1 does not include interlead flash or protursion. Interlead flash

or protrusion shall not exceed 0.25 mm per side.

3. The package top may be smaller than the package bottom. Dimensions D

and E1 are determinded at the outermost extremes of the plastic body

exclusive of mold flash, the bar burrs, gate burrs and interlead flash, but

including any mismatch between the top and bottom of the plastic body.

4. The dimensions apply to the flat section of the lead between 0.10 to

0.25 mm from the lead tip.

5. Dimension ‘b’ does not include the dambar protrusion. Allowable dambar

protrusion shall be 0.10 mm total in excess of the ‘b’ dimension at maximum

material condition. The dambar may not be located on the lower radius of

the foot.

6. ‘A1’ is defined as the vertical distance from the seating plane to the lowest

point on the package body excluding the lid or thermal enhancement on the

cavity down package configuration.

Notes:

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

D 12.80 BSC 2,3

E1 7.50 BSC 2,3

E 10.30 BSC

A - - 2.65

A1 0.10 - 0.30 6

A2 2.05 - -

e 1.27 BSC

b 0.31 - 0.51 4,5

L 0.40 - 1.27

C 0.20 - 0.33 4

E1 E

END VIEW

TOP VIEW

SIDE VIEW

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

12.6 44A – TQFP

DRAWING NO. REV. TITLE GPC

44A D

AIX

Package Drawing Contact:

packagedrawings@atmel.com

1/10/13

Notes: 1. This package conforms to JEDEC reference MS-026,

Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is 0.25 mm per side. Dimensions D1

and E1 are maximum plastic body size dimensions including

mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 11.75 12.00 12.25

D1 9.90 10.00 10.10 Note 2

E 11.75 12.00 12.25

E1 9.90 10.00 10.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

0°~7°

A1 A2 A

BOTTOM VIEW

SIDE VIEW

TOP VIEW

44A, 44-lead 10.0 x 10.0x1.0 mm Body, 0.80 mm

Lead Pitch, Thin Profile Plastic Quad Flat

Package (TQFP)

AT17LV65/128/256/512/010/002/040 [DATASHEET]

Atmel-2321J-FPGA-AT17LV65-128-256-512-010-002-040-Datasheet_102014

13. Revision History

Rev. No. Date History

2321J 10/2014

The AT17LV65 and AT17LV128 are not recommended for new designs.

Removed the commercial options.

Updated the 8P3, 8S1, 20S2, and 44A package outline drawings, ordering code details,

ordering code table, document’s template, Atmel logos, disclaimer page.

2321I 02/2008 Removed -10SC, 10SI, -10TQC, -10TQI, -10BJC and -10BJI devices from ordering information.

2321H 03/2006 Added last-time buy for AT17LVXXX-10CC and AT17LVXXX-10CI.

XXX

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