16-Bit, 100 kSPS PulSAR,
Differential ADC in MSOP
AD7684
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved.
FEATURES
16-bit resolution with no missing codes
Throughput: 100 kSPS
INL: ±1 LSB typical, ±3 LSB maximum
True differential analog input range: ±VREF
0 V to VREF with VREF up to VDD on both inputs
Single-supply operation: 2.7 V to 5.5 V
Serial interface SPI®-/QSPI-™/MICROWIRE-™/DSP-compatible
Power dissipation
4 mW @ 5 V
1.5 mW @ 2.7 V
150 μW @ 2.7 V/10 kSPS
Standby current: 1 nA
8-lead MSOP package
APPLICATIONS
Battery-powered equipment
Data acquisition
Instrumentation
Medical instruments
Process control
APPLICATION DIAGRAM
AD7684
REF
GND
VDD
+IN
–IN
DCLOCK
D
OUT
CS
3-WIRE SPI
INTERFACE
0.5V TO VDD 2.7V TO 5.5V
04302-001
0
V
REF
0
V
REF
Figure 1.
Table 1. MSOP, QFN (LFCSP)/SOT-23
14-/16-/18-Bit PulSAR ADC
Type
100
kSPS
250
kSPS
400 kSPS
to
500 kSPS
≥ 1000
kSPS
ADC
Driver
18-Bit True AD7691 AD7690 AD7982 ADA4941
Differential AD7984 ADA4841
16-Bit True AD7684 AD7687 AD7688 ADA4941
Differential AD7693 ADA4841
16-Bit Pseudo AD7680 AD7685 AD7686 AD7980 ADA4841
Differential AD7683 AD7694
14-Bit Pseudo
Differential
AD7940 AD7942 AD7946 ADA4841
GENERAL DESCRIPTION
The AD7684 is a 16-bit, charge redistribution, successive
approximation, PulSAR® analog-to-digital converter (ADC)
that operates from a single power supply, VDD, between 2.7 V
to 5.5 V. It contains a low power, high speed, 16-bit sampling
ADC with no missing codes, an internal conversion clock, and a
serial, SPI-compatible interface port. The part also contains a low
noise, wide bandwidth, short aperture delay, track-and-hold circuit.
On the CS falling edge, it samples the voltage difference
between +IN and –IN pins. The reference voltage, REF, is
applied externally and can be set up to the supply voltage. Its
power scales linearly with throughput.
The AD7684 is housed in an 8-lead MSOP, with an operating
temperature specified from −40°C to +85°C.
AD7684
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Application Diagram........................................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Ter mi no log y ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Application Information................................................................ 12
Circuit Information.................................................................... 12
Converter Operation.................................................................. 12
Transfer Functions ..................................................................... 12
Typical Connection Diagram ................................................... 13
Analog Inputs ............................................................................. 13
Driver Amplifier Choice ........................................................... 13
Voltage Reference Input ............................................................ 14
Power Supply............................................................................... 14
Digital Interface.......................................................................... 14
Layout .......................................................................................... 14
Evaluating the Performance of the AD7684............................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
10/07—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 1
Changes to Table 2............................................................................ 3
Changes to Layout ............................................................................ 5
Changes to Table 6 and Layout ....................................................... 6
Changes to Table 7............................................................................ 7
Changes to Figure 15 Caption....................................................... 10
Changes to Figure 21...................................................................... 12
Changes to Figure 22 and Analog Inputs Section ...................... 13
Changes to Table 9, Digital Interface Section, and Evaluating
the Performance of the AD7684 Section..................................... 14
Updated Outline Dimensions....................................................... 15
Changes to Ordering Guide .......................................................... 15
10/04— Revision 0: Initial Version
AD7684
Rev. A | Page 3 of 16
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; VREF = VDD; TA = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range1+IN − (−IN) −VREF +VREF V
Absolute Input Voltage +IN, −IN −0.1 VDD + 0.1 V
Common-Mode Input Range +IN, −IN 0 VREF/2 VREF/2 + 0.1 V
Analog Input CMRR fIN = 100 kHz 65 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance See the Analog Inputs section
THROUGHPUT SPEED
Complete Cycle 10 μs
Throughput Rate 0 100 kSPS
DCLOCK Frequency 0 2.9 MHz
REFERENCE
Voltage Range 0.5 VDD + 0.3 V
Load Current 100 kSPS, V+IN = V−IN = VREF/2 = 2.5 V 50 μA
DIGITAL INPUTS
Logic Levels
VIL −0.3 0.3 × VDD V
VIH 0.7 × VDD VDD + 0.3 V
IIL −1 +1 μA
IIH −1 +1 μA
Input Capacitance 5 pF
DIGITAL OUTPUTS
Data Format Serial 16 bits twos complement
VOH ISOURCE = −500 μA VDD − 0.3 V
VOL ISINK = +500 μA 0.4 V
POWER SUPPLIES
VDD Specified performance 2.7 5.5 V
VDD Range2 2.0 5.5 V
Operating Current 100 kSPS throughput
VDD = 5 V 800 μA
VDD = 2.7 V 560 μA
Standby Current3, 4VDD = 5 V, 25°C 1 50 nA
Power Dissipation VDD = 5 V 4 6 mW
VDD = 2.7 V 1.5 mW
VDD = 2.7 V, 10 kSPS throughput3 150 μW
TEMPERATURE RANGE
Specified Performance TMIN to TMAX −40 +85 °C
1 The inputs must be driven differentially 180° from each other. See Pin Configuration and Function Descriptions and Analog Inputs sections.
2 See the Typical Performance Characteristics section for more information.
3 With all digital inputs forced to VDD or GND, as required.
4 During acquisition phase.
AD7684
Rev. A | Page 4 of 16
VDD = 5 V; VREF = VDD; TA = −40°C to +85°C, unless otherwise noted.
Table 3.
Parameter Conditions Min Typ Max Unit
ACCURACY
No Missing Codes 16 Bits
Integral Linearity Error −3 ±1 +3 LSB
Transition Noise 0.5 LSB
Gain Error, 1 TMIN to TMAX ±2 ±15 LSB
Gain Error Temperature Drift ±0.3 ppm/°C
Zero Error,1 TMIN to TMAX ±0.4 ±1.6 mV
Zero Temperature Drift ±0.3 ppm/°C
Power Supply Sensitivity VDD = 5 V ± 5% ±0.05 LSB
AC ACCURACY
Signal-to-Noise Ratio fIN = 1 kHz 88 91 dB2
Spurious-Free Dynamic Range fIN = 1 kHz −108 dB
Total Harmonic Distortion fIN = 1 kHz −106 dB
Signal-to-(Noise + Distortion) fIN = 1 kHz 88 91 dB
Effective Number of Bits fIN = 1 kHz 14.8 Bits
1 See the Terminology section. These specifications include full temperature range variation but do not include the error contribution from the external reference.
2 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
VDD = 2.7 V; VREF = 2.5 V; TA = −40°C to +85°C, unless otherwise noted.
Table 4.
Parameter Conditions Min Typ Max Unit
ACCURACY
No Missing Codes 16 Bits
Integral Linearity Error −3 ±1 +3 LSB
Transition Noise 0.85 LSB
Gain Error,1 TMIN to TMAX ±2 ±15 LSB
Gain Error Temperature Drift ±0.3 ppm/°C
Zero Error,1 TMIN to TMAX ±0.7 ±3.5 mV
Zero Temperature Drift ±0.3 ppm/°C
Power Supply Sensitivity VDD = 2.7 V ± 5% ±0.05 LSB
AC ACCURACY
Signal-to-Noise Ratio fIN = 1 kHz 86 dB2
Spurious-Free Dynamic Range fIN = 1 kHz −100 dB
Total Harmonic Distortion fIN = 1 kHz −98 dB
Signal-to-(Noise + Distortion) fIN = 1 kHz 86 dB
Effective Number of Bits fIN = 1 kHz 14 Bits
1 See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
2 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
AD7684
Rev. A | Page 5 of 16
TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise noted.
Table 5.
Parameter Symbol Min Typ Max Unit
Throughput Rate tCYC 100 kHz
CS Falling to DCLOCK Low tCSD 0 μs
CS Falling to DCLOCK Rising tSUCS 20 ns
DCLOCK Falling to Data Remains Valid tHDO 5 16 ns
CS Rising Edge to DOUT High Impedance tDIS 14 100 ns
DCLOCK Falling to Data Valid tEN 16 50 ns
Acquisition Time tACQ 400 ns
DOUT Fall Time tF 11 25 ns
DOUT Rise Time tR 11 25 ns
Timing Diagrams
04302-002
D
OUT
DCLOCK
COMPLETE CYCLE
POWER DOWN
CS
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(MSB) (LSB)
Hi-Z 0Hi-Z
t
ACQ
t
DIS
0
145
t
HDO
t
EN
t
CSD
t
SUCS
t
CYC
NOTE:
A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES.
D
OUT
GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
Figure 2. Serial Interface Timing
04302-003
500μAI
OL
500μAI
OH
1.4VTO D
OUT
C
L
100pF
Figure 3. Load Circuit for Digital Interface Timing
0.8V 2V
2V
0.8V0.8V
2V
t
DELAY
t
DELAY
04302-004
Figure 4. Voltage Reference Levels for Timing
04302-005
DOUT 90%
10%
t
R
t
F
Figure 5. DOUT Rise and Fall Timing
AD7684
Rev. A | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Analog Inputs
+IN1, −IN1GND − 0.3 V to VDD + 0.3 V
or ±130 mA
REF GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD to GND −0.3 V to +6 V
Digital Inputs to GND −0.3 V to VDD + 0.3 V
Digital Outputs to GND −0.3 V to VDD + 0.3 V
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance 200°C/W
θJC Thermal Impedance 44°C/W
Lead Temperature JEDEC J-STD-20
1 See the Analog Inputs section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD7684
Rev. A | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
04302-006
REF
1
+IN
2
–IN
3
GND
4
VDD
8
DCLOCK
7
D
OUT
6
CS
5
AD7684
TOP VIEW
(Not to Scale)
Figure 6. 8-Lead MSOP Pin Configuration
Table 7. Pin Function Descriptions
Pin No. Mnemonic Type1Description
1 REF AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. This pin is referred to the GND pin and
should be decoupled closely to the GND pin with a ceramic capacitor of a few μF.
2 +IN AI
Differential Positive Analog Input. Referenced to −IN. The input range for +IN is between 0 V and VREF,
centered about VREF/2 and must be driven 180° out of phase with −IN.
3 –IN AI
Differential Negative Analog Input. Referenced to +IN. The input range for −IN is between VREF and 0 V,
centered about VREF/2 and must be driven 180° out of phase with +IN.
4 GND P Power Supply Ground.
5 CS DI Chip Select Input. On its falling edge, it initiates the conversions. The part returns to shutdown mode as
soon as the conversion is complete. It also enables DOUT. When high, DOUT is high impedance.
6 DOUT DO Serial Data Output. The conversion result is output on this pin. It is synchronized to DCLOCK.
7 DCLOCK DI Serial Data Clock Input.
8 VDD P Power Supply.
1 AI = analog input, DI = digital input, DO = digital output, and P = power.
AD7684
Rev. A | Page 8 of 16
TERMINOLOGY
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line
(see Figure 21).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Zero Error
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, and the actual voltage producing the midscale
output code, that is, 0 LSB.
Gain Error
The first transition (from 100 . . . 00 to 100 . . . 01) should
occur at a level ½ LSB above the nominal negative full scale
(−4.999924 V for the ±5 V range). The last transition (from
011…10 to 011…11) should occur for an analog voltage
1½ LSB below the nominal full scale (4.999771 V for the ±5 V
range). The gain error is the deviation of the difference between
the actual level of the last transition and the actual level of the
first transition from the difference between the ideal levels.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is the time between the falling edge of the CS input and when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
AD7684
Rev. A | Page 9 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
–3
–2
–1
0
1
2
3
0 16384 32768 49152 65536
CODE
INL (LSB)
04302-007
POSITIVE INL = +0.83LSB
NEG ATIV E INL = –1.07LSB
Figure 7. Integral Nonlinearity vs. Code
04302-008
151
94794
18557
17388
182
0
20000
40000
60000
80000
100000
120000
FFFD FFFE FFFF 0000 0001 0002 0003 0004 0005
CODE IN HEX
COUNTS
VDD = REF = 2.5V
00
00
Figure 8. Histogram of a DC Input at the Code Center
–
180
–
160
–
140
–
120
–
100
–
80
–
60
–
40
–
20
0
04302-009
010203040
FREQUENCY (kHz)
AMPLITUDE (dB of Full Scale)
50
16384 POINT FFT
VDD = REF = 5V
f
S
= 100kSPS
f
IN
= 20.43kHz
Figure 9. FFT Plot
–3
–2
–1
0
1
2
3
0 16384 32768 49152 65536
CODE
DNL (LSB)
04302-010
POSITIVE DNL = +0.9LSB
NEGATIVE DNL = –0.45LSB
Figure 10. Differential Nonlinearity vs. Code
04302-011
123872
4150
3050
0
50000
100000
150000
FFFB FFFC FFFD FFFE FFFF
CODE IN HEX
COUNTS
0
0
VDD = REF = 5V
Figure 11. Histogram of a DC Input at the Code Center
–
180
–
160
–
140
–
120
–
100
–
80
–
60
–
40
–
20
0
04302-012
010203040
FREQUENCY (kHz)
AMPLITUDE (dB of Full Scale)
50
16384 POINT FFT
VDD = REF = 2.5V
f
S
= 100kSPS
f
IN
= 20.43kHz
Figure 12. FFT Plot
AD7684
Rev. A | Page 10 of 16
ENO B (Bits)
13
14
15
16
17
80
85
90
95
100
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
REFE RE NCE V OLTAGE (V )
SNR, SINAD (dB)
04302-013
S/[N+D]
SNR
ENOB
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
70
75
80
85
90
95
100
0 50 100 150 200
FREQUENC Y ( kHz )
SINAD ( dB)
VREF = 5V, –1dB
VREF = 2.5V, –1dB
VREF = 5V, –10d B
04302-014
Figure 14. SINAD vs. Frequency
–115
–110
–105
–100
–95
–90
–85
–80
0 40 80 120 160 200
FREQUENCY (kHz)
THD (dB)
VREF = 2.5V, –1dB
VREF = 5V, –1dB
04302-015
Figure 15. THD vs. Frequency
0
200
400
600
800
1000
1200
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
SUPPLY (V)
OPERATING CURRENT (
μ
A)
04302-016
f
S
= 100kSPS
Figure 16. Operating Current vs. Supply
0
200
400
600
800
1000
TEMPERATURE (°C)
OPERATING CURRENT (μA)
04302-017
–55 –35 –15 5 25 45 65 85 105 125
VDD = 5V
VDD = 2.7V
Figure 17. Operating Current vs. Temperature
0
250
500
750
1000
TEMPERATURE (°C)
POWER-DOWN CURRENT (μA)
04302-018
–55 –35 –15 5 25 45 65 85 105 125
Figure 18. Power-Down Current vs. Temperature
AD7684
Rev. A | Page 11 of 16
–6
–4
–2
–3
–5
0
–1
2
1
4
3
6
5
–55 –35 –15 5 25 45 65 85 105 125
TEMPERAT URE ( °C)
ZERO ERRO R, GAIN ERRO R ( LSB)
04302-019
ZE RO ERROR
GAIN ERROR
Figure 19. Zero Error and Gain Error vs. Temperature
AD7684
Rev. A | Page 12 of 16
APPLICATION INFORMATION
SW+MSB
16,384C
+IN
LSB
COMP CONTROL
LOGIC
SWITCHES CONTROL
BUSY
OUTPUT CODE
CNV
REF
GND
–IN
4C 2C C C32,768C
SW–MSB
16,384C
LSB
4C 2C C C32,768C
04302-020
Figure 20. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7684 is a low power, single-supply, 16-bit ADC using a
successive approximation architecture. It is capable of converting
100,000 samples per second (100 kSPS) and powers down
between conversions. When operating at 10 kSPS, for example,
it consumes typically 150 μW with a 2.7 V supply, ideal for
battery-powered applications.
The AD7684 provides the user with an on-chip, track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple, multiplexed channel applications.
The AD7684 is specified from 2.7 V to 5.5 V. It is housed in an
8-lead MSOP.
CONVERTER OPERATION
The AD7684 is a successive approximation ADC based on a
charge redistribution DAC. Figure 20 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary-weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Therefore, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the +IN and −IN
inputs. When the acquisition phase is complete and the CS
input goes low, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW− are opened first. The
two capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the inputs, +IN and −IN, captured at the end of the
acquisition phase is applied to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and REF, the
comparator input varies by binary-weighted voltage steps
(VREF/2, VREF/4...VREF/65,536). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase and the control logic
generates the ADC output code.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7684 is shown in
Figure 21 and Table 8.
100...000
100...001
100...010
011...101
011...110
011...111
ADC CODE ( TWOS CO M P LEME NT)
ANALO G INP UT
+F S R – 1 .5 L S B
+F S R – 1 LSB
–FS R + 1 LSB
–FSR
–FS R + 0 .5 LSB
04302-021
Figure 21. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Description
Analog Input
VREF = 5 V Digital Output Code Hex
FSR − 1 LSB +4.999847 V 7FFF1
Midscale + 1 LSB +152.6 μV 0001
Midscale 0 V 0000
Midscale – 1 LSB −152.6 μV FFFF
−FSR + 1 LSB −4.999847 V 8001
−FSR −5 V 80002
1 This is also the code for an overranged analog input (V+IN − V−IN above
VREF − VGND).
2 This is also the code for an underranged analog input (V+IN − V−IN below
−VREF + VGND).
AD7684
Rev. A | Page 13 of 16
04302-022
AD7684
REF
GND
VDD
–IN
+IN
DCLOCK
D
OUT
CS
3-WIRE INTE RFACE
100nF 2 .7V TO 5.25V
2.2μF TO 10μF
(NOTE 2)
REF
0 TO V
REF
33Ω
2.7nF
(NOTE 3)
(NOTE 4)
(NOTE 1)
V
REF
TO 0
33Ω
2.7nF
(NOTE 3)
(NOTE 4)
NOTE 1: SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
NOTE 2: C
REF
IS USUALL Y A 10μF CERAM IC CAPACITO R (X5R).
NOTE 3: SE E DRIVER AMPLIFIER CHO ICE SE CTION.
NOTE 4: O P TIONAL F IL TER. S E E ANAL OG INPUT S E CTION.
NOTE 5: SE E DIGIT AL INT E RFACE F OR MOST CONVENIENT INTE RF ACE MODE.
Figure 22. Typical Application Diagram
TYPICAL CONNECTION DIAGRAM
Figure 22 shows an example of the recommended application
diagram for the AD7684.
ANALOG INPUTS
The analog inputs (+IN, −IN) need to be driven differentially
180° from each other, as shown in Figure 22. Holding either
input at GND or a fixed dc gives erroneous conversion results
because the AD7684 is intended for differential operation only.
For applications requiring –IN to be at GND (±100 mV), the
AD7683 should be used.
Figure 23 shows an equivalent circuit of the input structure of
the AD7684. The two diodes, D1 and D2, provide ESD protection
for the analog inputs, +IN and −IN. Care must be taken to
ensure that the analog input signal never exceeds the supply
rails by more than 0.3 V because this causes these diodes to
become forward-biased and start conducting current. However,
these diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions could eventually
occur when the supplies of the input buffer (U1) are different
from VDD. In such a case, an input buffer with a short-circuit
current limitation can be used to protect the part.
04302-023
C
IN
R
IN
D1
D2
C
PIN
+IN
OR –IN
GND
VDD
Figure 23. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the differential
signal between +IN and −IN. By using this differential input, small
signals common to both inputs are rejected. During the acquisition
phase, the impedance of the analog inputs can be modeled as a
parallel combination of the Capacitor CPIN and the network
formed by the series connection of RIN and CIN. CPIN is primarily
the pin capacitance. RIN is typically 600 Ω and is a lumped
component made up of some serial resistors and the on-
resistance of the switches. CIN is typically 30 pF and is mainly
the ADC sampling capacitor. During the conversion phase,
when the switches are opened, the input impedance is limited
to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces
undesirable aliasing effects and limits the noise.
When the source impedance of the driving circuit is low, the
AD7684 can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance.
DRIVER AMPLIFIER CHOICE
Although the AD7684 is easy to drive, the driver amplifier
needs to meet the following requirements:
• The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7684. Note that the AD7684
has a noise level much lower than most other 16-bit ADCs
and, therefore, can be driven by a noisier op amp while
preserving the same or better system performance. The
noise coming from the driver is filtered by the AD7684
analog input circuit 1-pole, low-pass filter made by RIN and
CIN or by the external filter, if one is used.
• For ac applications, the driver needs to have a THD
performance commensurate with the AD7684. Figure 15
shows the THD vs. frequency that the driver should exceed.
• For multichannel multiplexed applications, the driver
amplifier and the AD7684 analog input circuit must be
able to settle for a full-scale step of the capacitor array at a
16-bit level (0.0015%). In the data sheet of the amplifier,
settling at 0.1% to 0.01% is more commonly specified. This
could differ significantly from the settling time at a 16-bit
level and should be verified prior to driver selection.
AD7684
Rev. A | Page 14 of 16
Table 9. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4841-x Very low noise
ADA4941-1 Very low noise, single to differential
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8605, AD8615 5 V single-supply, low power
AD8519 Small, low power, and low frequency
AD8031 High frequency and low power
VOLTAGE REFERENCE INPUT
The AD7684 voltage reference input, REF, has a dynamic input
impedance. It should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in more detail in the Layout section.
When REF is driven by a very low impedance source (for
example, an unbuffered reference voltage such as the low
temperature drift ADR43x reference or a reference buffer using
the AD8031 or the AD8605), a 10 μF (X5R, 0805 size) ceramic
chip capacitor is appropriate for optimum performance.
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with minimal impact on performance,
especially DNL.
POWER SUPPLY
The AD7684 powers down automatically at the end of each
conversion phase and therefore the power scales linearly with
the sampling rate, as shown in Figure 24. This makes the part
ideal for low sampling rates (even of a few Hz) and low battery
powered applications.
0.01
0.1
1
10
100
1000
10010 1k 10k 100k
SAMPLING RATE (SPS)
OPERATING CURRENT (
μ
A)
04302-024
VDD = 5V
VDD = 2.7V
Figure 24. Operating Current vs. Sampling Rate
DIGITAL INTERFACE
The AD7684 is compatible with SPI, QSPI, digital hosts, and
DSPs (for example, Blackfin® ADSP-BF53x or ADSP-219x). The
connection diagram is shown in Figure 25, and the corresponding
timing is given in Figure 2.
A falling edge on CS initiates a conversion and the data transfer.
After the fifth DCLOCK falling edge, DOUT is enabled and forced
low. The data bits are then clocked MSB first by subsequent
DCLOCK falling edges. The data is valid on both DCLOCK
edges. Although the rising edge can be used to capture the data,
a digital host also using the DCLOCK falling edge allows a
faster reading rate, provided it has an acceptable hold time.
04302-025
CS
DCLOCK D
OUT
DATA IN
CLK
CONVERT
DIGITAL HOST
AD7684
Figure 25. Connection Diagram
LAYOUT
The printed circuit board housing the AD7684 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7684 with all its analog signals on the left side and all its
digital signals on the right side eases this task.
Avoid running digital lines under the device because these couple
noise onto the die, unless a ground plane under the AD7684 is
used as a shield. Fast switching signals, such as CS or clocks,
should never run near analog signal paths. Crossover of digital
and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In such a case,
it should be joined underneath the AD7684.
The AD7684 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and by connecting these pins with wide, low
impedance traces.
Finally, the power supply, VDD, of the AD7684 should be
decoupled with a ceramic capacitor, typically 100 nF, and placed
close to the AD7684. It should be connected using short and
large traces to provide low impedance paths and reduce the
effect of glitches on the power supply lines.
EVALUATING THE PERFORMANCE OF THE AD7684
Other recommended layouts for the AD7684 are outlined in the
evaluation board for the AD7684 (EVAL-AD7684CBZ). The
evaluation board package includes a fully assembled and tested
evaluation board, documentation, and software for controlling
the board from a PC via the EVAL-CONTROL BRD3Z.
AD7684
Rev. A | Page 15 of 16
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
8°
0°
4
8
1
5
PIN 1 0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure 26. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Integral
Nonlinearity Temperature Range Package Description Package Option
Ordering
Quantity Branding
AD7684BRM ±3 LSB maximum –40°C to +85°C 8-Lead MSOP RM-8 50 C1D
AD7684BRMRL7 ±3 LSB maximum –40°C to +85°C 8-Lead MSOP RM-8 1,000 C1D
AD7684BRMZ1±3 LSB maximum –40°C to +85°C 8-Lead MSOP RM-8 50 C39
AD7684BRMZRL71±3 LSB maximum –40°C to +85°C 8-Lead MSOP RM-8 1,000 C39
EVAL-AD7684CBZ1, 2 Evaluation Board
EVAL-CONTROL BRD3Z1, 3 Controller Board
1 Z = RoHS Compliant Part.
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes.
3 This board allows a PC to control and communicate with all the Analog Devices, Inc. evaluation boards ending in the CB designators.
AD7684
Rev. A | Page 16 of 16
NOTES
©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04302-0-10/07(A)
