SN54LVTH573, SN74LVTH573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DSupport Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC)
DSupport Unregulated Battery Operation
Down to 2.7 V
DTypical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
DIoff and Power-Up 3-State Support Hot
Insertion
DBus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
DLatch-Up Performance Exceeds 500 mA Per
JESD 17
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LVTH573 ...J OR W PACKAGE
SN74LVTH573 . . . DB, DW, NS,
OR PW PACKAGE
(TOP VIEW)
SN54LVTH573 . . . FK PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
VCC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
2D
1D
OE
8Q
7Q 1Q
8D
GND
LE
VCC
SN74LVTH573 . . . RGY PACKAGE
(TOP VIEW)
120
10 11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2D
3D
4D
5D
6D
7D
8D
LE V
GND
CC
OE
description/ordering information
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE MARKING
QFN − RGY Tape and reel SN74LVTH573RGYR LXH573
SOIC DW
Tube SN74LVTH573DW LVTH573
SOIC − DW Tape and reel SN74LVTH573DWR LVTH573
SOP − NS Tape and reel SN74LVTH573NSR LVTH573
−40°C to 85°CSSOP − DB Tape and reel SN74LVTH573DBR LXH573
40 C
to
85 C
TSSOP PW
Tube SN74LVTH573PW
LXH573
TSSOP − PW Tape and reel SN74LVTH573PWR LXH573
VFBGA − GQN
Tape and reel
SN74LVTH573GQNR
LXH573
VFBGA − ZQN (Pb-free) Tape and reel SN74LVTH573ZQNR LXH573
CDIP − J Tube SNJ54LVTH573J SNJ54LVTH573J
−55°C to 125°CCFP − W Tube SNJ54LVTH573W SNJ54LVTH573W
LCCC − FK Tube SNJ54LVTH573FK SNJ54LVTH573FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
Copyright © 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LVTH573, SN74LVTH573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
These octal latches are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to
provide a TTL interface to a 5-V system environment.
The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic
levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Use of pullup
or pulldown resistors with the bus-hold circuitry is not recommended.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
terminal assignments
1234
A1D OE VCC 1Q
B3D 3Q 2D 2Q
C5D 4D 5Q 4Q
D7D 7Q 6D 6Q
EGND 8D LE 8Q
FUNCTION TABLE
(each latch)
INPUTS OUTPUT
OE LE D
OUTPUT
Q
L H H H
LHL L
LLX Q
0
H X X Z
SN74LVTH573 . . . GQN OR ZQN PACKAGE
(TOP VIEW)
1234
A
B
C
D
E
SN54LVTH573, SN74LVTH573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
2
19
LE
1D
C1
1D 1Q
Pin numbers shown are for the DB, DW, FK, J, NS, PW, RGY, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . .
Current into any output in the low state, IO: SN54LVTH573 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVTH573 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, IO (see Note 2): SN54LVTH573 48 mA. . . . . . . . . . . . . . . . . . . . . . .
SN74LVTH573 64 mA. . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): GQN/ZQN package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 4): RGY package 37°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
SN54LVTH573, SN74LVTH573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 5)
SN54LVTH573 SN74LVTH573
UNIT
MIN MAX MIN MAX UNIT
VCC Supply voltage 2.7 3.6 2.7 3.6 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 5.5 5.5 V
IOH High-level output current −24 −32 mA
IOL Low-level output current 48 64 mA
Δt/ΔvInput transition rise or fall rate Outputs enabled 10 10 ns/V
Δt/ΔVCC Power-up ramp rate 200 200 μs/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 5: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54LVTH573, SN74LVTH573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LVTH573 SN74LVTH573
UNIT
PARAMETER TEST CONDITIONS MIN TYP†MAX MIN TYP†MAX UNIT
VIK VCC = 2.7 V, II = −18 mA −1.2 −1.2 V
VCC = 2.7 V to 3.6 V, IOH = −100 μA VCC−0.2 VCC−0.2
V
VCC = 2.7 V, IOH = −8 mA 2.4 2.4
V
VOH
IOH = −24 mA 2V
VCC = 3 V IOH = −32 mA 2
IOL = 100 μA 0.2 0.2
VCC = 2.7 V IOL = 24 mA 0.5 0.5
V
IOL = 16 mA 0.4 0.4
V
VOL
IOL = 32 mA 0.5 0.5 V
VCC = 3 V IOL = 48 mA 0.55
IOL = 64 mA 0.55
Control inputs
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
I
Control inputs VCC = 3.6 V, VI = VCC or GND ±1±1
A
II
Data inputs
VI = VCC 1 1 μA
Data inputs VCC = 3.6 V VI = 0 −5 −5
Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 μA
VI = 0.8 V 75 75
II
(
hold
)
Data inputs VCC = 3 V VI = 2 V −75 −75 μA
II(hold)
Data
inputs
VCC = 3.6 V‡, VI = 0 to 3.6 V ±500
μA
IOZH VCC = 3.6 V, VO = 3 V 5 5 μA
IOZL VCC = 3.6 V, VO = 0.5 V −5 −5 μA
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don’t care ±100* ±100 μA
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don’t care ±100* ±100 μA
=
Outputs high 0.19 0.19
ICC
CC =
.
,
IO = 0, Outputs low 5 5 mA
ICC
VI = VCC or GND Outputs disabled 0.19 0.19
mA
ΔICC§VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
Other inputs at VCC or GND 0.2 0.2 mA
CiVI = 3 V or 0 3 3 pF
CoVO = 3 V or 0 7 7 pF
*On products compliant to MIL-PRF-38535, this parameter is not production tested.
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
SN54LVTH573, SN74LVTH573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
SN54LVTH573 SN74LVTH573
VCC = 3.3 V
±0.3 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V VCC = 2.7 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
twPulse duration, LE high 3 3 3 3 ns
tsu Setup time, data before LE↓0.7 0.6 0.7 0.6 ns
thHold time, data after LE↓1.5 1.7 1.5 1.7 ns
switching characteristics over recommended free-air temperature, CL = 50 pF (unless otherwise
noted) (see Figure 1)
SN54LVTH573 SN74LVTH573
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 3.3 V
± 0.3 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V VCC = 2.7 V UNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
tPLH
D
Q
1.4 4.1 4.7 1.5 2.6 3.9 4.5
ns
tPHL
D Q 1.4 4.5 4.8 1.5 2.9 3.9 4.5 ns
tPLH
LE
Q
1 4.4 5.4 1.9 2.9 4.2 4.9
ns
tPHL
LE Q 1.4 4.4 5.1 1.9 2.9 4.2 4.9 ns
tPZH
OE
Q
1.4 5.2 6.2 1.5 3.2 5.1 5.9
ns
tPZL
OE Q1.4 5.2 6.2 1.5 3.9 5.1 5.9 ns
tPHZ
OE
Q
1.2 5.4 5.7 2 3.5 4.9 5.5
ns
tPLZ
OE Q1 5.2 5.2 2 3.2 4.6 4.9 ns
†All typical values are at VCC = 3.3 V, TA = 25°C.
SN54LVTH573, SN74LVTH573
3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V
2.7 V
0 V
1.5 V 1.5 V
2.7 V
0 V
2.7 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V
2.7 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
3 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH − 0.3 V
≈0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-9583101Q2A ACTIVE LCCC FK 20 1 TBD Call TI Call TI
5962-9583101QRA ACTIVE CDIP J 20 1 TBD Call TI Call TI
5962-9583101QSA ACTIVE CFP W 20 1 TBD Call TI Call TI
SN74LVTH573DBLE OBSOLETE SSOP DB 20 TBD Call TI Call TI
SN74LVTH573DBR ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573DW ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573DWE4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573DWG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573DWR ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573NSR ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573NSRE4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573NSRG4 ACTIVE SO NS 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573PW ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
SN74LVTH573PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573PWLE OBSOLETE TSSOP PW 20 TBD Call TI Call TI
SN74LVTH573PWR ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVTH573RGYR ACTIVE VQFN RGY 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SN74LVTH573RGYRG4 ACTIVE VQFN RGY 20 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
SNJ54LVTH573FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54LVTH573J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SNJ54LVTH573W ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 3
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVTH573, SN74LVTH573 :
•Catalog: SN74LVTH573
•Enhanced Product: SN74LVTH573-EP, SN74LVTH573-EP
•Military: SN54LVTH573
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74LVTH573DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74LVTH573DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN74LVTH573NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1
SN74LVTH573PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
SN74LVTH573RGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LVTH573DBR SSOP DB 20 2000 367.0 367.0 38.0
SN74LVTH573DWR SOIC DW 20 2000 367.0 367.0 45.0
SN74LVTH573NSR SO NS 20 2000 367.0 367.0 45.0
SN74LVTH573PWR TSSOP PW 20 2000 367.0 367.0 38.0
SN74LVTH573RGYR VQFN RGY 20 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2