1
CMOS DUAL ASYNCHRONOUS FIFO
DUAL 256 x 9, DUAL 512 x 9,
DUAL 1,024 x 9, DUAL 2,048 x 9,
DUAL 4,096 x 9, DUAL 8,192 x 9
IDT7280
IDT7281
IDT7282
IDT7283
IDT7284
IDT7285
JUNE 2012
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
©2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3208/9
FEATURES:
••
••
•The IDT7280 is equivalent to two IDT7200 256 x 9 FIFOs
••
••
•The IDT7281 is equivalent to two IDT7201 512 x 9 FIFOs
••
••
•The IDT7282 is equivalent to two IDT7202 1,024 x 9 FIFOs
••
••
•The IDT7283 is equivalent to two IDT7203 2,048 x 9 FIFOs
••
••
•The IDT7284 is equivalent to two IDT7204 4,096 x 9 FIFOs
••
••
•The IDT7285 is equivalent to two IDT7205 8,192 x 9 FIFOs
••
••
•Low power consumption
— Active: 685 mW (max.)
— Power-down: 83 mW (max.)
••
••
•Ultra high speed—12 ns access time
••
••
•Asynchronous and simultaneous read and write
••
••
•Offers optimal combination of data capacity, small foot print
and functional flexibility
••
••
•Ideal for bi-directional, width expansion, depth expansion,
bus-matching, and data sorting applications
••
••
•Status Flags: Empty, Half-Full, Full
••
••
•Auto-retransmit capability
••
••
•High-performance CMOS technology
••
••
•Space-saving TSSOP
••
••
•
Industrial temperature range (–40
°°
°°
°
C to +85
°°
°°
°
C) is available
DESCRIPTION:
The IDT7280/7281/7282/7283/7284/7285 are dual-FIFO memories that
load and empty data on a first-in/first-out basis. These devices are functional
and compatible to two IDT7200/7201/7202/7203/7204/7205 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins. The devices use Full and Empty flags to prevent data overflow and
underflow and expansion logic to allow for unlimited expansion capability in both
word size and depth.
The reads and writes are internally sequential through the use of ring pointers,
with no address information required to load and unload data. Data is toggled
in and out of the devices through the use of the Write (W) and Read (R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity bits
at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability that allows for reset
of the read pointer to its initial position when RT is pulsed LOW to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. They are
designed for those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications.
FUNCTIONAL BLOCK DIAGRAM
WA WRITE
CONTROL
READ
CONTROL
RA
FLAG
LOGIC
EXPANSION
LOGIC
XIA
WRITE
POINTER READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA
OUTPUTS
RSA
FLA/RTA
XOA/HFA FFA EFA
WB
WRITE
CONTROL
READ
CONTROL
RB
FLAG
LOGIC
EXPANSION
LOGIC
XIB
WRITE
POINTER
RAM
ARRAY B
256 x 9
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA
OUTPUTS
RSB
FLB/RTB
3208 drw 01
XOB/HFB FFB EFB
(DA
0
-DA
8
)(DB
0
-DB
8
)
(QB
0
-QB
8
)
(QA
0
-QA
8
)
RAM
ARRAY A
256 x 9
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
2
COMMERCIAL TEMPERATURE RANGE
IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
JUNE 29, 2012
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Symbol Rating Com'l & Ind'l Unit
VTERM Terminal Voltage with –0.5 to +7.0 V
Respect to GND
TSTG Storage Temperature –55 to +125 °C
IOUT DC Output Current –50 to +50 mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
CAPACITANCE (TA = +25
o
C, f = 1.0 MHz)
Symbol Parameter Condition Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
COUT Output Capacitance VOUT = 0V 8 pF
NOTE:
1. Characterized values, not currently tested.
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
VIH(1) Input High Voltage 2.0 — — V
VIL(2) Input Low Voltage — — 0.8 V
TAOperating Temperature 0 — 70 °C
Commercial
TAOperating Temperature –40 — 85 °C
Industrial
NOTES:
1. For RT/RS/XI input, VIH = 2.6V (commercial).
2. 1.5V undershoots are allowed for 10ns once per cycle.
RECOMMENDED DC OPERATING
CONDITIONS
TSSOP (SO56-2, order code: PA)
TOP VIEW
FFA
QA0
QA1
QA2
QA3
QA8
GND
RA
QA4
QA5
QA6
QA7
XOA/HFA
EFA
FFB
QB0
QB1
QB2
QB3
QB8
GND
RB
QB4
QB5
QB6
QB7
XOB/HFB
EFB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
XIA
DA0
DA1
DA2
DA3
DA8
WA
VCC
DA4
DA5
DA6
DA7
FLA/RTA
RSA
XIB
DB0
DB1
DB2
DB3
DB8
WB
VCC
DB4
DB5
DB6
DB7
FLB/RTB
RSB
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
3208 drw 02
3208 drw 03
30pF*
1.1K
5V
TO
OUTPUT
PIN
680Ω
or equivalent circuit
IDT7280L IDT7283L
IDT7281L IDT7284L
IDT7282L IDT7285lL
Commercial & Industrial(1) Commercial & Industrial(1)
tA = 12, 15 ns tA = 12, 15 ns
Symbol Parameter Min. Max. Min. Max. Unit
ILI(2) Input Leakage Current (Any Input) –1 1 –1 — μA
ILO(3) Output Leakage Current –10 10 –10 10 μA
VOH Output Logic “1” Voltage IOH = –2mA 2.4 — 2.4 — V
VOL Output Logic “0” Voltage IOL = 8mA — 0.4 — 0.4 V
ICC1(4,5) Active Power Supply Current (both FIFOs) — 125(6) —150mA
ICC2(4,7) Standby Current (R=W=RS=FL/RT=VIH)—15—15mA
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
NOTES:
1.
Industrial temperature range product for the 15ns speed grade is available as a standard
device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. Tested at f = 20 MHz.
6. Typical ICC1 = 2*[15 + 2*fS + 0.02*CL*fS] (in mA) with VCC = 5V, TA = 25
o
C, fS = WCLK
frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V.
Figure 1. Output Load
* Includes scope and jig capacitances.
3
COMMERCIAL TEMPERATURE RANGE
IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
JUNE 29, 2012
Commercial Commercial & Industrial(2)
IDT7280L12 IDT7280L15
IDT7281L12 IDT7281L15
IDT7282L12 IDT7282L15
IDT7283L12 IDT7283L15
IDT7284L12 IDT7284L15
IDT7285L12 IDT7285L15
Symbol Parameter Min. Max. Min. Max. Unit
tSShift Frequency — 50 — 40 M H z
tRC Read Cycle Time 20 — 25 — ns
tAAccess Time — 12 — 15 ns
tRR Read Recovery Time 8 — 10 — ns
tRPW Read Pulse Width(3) 12 — 15 — ns
tRLZ Read Pulse Low to Data Bus at Low Z(4) 3—3—ns
tWLZ Write Pulse High to Data Bus at Low Z(4,5) 5—5—ns
tDV Data Valid from Read Pulse High 5 — 5 — ns
tRHZ Read Pulse High to Data Bus at High Z(4) —12—15ns
tWC Write Cycle Time 20 — 25 — ns
tWPW Write Pulse Width(3) 12 — 15 — ns
tWR Write Recovery Time 8 — 10 — ns
tDS Data Set-up Time 9 — 11 — ns
tDH Data Hold Time 0 — 0 — ns
tRSC Reset Cycle Time 20 — 25 — ns
tRS Reset Pulse Width(3) 12 — 15 — ns
tRSS Reset Set-up Time(4) 12 — 15 — ns
tRSR Reset Recovery Time 8 — 10 — ns
tRTC Retransmit Cycle Time 20 — 25 — ns
tRT Retransmit Pulse Width(3) 12 — 15 — ns
tRTS Retransmit Set-up Time(4) 12 — 15 — ns
tRTR Retransmit Recovery Time 8 — 10 — ns
tEFL Reset to Empty Flag Low — 12 — 25 ns
tHFH,FFH Reset to Half-Full and Full Flag High — 17 — 25 ns
tRTF Retransmit Low to Flags Valid — 20 — 25 ns
tREF Read Low to Empty Flag Low — 12 — 15 ns
tRFF Read High to Full Flag High — 14 — 15 ns
tRPE Read Pulse Width after EF High 12 — 15 — ns
tWEF Write High to Empty Flag High — 12 — 15 ns
tWFF Write Low to Full Flag Low — 14 — 15 ns
tWHF Write Low to Half-Full Flag Low — 17 — 25 ns
tRHF Read High to Half-Full Flag High — 17 — 25 ns
tWPF Write Pulse Width after FF High 12 — 15 — ns
tXOL Read/Write to XO Low — 12 — 15 ns
tXOH Read/Write to XO High — 12 — 15 ns
tXI XI Pulse Width(3) 12 — 15 — ns
tXIR XI Recovery Time 8 — 10 — ns
tXIS XI Set-up Time 8 — 10 — ns
NOTES:
1. Timings referenced as in AC Test Conditions.
2.
Industrial temperature range product for the 15ns speed grade is available as a standard device.
3. Pulse widths less than minimum value are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
AC ELECTRICAL CHARACTERISTICS(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
4
COMMERCIAL TEMPERATURE RANGE
IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
JUNE 29, 2012
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 – D8)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW state.
During reset, both internal read and write pointers are set to the first location.
A reset is required after power up before a write operation can take place. Both
the Read Enable (R) and Write Enable (W) inputs must be in the HIGH
state during the window shown in Figure 2, (i.e., tRSS before the rising
edge of RS) and should not change until tRSR after the rising edge of
RS. Half-Full Flag (HF) will be reset to HIGH after Reset (RS).
WRITE ENABLE (W)
A write cycle is initiated on the falling edge of this input if the Full Flag (FF)
is not set. Data set-up and hold times must be adhered to with respect to the rising
edge of the Write Enable (W). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (HF) will be set to LOW and will remain set until the
difference between the write pointer and read pointer is less than or equal to
one half of the total memory of the device. The Half-Full Flag (HF) is then reset
by the rising edge of the read operation.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read operation, the Full Flag
(FF) will go HIGH after tRFF, allowing a valid write to begin. When the FIFO is
full, the internal write pointer is blocked from W, so external changes in W will
not affect the FIFO when it is full.
READ ENABLE (R)
A read cycle is initiated on the falling edge of the Read E
nable (R) provided
the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis,
independent of any ongoing write operations. After Read Enable (R) goes
HIGH, the Data Outputs (Q
0
– Q
8
) will return to a high impedance condition until
the next Read operation. When all data has been read from the FIFO, the Empty
Flag (EF) will go LOW, allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high impedance state. Once a
valid write operation has been accomplished, the Empty Flag (EF) will go HIGH
after t
WEF
and a valid Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from R so external changes in R will not affect the FIFO
when it is empty.
FIRST LOAD/RETRANSMIT (FL/RT)
This is a dual-purpose input. In the Depth Expansion Mode, this pin is
grounded to indicate that it is the first loaded (see Operating Modes). In the Single
Device Mode, this pin acts as the retransmit input. The Single Device Mode is
initiated by grounding the Expansion In (XI).
These devices can be made to retransmit data when the Retransmit Enable
control (RT) input is pulsed LOW. A retransmit operation will set the internal read
pointer to the first location and will not affect the write pointer. Read Enable (R)
and Write Enable (W) must be in the HIGH state during retransmit. This feature
is useful when less than 256/512/1,024/2,048/4,096/8,192 writes are per-
formed between resets. The retransmit feature is not compatible with the Depth
Expansion Mode and will affect the Half-Full Flag (HF), depending on the
relative locations of the read and write pointers.
EXPANSION IN (XI)
This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate
an operation in the single device mode. Expansion In (XI) is connected to
Expansion Out (XO) of the previous device in the Depth Expansion or Daisy
Chain Mode.
OUTPUTS:
FULL FLAG (FF)
The Full Flag (FF) will go LOW, inhibiting further write operation, when the
write pointer is one location less than the read pointer, indicating that the
device is full. If the read pointer is not moved after Reset (RS), the Full-Flag (FF)
will go LOW after 256 writes for IDT7280, 512 writes for the IDT7281, 1,024
writes for the IDT7282, 2,048 writes for the IDT7283, 4,096 writes for the
IDT7284 and 8,192 writes for the IDT7285.
EMPTY FLAG (EF)
The Empty Flag (EF) will go LOW, inhibiting further read operations, when
the read pointer is equal to the write pointer, indicating that the device is
empty.
EXPANSION OUT/HALF-FULL FLAG (XO/HF)
This is a dual-purpose output. In the single device mode, when Expan-
sion In (XI) is grounded, this output acts as an indication of a half-full memory.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (HF) will be set LOW and will remain set until the
difference between the write pointer and read pointer is less than or equal
to one half of the total memory of the device. The Half-Full Flag (HF) is then reset
by using rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion
Out (XO) of the previous device. This output acts as a signal to the next device
in the Daisy Chain by providing a pulse to the next device when the previous
device reaches the last location of memory.
DATA OUTPUTS (Q0 – Q8)
Data outputs for 9-bit wide data. This data is in a high impedance
condition whenever Read (R) is in a HIGH state.
5
COMMERCIAL TEMPERATURE RANGE
IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
JUNE 29, 2012
Figure 4. Full Flag From Last Write to First Read
NOTES:
1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC.
2. W and R = VIH around the rising edge of RS.
Figure 2. Reset
Figure 3. Asynchronous Write and Read Operation
W
RS
R
EF
HF, FF
t
RSC
t
RS
t
RSS
t
RSS
t
RSR
t
EFL
t
HFH
, t
FFH
3208 drw 04
t
A
R
t
RC
DATA
OUT
VALID DATA
OUT
VALID
t
RPW
t
RLZ
t
DV
t
A
t
RHZ
t
RR
t
WC
t
WR
t
WPW
DATA
IN
VALID DATA
IN
VALID
t
DS
t
DH
Q
0
-Q
8
3208 drw 05
W
D
0
-D
8
LAST WRITE
R
IGNORED
WRITE
FIRST READ ADDITIONAL
READS
FIRST
WRITE
W
FF
t
WFF
t
RFF
3208 drw 06
6
COMMERCIAL TEMPERATURE RANGE
IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
JUNE 29, 2012
Figure 5. Empty Flag From Last Read to First Write
Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse
Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse
Figure 6. Retransmit
LAST READ
R
IGNORED
READ
FIRST WRITE ADDITIONAL
WRITES
FIRST
READ
W
EF
t
WEF
3208 drw 07
VALID VALID
t
A
DATA OUT
REF
t
t
RTC
t
RT
t
RTS
RT
W,R
HF, EF, FF
t
RTR
FLAG VALID
3208 drw 08
RTF
t
EF
W
R
tWEF
tRPE
3208 drw 09
FF
R
W
t
RFF
t
WPF
3208 drw 10
7
COMMERCIAL TEMPERATURE RANGE
IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
JUNE 29, 2012
Figure 9. Half-Full Flag Timing
Figure 10. Expansion Out
Figure 11. Expansion In
OPERATING MODES:
Care must be taken to assure that the appropriate flag is monitored by
each system (i.e. FF is monitored on the device where W is used; EF is monitored
on the device where R is used).
SINGLE DEVICE MODE
A single IDT7280/7281/7282/7283/7284/7285 may be used when the
application requirements are for 256/512/1,024/2,048/4,096/8,192 words or
less. These FIFOs are in a Single Device Configuration when the Expansion
In (XI) control input is grounded (see Figure 12).
DEPTH EXPANSION
These devices can easily be adapted to applications when the require-
ments are for greater than 256/512/1,024/2,048/4,096/8,192 words. Figure
14 demonstrates a four-FIFO Depth Expansion using two IDT7280/7281/
7282/7283/7284/7285s. Any depth can be attained by adding additional
IDT7280/7281/7282/7283/7284/7285s. These FIFOs operate in the Depth
Expansion mode when the following conditions are met:
1. The first FIFO must be designated by grounding the First Load (FL) control
input.
2. All other FIFOs must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to the Expansion
In (XI) pin of the next device. See Figure 14.
4. External logic is needed to generate a composite Full Flag (FF) and Empty
Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e. all
must be set to generate the correct composite FF or EF). See Figure 14.
5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in
the Depth Expansion Mode.
R
W
HF
tRHF
3208 drw 11
HALF-FULL OR LESS MORE THAN HALF-FULL HALF-FULL OR LESS
tWHF
R
W
XO
3208 drw 12
WRITE TO
LAST PHYSICAL
LOCATION
t
XOL
t
XOH
READ FROM
LAST PHYSICAL
LOCATION
t
XOL
t
XOH
W
XI
R
3208 drw 13
WRITE TO
FIRST PHYSICAL
LOCATION
READ FROM
FIRST PHYSICAL
LOCATION
tXIS
tXIR
tXI
tXIS
8
COMMERCIAL TEMPERATURE RANGE
IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
JUNE 29, 2012
Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 FIFO Memory Used in Width Expansion Mode
Figure 12. Block Diagram of One 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 FIFO Used in Single Device Mode
USAGE MODES:
WIDTH EXPANSION
Word width may be increased simply by connecting the corresponding input
control signals of multiple FIFOs. Status flags (EF, FF and HF) can be detected
from any one FIFO. Figure 13 demonstrates an 18-bit word width by using the
two FIFOs contained in the IDT7280/7281/7282/7283/7284/7285s. Any word
width can be attained by adding FIFOs (Figure 13).
BIDIRECTIONAL OPERATION
Applications which require data buffering between two systems (each
system capable of Read and Write operations) can be achieved by pairing
IDT7280/7281/7282/7283/7384/7285s as shown in Figure 16. Both Depth
Expansion and Width Expansion may be used in this mode.
DATA FLOW-THROUGH
Two types of flow-through modes are permitted, a read flow-through
and write flow-through mode. For the read flow-through mode (Figure 17),
the FIFO permits a reading of a single word after writing one word of data into
an empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising
edge of W, called the first write edge, and it remains on the bus until the R line
is raised from LOW-to-HIGH, after which the bus would go into a three-state
mode after tRHZ ns. The EF line would have a pulse showing temporary
deassertion and then would be asserted.
In the write flow-through mode (Figure 18), the FIFO permits the writing
of a single word of data immediately after reading one word of data from a
full FIFO. The R line causes the FF to be deasserted but the W line being LOW
causes it to be asserted again in anticipation of a new data word. On the rising
edge of W, the new word is loaded in the FIFO. The W line must be toggled when
FF is not asserted to write new data in the FIFO and to increment the write pointer.
COMPOUND EXPANSION
The two expansion techniques described above can be applied together
in a straightforward manner to achieve large FIFO arrays (see Figure 15).
WRITE (W)
DATA IN (D)
FULL FLAG (FF)
RESET (RS)
9
READ (R)
9
DATA OUT (Q)
EMPTY FLAG (EF)
RETRANSMIT (RT)
EXPANSION IN (XI)
(HF)
FIFO
A or B
IDT
7280
7281
7282
7283
7284
7285
(HALF-FULL FLAG)
3208 drw 14
XIA XIB
9
9
18
9
18
HFB
HFA
9
DATA
WRITE (W)
FULL FLAG (FFA)
RESET (RS)
(D)
IN
READ (R)
EMPTY FLAG (EFB)
RETRANSMIT (RT)
DATA (Q)
OUT
3208 drw 15
FIFO A FIFO B
7280/7281/7282/
7283/7284/7285
9
COMMERCIAL TEMPERATURE RANGE
IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
JUNE 29, 2012
Figure 14. Block Diagram of 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9, 16,384 x 9, 32,768 x 9 FIFO Memory (Depth Expansion)
TABLE 1 — RESET AND RETRANSMIT
Single Device Configuration/Width Expansion Mode
Inputs Internal Status Outputs
Mode RS RT XI Read Pointer Write Pointer EF FF HF
Reset 0 X 0 Location Zero Location Zero 0 1 1
Retransmit 1 0 0 Location Zero Unchanged X X X
Read/Write 1 1 0 Increment(1) Increment(1) XXX
NOTE:
1. Pointer will increment if flag is High.
TABLE 2 — RESET AND FIRST LOAD TRUTH TABLE
Depth Expansion/Compound Expansion Mode
Inputs Internal Status Outputs
Mode RS FL XI Read Pointer Write Pointer EF FF
Reset First Device 0 0 (1) Location Zero Location Zero 0 1
Reset All Other Devices 0 1 (1) Location Zero Location Zero 0 1
Read/Write 1 X (1) X X X X
NOTE: 10
1. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output,
XI = Expansion Input, HF = Half-Full Flag Output
D
W
FFB
EFB
FLB
XOB
RSA
FULL EMPTY
V
CC
R
9
9
99
XIB
9Q
FFA EFA
FLA
XOA
XIA
FFB EFB
FLB
XIB
3208 drw 16
XOA
FIFO A
FIFO B
FIFO A
FIFO B
XIA
XOB
EFA
FLA
FFA
7280/7281/
7282/7283/
7284/7285
7280/7281/
7282/7283/
7284/7285
10
COMMERCIAL TEMPERATURE RANGE
IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
JUNE 29, 2012
Figure 16. Bidirectional FIFO Mode
NOTES:
1. For depth expansion block see section on Depth Expansion and Figure 14.
2. For Flag detection see section on Width Expansion and Figure 13.
Figure 15. Compound FIFO Expansion
IDT7280/7281/
7282/7283/
7284/7285
DEPTH
EXPANSION
BLOCK
R, W, RS
D
0
-D
N
IDT7280/7281/
7282/7283/
7284/7285
DEPTH
EXPANSION
BLOCK
IDT7280/7281/
7282/7283/
7284/7285
DEPTH
EXPANSION
BLOCK
3208 drw 17
Q
0
-Q
8
D
9
-D
N
D
(N-8)
-D
N
D
18
-D
N
D
(N-8)
-D
N
D
9
-D
17
D
0
-D
8
Q
0
-Q
8
Q
9
-Q
17
Q
9
-Q
17
Q
(N-8)
-Q
N
Q
(N-8)
-Q
N
IDT
7201A
RA
EFA
HFA
WA
FFA
WB
FFB
SIDE 1 SIDE 2
QA0-8
DB0-8
QB0-8
RB
HFB
EFB
IDT
7280
7281
7282
7283
7284
7285
DA0-8
FIFO B
3208 drw 18
FIFO A
11
COMMERCIAL TEMPERATURE RANGE
IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
JUNE 29, 2012
Figure 17. Read Data Flow-Through Mode
W
DATA
R
t
RPE
IN
EF
DATA
OUT
t
WLZ
t
WEF
t
A
t
REF
DATA VALID
OUT
3208 drw 19
Figure 18. Write Data Flow-Through Mode
R
DATA
W
IN
FF
DATA OUT
tDS
tDH
tA
tWFF
tRFF
tWPF
DATA IN VALID
DATA OUT VALID
3208 drw 20
12
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753
San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com
www.idt.com
ORDERING INFORMATION
NOTE:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
XXXX
Device Type
XXX
Speed
X
Power
X
Package
X
Process/
Temperature
Range
Blank
I(1)
7280
7281
7282
7283
7284
7285
12
15
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
256 x 9 ⎯ CMOS Dual Asynchronous FIFO
512 x 9 ⎯ CMOS Dual Asynchronous FIFO
1,024 x 9 ⎯ CMOS Dual Asynchronous FIFO
2,048 x 9 ⎯ CMOS Dual Asynchronous FIFO
4,096 x 9 ⎯ CMOS Dual Asynchronous FIFO
8,192 x 9 ⎯ CMOS Dual Asynchronous FIFO
L Low Power
PA Thin Shrink SOIC (TSSOP, SO56-2)
Access Time (t
A
)
Speed in Nanoseconds
3208 drw 21
Commercial Only
Commercial and Industrial
G
Green
XX
Blank
8
Tube or Tray
Tape and Reel
DATASHEET DOCUMENT HISTORY
07/13/2001 pgs. 2, 3 and 12.
01/13/2009 pg. 12.
06/29/2012 pgs. 1 and 12.
