TESDV5V0A
Steering Diode Structure ESD Protection Array
Small Signal Diode
Meet IEC61000-4-4 (EFT) rating. 40A (5/50ήs)
Protects four high speed I/O lines
Working Voltage : 5V
Min Max Min Max
1.80 2.00 0.071 0.079
Case : SOT-363 standard package, molded plastic 1.15 1.35 0.045 0.053
0.15 0.30 0.006 0.012
- 1.10 - 0.043
Notebooks, Desktops, Servers and Video Graphics Cards
Monitors and Flat Panel Displays
Portable Instrumentation
Set Top Box
Part No. Package Packing Marking
TESDV5V0A SOT-363 3K / 7" Reel B54
Maximum Ratings and Electrical Characteristics
Maximum Ratings
Electrical Characteristics
1mA
5V
1A
3A
Pb free version, RoHS compliant, and Halogen free
G
Unit (mm) Unit (inch)
0.42 0.017
D
A
B
C
0.051 BSC
°C
V
6
-
-25
-
15
1
pF
W
Units
A
V
uA
0.083 BSC
2 (Typ.)
Terminal: Matte tin plated, lead free, solderable
per MIL-STD-202, Method 202 guaranteed
Meet IEC61000-4-2 (ESD) ±15kV (air), ±8kV (contact)
Marking Code : B54
Molding Compound Flammability Rating : UL 94V-O
Features
Mechanical Data
E
Dimensions
High temperature soldering guaranteed: 260°C/10s
KV
Type Number
Rating at 25°C ambient temperature unless otherwise specified.
Peak Pulse Power (tp=8/20μs waveform)
Weight :8 mg (approximately)
Ordering Information
Symbol
Packing Code
VESD
Max
Junction and Storage Temperature Range
PPP
TJ, TSTG
150
Peak Pulse Current (tp = 8/20μs) IPP 3
Type Number
Vc
Reverse Breakdown Volta
g
IR=
Reverse Leakage Current
IPP=
Clamping Voltage
VReverse Stand-Off Voltage
Units
Applications Pin Confi
g
utation
USB Power & Data Line Protection
RFG
±16
±8
Symbol
VRWM
-
F
SOT-363
5
ESD per IEC 61000-4-2 (Air)
ESD per IEC 61000-4-2 (Contact)
Value
.-55 to + 150.
Min
Junction Capacitance
IPP=
VR=
1.30 BSC
2.10 BSC
CJ
IR
V(BR)
VR=0V, f=1.0MHz
-
Version : A11
1
IO#1
2
GND
3
IO#2
6
IO#4
5
VDD
4
IO#3
TESDV5V0A
Steering Diode Structure ESD Protection Array
Small Signal Diode
Rating and Characteristic Curves
Ambient Tempeatature (oC)
FIG 4 Typical Junction Capacitance
0
0.4
0.8
1.2
1.6
2
012345
Normalized Capacitance
0
5
10
15
20
25
30
012345
Clamping Voltage (V)
FIG 5 Clamping Voltage vs. Peak Pulse Current
Peak Pulse Current (A)
Waveform Parameters:
tr = 8μs, td = 20μs
Reverse Voltage (V)
FIG 2 Pulse Waveform
0
10
20
30
40
50
60
70
80
90
100
110
0 5 10 15 20 25 30
Percent of IPP
0.01
0.1
1
10
0.1 1 10 100 1000
Peak Pulse Power Ppp (KW)
Pulse Duration (us) Time (us)
FIG 1 Non-Repetitive Peak Pulse Power vs. Pulse Time
Waveform Parameters:
tr = 8μs, td = 20μs
FIG 3 Admissible Power Dissipation Curve
0
40
80
120
160
200
0 20 40 60 80 100 120 140 160 180
Power Rating (%)
f = 1.0MHz
td=Ipp/2
e-1
Version : A11
TESDV5V0A
Steering Diode Structure ESD Protection Array
Small Signal Diode
Applications Information
TESDS5V0ALC incorporates eight surge rated, low capacitance steering diodes and a TVS diode in a single package
During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground
The internal TVS diode prevents over-voltage on the power line, protecting any downstream components
Circuit Board Layout Recommendations
Data Line Protection Using Internal TVS Diode as Reference
Designed to protect protect high speed data interfaces
Data Line and Power Supply Protection Using Vcc as reference Data Line Protection with Bias and Power Supply Isolation
Designed to protect four data lines from transient over-voltages by clamping them to a fixed reference
To protect data lines and the power line, connect pin 5 directly to the VDD. In this configuration the data lines are referenced to
the supply voltage. The internal TVS diode prevents over-voltage on the supply rail.
The TESDS5V0ALC can be isolated from the power supply by adding a series resistor between pin 5 and VDD. A value of 100kΩ is
recommended. The internal TVS and steering diodes remain biased, providing the advantage of lower capacitance.
²In applications where no positive supply reference is available, or complete supply isolation is desired, the internal TVS may
be used as the reference. In this case, pin 5 is not connected. The steering diodes will begin to conduct when the voltage
Designed to protect protect sensitive components which are connected to data and transmission lines from overvoltage caused by
electrostatic discharge (ESD), electrical fast transients (EFT), and lightning.
I/O#1
I/O#2
I/O#3
I/O#4
To
Protected
Device
To
Protected
Device
I/O#1
I/O#2
I/O#3
I/O#4
To
Protected
Device
To
Protected
Device
VDD
I/O#1
I/O#2
I/O#3
I/O#4
To
Protected
Device
To
Protected
Device
VDD
100K Ω
Version : A11
TESDV5V0A
Steering Diode Structure ESD Protection Array
Small Signal Diode
Tape & Reel specification
Suggested PAD Layout
Note 1: A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be
within 0.05 mm min. to 0.5 mm max. The component cannot rote more than 10 o within the determined cavity.
Note 2: If B1 exceeds 4.2 mm(0.165'') for 8 mm embossed tape, the tape may not feed through all tape feeders.
Note 3: The suggested land pattern dimensions have been provided for reference only, as actual pad layouts
may vary despending on application.
Item Symbol Dimension
( mm )
Carrier depth K 1.22 Max.
Sprocket hole D 1.50 +0.10
Reel outside diameter A 180 ± 1
Reel inner diameter D1 50 Min.
Feed hole width D2 13.0 ± 0.5
Sprocke hole position E 1.75 ±0.10
Sprocke hole pitch P0 4.00 ±0.10
Embossment center P1 2.00 ±0.10
Overall tape thickness T 0.6 Max.
Tape width W 8.30 Max.
Reel width W1 14.4 Max.
Dimensions Unit (inch) Unit (mm)
A 0.073 1.85
B 0.039 1.00
C 0.026 0.65
D 0.016 0.40
E 0.033 0.85
F 0.106 2.70
Direction of Feed
Top Cover Tape
Carieer Tape
Any Additional Label (If Required)
TSC label
W1
D1D2
A
Version : A11
For Machine Reference
Only
Including Draft and RADLL
Concentric Around B0
T
Top
Cover Tape
See Note1
B0
K Center Lines
of Cavity
F
E
W
For Components
2.0mm X 1.2mm
and Larger
D'
DP1
10 Pitches Cumulative
Tolerance on Tape
±2.0mm ( ±0.008")
B0
Embossment
A0
K0
B1
P0
C
D
AB
E
F
