8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet The SST39WF800B is a 512K x16 CMOS Multi-Purpose Flash (MPF) manufactured with proprietary, high-performance CMOS SuperFlash technology. The splitgate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared to alternate approaches. The SST39WF800B writes (Program or Erase) with a 1.65-1.95V power supply. This device conforms to JEDEC standard pin assignments for x16 memories Features * Organized as 512K x16 * Fast Erase and Word-Program - Sector-Erase Time: 36 ms (typical) - Block-Erase Time: 36 ms (typical) - Chip-Erase Time: 140 ms (typical) - Word-Program Time: 28 s (typical) * Single Voltage Read and Write Operations - 1.65-1.95V * Superior Reliability * Automatic Write Timing - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention - Internal VPP Generation * Low Power Consumption (typical values at 5 MHz) - Active Current: 5 mA (typical) - Standby Current: 5 A (typical) * Sector-Erase Capability - Uniform 2 KWord sectors * Block-Erase Capability - Uniform 32 KWord blocks * Fast Read Access Time - 70 ns * Latched Address and Data * End-of-Write Detection - Toggle Bit - Data# Polling * CMOS I/O Compatibility * JEDEC Standard - Flash EEPROM Pinouts and command sets * Packages Available - 48-ball TFBGA (6mm x 8mm) - 48-ball WFBGA (4mm x 6mm) Micro-Package - 48-ball XFLGA (5mm x 6mm) Micro-Package - 48-ball XFLGA (4mm x 6mm) Micro-Package * All devices are RoHS compliant (c)2011 Silicon Storage Technology, Inc. www.microchip.com DS25031A 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Product Description The SST39WF800B is a 512K x16 CMOS Multi-Purpose Flash (MPF) manufactured with SST proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared to alternate approaches. The SST39WF800B writes (Program or Erase) with a 1.65-1.95V power supply. This device conforms to JEDEC standard pin assignments for x16 memories. The SST39WF800B features high-performance Word-Programming which provides a typical WordProgram time of 28 sec. It uses Toggle Bit or Data# Polling to detect the completion of the Program or Erase operation. On-chip hardware and software data protection schemes protects against inadvertent writes. Designed, manufactured, and tested for a wide spectrum of applications, the SST39WF800B is offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39WF800B is suited for applications that require convenient and economical updating of program, configuration, or data memory. It significantly improves performance and reliability of all system applications while lowering power consumption. It inherently uses less energy during Erase and Program than alternative flash technologies. When programming a flash device, the total energy consumed is a function of the applied voltage, current, and time of application. For any given voltage range, SuperFlash technology uses less current to program and has a shorter erase time; therefore, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. SuperFlash technology provides fixed Erase and Program times independent of the number of Erase/ Program cycles that have occurred. Consequently, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet surface mount requirements, the SST39WF800B is offered in 48-ball TFBGA, 48-ball WFBGA, and a 48-ball XFLGA packages. See Figures 2 and 3 for pin assignments and Table 1 for pin descriptions. (c)2011 Silicon Storage Technology, Inc. DS25031A 2 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Block Diagram X-Decoder Memory Address SuperFlash Memory Address Buffer Latches Y-Decoder CE# OE# Control Logic I/O Buffers and Data Latches WE# DQ15 - DQ0 1344 B1.0 Figure 1: Functional Block Diagram (c)2011 Silicon Storage Technology, Inc. DS25031A 3 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Pin Assignments TOP VIEW (balls facing down) SST39WF800B 6 A2 A4 A6 A17 A1 A3 A7 NC A0 A5 A18 NC WE# NC NC A9 A11 NC A10 A13 A14 A8 A12 A15 5 4 3 CE# DQ8 DQ10 VSS OE# DQ9 DQ4 DQ11 A16 2 NC NC DQ5 DQ6 DQ7 1 DQ0 DQ1 DQ2 DQ3 A B C D VDD DQ12 DQ13 DQ14 DQ15 VSS E F G H J K L 1344 48-wfbga M2Q P02.0 Figure 2: Pin Assignments for 48-Ball WFBGA and 48-Ball XFLGA TOP VIEW (balls facing down) SST39WF800B 6 A13 A12 A14 A15 A16 A9 A8 A10 A11 DQ7 DQ14 DQ13 DQ6 WE# NC NC NC DQ5 DQ12 VDD DQ4 NC NC A18 NC DQ2 DQ10 DQ11 DQ3 A7 A17 A6 A5 A3 A4 A2 A1 A0 CE# OE# VSS A B C D E F 5 NC DQ15 VSS 4 3 2 DQ0 DQ8 DQ9 DQ1 1 G H 1344 48-tfbga P01.0 Figure 3: Pin Assignments for 48-ball TFBGA (c)2011 Silicon Storage Technology, Inc. DS25031A 4 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Table 1: Pin Description Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A11 address lines will select the sector. During Block-Erase AMS-A15 address lines will select the block. DQ15-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. To provide power supply voltage: VDD Power Supply VSS Ground NC No Connection 1.65-1.95V for SST39WF800B Unconnected pins. T1.0 25031 1. AMS = Most significant address AMS = A18 for SST39WF800B (c)2011 Silicon Storage Technology, Inc. DS25031A 5 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Device Operation Commands, which are used to initiate the memory operation functions of the device, are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Read The Read operation of the SST39WF800B is controlled by CE# and OE#; both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. See Figure 5. Word-Program Operation The SST39WF800B is programmed on a word-by-word basis. The sector where the word exists must be fully erased before programming. Programming is accomplished in three steps: 1. Load the three-byte sequence for Software Data Protection. 2. Load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. 3. Initiate the internal Program operation after the rising edge of the fourth WE# or CE#, whichever occurs first. Once initiated, the Program operation will be completed within 40 s. See Figures 6 and 7 for WE# and CE# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. (c)2011 Silicon Storage Technology, Inc. DS25031A 6 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Sector-/Block-Erase Operation The SST39WF800B offers both Sector-Erase and Block-Erase modes which allow the system to erase the device on a sector-by-sector, or block-by-block, basis. The sector architecture is based on uniform sector size of 2 KWord. Initiate the Sector-Erase operation by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase mode is based on uniform block size of 32 KWord. Initiate the Block-Erase operation by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 10 and 11 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. Chip-Erase Operation The SST39WF800B provides a Chip-Erase operation, which allows the user to erase the entire memory array to the `1' state. This is useful when the entire device must be quickly erased. Initiate the Chip-Erase operation by executing a six-byte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 9 for the timing diagram, and Figure 20 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. Write Operation Status Detection To optimize the system write cycle time, the SST39WF800B provides two software means to detect the completion of a Program or Erase write cycle. The software detection includes two status bits--Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The completion of the nonvolatile Write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may occur simultaneously with the completion of the Write cycle. If this occurs, the system may get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. To prevent spurious rejection in the event of an erroneous result, the software routine must include a loop to read the accessed location an additional two (2) times. If both Reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. (c)2011 Silicon Storage Technology, Inc. DS25031A 7 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Data# Polling (DQ7) When the SST39WF800B is in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is complete, DQ7 will produce true data. Although DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid. Valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During an internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is complete, DQ7 will produce a `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 18 for a flowchart. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating `1's and `0's, i.e., toggling between `1' and `0'. When the Program or Erase operation is complete, the DQ6 bit will stop toggling and the device is ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 0-1 for Toggle Bit timing diagram and Figure 18 for a flowchart. Data Protection The SST39WF800B provides both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.0V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST39WF800B provides the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the threebyte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. This group of devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. (c)2011 Silicon Storage Technology, Inc. DS25031A 8 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Common Flash Memory Interface (CFI) The SST39WF800A contains the CFI information that describes the characteristics of the device, and supports both the original SST CFI Query mode implementation for compatibility with existing SST devices, as well as the general CFI Query mode. To enter the SST CFI Query mode, the system must write the three-byte sequence, same as the Product ID Entry command, with 98H (CFI Query command) to address 5555H in the last byte sequence. To enter the general CFI Query mode, the system must write a one-byte sequence using the Entry command with 98H to address 55H. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 5 through 7. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. Product Identification The Product Identification mode identifies the device as the SST39WF800B and manufacturer as SST. This mode is accessed by software operations. Use Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 12 for the Software ID Entry and Read timing diagram, and Figure 19 for the Software ID Entry command sequence flowchart. Table 2: Product Identification Table Manufacturer's ID Address Data 0000H 00BFH 0001H 273EH Device ID SST39WF800B T2.0 25031 Product Identification Mode Exit/CFI Mode Exit To return to the standard Read mode, exit the Software Product Identification mode. Issue the Software ID Exit command sequence which returns the device to the Read mode. The Software ID Exit command may also be used to reset the device to the Read mode after any inadvertent transient condition that causes the device to behave abnormally, e.g., not read correctly. The Software ID Exit/CFI Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 14 for timing waveform, and Figure 19 for a flowchart. (c)2011 Silicon Storage Technology, Inc. DS25031A 9 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Operations Table 3: Operation Modes Selection Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Program VIL VIH VIL DIN AIN VIH VIL X1 Sector or Block address, XXH for Chip-Erase Erase VIL Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit Product Identification Software Mode See Table 4 T3.0 25031 1. X can be VIL or VIH, but no other value. Table 4: Software Command Sequence Command Sequence 1st Bus Write Cycle Addr1 Data2 2nd Bus Write Cycle Addr1 3rd Bus Write Cycle 4th Bus Write Cycle Data2 Addr1 Data2 Addr1 Data2 Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3 Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H Data AAH 5th Bus Write Cycle Addr1 2AAAH 6th Bus Write Cycle Data2 Addr1 Data2 55H SAX4 30H 50H 10H Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX4 Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H Software ID Entry5,6 5555H AAH 2AAAH 55H 5555H 90H SST CFI Query Entry5 5555H AAH 2AAAH 55H 5555H 98H General CFI Query Mode 55H 98H Software ID Exit7/ CFI Exit XXH F0H Software ID Exit7/ CFI Exit 5555H AAH 2AAAH 55H 5555H F0H T4.0 25031 1. Address format A14-A0 (Hex), Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence. AMS = Most significant address AMS = A18 for SST39WF800B 2. DQ15-DQ8 can be VIL or VIH, but no other value, for the Command sequence 3. WA = Program word address 4. SAX for Sector-Erase; uses AMS-A11 address lines BAX for Block-Erase; uses AMS-A15 address lines 5. The device does not remain in Software Product ID mode if powered down. 6. With AMS-A1 = 0; SST Manufacturer's ID = 00BFH, is read with A0 = 0, SST39WF800B Device ID = 273EH, is read with A0 = 1. 7. Both Software ID Exit operations are equivalent (c)2011 Silicon Storage Technology, Inc. DS25031A 10 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Table 5: CFI Query Identification String1 for SST39WF800B Address Data 10H 0051H Data 11H 0052H 12H 0059H 13H 0001H 14H 0007H 15H 0000H 16H 0000H 17H 0000H 18H 0000H 19H 0000H 1AH 0000H Query Unique ASCII string "QRY" Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T5.0 25031 1. Refer to CFI publication 100 for more details. Table 6: System Interface Information for SST39WF800B Address Data 1BH 0016H VDD Min (Program/Erase) Data 1CH 0020H VDD Max (Program/Erase) 1DH 0000H VPP min (00H = no VPP pin) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts 1EH 0000H VPP max (00H = no VPP pin) 1FH 0005H Typical time out for Word-Program 2N s (25 = 32 s) 20H 0000H Typical time out for min size buffer program 2N s (00H = not supported) 21H 0005H Typical time out for individual Sector/Block-Erase 2N ms (25 = 32 ms) 22H 0007H Typical time out for Chip-Erase 2N ms (27 = 128 ms) 23H 0001H Maximum time out for Word-Program 2N times typical (21 x 25 = 64 s) 24H 0000H Maximum time out for buffer program 2N times typical 25H 0001H Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 25 = 64 ms) 26H 0001H Maximum time out for Chip-Erase 2N times typical (21 x 27 = 256 ms) T6.0 25031 (c)2011 Silicon Storage Technology, Inc. DS25031A 11 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Table 7: Device Geometry Information for SST39WF800B Address Data 27H 0014H Device size = 2N Byte (14H = 20; 220 = 1 MByte) Data 28H 0001H Flash Device Interface description; 0001H = x16-only asynchronous interface 29H 0000H 2AH 0000H 2BH 0000H Maximum number of byte in multi-byte write = 2N (00H = not supported) 2CH 0002H Number of Erase Sector/Block sizes supported by device 2DH 00FFH Sector Information (y + 1 = Number of sectors; z x 256B = sector size) 2EH 0000H y = 255 + 1 = 256 sectors (00FFH = 255) 2FH 0010H 30H 0000H z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16) 31H 000FH Block Information (y + 1 = Number of blocks; z x 256B = block size) 32H 0000H y = 15 + 1 = 16 blocks (000FH = 15) 33H 0000H 34H 0001H z = 256 x 256 Bytes = 64 KByte/block (0100H = 256) T7.0 25031 (c)2011 Silicon Storage Technology, Inc. DS25031A 12 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Electrical Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 11V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Excluding certain with-Pb 32-PLCC units, all packages are 260C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240C for 10 seconds; please consult the factory for the latest information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time. Table 8: Operating Range Range Commercial Industrial Ambient Temp VDD 0C to +70C 1.65-1.95V -40C to +85C 1.65-1.95V T8.1 25031 Table 9: AC Conditions of Test1 Input Rise/Fall Time Output Load 5ns CL = 30 pF T9.1 25031 1. See Figures 15 and 16 (c)2011 Silicon Storage Technology, Inc. DS25031A 13 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Power-Up Specifications All functionalities and DC specifications are specified for a VDD ramp rate faster than 1V per 100 ms (0V to 1.8V in less than 180 ms). In addition, a VDD ramp rate slower than 1V per 20 s is recommended. See Table 10 and Figure 4 for more information. Table 10:Recommended System Power-up Timings Symbol Parameter Minimum Units TPU-READ1 VDD Min to Read Operation 100 s VDD Min to Write Operation 100 s TPU-WRITE 1 T10.0 25031 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TPU-READ VDD min VDD 0V CE# 1344 F37.1 Figure 4:Power-Up Reset Diagram (c)2011 Silicon Storage Technology, Inc. DS25031A 14 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet DC Characteristics Table 11:DC Operating Characteristics, VDD = 1.65-1.95V1 Limits Symbol Parameter Min Max Units Test Conditions Power Supply Current IDD Address input=VILT/VIHT, at f=5 MHz, VDD=VDD Max Read 15 mA CE#=VIL, OE#=WE#=VIH, all I/Os open Program and Erase 20 mA CE#=WE#=VIL, OE#=VIH ISB Standby VDD Current2 40 A CE#=VDD, VDD=VDD Max ILI Input Leakage Current 1 A VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 1 A VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage 0.2VDD 0.8VDD 0.1 VDD-0.1 VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min V VDD=VDD Max V IOL=100 A, VDD=VDD Min V IOH=-100 A, VDD=VDD Min T11.0 25031 1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25C (room temperature), and VDD = 1.8V. Not 100% tested. 2. 40 A is the maximum ISB for all SST39WF800B commercial grade devices. 40 A is the maximum ISB for all 39WF800A industrial grade devices. For all SST39WF800B commercial and industrial devices, ISB typical is under 5 A. Table 12:Capacitance (TA = 25C, f=1 MHz, other pins open) Parameter CI/O 1 CIN1 Description Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF T12.0 25031 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 13:Reliability Characteristics Symbol NEND 1,2 Parameter Minimum Specification Units Test Method Endurance 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA JEDEC Standard 78 TDR1 Data Retention ILTH1 Latch Up T13.0 25031 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification. (c)2011 Silicon Storage Technology, Inc. DS25031A 15 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet AC Characteristics Table 14:Read Cycle Timing Parameters 70 ns Symbol Parameter TRC Read Cycle Time TCE Chip Enable Access Time 70 ns TAA Address Access Time 70 ns TOE Output Enable Access Time TCLZ1 CE# Low to Active Output 0 TOLZ1 OE# Low to Active Output 0 TCHZ1 CE# High to High-Z Output 1 OE# High to High-Z Output TOHZ TOH1 Min Max Units 70 ns 35 ns ns ns 40 ns 40 Output Hold from Address Change ns 0 ns T14.0 25031 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. Table 15:Program/Erase Cycle Timing Parameters Symbol Parameter Min Max Units TBP Word-Program Time TAS Address Setup Time 0 40 s TAH Address Hold Time 50 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 50 ns ns TWP WE# Pulse Width 50 ns TWPH1 WE# Pulse Width High 30 ns 1 CE# Pulse Width High 30 ns TDS Data Setup Time 50 ns TDH1 TIDA1 Data Hold Time 0 Software ID Access and Exit Time 150 ns TCPH ns TSE Sector-Erase 50 ms TBE Block-Erase 50 ms TSCE Chip-Erase 200 ms T15.0 25031 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2011 Silicon Storage Technology, Inc. DS25031A 16 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet TRC TAA ADDRESS AMS-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# HIGH-Z DQ15-0 TCHZ TOH TCLZ DATA VALID HIGH-Z DATA VALID 1344 F03.0 Note: AMS = Most significant address AMS = A18 for SST39WF800B Figure 5: Read Cycle Timing Diagram INTERNAL PROGRAM OPERATION STARTS TBP 5555 ADDRESS AMS-0 2AAA 5555 ADDR TAH TDH TWP WE# TAS TWPH TDS OE# TCH CE# TCS DQ15-0 XXAA XX55 XXA0 DATA SW0 SW1 SW2 WORD (ADDR/DATA) 1344 F04.0 Note: AMS = Most significant address AMS = A18 for SST39WF800B X can be VIL or VIH, but no other value. Figure 6: WE# Controlled Program Cycle Timing Diagram (c)2011 Silicon Storage Technology, Inc. DS25031A 17 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet INTERNAL PROGRAM OPERATION STARTS TBP 5555 ADDRESS AMS-0 2AAA 5555 ADDR TAH TDH TCP CE# TAS TDS TCPH OE# TCH WE# TCS DQ15-0 XXAA XX55 XXA0 DATA SW0 SW1 SW2 WORD (ADDR/DATA) 1344 F05.0 Note: AMS = Most significant address AMS = A18 for SST39WF800B X can be VIL or VIH, but no other value. Figure 7: CE# Controlled Program Cycle Timing Diagram ADDRESS AMS-0 TCE CE# TOES TOEH OE# TOE WE# DQ7 DATA DATA# DATA# DATA 1344 F06.0 Note: AMS = Most significant address AMS = A18 for SST39WF800B Figure 8: Data# Polling Timing Diagram (c)2011 Silicon Storage Technology, Inc. DS25031A 18 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet ADDRESS AMS-0 TCE CE# TOEH TOES TOE OE# WE# DQ6 TWO READ CYCLES WITH SAME OUTPUTS 1344 F07.0 Note: AMS = Most significant address AMS = A18 for SST39WF800B FIGURE 0-1: TOGGLE BIT TIMING DIAGRAM TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555 CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 SW0 SW1 SW2 SW3 SW4 SW5 1344 F08.0 Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 15) AMS = Most significant address AMS = A18 for SST39WF800B X can be VIL or VIH, but no other value. Figure 9: WE# Controlled Chip-Erase Timing Diagram (c)2011 Silicon Storage Technology, Inc. DS25031A 19 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet TBE SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA BAX CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 SW0 SW1 SW2 SW3 SW4 SW5 1344 F09.0 Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 15) AMS = Most significant address AMS = A18 for SST39WF800B X can be VIL or VIH, but no other value. Figure 10:WE# Controlled Block-Erase Timing Diagram TSE SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA SAX CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 SW0 SW1 SW2 SW3 SW4 SW5 1344 F10.0 Note: This device also supports CE# controlled Sector-Erase operation The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 15) AMS = Most significant address AMS = A18 for SST39WF800B X can be VIL or VIH, but no other value. Figure 11:WE# Controlled Sector-Erase Timing Diagram (c)2011 Silicon Storage Technology, Inc. DS25031A 20 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001 CE# OE# TWP TIDA WE# TWPH DQ15-0 TAA XXAA XX55 XX90 SW0 SW1 SW2 00BF Device ID 1344 F11.0 Note: Device ID = 273FH for SST39WF800B X can be VIL or VIH, but no other value. Figure 12:Software ID Entry and Read THREE-BYTE SEQUENCE FOR SST CFI QUERY ENTRY ADDRESS A14-0 5555 2AAA 5555 CE# OE# TWP TIDA WE# TAA TWPH DQ15-0 XXAA XX55 XX98 SW0 SW1 SW2 1344 F12.0 Note: X can be VIL or VIH, but no other value. Figure 13:SST CFI Query Entry and Read (c)2011 Silicon Storage Technology, Inc. DS25031A 21 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A14-0 5555 DQ15-0 2AAA XXAA 5555 XX55 XXF0 TIDA CE# OE# TWP TWHP WE# SW0 SW1 SW2 1344 F13.0 Note: X can be VIL or VIH, but no other value. Figure 14:Software ID Exit/CFI Exit VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1344 F14.0 AC test inputs are driven at VIHT (VDD) for a logic `1' and VILT (VSS) for a logic `0'. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times are (10% 90%) <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test Figure 15:AC Input/Output Reference Waveforms (c)2011 Silicon Storage Technology, Inc. DS25031A 22 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet VDD TO TESTER 25K TO DUT CL 25K 1344 F15.0 Figure 16:A Test Load Example (c)2011 Silicon Storage Technology, Inc. DS25031A 23 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Start Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XXA0H Address: 5555H Load Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed Note: X can be VIL or VIH, but no other value. 1344 F16.0 Figure 17:Word-Program Algorithm (c)2011 Silicon Storage Technology, Inc. DS25031A 24 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read word Read DQ7 Read same word Program/Erase Completed No Is DQ7 = true data Yes No Does DQ6 match Program/Erase Completed Yes Program/Erase Completed 1344 F17.0 Figure 18:Wait Options (c)2011 Silicon Storage Technology, Inc. DS25031A 25 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet CFI Query Entry Command Sequence Software ID Entry Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXF0H Address: XXH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Wait TIDA Load data: XX98H Address: 5555H Load data: XX90H Address: 5555H Load data: XXF0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Wait TIDA Read CFI data Read Software ID Return to normal operation Note: Software ID Exit/CFI Exit Command Sequence X can be VIL or VIH, but no other value. 1344 F18.0 Figure 19:Software ID/CFI Command Flowcharts (c)2011 Silicon Storage Technology, Inc. DS25031A 26 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX10H Address: 5555H Load data: XX30H Address: SAX Load data: XX50H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH Note: X can be VIL or VIH, but no other value. 1344 F19.0 Figure 20:Erase Command Sequence (c)2011 Silicon Storage Technology, Inc. DS25031A 27 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Product Ordering Information SST 39 WF XX XX 800B XXXX - 70 XX - 4C XX - B3KE XXXX Environmental Attribute E1 = non-Pb Package Modifier K = 48 balls Q = 48 balls (66 possible positions) Package Type B3 = TFBGA (0.8mm pitch, 6mm x 8mm) C2 = XFLGA (0.5mm pitch, 5mm x 6mm) MA= WFBGA (0.5mm pitch, 4mm x 6mm) CA = XFLGA (0.5mm pitch, 4mm x 6mm) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns Device Density 800 = 8 Mbit Voltage W = 1.65-1.95V Product Series 39 = Multi-Purpose Flash 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". Valid combinations for SST39WF800B SST39WF800B-70-4C-B3KE SST39WF800B-70-4C-C2QE SST39WF800B-70-4C-MAQE SST39WF800B-70-4C-CAQE SST39WF800B-70-4I-B3KE SST39WF800B-70-4I-C2QE SST39WF800B-70-4I-MAQE SST39WF800B-70-4I-CAQE Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2011 Silicon Storage Technology, Inc. DS25031A 28 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Packaging Diagrams TOP VIEW BOTTOM VIEW 5.60 8.00 0.10 0.45 0.05 (48X) 0.80 6 6 5 5 4.00 4 4 6.00 0.10 3 3 2 2 1 1 0.80 A B C D E F G H A1 CORNER SIDE VIEW H G F E D C B A A1 CORNER 1.10 0.10 0.12 SEATING PLANE 1mm 0.35 0.05 Note: 1. Complies with JEDEC Publication 95, MO-210, variant AB-1 , although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm) 48-tfbga-B3K-6x8-450mic-5 Figure 21:48-Ball Thin-Profile, Fine-Pitch Ball Grid Array (TFBGA) 6mm x 8mm SST Package Code: B3K (c)2011 Silicon Storage Technology, Inc. DS25031A 29 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet TOP VIEW BOTTOM VIEW 6.00 0.08 6 5 4 3 2 1 5.00 0.50 5.00 0.08 0.29 0.05 (48X) 6 5 4 3 2 1 2.50 0.50 A B C D E F G H J K L L K J H G F E D C B A A1 INDICATOR4 A1 CORNER DETAIL 0.52 max. 0.473 nom. SIDE VIEW 0.08 SEATING PLANE 0.04 + 0.025/ - 0.015 1mm Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-222, this specific package is not registered. 2. All linear dimensions are in millimeters. 3. For low-profile mounting on PCB, SST recommends underfill for best solder joint reliability. 4. Coplanarity: 0.08 mm 48-xflga-C2Q-5x6-29mic-NR 5. No bump is present in position A1; a gold-colored indicator is present. Figure 22: 48-Ball Extremely Thin-Profile, Fine-Pitch Land Grid Array (XFLGA) 5mm x 6mm SST Package Code: C2Q (c)2011 Silicon Storage Technology, Inc. DS25031A 30 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet TOP VIEW BOTTOM VIEW 5.00 6.00 0.08 6 5 4 3 2 1 0.50 4.00 0.08 0.50 A1 CORNER DETAIL 6 5 4 3 2 1 2.50 A B C D E F G H J K L 0.32 0.05 (48X) L K J H G F E D C B A A1 INDICATOR 0.73 max. 0.636 nom. SIDE VIEW 0.08 SEATING PLANE 0.20 0.06 Note: 1mm 1. Complies with JEDEC Publication 95, MO-207, Variant CB-4 except nominal ball size is larger and bottom side A1 indicator is triangle at corner. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.08 mm 4. Ball opening size is 0.29 mm ( 0.05 mm) 48-wfbga-MAQ-4x6-32mic-2.0 Figure 23:48-Ball Very-Very-Thin-Profile, Fine-Pitch Ball Grid Array (WFBGA) 4mm x 6mm SST Package Code: MAQ (c)2011 Silicon Storage Technology, Inc. DS25031A 31 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet TOP VIEW BOTTOM VIEW 6.00 0.08 5.00 0.29 0.05 (48X) 0.50 6 5 4 3 2 1 4.00 0.08 2.50 0.50 A B C D E F G H J K L L K J H G F E D C B A A1 INDICATOR A1 CORNER DETAIL 6 5 4 3 2 1 0.52 max. 0.473 nom. SIDE VIEW 0.08 SEATING PLANE 0.04 +0.025/-0.015 1mm Note: 1. Complies with JEDEC Publication 95, MO-207, variant CZB-4, dimensions except the bump height is much less, and the A1 indicator is different. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.08 mm. 4. For low-profile mounting on PCB, SST recommends underfill for best solder joint reliability. 48-xflga-CAQ-4x6-29mic-6.0 Figure 24: 48-Ball Extremely Thin-Profile, Fine-Pitch Land Grid Array (XFLGA) 4mm x 6mm SST Package Code: CAQ (c)2011 Silicon Storage Technology, Inc. DS25031A 32 08/11 8 Mbit (x16) Multi-Purpose Flash SST39WF800B A Microchip Technology Company Data Sheet Table 16:Revision History Number 00 01 02 A Description * * * * * * * * * Initial release of data sheet Added "Power-Up Specifications" on page 14 Removed the M2QE and MBQE packages Added Y1QE package information EOL of all Y1QE parts. Replacement parts are MAQE parts listed in this document. Added information for the MAQE and CAQE packages. Applied new document format Released document under letter revision system Updated spec number from S71344 to DS25031 Date Feb 2007 Jul 2007 Dec 2009 Aug 2011 ISBN:978-1-61341-405-7 (c) 2011 Silicon Storage Technology, Inc-a Microchip Technology Company. All rights reserved. SST, Silicon Storage Technology, the SST logo, SuperFlash, MTP, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc. MPF, SQI, Serial Quad I/O, and Z-Scale are trademarks of Silicon Storage Technology, Inc. All other trademarks and registered trademarks mentioned herein are the property of their respective owners. Specifications are subject to change without notice. Refer to www.microchip.com for the most recent documentation. For the most current package drawings, please see the Packaging Specification located at http://www.microchip.com/packaging. Memory sizes denote raw storage capacity; actual usable capacity may be less. SST makes no warranty for the use of its products other than those expressly contained in the Standard Terms and Conditions of Sale. For sales office(s) location and information, please see www.microchip.com. Silicon Storage Technology, Inc. A Microchip Technology Company www.microchip.com (c)2011 Silicon Storage Technology, Inc. DS25031A 33 08/11