Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TLV733P SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 TLV733P Capacitor-Free, 300-mA, Low-Dropout Regulator in 1-mm x 1-mm SON Package 1 Features 3 Description * * * * The TLV733 series of low-dropout linear regulators (LDOs) are ultra-small, low quiescent current LDOs that can source 300 mA with good line and load transient performance. These devices provide a typical accuracy of 1%. 1 * * * * * * Input Voltage Range: 1.4 V to 5.5 V Stable Operation With or Without Capacitors Foldback Overcurrent Protection Packages: - 1.0-mm x 1.0-mm X2SON (4) - SOT-23 (5) Very Low Dropout: 125 mV at 300 mA (3.3 VOUT) Accuracy: 1% typical, 1.4% maximum Low IQ: 34 A Available in Fixed-Output Voltages: 1.0 V to 3.3 V High PSRR: 50 dB at 1 kHz Active Output Discharge The TLV733 provides an active pull-down circuit to quickly discharge output loads when disabled. 2 Applications * * * * * * The TLV733 series is designed with a modern capacitor-free architecture to ensure stability without an input or output capacitor. The removal of the output capacitor allows for a very small solution size, and can eliminate inrush current at startup. However, the TLV733 series is also stable with ceramic output capacitors if an output capacitor is necessary. The TLV733 also provides foldback current control during device power-up and enabling if an output capacitor is used. This functionality is especially important in battery-operated devices. Tablets Smartphones Notebook and Desktop Computers Portable Industrial and Consumer Products WLAN and Other PC Add-On Cards Camera Modules The TLV733 series is available in standard DBV (SOT-23) and DQN (X2SON) packages. Device Information(1) PART NUMBER TLV733P PACKAGE BODY SIZE (NOM) SOT-23 (5) 2.90 mm x 1.60 mm X2SON (4) 1.00 mm x 1.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. Typical Application Circuit Dropout Voltage vs Output Current 180 TLV733 CIN EN Optional ON OFF OUT 140 COUT GND VOUT = 3.3 V VOUT = 1.8 V 160 120 Optional VDO (mV) IN 100 80 60 40 20 0 0 30 60 90 120 150 180 IOUT (mA) 210 240 270 300 D020 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLV733P SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description ............................................ 12 7.1 Overview ................................................................. 12 7.2 Functional Block Diagram ....................................... 12 7.3 Feature Description................................................. 13 7.4 Device Functional Modes........................................ 14 8 Application and Implementation ........................ 15 8.1 Application Information............................................ 15 8.2 Typical Applications ............................................... 17 9 Power-Supply Recommendations...................... 19 10 Layout................................................................... 19 10.1 Layout Guidelines ................................................. 19 10.2 Layout Examples................................................... 19 11 Device and Documentation Support ................. 20 11.1 11.2 11.3 11.4 11.5 Device Support .................................................... Documentation Support ........................................ Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 20 20 20 20 20 12 Mechanical, Packaging, and Orderable Information ........................................................... 20 4 Revision History Changes from Revision A (December 2014) to Revision B Page * Changed Low Dropout Feature bullet value from 122 mV to 125 mV to match value in Electrical Characteristics ............. 1 * Changed VOUT labels on front page plot ................................................................................................................................. 1 * Changed min junction temperature value from -55 to -40 in Absolute Maximum Ratings table .......................................... 4 * Changed max junction temperature value from 160 to 150 in Absolute Maximum Ratings table ........................................ 4 * Changed max storage temperature value from 150 to 160 in Absolute Maximum Ratings table.......................................... 4 * Added test condition to line regulation parameter in Electrical Characteristics table............................................................. 5 * Changed unit for line regulation parameter from mV/V to mV ............................................................................................... 5 * Added test condition to load regulation parameter in Electrical Characteristics table .......................................................... 5 Changes from Original (October 2014) to Revision A Page * Changed top page header information for data sheet to reflect device family instead of individual devices......................... 1 * Changed Input Voltage Range Features bullet to be first in list ............................................................................................. 1 * Changed Typical Application Circuit on front page; corrected error in optional capacitor identification ................................ 1 * Changed format of I/O column contents and order of packages in Pin Functions table ....................................................... 3 * Moved storage temperature range specification to Absolute Maximum Ratings table ......................................................... 4 * Changed Handling Ratings table title to ESD Ratings, updated table format ........................................................................ 4 * Added new first row to the VDO parameter in the Electrical Characteristics table .................................................................. 5 * Changed condition text for Figure 34 .................................................................................................................................. 16 * Added Evaluation Module subsection ................................................................................................................................. 20 * Deleted Related Links section ............................................................................................................................................. 20 2 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P TLV733P www.ti.com SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View IN 1 GND 2 EN 3 5 OUT 4 NC DQN Package 4-Pin 1-mm x 1-mm X2SON Top View IN EN 4 3 1 2 OUT GND Pin Functions PIN NO. NAME DQN DBV I/O DESCRIPTION Enable pin. Drive EN greater than 0.9 V to turn on the regulator. Drive EN less than 0.35 V to put the LDO into shutdown mode. EN 3 3 I GND 2 2 -- IN 4 1 I NC N/A 4 -- No internal connection OUT 1 5 O Regulated output voltage pin. For best transient response, use a small 1-F ceramic capacitor from this pin to ground. See the Input and Output Capacitor Selection section for more details. -- -- The thermal pad is electrically connected to the GND node. Connect to the GND plane for improved thermal performance. Thermal pad Ground pin Input pin. A small capacitor is recommended from this pin to ground. See the Input and Output Capacitor Selection section for more details. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P 3 TLV733P SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating junction temperature range (unless otherwise noted); all voltages are with respect to GND (1) Voltage Current MIN MAX VIN -0.3 6.0 VEN -0.3 VIN + 0.3 VOUT -0.3 3.6 IOUT V Internally limited Output short-circuit duration A Indefinite Temperature (1) UNIT Operating junction, TJ -40 150 Storage, Tstg -65 160 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) 500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) MIN NOM MAX UNIT Input range, VIN 1.4 5.5 V Output range, VOUT 1.0 3.3 V Output current, IOUT 0 300 mA Enable range, VEN 0 VIN V -40 125 C Junction temperature, TJ 6.4 Thermal Information TLV733P THERMAL METRIC (1) DQN (X2SON) DBV (SOT-23) UNIT 4 PINS 5 PINS RJA Junction-to-ambient thermal resistance 218.6 228.4 C/W RJC(top) Junction-to-case (top) thermal resistance 164.8 151.5 C/W RJB Junction-to-board thermal resistance 164.9 55.8 C/W JT Junction-to-top characterization parameter 5.6 31.4 C/W JB Junction-to-board characterization parameter 163.9 54.8 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 131.4 N/A C/W (1) 4 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P TLV733P www.ti.com SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 6.5 Electrical Characteristics At operating temperature range (TJ = -40C to +125C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 F (unless otherwise noted). All typical values at TJ = 25C. PARAMETER VIN TEST CONDITIONS Input voltage DC output accuracy UVLO Undervoltage lockout VO(VI) Line regulation VO(IO) Load regulation Dropout voltage (1) VDO MIN TYP 1.4 TJ = 25C -40C TJ +125C -1% 1% -1.4% 1.4% 1.3 VIN falling 1.25 VI = VIN(nom) to VIN(nom) + 1 1 DQN package 16 DBV package 25 VOUT = 0.98 x VOUT(nom), IOUT = 300 mA UNIT 5.5 VIN rising IO = 1 mA to 300 mA MAX 1.4 V mV mV VOUT = 1.1 V, -40C TJ 85C 460 1.2 V VOUT < 1.5 V, -40C TJ 85C 420 1.5 V VOUT < 1.8 V, -40C TJ 85C 370 1.8 V VOUT < 2.5 V, -40C TJ 85C 270 2.5 V VOUT < 3.3 V, -40C TJ 85C V 260 VOUT = 3.3 V, -40C TJ 85C 125 220 1.2 V VOUT < 1.5 V, -40C TJ 125C 450 1.5 V VOUT < 1.8 V, -40C TJ 125C 400 1.8 V VOUT < 2.5 V, -40C TJ 125C 300 2.5 V VOUT < 3.3 V, -40C TJ 125C 290 VOUT = 3.3 V, -40C TJ 125C mV 125 270 IGND Ground pin current IOUT = 0 mA 34 60 A ISHDN Shutdown current VEN 0.35 V, 2.0 V VIN 5.5 V, TJ = 25C 0.1 1 A f = 100 Hz 68 PSRR Power-supply rejection ratio VOUT = 1.8 V, IOUT = 300 mA f = 10 kHz 35 f = 100 kHz 28 Vn Output noise voltage VEN(HI) EN pin high voltage (enabled) VEN(LO) EN pin low voltage (disabled) IEN EN pin current tSTR Startup time Pull-down resistor ILIM Output current limit IOS Short-circuit current limit Tsd Thermal shutdown (1) BW = 10 Hz to 100 kHz, VOUT = 1.8 V, IOUT = 10 mA 0.9 dB 120 VRMS 0.63 V 0.52 VEN = 5.5 V 0.01 Time from EN assertion to 98% x VOUT(nom), VOUT = 1.0 V, IOUT = 0 mA 250 Time from EN assertion to 98% x VOUT(nom), VOUT = 3.3 V, IOUT = 0 mA 800 VIN = 2.3 V 120 0.35 V A s 360 mA VOUT shorted to GND, VOUT = 1.0 V 150 VOUT shorted to GND, VOUT = 3.3 V 170 Shutdown, temperature increasing 160 Reset, temperature decreasing 140 mA C Dropout voltage for the TLV73310P is not valid at room temperature. The device engages undervoltage lockout (VIN < UVLOFALL) before the dropout condition is met. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P 5 TLV733P SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 www.ti.com 6.6 Typical Characteristics at operating temperature range (TJ = -40C to +125C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 F (unless otherwise noted) 1.03 1.004 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 1.02 0.996 VOUT (V) VOUT (V) 1.01 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 1 1 0.99 0.992 0.988 0.98 0.984 0.97 0.98 0.96 0.976 0 50 100 150 200 Current (mA) 250 300 0 50 TLV73310PDBV Figure 1. 1.0-V Load Regulation vs IOUT and Temperature 300 D005 1.8 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 1.797 1.794 VOUT (V) 1.8 VOUT (V) 250 Figure 2. 1.0-V Load Regulation vs IOUT and Temperature TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 1.808 1.792 1.784 1.791 1.788 1.776 1.785 1.768 1.782 1.76 1.779 0 50 100 150 200 Current (mA) 250 300 0 50 100 D002 TLV73318PDBV 150 200 Current (mA) 250 300 D006 TLV73318PDQN Figure 3. 1.8-V Load Regulation vs IO and Temperature Figure 4. 1.8-V Load Regulation vs IOUT and Temperature 3.345 3.32 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 3.33 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 3.312 3.304 VOUT (V) 3.315 VOUT (V) 150 200 Current (mA) TLV73310PDQN 1.816 3.3 3.285 3.296 3.288 3.27 3.28 3.255 3.272 3.24 3.264 0 50 100 150 200 Current (mA) 250 300 0 D003 TLV73333PDBV 50 100 150 200 Current (mA) 250 300 D007 TLV73333PDQN Figure 5. 3.3-V Load Regulation vs IOUT and Temperature 6 100 D001 Figure 6. 3.3-V Load Regulation vs IOUT and Temperature Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P TLV733P www.ti.com SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 Typical Characteristics (continued) at operating temperature range (TJ = -40C to +125C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 F (unless otherwise noted) 390 400 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 350 330 300 VDO (mV) VDO (mV) 300 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 360 250 200 270 240 210 180 150 150 120 100 90 60 50 0 30 60 90 120 150 180 Current (mA) 210 240 270 0 300 30 60 90 D024 TLV73312PDBV 210 240 270 300 D025 TLV73312PDQN Figure 7. 1.2-V Dropout Voltage vs IOUT and Temperature Figure 8. 1.2-V Dropout Voltage vs IOUT and Temperature 300 275 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 250 225 200 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 250 200 175 VDO (mV) VDO (mV) 120 150 180 Current (mA) 150 125 100 150 100 75 50 50 25 0 0 0 30 60 90 120 150 180 Current (mA) 210 240 270 300 0 30 60 90 D008 TLV73318PDBV 210 240 270 300 D010 TLV73318PDQN Figure 9. 1.8-V Dropout Voltage vs IOUT and Temperature Figure 10. 1.8-V Dropout Voltage vs IOUT and Temperature 300 300 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 250 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 250 200 VDO (mV) 200 VDO (mV) 120 150 180 Current (mA) 150 150 100 100 50 50 0 0 0 30 60 90 120 150 180 Current (mA) 210 240 270 300 0 D009 TLV73333PDBV 30 60 90 120 150 180 Current (mA) 210 240 270 300 D011 TLV73333PDQN Figure 11. 3.3-V Dropout Voltage vs IOUT and Temperature Figure 12. 3.3-V Dropout Voltage vs IOUT and Temperature Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P 7 TLV733P SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 www.ti.com Typical Characteristics (continued) at operating temperature range (TJ = -40C to +125C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 F (unless otherwise noted) 1.816 70 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 1.814 1.812 60 55 1.808 IGND (PA) VOUT (V) 1.81 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 65 1.806 1.804 50 45 40 1.802 1.8 35 1.798 30 1.796 25 2 2.5 3 3.5 4 VIN (V) 4.5 5 5.5 0 30 60 90 120 150 180 IOUT (mA) D019 D010 210 240 270 300 D012 TLV73318PDBV Figure 13. 1.8-V Regulation vs VIN (Line Regulation) and Temperature Figure 14. Ground Pin Current vs IOUT and Temperature 100 50 40 TJ = 25 qC 20 10 5 24 ISHDN (PA) IGND (PA) 32 16 2 1 0.5 0.2 0.1 0.05 8 0 0.5 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 0.02 0.01 1 1.5 2 2.5 3 3.5 VIN (V) 4 4.5 5 0 5.5 1 D013 2 3 VIN (V) 4 5 6 D015 IOUT = 0 mA Figure 15. Ground Pin Current vs VIN Figure 16. Shutdown Current vs VIN and Temperature 1 0.675 VEN(LO) VEN(HI) 0.9 0.625 0.8 0.6 0.7 0.575 0.6 VOUT (V) Enable Threshold (V) 0.65 0.55 0.525 0.5 0.4 0.5 0.3 0.475 0.2 0.45 0.1 0.425 -40 -20 0 20 40 60 TJ (qC) 80 100 120 140 D014 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 0 150 200 250 300 350 400 450 500 550 600 650 700 Foldback Current Limit (mA) D023 TLV73310PDBV Figure 17. Enable Threshold vs Temperature 8 Submit Documentation Feedback Figure 18. 1.0-V Foldback Current Limit vs IOUT and Temperature Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P TLV733P www.ti.com SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 Typical Characteristics (continued) at operating temperature range (TJ = -40C to +125C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 F (unless otherwise noted) 2 1.75 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 3 2.5 1.25 VOUT (V) VOUT (V) 1.5 3.5 TJ = -40 qC TJ = 0 qC TJ = 25 qC TJ = 85 qC TJ = 125 qC 1 2 1.5 0.75 1 0.5 0.5 0.25 0 150 200 250 300 350 400 Foldback Current Limit (mA) 450 0 150 500 200 D021 TLV73318PDBV 450 500 D022 TLV73333PDBV Figure 19. 1.8-V Foldback Current Limit vs IOUT and Temperature Figure 20. 3.3-V Foldback Current Limit vs IOUT and Temperature 80 10 No Output Capacitor 1 PF Output Capacitor VOUT = 1 V VOUT = 1.8 V VOUT = 3.3 V 5 Noise Density (PV/--Hz) 60 PSRR (dB) 250 300 350 400 Foldback Current Limit (mA) 40 20 2 1 0.5 0.2 0.1 0.05 0.02 0.01 0 10 20 50 100 1000 10000 Frequency (Hz) 100000 1000000 0.005 10 20 D017 TLV73318PDQN, IOUT = 300 mA 50 100 1000 10000 Frequency (Hz) 100000 1000000 D016 IOUT = 300 mA Figure 21. Power-Supply Rejection Ratio vs Frequency Figure 22. Output Spectral Noise Density VIN (2 V/div) VIN (2 V/div) VOUT (1 V/div, AC Coupled) VOUT (1 V/div, AC Coupled) Time (20 s/div) Time (20 s/div) TLV73318PDBV, IOUT = 10 mA, 1-F output capacitor TLV73318PDBV, IOUT = 300 mA, 1-F output capacitor Figure 23. Line Transient Figure 24. Line Transient Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P 9 TLV733P SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 www.ti.com Typical Characteristics (continued) at operating temperature range (TJ = -40C to +125C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 F (unless otherwise noted) VOUT (200 mV/div, AC Coupled) VOUT (200 mV/div, AC Coupled) ILOAD (100 mA/div) ILOAD (100 mA/div) Time (20 s/div) Time (20 s/div) TLV73310PDBV, VIN = 2.0 V, 1-F output capacitor, output current slew rate = 0.25 A/s TLV73310PDBV, VIN = 2.0 V, no output capacitor, output current slew rate = 0.25 A/s Figure 25. 1.0-V, 50-mA to 300-mA Load Transient Figure 26. 1.0 V, 50-mA to 300-mA Load Transient VOUT (100 mV/div, AC Coupled) VOUT (100 mV/div, AC coupled) ILOAD (100 mA/div) ILOAD (200 mA/div) Time (20 s/div) Time (50 s/div) TLV73333PDBV, VIN = 3.8 V,1-F output capacitor, output current slew rate = 0.25 A/s TLV73333PDBV, VIN = 3.8 V, no output capacitor, output current slew rate = 0.25 A/s Figure 27. 3.3 V, 50-mA to 300-mA Load Transient Figure 28. 3.3 V, 50-mA to 300-mA Load Transient VEN (500 mV/div) VIN (1 V/div) VOUT (1 V/div) ILOAD (200 mA/div) VOUT (500 mV/div) Time (100 s/div) Time (100 s/div) TLV73318PDBV, RL = 6.2 , VEN = VIN, 1-F output capacitor TLV73318PDBV, RL = 6.2 , 1-F output capacitor Figure 29. VIN Power-Up and Power-Down 10 Submit Documentation Feedback Figure 30. Startup with EN Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P TLV733P www.ti.com SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 Typical Characteristics (continued) at operating temperature range (TJ = -40C to +125C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA, VEN = VIN, and CIN = COUT = 1 F (unless otherwise noted) VOUT (500 mV/div) VEN (500 mV/div) VOUT (500 mV/div) ILOAD (200 mA/div) Time (100 s/div) Time (100 s/div) TLV73318PDBV, IOUT = 300 mA, 1-F output capacitor TLV73318PDBV, 1-F output capacitor Figure 31. Shutdown Response with Enable Figure 32. Foldback Current Limit Response Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P 11 TLV733P SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The TLV733 belongs to a new family of next-generation, low-dropout regulators (LDOs). These devices consume low quiescent current and deliver excellent line and load transient performance. These characteristics, combined with low noise, good PSRR with low dropout voltage, make this family of devices ideal for portable consumer applications. This family of regulators offers foldback current limit, shutdown, and thermal protection. The operating junction temperature for this family of devices is -40C to 125C. 7.2 Functional Block Diagram IN OUT Current Limit Thermal Shutdown UVLO EN 120 W Bandgap Logic TLV733 GND 12 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P TLV733P www.ti.com SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 7.3 Feature Description 7.3.1 Undervoltage Lockout (UVLO) The TLV733 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is greater than the rising UVLO voltage, UVLORISE. This circuit ensures that the device does not exhibit any unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry. During UVLO disable, the output is connected to ground with a 120- pulldown resistor. 7.3.2 Shutdown The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI) (0.9 V, minimum). Turn off the device by forcing the EN pin to drop below 0.35 V. If shutdown capability is not required, connect EN to IN. The TLV733 has an internal pulldown MOSFET that connects a 120- resistor to ground when the device is disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance (RL) in parallel with the 120- pulldown resistor. The time constant is calculated in Equation 1: 120 * RL t= * COUT 120 + RL (1) 7.3.3 Internal Foldback Current Limit The TLV733 has an internal foldback current limit that protects the regulator during fault conditions. The current allowed through the device is reduced as the output voltage falls. When the output is shorted, the LDO supplies a typical current of 150 mA. The output voltage is not regulated when the device is in current limit. In this condition, the output voltage is the product of the regulated current and the load resistance. When the device output is shorted, the PMOS pass transistor dissipates power [(VIN - VOUT) x IOS] until thermal shutdown is triggered and the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on. If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal Information table for more details. The foldback current-limit circuit limits the current allowed through the device to current levels lower than the minimum current limit at nominal VOUT current limit (ILIM) during startup. See Figure 18 to Figure 20 for typical foldback current limit values. If the output is loaded by a constant-current load during startup, or if the output voltage is negative when the device is enabled, then the load current demanded by the load may exceed the foldback current limit and the device may not rise to the full output voltage. For constant-current loads, disable the output load until the TLV733 has fully risen to its nominal output voltage. The TLV733 PMOS pass element has an intrinsic body diode that conducts current when the voltage at the OUT pin exceeds the voltage at the IN pin. Do not force the output voltage to exceed the input voltage because excessively high current may flow through the body diode. 7.3.4 Thermal Shutdown Thermal shutdown protection disables the output when the junction temperature rises to approximately 160C. Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the junction temperature cools to approximately 140C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits regulator dissipation, protecting it from damage as a result of overheating. Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product of the (VIN -VOUT) voltage and the load current. For reliable operation, limit junction temperature to 125C maximum. To estimate the margin of safety in a complete design, increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. The TLV733 internal protection circuitry protects against overload conditions but is not intended to be activated in normal operation. Continuously running the TLV733 into thermal shutdown degrades device reliability. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P 13 TLV733P SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 www.ti.com 7.4 Device Functional Modes 7.4.1 Normal Operation The device regulates to the nominal output voltage under the following conditions: * The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLO falling threshold. The input voltage is greater than the nominal output voltage added to the dropout voltage. The enable voltage has previously exceeded the enable rising threshold voltage and not decreased below the enable falling threshold. The output current is less than the current limit. The device junction temperature is less than the thermal shutdown temperature. * * * * 7.4.2 Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage is the same the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device is in a triode state and no longer controls the current through the LDO. Line or load transients in dropout may result in large output voltage deviations. 7.4.3 Disabled The device is disabled under the following conditions: * The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold. * The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising threshold. * The device junction temperature is greater than the thermal shutdown temperature. When the device is disabled, the active pulldown resistor discharges the output. Table 1 shows the conditions that lead to the different modes of operation. Table 1. Device Functional Mode Comparison PARAMETER OPERATING MODE VIN VEN IOUT TJ Normal mode VIN > VOUT(nom) + VDO and VIN > UVLORISE VEN > VEN(HI) IOUT < ILIM TJ < 160C Dropout mode UVLORISE < VIN < VOUT(nom) + VDO VEN > VEN(HI) IOUT < ILIM TJ < 160C VIN < UVLOFALL VEN < VEN(LO) -- TJ > 160C Disabled mode (any true condition disables the device) 14 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P TLV733P www.ti.com SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 8 Application and Implementation 8.1 Application Information 8.1.1 Input and Output Capacitor Selection The TLV733 uses an advanced internal control loop to obtain stable operation both with and without the use of input or output capacitors. Dynamic performance is improved with the use of an output capacitor, and may be improved with an input capacitor. An output capacitance of 0.1 F or larger generally provides good dynamic response. Use X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value and equivalent series resistance (ESR) over temperature. Although an input capacitor is not required for stability, increased output impedance from the input supply may compromise the performance of the TLV733. Good analog design practice is to connect a 0.1-F to 1-F capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response, input ripple, and PSRR. Use an input capacitor if the source impedance is greater than 0.5 . Use a higher-value capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several inches from the input power source. Figure 33 shows the transient performance improvements with an external 1-F capacitor on the output versus no output capacitor. The data in this figure are taken with an increasing load step from 50 mA to 300 mA, and the peak output voltage deviation (load transient response) is measured. For low output current slew rates, (< 0.1 A/s), the transient performance of the device is similar with or without an output capacitor. As the current slew rate is increased, the peak voltage deviation is significantly increased. For loads that exhibit fast current slew rates above 0.1 A/s, use an output capacitor. For best performance, the maximum recommended output capacitance is 100 F. Peak Output Voltage Change (%VOUT) 35 30 1 PF COUT COUT Removed 25 20 15 10 5 0 0.01 0.02 0.03 0.050.07 0.1 0.2 0.3 0.5 0.7 Output Load Transient Slew Rate (A/Ps) 1 D027 TLV73333PDBV, output current stepped from 50 mA to 300 mA, output voltage change measured at positive dI/dt Figure 33. Output Voltage Deviation vs Load Step Slew Rate Some applications benefit from the removal of the output capacitor. In addition to space and cost savings, the removal of the output capacitor lowers inrush current as a result of eliminating the required current flow into the output capacitor upon startup. In these cases, take care to ensure that the load is tolerant of the additional output voltage deviations. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P 15 TLV733P SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 www.ti.com Application Information (continued) 8.1.2 Dropout Voltage The TLV733 uses a PMOS pass transistor to achieve low dropout. When (VIN - VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as (VIN - VOUT) approaches dropout operation. See Figure 7 to Figure 12 for typical dropout values. 8.1.3 Power Dissipation The ability to remove heat from the die is different for each package type, presenting different considerations in the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to ambient air. Performance data for JEDEC high-K boards are given in the Thermal Information table. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness. Power dissipation (PD) depends on input voltage and load conditions. PD is equal to the product of the output current and voltage drop across the output pass element, as shown in Equation 2. PD = (VIN - VOUT) x IOUT (2) Maximum Ambient Temperature (qC) Figure 34 shows the maximum ambient temperature versus the power dissipation of the TLV733 in the DQN package. This figure assumes the device is soldered on JEDEC standard high-K layout with no airflow over the board. Actual board thermal impedances vary widely. If the application requires high power dissipation, having a thorough understanding of the board temperature and thermal impedances is helpful to make sure the TLV733 does not operate continuously above a junction temperature of 125C. 125 120 115 110 105 100 95 90 85 80 75 70 65 60 55 TLV733 DQN, High-K Layout TLV733 DBV, High-K Layout 0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 Power Dissipation (W) 0.3 D028 TLV733, high-K layout Figure 34. Maximum Ambient Temperature vs Device Power Dissipation 16 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P TLV733P www.ti.com SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 8.2 Typical Applications 8.2.1 DC-DC Converter Post Regulation VOUT 1.8 V IN CIN 1 F DC-DC Converter OUT VOUT 1.5 V COUT 1 F TLV733 EN Load GND ON OFF Figure 35. DC-DC Converter Post Regulation 8.2.1.1 Design Requirements Table 2. Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 1.8 V, 5% Output voltage 1.5 V, 1% Output current 200-mA dc, 300-mA peak Output voltage transient deviation < 10%, 1-A/s load step from 50 mA to 200 mA Maximum ambient temperature 85C 8.2.1.2 Design Considerations Input and output capacitors are required to achieve the output voltage transient requirements. Capacitance values of 1 F are selected to give the maximum output capacitance in a small, low-cost package. Figure 7 shows the 1.2-V option dropout voltage. Given that dropout voltages are higher for lower output-voltage options, and given that the 1.2-V option dropout voltage is typically less than 300 mV at 125C, then the 1.5-V option dropout voltage is typically less than 300 mV at 125C. Verify that the maximum junction temperature is not exceeded by referring to Figure 34. 8.2.1.3 Application Curve VIN (500 mV/div) VOUT (500 mV/div) IOUT (100 mA/div) Time (50 s/div) Figure 36. 1.8-V to 1.5-V Regulation at 300 mA Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P 17 TLV733P SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 www.ti.com 8.2.2 Capacitor-Free Operation from Battery Input Supply IN OUT TLV733 VBAT Load EN GND Figure 37. Capacitor-Free Operation from Battery Input Supply 8.2.2.1 Design Requirements Table 3. Design Parameters PARAMETER DESIGN REQUIREMENT Input voltage 3.0 V to 1.8 V (two 1.5-V batteries) Output voltage 1.0 V, 1% Input current 200 mA, maximum Output load 100-mA dc Maximum ambient temperature 70C 8.2.2.2 Design Considerations An input capacitor is not required for this design because of the low impedance connection directly to the battery. No output capacitor allows for the minimal possible inrush current during startup, ensuring the 200-mA maximum input current is not exceeded. Verify that the maximum junction temperature is not exceeded by referring to Figure 34. 8.2.2.3 Application Curve VIN (1 V/div) VOUT (500 mV/div) IIN (100 mA/div) Time (50 s/div) Figure 38. No Inrush Startup, 3.0-V to 1.0-V Regulation 18 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P TLV733P www.ti.com SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 9 Power-Supply Recommendations Connect a low output impedance power supply directly to the IN pin of the TLV733. Inductive impedances between the input supply and the IN pin can create significant voltage excursions at the IN pin during startup or load transient events. If inductive impedances are unavoidable, use an input capacitor. 10 Layout 10.1 Layout Guidelines * * * * Place input and output capacitors as close to the device as possible. Use copper planes for device connections, in order to optimize thermal performance. Place thermal vias around the device to distribute the heat. Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder joint on the thermal pad. 10.2 Layout Examples VOUT VIN TLV733 1 4 COUT* CIN* 3 2 GND PLANE Represents via used for application specific connections *not required Figure 39. Layout Example for the DQN package VOUT VIN 1 CIN* 5 COUT* 2 3 4 GND PLANE Represents via used for application specific connections *not required Figure 40. Layout Example for the DBV Package Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P 19 TLV733P SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Evaluation Module An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV733. The TLV73312PEVM-643 evaluation module (and related user guide) can be requested at the Texas Instruments website through the product folders or purchased directly from the TI eStore. 11.1.2 Device Nomenclature Table 4. Device Nomenclature (1) (2) (1) (2) PRODUCT VOUT TLV733xx(x)Pyyyz xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V). P indicates an active output discharge feature. All members of the TLV733 family will actively discharge the output when the device is disabled. yyy is the package designator. z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces). For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the device product folder on www.ti.com. Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability. 11.2 Documentation Support 11.2.1 Related Documentation TLV73312PDQN-643 Evaluation Module User Guide, SBVU024 11.3 Trademarks All trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 20 Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P TLV733P www.ti.com SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 PACKAGE OUTLINE DQN0004A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4215302/D 06/2016 NOTES: 1. 2. 3. 4. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. This drawing is subject to change without notice. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P 21 TLV733P SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 www.ti.com EXAMPLE BOARD LAYOUT DQN0004A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4215302/D 06/2016 NOTES: (continued) 22 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 6. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P TLV733P www.ti.com SBVS235B - OCTOBER 2014 - REVISED NOVEMBER 2015 EXAMPLE STENCIL DESIGN DQN0004A X2SON - 0.4 mm max height PLASTIC SMALL OUTLINE - NO LEAD 4215302/D 06/2016 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. Submit Documentation Feedback Copyright (c) 2014-2015, Texas Instruments Incorporated Product Folder Links: TLV733P 23 PACKAGE OPTION ADDENDUM www.ti.com 9-Oct-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TLV73310PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 VCCQ TLV73310PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 VCCQ TLV73310PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FG TLV73310PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FG TLV73311PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ZBLW TLV73311PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ZBLW TLV73311PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 GR TLV73311PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 GR TLV73312PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 VCDQ TLV73312PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 VCDQ TLV73312PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FI TLV73312PDQNR3 ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FI TLV73312PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FI TLV73315PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 VCFQ TLV73315PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 VCFQ TLV73315PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FJ TLV73315PDQNR3 ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FJ Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 9-Oct-2016 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TLV73315PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FJ TLV73318PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 VCGQ TLV73318PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 VCGQ TLV73318PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FK TLV73318PDQNR3 ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FK TLV73318PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FK TLV73325PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 VCHQ TLV73325PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 VCHQ TLV73325PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FL TLV73325PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FL TLV733285PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ZDRW TLV733285PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ZDRW TLV733285PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 GZ TLV733285PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 GZ TLV73328PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ZDQW TLV73328PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ZDQW TLV73328PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 GY TLV73328PDQNR3 ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 GY Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 9-Oct-2016 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TLV73328PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 GY TLV73330PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ZDMW TLV73330PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 ZDMW TLV73330PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 GW TLV73330PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 GW TLV73333PDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 VCIQ TLV73333PDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 VCIQ TLV73333PDQNR ACTIVE X2SON DQN 4 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FM TLV73333PDQNT ACTIVE X2SON DQN 4 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 125 FM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 3 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 9-Oct-2016 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TLV733P : * Automotive: TLV733P-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 3-May-2017 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ TLV73310PDBVR SOT-23 3000 178.0 9.0 DBV 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 TLV73310PDBVT SOT-23 DBV 5 250 178.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TLV73310PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73310PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73311PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV73311PDBVT SOT-23 DBV 5 250 178.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TLV73311PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73311PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73312PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV73312PDBVT SOT-23 DBV 5 250 178.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TLV73312PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73312PDQNR3 X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q3 TLV73312PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73315PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV73315PDBVT SOT-23 DBV 5 250 178.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TLV73315PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73315PDQNR3 X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q3 TLV73315PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 3-May-2017 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TLV73318PDBVR SOT-23 DBV 5 3000 178.0 9.0 TLV73318PDBVT SOT-23 DBV 5 250 178.0 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 3.23 3.17 1.37 4.0 8.0 Q3 TLV73318PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73318PDQNR3 X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q3 TLV73318PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73325PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV73325PDBVT SOT-23 DBV 5 250 178.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TLV73325PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73325PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV733285PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV733285PDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV733285PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV733285PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73328PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV73328PDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV73328PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73328PDQNR3 X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q3 TLV73328PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73330PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV73330PDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV73330PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73330PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73333PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3 TLV73333PDBVT SOT-23 DBV 5 250 178.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3 TLV73333PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 TLV73333PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 3-May-2017 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV73310PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV73310PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TLV73310PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TLV73310PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TLV73311PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV73311PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TLV73311PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TLV73311PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TLV73312PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV73312PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TLV73312PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TLV73312PDQNR3 X2SON DQN 4 3000 184.0 184.0 19.0 TLV73312PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TLV73315PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV73315PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TLV73315PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TLV73315PDQNR3 X2SON DQN 4 3000 184.0 184.0 19.0 TLV73315PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TLV73318PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV73318PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 Pack Materials-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 3-May-2017 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV73318PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TLV73318PDQNR3 X2SON DQN 4 3000 184.0 184.0 19.0 TLV73318PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TLV73325PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV73325PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TLV73325PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TLV73325PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TLV733285PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV733285PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TLV733285PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TLV733285PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TLV73328PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV73328PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TLV73328PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TLV73328PDQNR3 X2SON DQN 4 3000 184.0 184.0 19.0 TLV73328PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TLV73330PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV73330PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TLV73330PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TLV73330PDQNT X2SON DQN 4 250 184.0 184.0 19.0 TLV73333PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0 TLV73333PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0 TLV73333PDQNR X2SON DQN 4 3000 184.0 184.0 19.0 TLV73333PDQNT X2SON DQN 4 250 184.0 184.0 19.0 Pack Materials-Page 4 PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com PACKAGE OUTLINE DBV0005A SOT-23 - 1.45 mm max height SCALE 4.000 SMALL OUTLINE TRANSISTOR C 3.0 2.6 1.75 1.45 PIN 1 INDEX AREA 1 0.1 C B A 5 2X 0.95 1.9 1.45 MAX 3.05 2.75 1.9 2 4 0.5 5X 0.3 0.2 3 (1.1) C A B 0.15 TYP 0.00 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/C 04/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. www.ti.com EXAMPLE BOARD LAYOUT DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X (0.95) 3 4 (R0.05) TYP (2.6) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS 4214839/C 04/2017 NOTES: (continued) 4. Publication IPC-7351 may have alternate designs. 5. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DBV0005A SOT-23 - 1.45 mm max height SMALL OUTLINE TRANSISTOR PKG 5X (1.1) 1 5 5X (0.6) SYMM (1.9) 2 2X(0.95) 4 3 (R0.05) TYP (2.6) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X 4214839/C 04/2017 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 7. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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