64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM SMALL-OUTLINE DDR SDRAM DIMM MT5VDDT872H - 64MB MT5VDDT1672H - 128MB For the latest data sheet, please refer to the Microna Web site: www.micron.com/moduleds Features Figure 1: 200-Pin SODIMM (MO-224) * JEDEC standard 200-pin, small-outline, dual in-line memory module (DDR SODIMM) * Fast data transfer rates PC1600, PC2100, or PC2700 * Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR SDRAM components * 64MB (8 Meg x 72) and 128MB (16 Meg x 72) * ECC-1-bit error detection and correction * VDD = VDDQ= +2.5V * VDDSPD = +2.3V to +3.6V * 2.5V I/O (SSTL_2 compatible) * Commands entered on each positive CK edge * DQS edge-aligned with data for READs; centeraligned with data for WRITEs * Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle * Bidirectional data strobe (DQS) transmitted/ received with data--i.e., source-synchronous data capture * Differential clock inputs (CK and CK#) * Four internal device banks for concurrent operation * Selectable burst lengths: 2, 4, or 8 * Auto precharge option * Auto Refresh and Self Refresh Modes 15.625s (64MB); 7.8125s (128MB) maximum average periodic refresh interval * Serial Presence Detect (SPD) with EEPROM * Selectable READ CAS latency for maximum compatibility * Gold edge contacts OPTIONS MARKING * Package 200-pin SODIMM (Standard) 200-pin SODIMM (Lead-free)1 * Memory Clock/Speed/CAS Latency2 6ns (167 MHz), 333 MT/s, CL = 2.5 7.5ns (133 MHz), 266 MT/s, CL = 2 7.5ns (133 MHz), 266 MT/s, CL = 2 7.5ns (133 MHz), 266 MT/s, CL = 2.5 10ns (100 MHz), 200 MT/s, CL = 2 NOTE: -335 -262 -26A -265 -202 1. Consult factory for availability of lead-free products. 2. CL = Device CAS (READ) Latency Table 1: Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN G Y 1 64MB 128MB 4K 4K (A0-A11) 4 (BA0, BA1) 8 Meg x 16 512 (A0-A8) 1 (S0#) 8K 8K(A0-A12) 4 (BA0, BA1) 16 Meg x 16 512 (A0-A8) 1 (S0#) (c)2003 Micron Technology, Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 2: Part Numbers and Timing Parameters PART NUMBER MT5VDDT872HG-335__ MT5VDDT872HY-335__ MT5VDDT872HG-262__ MT5VDDT872HY-262__ MT5VDDT872HG-26A__ MT5VDDT872HY-26A__ MT5VDDT872HG-265__ MT5VDDT872HY-265__ MT5VDDT872HG-202__ MT5VDDT872HY-202__ MT5VDDT1672HG-335__ MT5VDDT1672HY-335__ MT5VDDT1672HG-262__ MT5VDDT1672HY-262__ MT5VDDT1672HG-26A__ MT5VDDT1672HY-26A__ MT5VDDT1672HG-265__ MT5VDDT1672HY-265__ MT5VDDT1672HG-202__ MT5VDDT1672HY-202__ MODULE DENSITY 64MB 64MB 64MB 64MB 64MB 64MB 64MB 64MB 64MB 64MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB MODULE CONFIGURATION BANDWIDTH 8 Meg x 72 8 Meg x 72 8 Meg x 72 8 Meg x 72 8 Meg x 72 8 Meg x 72 8 Meg x 72 8 Meg x 72 8 Meg x 72 8 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 2.7GB/s 2.7GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 1.6GB/s 1.6GB/s 2.7GB/s 2.7GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 2.1GB/s 1.6GB/s 1.6GB/s MEMORY CLOCK/ DATA RATE CLOCK LATENCY (CL - tRCD - tRP) 6ns,333MT/s 6ns,333MT/s 7.5ns,266MT/s 7.5ns,266MT/s 7.5ns,266MT/s 7.5ns,266MT/s 7.5ns,266 MT/s 7.5ns,266 MT/s 10ns,200MT/s 10ns,200MT/s 6ns,333MT/s 6ns,333MT/s 7.5ns,266MT/s 7.5ns,266MT/s 7.5ns,266MT/s 7.5ns,266MT/s 7.5ns,266 MT/s 7.5ns,266 MT/s 10ns,200MT/s 10ns,200MT/s 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT5VDDT1672HG-265A1. 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 3: Pin Assignment (200-Pin SODIMM Front) Table 4: Pin Assignment (200-Pin SODIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0# VSS DQ16 DQ17 VDD DQS2 DQ18 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 NC VSS CK2 CK2# VDD NC NC NC/A12 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 A9 VSS A7 A5 A3 A1 VDD A10 BA0 WE# S0# NC VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS 151 DQ42 153 DQ43 155 VDD 157 VDD 159 VSS 161 VSS 163 DQ48 165 DQ49 167 VDD 169 DQS6 171 DQ50 173 VSS 175 DQ51 177 DQ56 179 VDD 181 DQ57 183 DQS7 185 VSS 187 DQ58 189 DQ59 191 VDD 193 SDA 195 SCL 197 VDDSPD 199 NC VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7 NC VSS VSS VDD VDD CKE0 NC A11 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 A8 VSS A6 A4 A2 A0 VDD BA1 RAS# CAS# NC NC VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DQ46 DQ47 VDD CK1# CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 NC NOTE: Pin 99 is NC for 64MB, A12 for 128MB. Figure 2: 200-Pin SODIMM Module Layout Back View Front View U6 U1 U2 PIN 1 U3 (all odd pins) U5 U4 PIN 200 PIN 199 Indicates a VDD or VDDQ pin 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 3 (all even pins) PIN 2 Indicates a VSS pin Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS 118, 119, 120 35, 37, 89, 91, 158, 160 SYMBOL TYPE DESCRIPTION WE#, CAS#, RAS# CK0, CK0#, CK1, CK1#, CK2, CK2# Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Clocks: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is refer- enced to the crossings of CK and CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER- DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE ) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input only. Chip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All com- mands are masked when S# is registered HIGH. S# is considered part of the command code. Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presencedetect portion of the module. Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Input 96 CKE0 Input 121 S0# Input 116, 117 BA0, BA1 Input 99 (128MB), 100, 101, 102, 105, 106, 107, 108, 109, 110, 111, 112, 115 A0-A11 (64MB) A0-A12 (128MB) Input 12, 26, 48, 62, 78, 134, 148, 170, 184 DM0-DM8 Input 193 SDA Input/ Output 195 SCL Input 194, 196, 198 SA0-SA2 Input 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS SYMBOL TYPE DESCRIPTION 11, 25, 47, 61, 77, 133, 147, 169, 183 DQS0-DQS8 Input/ Output 71, 72, 73, 74, 79, 80, 83, 84 CB0 - CB7 5, 6, 7, 8, 13, 14, 17, 18, 19, 20, 23, 24, 29, 30, 31, 32, 41, 42, 43, 44, 49, 50, 53, 54, 55, 56, 59, 60, 65, 66, 67, 68, 127, 128, 129, 130, 135, 136, 139, 140, 141, 142, 145, 146, 151, 152, 153, 154, 163, 164, 165, 166, 171, 172, 175, 176, 177, 178, 181, 182, 187, 188, 189, 190 1, 2 9, 10, 21, 22, 33, 34, 36, 45,46, 57, 58, 69, 70, 81, 82, 92, 93, 94, 113, 114, 131, 132, 143, 144, 155, 156, 157, 167, 168, 179, 180, 191, 192 3, 4, 15, 16, 27, 28, 38, 39, 40, 51, 52, 63, 64, 75, 76, 87, 88, 90, 103, 104, 125, 126, 137, 138, 149, 150, 159, 161, 162, 173, 174, 185, 186 197 85, 86, 95, 97, 98, 99 (64MB), 123, 122, 124, 199, 200 DQ0-DQ63 Input/ Output Input/ Output Data Strobe: Output with READ data, input with WRITE data. DQS is edge-aligned with READ data, centered in WRITE data. Used to capture data. Check Bits: ECC 1-bit error checking and correction. 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN Data I/Os: Data bus. VREF VDD Input Supply SSTL_2 reference voltage. Power Supply: +2.5V 0.2V. (See note 50 on page 22.) VSS Supply Ground. VDDSPD NC Supply - Serial EEPROM positive power supply: +2.3V to +3.6V. No Connect: These pins should be left unconnected. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Figure 3: Functional Block Diagram S0# S0# DQS0 DM0 UDQS UDM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ DQ DQ DQ DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ DQ DQ DQ DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 LDQS LDM DQ DQ DQ DQ DQ DQ DQ DQ DQS3 DM3 S0# DQS6 DM6 A0 DDR SDRAMs A1 U3 47K VDD VDD 47K NC NC NC NC NC NC NC NC LDM DQ DQ DQ DQ DQ DQ DQ DQ U4 A2 VDDSPD SDA SPD VDD DDR SDRAMs VREF DDR SDRAMs VSS DDR SDRAMs SA0 SA1 SA2 DDR SDRAMs DDR SDRAMs 120 120 DDR SDRAMs U1, U2 U5 LDQS S0# DDR SDRAMs CK1 CK1# DDR SDRAMs U3, U4 CK2 CK2# DDR SDRAM U5 6.6pF 6.6pF DDR SDRAM = MT46V8M16TG for 64MB DDR SDRAM = MT46V16M16TG 128MB NOTE: Unless otherwise stated, all resistors are 22W. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/ numberguide. 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 S0# DQ DQ DQ DQ DQ DQ DQ DQ SERIAL PD U6 SCL WP 120 1. 2. UDQS UDM DQ DQ DQ DQ DQ DQ DQ DQ LDQS LDM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DDR SDRAMs DDR SDRAMs 6.6pF DQ DQ DQ DQ DQ DQ DQ DQ DQS7 DM7 DDR SDRAMs CK0 CK0# UDQS UDM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 U2 DQS8 DM8 S0# LDQS LDM DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 BA0-BA1 CAS# WE# CKE0 DQ DQ DQ DQ DQ DQ DQ DQ DQS5 DM5 A0-A11(64MB) A0-A12(128MB) RAS# UDQS UDM DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U1 LDQS LDM DQ DQ DQ DQ DQ DQ DQ DQ UDQS UDM DQS4 DM4 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM General Description The MT5VDDT872H and MT5VDDT1672H are high-speed CMOS, dynamic random-access, 64MB and 128MB memory modules organized in a x72 (ECC) configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for DDR SDRAM modules effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clocks (CK, CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select device bank; A0-A11 select device row for 64MB, A0-A12 select device row for 128MB ). The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access. DDR SDRAM modules provide for programmable read or write burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 128Mb and 256Mb DDR SDRAM component data sheets. Serial Presence- Detect Operation DDR SDRAM modules incorporate serial presencedetect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA(2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Mode Register Definition The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in the Mode Register Diagram. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A11 (64MB), or A7-A12 (128MB) specify the operating mode. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Burst Length Reserved states should not be used as unknown operation or incompatibility with future versions may result. Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Mode Register Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration; see Note 5 for Figure 6, Burst Definition Table, on page 9). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both read and write bursts. Figure 4: Mode Register Definition Diagram 64MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 13 12 0* 0* 11 10 9 8 7 6 5 4 3 2 1 0 Operating Mode CAS Latency BT Burst Length Address Bus Mode Register (Mx) * M13 and M12 (BA1 and BA0) must be "0, 0" to select the base mode register (vs. the extended mode register). 128MB Module BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 13 12 11 10 9 8 Operating Mode 0* 0* 7 6 5 4 3 2 1 0 CAS Latency BT Burst Length * M14 and M13 (BA1 and BA0) must be "0, 0" to select the base mode register (vs. the extended mode register). Address Bus Mode Register (Mx) Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 Reserved Reserved 0 0 1 2 2 0 1 0 4 4 Burst Type 0 1 1 8 8 Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definition Table. 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved Read Latency 0 Sequential 1 Interleaved CAS Latency M6 M5 M4 The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in CAS Latency Diagram. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. The CAS Latency Table indicates the operating frequencies at which each CAS latency setting can be used. 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN Burst Type M3 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved M12 M11 M10 M9 M8 M7 8 M6-M0 Operating Mode 0 0 0 0 0 0 Valid Normal Operation 0 0 0 0 1 0 Valid Normal Operation/Reset DLL - - - - - - - All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 6: STARTING COLUMN ADDRESS BURST LENGTH A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 4 8 T0 T1 T2 READ NOP NOP T2n T3 T3n CK# ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL 2 Figure 5: CAS Latency Diagram Burst Definition Table CK COMMAND TYPE = INTERLEAVED NOP CL = 2 DQS 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 DQ CK# T0 T1 T2 READ NOP NOP T2n T3 T3n CK COMMAND NOP CL = 2.5 DQS 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 DQ Burst Length = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ TRANSITIONING DATA DON'T CARE NOTE: Operating Mode 1. For a burst length of two, A1-Ai select the two-dataelement block; A0 selects the first access within the block. 2. For a burst length of four, A2-Ai select the four-dataelement block; A0-A1 select the first access within the block. 3. For a burst length of eight, A3-Ai select the eight-dataelement block; A0-A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. Ai = A8 The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A11 (64MB) or A7-A12 (128MB) each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A11 (64MB) or A9-A12 (128MB) each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A11 (64MB) or A7-A12 (128MB) are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Table 7: CAS Latency (CL) Table ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ) SPEED CL = 2 CL = 2.5 -335 -262 -26A -265 -202 NA 75 f 133 75 f 133 75 f 100 75 f 100 75 f 167 75 f 133 75 f 133 75 f 133 75 f 125 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and output drive strength. These functions are controlled via the bits shown in the Extended Mode Register Definition Diagram. The extended mode register is programmed via the LOAD MODE REGISTER command 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both low) to reset the DLL. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. Figure 6: Extended Mode Register Definition Diagram 64MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 13 12 11 10 01 11 8 7 6 5 4 Operating Mode 3 2 1 0 DS DLL Extended Mode Register (Ex) 128MB Module Output Drive Strength BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 The normal full drive strength for all outputs is specified to be SSTL2, Class II. The x16 supports an option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQ and DQS from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive strength. For detailed information on programmable and reduced drive strength option, refer to the 128Mb or 256Mb DDR SDRAM data sheets. 14 13 12 11 10 01 11 9 8 7 6 5 Operating Mode 4 3 2 1 0 DS DLL E1 DLL Enable/Disable E11 E10 E9 E8 E7 E6 E5 E4 E3 E22 The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 9 Address Bus E1, E0 0 0 0 0 0 0 0 0 0 0 Valid - - - - - - - - - - - Address Bus Extended Mode Register (Ex) E0 DLL 0 Enable 1 Disable Drive Strength 0 Normal 1 Reduced Operating Mode Normal Operation All other states reserved NOTE: 1. BA1 and BA0 (E13 and E12 for 64MB, E14 and E13 for 128MB) must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register). 2. The QFC# option is not supported. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Commands The Truth Tables below provides a general reference of available commands. For a more detailed descrip- Table 8: tion of commands and operations, refer to the 128Mb or 256Mb DDR SDRAM component data sheet. Truth Table - Commands CKE is HIGH for all commands shown except SELF REFRESH NAME (FUNCTION) DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select device bank and activate row) READ (Select device bank and column, and start READ burst) WRITE (Select device bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in device bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER CS# RAS# H L L L L L L L L X H L H H H L L L CAS# WE# X H H L L H H L L X H H H L L L H L ADDR NOTES X X Bank/Row Bank/Col Bank/Col X Code X Op-Code 1 1 2 3 3 4 5 6, 7 8 NOTE: 1. DESELECT and NOP are functionally interchangeable. 2. BA0-BA1 provide device bank address and A0-A11 (64MB) or A0-A12 (128MB) provide row address. 3. BA0-BA1 provide device bank address; A0-A8, provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 5. A10 LOW: BA0-BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. 8. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 (64MB) or A0-A12 (128MB) provide the op-code to be written to the selected mode register. Table 9: Truth Table - DM Operation Used to mask write data; provided coincident with the corresponding data NAME (FUNCTION) WRITE Enable WRITE Inhibit 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 11 DM DQS L H Valid X Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VDDQ Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VREF and Inputs Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on I/O Pins Relative to VSS . . . . . . . . . . . . . -0.5V to VDDQ +0.5V Operating Temperature TA (ambient) . . . . . . . . . . . . . . . . . . . .. 0C to +70C Storage Temperature (plastic) . . . . . . -55C to +150C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 5W Short Circuit Output Current. . . . . . . . . . . . . . . 50mA Table 10: DC Electrical Characteristics and Operating Conditions Notes: 1-5, 14, 50; notes appear on pages 19-22; 0C TA +70C PARAMETER/CONDITION SYMBOL Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any input Command/Address, 0V VIN VDD, Vref pin 0V VIN 1.35V RAS#, CAS#, WE#, (All other pins not under test = 0V) CKE, S# CK0, CK0#, CK1, CK1# DM, CK2, CK2# OUTPUT LEAKAGE CURRENT DQ, DQS (DQ pins are disabled; 0V VOUT VDDQ) OUTPUT LEVELS High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) VDD VDDQ VREF VTT VIH(DC) VIL(DC) OUTPUT LEVELS (Reduced drive option) High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) MIN MAX UNITS NOTES V V V V V V 32, 37 32, 37, 40 6, 40 7, 40 25 25 A 49 A 49 2.3 2.7 2.3 2.7 0.49 VDDQ 0.51 VDDQ VREF - 0.04 VREF + 0.04 VREF + 0.15 VDD + 0.3 -0.3 VREF - 0.15 IOZ -10 -4 -2 -5 10 4 2 5 IOH IOL -16.8 16.8 - - mA mA 33, 35 IOH IOL -9 9 - - mA mA 34, 35 II Table 11: AC Input Operating Conditions Notes: 1-5, 14, 50; notes appear on pages 19-22; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V PARAMETER/CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage I/O Reference Voltage 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN SYMBOL MIN MAX UNITS NOTES VIH(AC) VIL(AC) VREF(AC) VREF + 0.310 - 0.49 VDDQ - VREF - 0.310 0.51 VDDQ V V V 12, 25, 36 12, 25, 36 6 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 12: IDD Specifications and Conditions - 64MB Module DDR SDRAM component values only Notes: 1-5, 8, 10, 14, 50; notes appear on pages 19-22; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V MAX PARAMETER/CONDITION SYM IDD0 OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles IDD1 OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD2P PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2F IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank IDD3P active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3N ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); t CK = tCK (MIN); DQ, DM andDQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD4R OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4W OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle t IDD5 RC = tRC (MIN) AUTO REFRESH CURRENT t IDD5A RC = 15.625s IDD6 SELF REFRESH CURRENT: CKE 0.2V IDD7 OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ or WRITE commands 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 13 -335 -262 -26A/ -265 -202 600 575 550 525 mA 20, 44 675 675 650 600 mA 20, 44 15 15 15 15 mA 225 225 225 175 mA 21, 28, 46 47 125 125 100 100 mA 250 250 225 200 mA 21, 28, 46 20, 43 750 725 725 675 mA 20, 44 700 675 625 575 mA 20 1,175 25 15 1,800 1,075 25 15 1,800 1,050 25 10 1,675 950 25 10 1,550 mA mA mA mA 24, 46 24, 46 9 20, 45 UNITS NOTES Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 13: IDD Specifications and Conditions - 128MB Module DDR SDRAM component values only Notes: 1-5, 8, 10, 14, 50; notes appear on pages 19-22; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V MAX PARAMETER/CONDITION SYM IDD0 OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles IDD1 OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle IDD2P PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDD2F IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; t CK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank IDD3P active; Power-down mode; tCK = tCK (MIN); CKE = LOW IDD3N ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); t CK = tCK (MIN); DQ, DM andDQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle IDD4R OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA IDD4W OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle t IDD5 RC = tRC (MIN) AUTO REFRESH CURRENT t IDD5A RC = 7.8125s IDD6 SELF REFRESH CURRENT: CKE 0.2V IDD7 OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ or WRITE commands 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 14 -335 -262 -26A/ -265 -202 625 625 525 600 mA 20, 44 900 850 775 825 mA 20, 44 20 20 20 20 mA 250 225 225 225 mA 21, 28, 46 47 150 125 125 150 mA 300 250 250 250 mA 21, 28, 46 20, 43 1,100 925 925 1250 mA 20, 44 825 725 725 1,250 mA 20 1,275 30 20 2,200 1,175 30 20 1,900 1,175 30 20 1,900 1,225 30 20 2,000 mA mA mA mA 24, 46 24, 46 9 20, 45 UNITS NOTES Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 14: Capacitance Note: 11; notes appearon pages 19-22 PARAMETER SYMBOL MIN MAX UNITS CIO CI1 CI2 CI2 4 10 10.6 8.6 5 15 12.6 9.6 pF pF pF pF Input/Output Capacitance: DQ, DQS Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK0, CK0#, CK1, CK1# Input Capacitance: CK2, CK2# Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) Notes: 1-5, 12-15, 29, 50; notes appear on pages 19-22; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC CHARACTERISTICS -335 PARAMETER SYMBOL t AC CH t CL t CK (2.5) CL=2.5 t CK (2) CL=2 t DH DQ and DM input hold time relative to DQS t DS DQ and DM input setup time relative to DQS t DIPW DQ and DM input pulse width (for each input) t DQSCK Access window of DQS from CK/CK# t DQSH DQS input high pulse width t DQSL DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ t DQSS Write command to first DQS latching transition t DSS DQS falling edge to CK rising - setup time t DSH DQS falling edge from CK rising - hold time t HP Half clock period Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time t t Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access HZ LZ t IHF t ISF t IHS t ISS t MRD t QH Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command t ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN t QHS RAS t 64MB 128MB t RAP t RC RFC t RCD t 15 -262 MIN MAX MIN MAX -0.7 0.45 0.45 6 7.5 0.45 0.45 1.75 -0.60 0.35 0.35 +0.75 0.55 0.55 13 13 -0.70 0.45 0.45 6 7.5 0.45 0.45 1.75 -0.65 0.35 0.35 +0.70 0.55 0.55 13 13 +0.60 0.45 0.75 1.25 0.2 0.2 t CH, tCL +0.70 -0.70 0.75 0.75 0.80 0.80 12 t HP - tQHS 42 18 18 60 72 18 0.55 70,000 0.75 0.2 0.2 +0.6 0.45 1.25 t CH,tCL +0.7 -0.7 0.75 0.75 0.8 0.8 15 t HP-tQHS 0.75 40 120,000 15 15 60 75 15 UNITS ns CK t CK ns ns ns ns ns ns t CK t CK ns t CK t CK t CK ns t ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 26 26 41, 48 41, 48 23, 27 23, 27 27 22, 23 30 16, 38 16, 39 12 12 12 12 22, 23 31 42 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) (Continued) Notes: 1-5, 12-15, 29, 50; notes appear on pages 19-22; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC CHARACTERISTICS -335 PARAMETER SYMBOL t RP t RPRE t RPST t RRD t WPRE t WPRES t WPST t WR t WTR na PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 64MB 128MB 64MB 128MB t MIN MAX MIN 18 0.9 1.1 0.4 0.6 12 0.25 0 0.4 0.6 15 1 t QH - tDQSQ 15 0.9 0.4 15 0.25 0 0.4 15 1 140.6 70.3 15.6 7.8 REFC t REFI t VTD XSNR t XSRD t 16 -262 0 75 200 t MAX 1.1 0.6 0.6 QH -tDQSQ 140.6 70.3 15.6 7.8 0 75 200 UNITS ns t CK t CK ns t CK ns t CK ns t CK ns s s s s ns ns t CK NOTES 38 18, 19 17 22 21 21 21 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) Notes: 1-5, 12-15, 29, 50; notes appear on pages 19-22; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC CHARACTERISTICS -26A/-265 PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time SYMBOL t CL=2.5 CL=2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command 64MB 128MB ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN AC CH t CL t CK (2.5) t CK (2) t DH t DS t DIPW t DQSCK t DQSH t DQSL t DQSQ t DQSS t DSS t DSH t HP t HZ t LZ t IHF t ISF t IHS t ISS t MRD t QH t QHS t RAS t t RAP t RC RFC t RCD t RP t RPRE t RPST t RRD t WPRE t WPRES t WPST t WR t WTR na t 17 -202 MIN MAX MIN MAX -0.75 0.45 0.45 7.5 7.5/10 0.5 0.5 1.75 -0.75 0.35 0.35 +0.75 0.55 0.55 13 13 -0.8 0.45 0.45 8 10 0.6 0.6 2 -0.8 0.35 0.35 +0.8 0.55 0.55 13 13 +0.75 0.5 1.25 +0.8 0.6 1.25 0.75 0.75 0.2 0.2 0.2 0.2 t t CH, tCL CH, tCL +0.75 +0.8 -0.75 -0.8 0.90 1.1 0.90 1.1 1 1.1 1 1.1 15 16 t t HP - tQHS HP - tQHS 0.75 1 40 120,000 40 120,000 t RAS(MIN)-(burst length*tCK/2) 20 20 65 70 75 80 20 20 20 20 0.9 1.1 0.9 1.1 0.4 0.6 0.4 0.6 15 15 0.25 0.25 0 0 0.4 0.6 0.4 0.6 15 15 1 1 t t QH - tDQSQ QH - tDQSQ UNITS ns CK t CK ns ns ns ns ns ns t CK t CK ns t CK t CK t CK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t CK t CK ns t CK ns t CK ns t CK ns t NOTES 26 26 41, 48 41, 48 23, 27 23, 27 27 22, 23 30 16, 38 16, 39 12 12 12 12 22, 23 31 42 46 38 18, 19 17 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) (Continued) Notes: 1-5, 12-15, 29, 50; notes appear on pages 19-22; 0C TA +70C; VDD = VDDQ = +2.5V 0.2V AC CHARACTERISTICS -26A/-265 PARAMETER REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN SYMBOL 64MB 128MB 64MB 128MB t MIN REFC REFI t VTD XSNR t XSRD 18 MIN 140.6 70.3 15.6 7.8 t t MAX -202 0 75 200 0 80 200 MAX UNITS NOTES 140.6 70.3 15.6 7.8 s s s s ns ns t CK 21 21 21 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: VTT Output (VOUT) 50 Reference QFC# Point (VOUT) 30pF 11. This parameter is sampled. VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V, VREF = VSS, f = 100 MHz, TA = 25C, VOUT (DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 12. Command/Address input slew rate = 0.5V/ns. For -335, -262, -26A, and -265 with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ ns, timing must be derated: tIS has an additional 50ps per each 100mV/ ns reduction in slew rate from the 500mV/ns, while tIH remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. 13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 14. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VDDQ is recognized as LOW. 15. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. t 16. HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 17. If DQS transitions to HIGH above VIH (DC) MIN, then it must not transition to LOW below VIH (DC) MIN prior to tDQSH (MIN). 18. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. VTT 75 Reference Point 15pF 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL (ACV) and VIH (AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -262, -26A, and -202, CL = 2.5 for-335 and -265 with the outputs open. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Figure 7: Derating Data Valid Window 3.8 3.750 3.700 3.6 3.400 3.4 3.350 3.650 3.600 3.550 3.500 3.450 3.300 3.400 3.250 3.200 3.150 3.2 NA -335 -262/-26A/-265 @ tCK = 10ns -202 @ tCK = 10ns -262/-26A/-265 @ tCK = 7.5ns -202 @ tCK = 8ns ns 3.0 2.8 2.6 3.100 2.500 2.463 2.425 2.388 2.4 3.350 2.313 2.275 3.250 3.050 3.000 2.350 3.300 2.238 2.200 2.950 2.163 2.2 2.900 2.125 2.0 1.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 Clock Duty Cycle 21. The refresh period is 64ms. This equates to an average refresh rate of 15.625s (128MB module) or 7.8125s (256MB module). However, an AUTO REFRESH command must be asserted at least once every 140.6s (128MB module) or 70.3s (256MB module); burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. Figure 7, Derating Data Valid Window, shows derating curves for duty cycles between 50/ 50 and 45/55. 23. Each byte lane has a corresponding DQS. 24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 25. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC). 26. JEDEC specifies CK and CK# input slew rate must be 1V/ns (2V/ns differentially). 27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and t DH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 28. VDD must not vary more than 4 percent if CKE is not active while any device bank is active. 29. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. 30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM CK/ inputs, collectively during device bank active. 31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +400mV or 2.9V maximum, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V minimum, whichever is more positive. 33. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source voltages from 0.1V to 1.0V. 34. Reduced Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 10, Reduced Output Pull-Down Characteristics, on page 22. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 10, Reduced Output Pull-Down Characteristics, on page 22. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 11, Reduced Output Pull-Up Characteristics, on page 22. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 11, Reduced Output Pull-Up Characteristics, on page 22. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source voltages from 0.1V to 1.0V. Figure 8: Pull-Down Characteristics Figure 9: Pull-Up Characteristics 160 0 140 Maxim -20 um Maximum -40 120 IOUT (mA) 80 Nominal low 60 -80 -100 Nom -120 inal -140 Minimum 40 Nominal high -60 high IOUT (mA) Nominal 100 Min imu -160 20 low m -180 -200 0 0.0 0.5 1.0 1.5 2.0 0.0 2.5 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 0.5 1.0 1.5 2.0 2.5 VDDQ - VOUT (V) VOUT (V) 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM 35. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 36. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 37. VDD and VDDQ must track each other. 38. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZ(MAX) and the last DVW. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over t DQSCK (MIN) + tRPRE (MAX) condition. 39. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. 40. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V, provided a minimum of 42W of series resistance is used between the VTT supply and the input pin. 41. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 42. tRAP tRCD. Does not apply to -335 speed grade. 43. For -335, -262, -26A, and -265, IDD3N is specified to be 35mA at 100 MHz. 44. Random addressing changing and 50 percent of data changing at every transfer. 45. Random addressing changing and 100 percent of data changing at every transfer. 46. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t REF later. 47. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." 48. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). 49. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 50. The -335 module speed grade, using the -6R speed device, has VDD (MIN) = 2.4V. Figure 10: Reduced Output Pull-Down Characteristics Figure 11: Reduced Output Pull-Up Characteristics 80 0 -5 imum 70 Max -10 60 40 IOUT (mA) IOUT (mA) -15 Nominal high 50 Nominal low Minimum -20 Nomin al low Nom inal high -25 -30 30 -35 Minimum 20 Ma xim -40 um -45 10 -50 0 0.0 0.0 0.5 1.0 1.5 2.0 2.5 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VDDQ - VOUT (V) VOUT (V) 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 12, Data Validity, and Figure 13, Definition of Start and Stop). Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Figure 14, Acknowledge Response from Receiver). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure 12: Data Validity Figure 13: Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT STOP BIT Figure 14: Acknowledge Response from Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 17: EEPROM Device Select Code Most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW Table 18: EEPROM Operating Modes MODE RW BIT WC BYTES 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 1 1 1 1 16 Current Address Read Random Address Read Sequential Read Byte Write Page Write INITIAL SEQUENCE START, Device Select, RW = `1' START, Device Select, RW = `0', Address reSTART, Device Select, RW = `1' Similar to Current or Random Address Read START, Device Select, RW = `0' START, Device Select, RW = `0' Figure 15: SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL MIN MAX UNITS VDDSPD VIH VIL VOL ILI ILO ISB ICC 2.3 VDDSPD 0.7 -1 - - - - - 3.6 VDDSPD + 0.5 VDDSPD 0.3 0.4 10 10 30 2 V V V V A A A mA SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz Table 20: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL t AA BUF t DH t F t HD:DAT t HD:STA t HIGH t I t LOW t R t SCL t SU:DAT t SU:STA t SU:STO t WRC SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time t MIN MAX UNITS NOTES 0.3 4.7 300 3.5 s s ns ns s s s ns s s KHz ns s s ms 1 300 0 4 4 100 4.7 1 100 250 4.7 4.7 10 NOTE: 1. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 21: Serial Presence-Detect Matrix "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear following matrix BYTE DESCRIPTION 0 1 2 3 4 5 6 7 8 9 Number of SPD Bytes Used by Micron Total Number of Bytes in SPD Device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of Physical Ranks on DIMM Module Data Width Module Data Width (Continued) Module Voltage Interface Levels (VDDQ) SDRAM Cycle Time, (tCK) CAS Latency = 2.5 (See note 1) 10 SDRAM Access From Clock (tAC) CAS Latency = 2.5 11 12 13 14 15 16 17 18 19 20 21 22 23 Module Configuration Type Refresh Rate/Type SDRAM Device Width (Primary DDR SDRAM) Error-checking DDR SDRAM Data Width Minimum Clock Delay, Back-to-Back Random Column Access Burst Lengths Supported Number of Banks on DDR SDRAM Device CAS Latencies Supported CS Latency WE Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, (tCK) CAS Latency = 2 24 SDRAM Access From Clock (tAC) CAS Latency = 2 25 26 27 SDRAM Cycle Time, (tCK) CAS Latency = 1.5 SDRAM Access from CK , (tAC) CAS Latency = 1.5 Minimum Row Precharge Time, (tRP) 28 Minimum Row Active to Row Active, (tRRD) 29 Minimum RAS# to CAS# Delay, (tRCD) 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN ENTRY (VERSION) MT5VDDT872H MT5VDDT1672H 128 256 DDR SDRAM 12,13 10 1 72 0 SSTL 2.5V 6ns (-335) 7ns (-262/-26A) 7.5ns (-265) 8ns (-202) 0.7ns (-335) 0.75ns (-262/-26A/-265) 0.8ns (-202) ECC 15.62s, 7.8s/SELF 16 16 1 clock 80 08 07 0C 09 01 48 00 04 60 70 75 80 70 75 80 02 80 10 10 01 80 08 07 0D 09 01 48 00 04 60 70 75 80 70 75 80 02 82 10 10 01 2, 4, 8 4 2, 2.5 0 1 Unbuffered/Diff. Clock Fast/Concurrent AP 7.5ns (-335/-262/-26A) 10ns (-265/-202) 0.7ns (-335) 0.75ns (-262/-26A/-265) 0.8ns (-202) N/A N/A 18ns (-335) 15ns (-262) 20ns (-26A/-265/-202) 12ns (-335) 15ns (-262/-26A/-265/-202) 18ns (-335) 15ns (-262) 20ns (-26A/-265/-202) 0E 04 0C 01 02 20 C1 75 A0 70 75 80 00 00 48 3C 50 30 3C 48 3C 50 0E 04 0C 01 02 20 C1 75 A0 70 75 80 01 01 48 3C 50 30 3C 48 3C 50 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 21: Serial Presence-Detect Matrix (Continued) "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear following matrix BYTE DESCRIPTION (t 30 Minimum RAS# Pulse Width, RAS), (See note 3) 31 32 Module Rank Density Address and Command Setup Time, (tIS), (See note 4) 33 Address and Command Hold Time, (tIH), (See note 4) 34 Data/Data Mask Input Setup Time, (tDS) 35 Data/Data Mask Input Hold Time, (tDH) 36-40 Reserved 41 Minimum Active Auto Refresh Time (tRC) 42 Minimum Auto Refresh to Active/Auto Refresh Command Period, (tRFC) 43 SDRAM Device Max Cycle Time (tCKMAX) 44 SDRAM Device Max DQS-DQ Skew Time (tDQSQ) 45 SDRAM Device Max Read Data Hold Skew Factor (tQHS) 46 47 48-61 62 63 Reserved DIMM Height Reserved SPD Revision Checksum for Bytes 0-62 64 65-71 72 73-90 91 92 Manufacturer's JEDEC ID Code Manufacturer's JEDEC IDCode Manufacturing Location Module Part Number (ASCII) PCB Identification Code Identification Code (Continued) 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN ENTRY (VERSION) MT5VDDT872H MT5VDDT1672H 42ns (-335) 45ns (-262/-26A/-265) 40ns (-202) 64MB, 128MB 0.8ns (-335) 1.0ns (-262/-26A/-265) 1.1ns (-202) 0.8ns (-335) 1.0ns (-262/-26A/-265) 1.1ns (-202) 0.45ns (-335) 0.5ns (-262/-26A/-265) 0.6ns (-202) 0.45ns (-335) 0.5ns (-262/-26A/-265) 0.6ns (-202) 2A 2D 28 10 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 2D 32 3C 55 75 A0 00 01 00 10 16 E9 16 46 E1 2C 00 01 - 0C Variable Data 01 - 09 00 2A 2D 28 20 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 2D 32 3C 55 75 A0 00 01 00 10 29 BC E9 19 B4 2C 00 01 - 0C Variable Data 01 - 09 00 60ns (335/-262) 65ns (-26A/-265) 70ns (-202) 72ns (-335) 75ns (-262/-26A/-265) 80ns (-202) 12ns (-335) 13ns (-262/-26A/-265/-202) 0.45ns (-335) 0.5ns (-262/-26A/-265) 0.6ns (-202) 0.55ns (-335) 0.75ns (-262/-26A/-265) 1.0ns (-202) Release 1.0 -335 -262 -26A -265 -202 MICRON (Continued) 01-12 1-9 0 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Table 21: Serial Presence-Detect Matrix (Continued) "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes appear following matrix BYTE 93 94 95-98 99-127 DESCRIPTION ENTRY (VERSION) Year of Manufacture in BCD Week of Manufacturein BCD Module Serial Number Manufacturer-specific Data (RSVD) MT5VDDT872H MT5VDDT1672H Variable Data Variable Data Variable Data - Variable Data Variable Data Variable Data - NOTE: 1. Value for -26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns. 2. The value of tRAS used for -262/-26A/-265 modules is calculated from tRC - tRP. Actual device spec. value is 40 ns. 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met. 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology. Inc. 64MB, 128MB (x72, ECC) 200-PIN DDR SDRAM SODIMM Figure 16: 200-Pin SODIMM Dimensions FRONT VIEW 0.150 (3.80) MAX 2.666 (67.72) 2.656 (67.45) 0.079 (2.00) R (2X) U1 U2 U3 U4 1.244 (31.60) 1.256 (31.90) 0.071 (1.80) (2X) 0.787 (20.00) TYP 0.236 (6.00) 0.091 (2.30) 0.043 (1.10) 0.035 (0.90) 0.085 (2.15) 0.039 (1.0) TYP 0.018 (0.45) TYP 0.024 (0.60) TYP PIN 199 PIN 1 2.504 (63.60) TYP BACK VIEW U6 U5 PIN 200 0.449 (11.40) TYP 1.87 (47.40) TYP PIN 2 NOTE: All dimensions are in inches (millimeters) MAX or typical where noted. MIN Data Sheet Designation Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete power supply and temrperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. 09005aef80a8e767 DD5C8_16x72HG_C.fm - Rev. C 7/03 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice.. (c)2003 Micron Technology, Inc