MT5VDDT1672HG-202XX - Micron Technology, Inc.

09005aef80a8e767

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

SMALL-OUTLINE

DDR SDRAM DIMM

MT5VDDT872H – 64MB

MT5VDDT1672H – 128MB

For the latest data sheet, please refer to the Micronâ Web

site: www.micron.com/moduleds

Features

• JEDEC standard 200-pin, small-outline, dual in-line

memory module (DDR SODIMM)

• Fast data transfer rates PC1600, PC2100, or PC2700

• Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR

SDRAM components

• 64MB (8 Meg x 72) and 128MB (16 Meg x 72)

• ECC-1-bit error detection and correction

•V

DD = VDDQ= +2.5V

•V

DDSPD = +2.3V to +3.6V

• 2.5V I/O (SSTL_2 compatible)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Bidirectional data strobe (DQS) transmitted/

received with data—i.e., source-synchronous data

capture

• Differential clock inputs (CK and CK#)

• Four internal device banks for concurrent operation

• Selectable burst lengths: 2, 4, or 8

• Auto precharge option

• Auto Refresh and Self Refresh Modes 15.625µs

(64MB); 7.8125µs (128MB) maximum average

periodic refresh interval

• Serial Presence Detect (SPD) with EEPROM

• Selectable READ CAS latency for maximum

compatibility

•Gold edge contacts

Figure 1: 200-Pin SODIMM (MO-224)

NOTE: 1. Consult factory for availability of lead-free prod-

ucts.

2. CL = Device CAS (READ) Latency

OPTIONS MARKING

•Package

200-pin SODIMM (Standard) G

200-pin SODIMM (Lead-free)1Y

• Memory Clock/Speed/CAS Latency2

6ns (167 MHz), 333 MT/s, CL = 2.5 -335

7.5ns (133 MHz), 266 MT/s, CL = 2 -262

7.5ns (133 MHz), 266 MT/s, CL = 2 -26A

7.5ns (133 MHz), 266 MT/s, CL = 2.5 -265

10ns (100 MHz), 200 MT/s, CL = 2 -202

Table 1: Address Table

64MB 128MB

Refresh Count 4K 8K

Row Addressing 4K (A0–A11) 8K(A0–A12)

Device Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1)

Device Configuration 8 Meg x 16 16 Meg x 16

Column Addressing 512 (A0–A8) 512 (A0–A8)

Module Rank Addressing 1 (S0#) 1 (S0#)

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult fac-

tory for current revision codes. Example: MT5VDDT1672HG-265A1.

Table 2: Part Numbers and Timing Parameters

PART NUMBER

MODULE

DENSITY CONFIGURATION

MODULE

BANDWIDTH

MEMORY CLOCK/

DATA RATE

CLOCK LATENCY

(CL - tRCD - tRP)

MT5VDDT872HG-335__ 64MB 8 Meg x 72 2.7GB/s 6ns,333MT/s 2.5-3-3

MT5VDDT872HY-335__ 64MB 8 Meg x 72 2.7GB/s 6ns,333MT/s 2.5-3-3

MT5VDDT872HG-262__ 64MB 8 Meg x 72 2.1GB/s 7.5ns,266MT/s 2-2-2

MT5VDDT872HY-262__ 64MB 8 Meg x 72 2.1GB/s 7.5ns,266MT/s 2-2-2

MT5VDDT872HG-26A__ 64MB 8 Meg x 72 2.1GB/s 7.5ns,266MT/s 2-3-3

MT5VDDT872HY-26A__ 64MB 8 Meg x 72 2.1GB/s 7.5ns,266MT/s 2-3-3

MT5VDDT872HG-265__ 64MB 8 Meg x 72 2.1GB/s 7.5ns,266 MT/s 2.5-3-3

MT5VDDT872HY-265__ 64MB 8 Meg x 72 2.1GB/s 7.5ns,266 MT/s 2.5-3-3

MT5VDDT872HG-202__ 64MB 8 Meg x 72 1.6GB/s 10ns,200MT/s 2-2-2

MT5VDDT872HY-202__ 64MB 8 Meg x 72 1.6GB/s 10ns,200MT/s 2-2-2

MT5VDDT1672HG-335__ 128MB 16 Meg x 72 2.7GB/s 6ns,333MT/s 2.5-3-3

MT5VDDT1672HY-335__ 128MB 16 Meg x 72 2.7GB/s 6ns,333MT/s 2.5-3-3

MT5VDDT1672HG-262__ 128MB 16 Meg x 72 2.1GB/s 7.5ns,266MT/s 2-2-2

MT5VDDT1672HY-262__ 128MB 16 Meg x 72 2.1GB/s 7.5ns,266MT/s 2-2-2

MT5VDDT1672HG-26A__ 128MB 16 Meg x 72 2.1GB/s 7.5ns,266MT/s 2-3-3

MT5VDDT1672HY-26A__ 128MB 16 Meg x 72 2.1GB/s 7.5ns,266MT/s 2-3-3

MT5VDDT1672HG-265__ 128MB 16 Meg x 72 2.1GB/s 7.5ns,266 MT/s 2.5-3-3

MT5VDDT1672HY-265__ 128MB 16 Meg x 72 2.1GB/s 7.5ns,266 MT/s 2.5-3-3

MT5VDDT1672HG-202__ 128MB 16 Meg x 72 1.6GB/s 10ns,200MT/s 2-2-2

MT5VDDT1672HY-202__ 128MB 16 Meg x 72 1.6GB/s 10ns,200MT/s 2-2-2

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

Pin 99 is NC for 64MB, A12 for 128MB.

Figure 2: 200-Pin SODIMM Module Layout

Table 3: Pin Assignment

(200-Pin SODIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

1VREF 51 VSS 101 A9 151 DQ42

3VSS 53 DQ19 103 VSS 153 DQ43

5DQ055DQ24105 A7 155 VDD

7DQ157 VDD 107 A5 157 VDD

9VDD 59 DQ25 109 A3 159 VSS

11 DQS0 61 DQS3 111 A1 161 VSS

13 DQ2 63 VSS 113 VDD 163 DQ48

15 VSS 65 DQ26 115 A10 165 DQ49

17 DQ3 67 DQ27 117 BA0 167 VDD

19 DQ8 69 VDD 119 WE# 169 DQS6

21 VDD 71 CB0 121 S0# 171 DQ50

23 DQ9 73 CB1 123 NC 173 VSS

25 DQS1 75 VSS 125 VSS 175 DQ51

27 VSS 77 DQS8 127 DQ32 177 DQ56

29 DQ10 79 CB2 129 DQ33 179 VDD

31 DQ11 81 VDD 131 VDD 181 DQ57

33 VDD 83 CB3 133 DQS4 183 DQS7

35 CK0 85 NC 135 DQ34 185 VSS

37 CK0# 87 VSS 137 VSS 187 DQ58

39 VSS 89 CK2 139 DQ35 189 DQ59

41 DQ16 91 CK2# 141 DQ40 191 VDD

43 DQ17 93 VDD 143 VDD 193 SDA

45 VDD 95 NC 145 DQ41 195 SCL

47 DQS2 97 NC 147 DQS5 197 VDDSPD

49 DQ18 99 NC/A12 149 VSS 199 NC

Table 4: Pin Assignment

(200-Pin SODIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

2VREF 52 VSS 102 A8 152 DQ46

4VSS 54 DQ23 104 VSS 154 DQ47

6 DQ4 56 DQ28 106 A6 156 VDD

8DQ558 VDD 108 A4 158 CK1#

10 VDD 60 DQ29 110 A2 160 CK1

12DM062DM3112 A0 162 VSS

14 DQ6 64 VSS 114 VDD 164 DQ52

16 VSS 66 DQ30 116 BA1 166 DQ53

18 DQ7 68 DQ31 118RAS#168 V

20 DQ12 70 VDD 120CAS#170DM6

22 VDD 72 CB4 122 NC 172 DQ54

24 DQ13 74 CB5 124 NC 174 VSS

26 DM1 76 VSS 126 VSS 176 DQ55

28 VSS 78 DM8 128 DQ36 178 DQ60

30 DQ14 80 CB6 130 DQ37 180 VDD

32 DQ15 82 VDD 132 VDD 182 DQ61

34 VDD 84 CB7 134 DM4 184 DM7

36 VDD 86 NC 136 DQ38 186 VSS

38 VSS 88 VSS 138 VSS 188 DQ62

40 VSS 90 VSS 140 DQ39 190 DQ63

42 DQ20 92 VDD 142 DQ44 192 VDD

44 DQ21 94 VDD 144 VDD 194 SA0

46 VDD 96 CKE0 146 DQ45 196 SA1

48 DM2 98 NC 148 DM5 198 SA2

50 DQ22 100 A11 150 VSS 200 NC

U1 U2 U3 U4 U5

Front View Back View

PIN 1 PIN 199

(all odd pins)

PIN 2

PIN 200 (all even pins)

Indicates a V

or V

DDQ

pin Indicates a V

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 5: Pin Descriptions

Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information

PIN NUMBERS SYMBOL TYPE DESCRIPTION

118, 119, 120 WE#, CAS#,

RAS#

Input Command Inputs: RAS#, CAS#, and WE# (along with S#)

define the command being entered.

35, 37, 89, 91, 158, 160 CK0, CK0#, CK1,

CK1#, CK2, CK2#

Input Clocks: CK and CK# are differential clock inputs. All address

and control input signals are sampled on the crossing of the

positive edge of CK and negative edge of CK#. Output data

(DQs and DQS) is refer- enced to the crossings of CK and CK#.

96 CKE0 Input Clock Enable: CKE HIGH activates and CKE LOW deactivates

the internal clock, input buffers and output drivers. Taking

CKE LOW provides PRECHARGE POWER- DOWN and SELF

REFRESH operations (all device banks idle), or ACTIVE

POWER-DOWN (row ACTIVE in any device bank). CKE is

synchronous for POWER-DOWN entry and exit, and for SELF

REFRESH entry. CKE is asynchronous for SELF REFRESH exit

and for disabling the outputs. CKE must be maintained HIGH

throughout read and write accesses. Input buffers (excluding

CK, CK# and CKE ) are disabled during POWER-DOWN. Input

buffers (excluding CKE) are disabled during SELF REFRESH.

CKE is an SSTL_2 input but will detect an LVCMOS LOW level

after VDD is applied and until CKE is first brought HIGH.

After CKE is brought HIGH, it becomes an SSTL_2 input only.

121 S0# Input Chip Select: S# enables (registered LOW) and disables

(registered HIGH) the command decoder. All com- mands are

masked when S# is registered HIGH. S# is considered part of

the command code.

116, 117 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank an

ACTIVE, READ, WRITE, or PRECHARGE command is being

applied.

99 (128MB), 100, 101,

102, 105, 106, 107, 108,

109, 110, 111, 112, 115

A0-A11 (64MB)

A0-A12 (128MB)

Input Address Inputs: Provide the row address for ACTIVE

commands, and the column address and auto precharge bit

(A10) for READ/WRITE commands, to select one location out

of the memory array in the respective device bank. A10

sampled during a PRECHARGE command determines whether

the PRECHARGE applies to one device bank (A10 LOW, device

bank selected by BA0, BA1) or all device banks (A10 HIGH).

The address inputs also provide the op-code during a MODE

during the LOAD MODE REGISTER command.

12, 26, 48, 62, 78, 134,

148, 170, 184

DM0-DM8 Input Data Mask: DM is an input mask signal for write data. Input

data is masked when DM is sampled HIGH along with that

input data during a WRITE access. DM is sampled on both

edges of DQS. Although DM pins are input-only, the DM

loading is designed to match that of DQ and DQS pins.

193 SDA Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to

transfer addresses and data into and out of the presence-

detect portion of the module.

195 SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize

the presence-detect data transfer to and from the module.

194, 196, 198 SA0-SA2 Input Presence-Detect Address Inputs: These pins are used to

configure the presence-detect device.

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

11, 25, 47, 61, 77, 133, 147,

169, 183

DQS0-DQS8 Input/

Output

Data Strobe: Output with READ data, input with WRITE data.

DQS is edge-aligned with READ data, centered in WRITE

data. Used to capture data.

71, 72, 73, 74, 79, 80, 83, 84 CB0 - CB7 Input/

Output

Check Bits: ECC 1-bit error checking and correction.

5, 6, 7, 8, 13, 14, 17, 18, 19,

20, 23, 24, 29, 30, 31, 32, 41,

42, 43, 44, 49, 50, 53, 54, 55,

56, 59, 60, 65, 66, 67, 68,

127, 128, 129, 130, 135, 136,

139, 140, 141, 142, 145, 146,

151, 152, 153, 154, 163, 164,

165, 166, 171, 172, 175, 176,

177, 178, 181, 182, 187, 188,

189, 190

DQ0-DQ63 Input/

Output

Data I/Os: Data bus.

1, 2 VREF Input SSTL_2 reference voltage.

9, 10, 21, 22, 33, 34, 36,

45,46, 57, 58, 69, 70, 81, 82,

92, 93, 94, 113, 114, 131,

132, 143, 144, 155, 156, 157,

167, 168, 179, 180, 191, 192

VDD Supply Power Supply: +2.5V ±0.2V.

(See note 50 on page 22.)

3, 4, 15, 16, 27, 28, 38, 39,

40, 51, 52, 63, 64, 75, 76, 87,

88, 90, 103, 104, 125, 126,

137, 138, 149, 150, 159, 161,

162, 173, 174, 185, 186

VSS Supply Ground.

197 VDDSPD Supply Serial EEPROM positive power supply: +2.3V to +3.6V.

85, 86, 95, 97, 98,

99 (64MB), 123, 122, 124,

199, 200

NC – No Connect: These pins should be left unconnected.

Table 5: Pin Descriptions

Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 3 for more information

PIN NUMBERS SYMBOL TYPE DESCRIPTION

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 3: Functional Block Diagram

DM3

DM2

DQ0

DQ1

DQ2

DQ3

DM0

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ40

DQ41

DQ42

DQ43

DM4

DQ44

DQ45

DQ46

DQ47

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DM1

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DM5

DM6

DM7

S0#

LDM

UDM

S0#

BA0-BA1

A0-A11(64MB)

RAS#

CAS#

WE#

CKE0

DDR SDRAMs

CK0 CK1

DDR SDRAMs U1, U2 DDR SDRAMs U3, U4

DQS0 UDQS

DQS1 LDQS

DQS2

DQS3 DQS7

DQS6

DQS5

DQS4

CK1#

CK0#

DDR SDRAMs

S0#

SA0

SERIAL PD

SDA

SA1

SA2

SCL U6

VREF

VSS

DDR SDRAMs

VDD DDR SDRAMs

VDDSPD SPD

A0-A12(128MB) DDR SDRAMs

LDM

UDM

UDQS

LDQS

LDM

UDM

UDQS

LDQS

LDM

UDM

UDQS

LDQS

VDD

DM8

S0#

DQS8

VDD

LDM

UDM

UDQS

LDQS

CB0

CB1

CB2

CB3

CB4

CB5

CB6

CB7

CK2

CK2# DDR SDRAM U5

47K

120

6.6pF

120

6.6pF

120

6.6pF

NOTE:

1. Unless otherwise stated, all resistors are 22W.

2. Per industry standard, Micron utilizes various component speed grades as

referenced in the Module Part Numbering Guide at www.micron.com/

numberguide.

DDR SDRAM = MT46V8M16TG for 64MB

DDR SDRAM = MT46V16M16TG 128MB

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

General Description

The MT5VDDT872H and MT5VDDT1672H are

high-speed CMOS, dynamic random-access, 64MB

and 128MB memory modules organized in a x72 (ECC)

configuration. DDR SDRAM modules use internally

configured quad-bank DDR SDRAM devices.

DDR SDRAM modules use a double data rate archi-

tecture to achieve high-speed operation. The double

data rate architecture is essentially a 2n-prefetch

architecture with an interface designed to transfer two

data words per clock cycle at the I/O pins. A single

read or write access for DDR SDRAM modules effec-

tively consists of a single 2n-bit wide, one-clock-cycle

data transfer at the internal DRAM core and two corre-

sponding n-bit wide, one-half-clock-cycle data trans-

fers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at

the receiver. DQS is an intermittent strobe transmitted

by the DDR SDRAM during READs and by the memory

controller during WRITEs. DQS is edge-aligned with

data for READs and center-aligned with data for

WRITEs.

DDR SDRAM modules operate from differential

clocks (CK, CK#); the crossing of CK going HIGH and

CK# going LOW will be referred to as the positive edge

of CK. Commands (address and control signals) are

registered at every positive edge of CK. Input data is

registered on both edges of DQS, and output data is

referenced to both edges of DQS, as well as to both

edges of CK.

Read and write accesses to DDR SDRAM modules

are burst oriented; accesses start at a selected location

and continue for a programmed number of locations

in a programmed sequence. Accesses begin with the

registration of an ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command

are used to select the device bank and row to be

accessed (BA0, BA1 select device bank; A0–A11 select

device row for 64MB, A0–A12 select device row for

128MB ). The address bits registered coincident with

the READ or WRITE command are used to select the

device bank and the starting device column location

for the burst access.

DDR SDRAM modules provide for programmable

read or write burst lengths of 2, 4, or 8 locations. An

auto precharge function may be enabled to provide a

self-timed row precharge that is initiated at the end of

the burst access.

The pipelined, multibank architecture of DDR

SDRAM modules allows for concurrent operation,

thereby providing high effective bandwidth by hiding

row precharge and activation time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-

patible with the JEDEC Standard for SSTL_2. All out-

puts are SSTL_2, Class II compatible. For more

information regarding DDR SDRAM operation, refer to

the 128Mb and 256Mb DDR SDRAM component data

sheets.

Serial Presence- Detect Operation

DDR SDRAM modules incorporate serial presence-

detect (SPD). The SPD function is implemented using

a 2,048-bit EEPROM. This nonvolatile storage device

contains 256 bytes. The first 128 bytes can be pro-

grammed by Micron to identify the module type and

various SDRAM organizations and timing parameters.

The remaining 128 bytes of storage are available for

use by the customer. System READ/WRITE operations

between the master (system logic) and the slave

EEPROM device (DIMM) occur via a standard I2C bus

using the DIMM’s SCL (clock) and SDA (data) signals,

together with SA(2:0), which provide eight unique

DIMM/EEPROM addresses. Write protect (WP) is tied

to ground on the module, permanently disabling hard-

ware write protect.

Mode Register Definition

The mode register is used to define the specific

mode of operation of the DDR SDRAM. This definition

includes the selection of a burst length, a burst type, a

CAS latency and an operating mode, as shown in the

Mode Register Diagram. The mode register is pro-

grammed via the MODE REGISTER SET command

(with BA0 = 0 and BA1 = 0) and will retain the stored

information until it is programmed again or the device

loses power (except for bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed cor-

rectly. The mode register must be loaded (reloaded)

when all device banks are idle and no bursts are in

progress, and the controller must wait the specified

time before initiating the subsequent operation. Vio-

lating either of these requirements will result in

unspecified operation.

Mode register bits A0–A2 specify the burst length,

A3 specifies the type of burst (sequential or inter-

leaved), A4–A6 specify the CAS latency, and A7–A11

(64MB), or A7–A12 (128MB) specify the operating

mode.

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-

mable, as shown in Mode Register Diagram. The burst

length determines the maximum number of column

locations that can be accessed for a given READ or

WRITE command. Burst lengths of 2, 4, or 8 locations

are available for both the sequential and the inter-

leaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively

selected. All accesses for that burst take place within

this block, meaning that the burst will wrap within the

block if a boundary is reached. The block is uniquely

selected by A1–Ai when the burst length is set to two,

by A2–Ai when the burst length is set to four and by

A3–Ai when the burst length is set to eight (where Ai is

the most significant column address bit for a given

configuration; see Note 5 for Figure 6, Burst Definition

Table, on page 9). The remaining (least significant)

address bit(s) is (are) used to select the starting loca-

tion within the block. The programmed burst length

applies to both read and write bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-

ing column address, as shown in Burst Definition

Table.

Read Latency

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the

availability of the first bit of output data. The latency

can be set to 2 or 2.5 clocks, as shown in CAS Latency

Diagram.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available

nominally coincident with clock edge n + m. The CAS

Latency Table indicates the operating frequencies at

which each CAS latency setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may

result.

Figure 4:

Mode Register Definition Diagram

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst LengthCAS Latency BT0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

M6-M0

M8 M7

Operating Mode

A10

A12 A11

BA0

BA1

* M14 and M13 (BA1 and BA0)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

M9M10M12 M11

Burst LengthCAS Latency BT0*0*

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

Operating Mode

A10

A11

BA0

BA1

* M13 and M12 (BA1 and BA0)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

64MB Module

128MB Module

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. For a burst length of two, A1–Ai select the two-data-

element block; A0 selects the first access within the

block.

2. For a burst length of four, A2–Ai select the four-data-

element block; A0–A1 select the first access within the

block.

3. For a burst length of eight, A3–Ai select the eight-data-

element block; A0–A2 select the first access within the

block.

4. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps

within the block.

5. Ai = A8

Figure 5: CAS Latency Diagram

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7–A11

(64MB) or A7–A12 (128MB) each set to zero, and bits

A0–A6 set to the desired values. A DLL reset is initiated

by issuing a MODE REGISTER SET command with bits

A7 and A9–A11 (64MB) or A9–A12 (128MB) each set to

zero, bit A8 set to one, and bits A0–A6 set to the desired

values. Although not required by the Micron device,

JEDEC specifications recommend when a LOAD

MODE REGISTER command is issued to reset the DLL,

it should always be followed by a LOAD MODE REGIS-

TER command to select normal operating mode.

All other combinations of values for A7–A11 (64MB)

or A7–A12 (128MB) are reserved for future use and/or

test modes. Test modes and reserved states should not

be used because unknown operation or incompatibil-

ity with future versions may result.

Extended Mode Register

The extended mode register controls functions

beyond those controlled by the mode register; these

additional functions are DLL enable/disable and out-

put drive strength. These functions are controlled via

the bits shown in the Extended Mode Register Defini-

tion Diagram. The extended mode register is pro-

grammed via the LOAD MODE REGISTER command

Table 6: Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES

WITHIN A BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

00-1 0-1

11-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Table 7: CAS Latency (CL) Table

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHZ)

SPEED CL = 2 CL = 2.5

-335 NA 75 £ f £ 167

-262 75 £ f £ 133 75 £ f £133

-26A 75 £ f £ 133 75 £ f £133

-265 75 £ f £ 100 75 £ f £ 133

-202 75 £ f £ 100 75 £ f £ 125

CK#

COMMAND

DQS

CL = 2

READ NOP NOP NOP

Burst Length = 4 in the cases shown

Shown with nominal tAC, tDQSCK, and tDQSQ

CK#

COMMAND

DQS

CL = 2.5

T0 T1 T2 T2n T3 T3n

DON’T CARETRANSITIONING DATA

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

to the mode register (with BA0 = 1 and BA1 = 0) and

will retain the stored information until it is pro-

grammed again or the device loses power. The

enabling of the DLL should always be followed by a

LOAD MODE REGISTER command to the mode regis-

ter (BA0/BA1 both low) to reset the DLL.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,

and the controller must wait the specified time before

initiating any subsequent operation. Violating either

of these requirements could result in unspecified oper-

ation.

Output Drive Strength

The normal full drive strength for all outputs is

specified to be SSTL2, Class II. The x16 supports an

option for reduced drive. This option is intended for

the support of the lighter load and/or point-to-point

environments.

The selection of the reduced drive strength will alter

the DQ and DQS from SSTL2, Class II drive strength to

a reduced drive strength, which is approximately 54

percent of the SSTL2, Class II drive strength.

For detailed information on programmable and

reduced drive strength option, refer to the 128Mb or

256Mb DDR SDRAM data sheets.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization

and upon returning to normal operation after having

disabled the DLL for the purpose of debug or evalua-

tion. (When the device exits self refresh mode, the DLL

is enabled automatically.) Any time the DLL is

enabled, 200 clock cycles must occur before a READ

command can be issued.

Figure 6: Extended Mode Register

Definition Diagram

NOTE:

1. BA1 and BA0 (E13 and E12 for 64MB, E14 and E13

for 128MB) must be “0, 1” to select the Extended

Mode Register (vs. the base Mode Register).

2. The QFC# option is not supported.

Operating Mode

Normal Operation

All other states reserved

–

Valid

–

DLL

Enable

Disable

DLL

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

Drive Strength

Normal

Reduced

E1,

Operating Mode

A10A11BA1 BA0

10111213

E3E4

–

E6 E5

E7E8E9

–

E10E11

DLL

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

Operating Mode

A10A11A12BA1 BA0

1011121314

64MB Module

128MB Module

–

E22

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Commands

The Truth Tables below provides a general reference

of available commands. For a more detailed descrip-

tion of commands and operations, refer to the 128Mb

or 256Mb DDR SDRAM component data sheet.

NOTE:

1. DESELECT and NOP are functionally interchangeable.

2. BA0–BA1 provide device bank address and A0–A11 (64MB) or A0–A12 (128MB) provide row address.

3. BA0–BA1 provide device bank address; A0–A8, provide column address; A10 HIGH enables the auto precharge feature

(nonpersistent), and A10 LOW disables the auto precharge feature.

4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ

bursts with auto precharge enabled and for WRITE bursts.

5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0-

BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0

= 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved).

A0–A11 (64MB) or A0–A12 (128MB) provide the op-code to be written to the selected mode register.

Table 8: Truth Table – Commands

CKE is HIGH for all commands shown except SELF REFRESH

NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES

DESELECT (NOP) HX XX X 1

NO OPERATION (NOP) LH HH X 1

ACTIVE (Select device bank and activate row) L L H H Bank/Row 2

READ (Select device bank and column, and start READ burst) L H L H Bank/Col 3

WRITE (Select device bank and column, and start WRITE burst) L H L L Bank/Col 3

BURST TERMINATE LH HL X 4

PRECHARGE (Deactivate row in device bank or banks) L L H L Code 5

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LL LH X 6, 7

LOAD MODE REGISTER LL LLOp-Code 8

Table 9: Truth Table – DM Operation

Used to mask write data; provided coincident with the corresponding data

NAME (FUNCTION) DM DQS

WRITE Enable L Valid

WRITE Inhibit HX

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,

and functional operation of the device at these or any

other conditions above those indicated in the opera-

tional sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

Voltage on VDD Supply

Relative to VSS. . . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on VDDQ Supply

Relative to VSS. . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on VREF and Inputs

Relative to VSS. . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on I/O Pins

Relative to VSS. . . . . . . . . . . . . -0.5V to VDDQ +0.5V

Operating Temperature

TA (ambient) . . . . . . . . . . . . . . . . . . . .. 0°C to +70°C

Storage Temperature (plastic) . . . . . .-55°C to +150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 5W

Short Circuit Output Current. . . . . . . . . . . . . . . 50mA

Table 10: DC Electrical Characteristics and Operating Conditions

Notes: 1–5, 14, 50; notes appear on pages 19–22; 0°C £ TA £ +70°C

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD 2.3 2.7 V 32, 37

I/O Supply Voltage VDDQ 2.3 2.7 V 32, 37, 40

I/O Reference Voltage VREF 0.49 ´ VDDQ0.51 ´ VDDQ V 6, 40

I/O Termination Voltage (system) VTT VREF - 0.04 VREF + 0.04 V 7, 40

Input High (Logic 1) Voltage VIH(DC)VREF + 0.15 VDD + 0.3 V 25

Input Low (Logic 0) Voltage VIL(DC)-0.3VREF - 0.15 V 25

INPUT LEAKAGE CURRENT Any input

0V £ VIN £ VDD, Vref pin 0V £ VIN £ 1.35V

(All other pins not under test = 0V)

Command/Address,

RAS#, CAS#, WE#,

CKE, S#

-10 10

µA 49

CK0, CK0#, CK1, CK1# -4 4

DM, CK2, CK2# -2 2

OUTPUT LEAKAGE CURRENT

(DQ pins are disabled; 0V £ VOUT £ VDDQ)

DQ, DQS IOZ -5 5 µA 49

OUTPUT LEVELS

High Current (V

OUT

= V

Q - 0.373V, minimum V

REF

, minimum V

)

Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)

IOH -16.8 – mA

33, 35

IOL 16.8 – mA

OUTPUT LEVELS (Reduced drive option)

High Current (V

OUT

= V

Q - 0.373V, minimum V

REF

, minimum V

)

Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)

IOH -9 – mA

34, 35

IOL 9–mA

Table 11: AC Input Operating Conditions

Notes: 1–5, 14, 50; notes appear on pages 19–22; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH(AC)VREF + 0.310 – V 12, 25, 36

Input Low (Logic 0) Voltage VIL(AC)–VREF - 0.310 V 12, 25, 36

I/O Reference Voltage VREF(AC)0.49 ´ VDDQ0.51 ´ VDDQV 6

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 12 : IDD Specifications and Conditions – 64MB Module

DDR SDRAM component values only

Notes: 1–5, 8, 10, 14, 50; notes appear on pages 19–22; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V

MAX

PARAMETER/CONDITION SYM -335 -262

-26A/

-265 -202 UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs

changing once every two clock cycles

IDD0 600 575 550 525 mA 20, 44

OPERATING CURRENT: One device bank; Active -Read

Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);

IOUT = 0mA; Address and control inputs changing once per

clock cycle

IDD1 675 675 650 600 mA 20, 44

PRECHARGE POWER-DOWN STANDBY CURRENT: All device

banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)

IDD2P 15 15 15 15 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

tCK = tCK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle. VIN = VREF for DQ, DQS, and

IDD2F 225 225 225 175 mA 47

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank

active; Power-down mode; tCK = tCK (MIN); CKE = LOW

IDD3P 125 125 100 100 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One

device bank; Active-Precharge; tRC = tRAS (MAX);

tCK = tCK (MIN); DQ, DM andDQS inputs changing twice per

clock cycle; Address and other control inputs changing once

per clock cycle

IDD3N 250 250 225 200 mA 20, 43

OPERATING CURRENT: Burst = 2; Reads; Continuous burst;

One device bank active; Address and control inputs changing

once per clock cycle; tCK = tCK (MIN); IOUT = 0mA

IDD4R 750 725 725 675 mA 20, 44

OPERATING CURRENT: Burst = 2; Writes; Continuous burst;

One device bank active; Address and control inputs changing

once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS

inputs changing twice per clock cycle

IDD4W 700 675 625 575 mA 20

AUTO REFRESH CURRENT tRC = tRC (MIN) IDD5 1,175 1,075 1,050 950 mA 24, 46

tRC = 15.625µs IDD5A 25 25 25 25 mA 24, 46

SELF REFRESH CURRENT: CKE £ 0.2V IDD6 15 15 10 10 mA 9

OPERATING CURRENT: Four device bank interleaving READs

(BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK

(MIN); Address and control inputs change only during Active

READ or WRITE commands

IDD7 1,800 1,800 1,675 1,550 mA 20, 45

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 13 : IDD Specifications and Conditions – 128MB Module

DDR SDRAM component values only

Notes: 1–5, 8, 10, 14, 50; notes appear on pages 19–22; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V

MAX

PARAMETER/CONDITION SYM -335 -262

-26A/

-265 -202 UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs

changing once per clock cyle; Address and control inputs

changing once every two clock cycles

IDD0 625 625 525 600 mA 20, 44

OPERATING CURRENT: One device bank; Active -Read

Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);

IOUT = 0mA; Address and control inputs changing once per

clock cycle

IDD1 900 850 775 825 mA 20, 44

PRECHARGE POWER-DOWN STANDBY CURRENT: All device

banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW)

IDD2P 20 20 20 20 mA 21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

tCK = tCK MIN; CKE = HIGH; Address and other control inputs

changing once per clock cycle. VIN = VREF for DQ, DQS, and

IDD2F 250 225 225 225 mA 47

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank

active; Power-down mode; tCK = tCK (MIN); CKE = LOW

IDD3P 150 125 125 150 mA 21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One

device bank; Active-Precharge; tRC = tRAS (MAX);

tCK = tCK (MIN); DQ, DM andDQS inputs changing twice per

clock cycle; Address and other control inputs changing once

per clock cycle

IDD3N 300 250 250 250 mA 20, 43

OPERATING CURRENT: Burst = 2; Reads; Continuous burst;

One device bank active; Address and control inputs changing

once per clock cycle; tCK = tCK (MIN); IOUT = 0mA

IDD4R 1,100 925 925 1250 mA 20, 44

OPERATING CURRENT: Burst = 2; Writes; Continuous burst;

One device bank active; Address and control inputs changing

once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS

inputs changing twice per clock cycle

IDD4W 825 725 725 1,250 mA 20

AUTO REFRESH CURRENT tRC = tRC (MIN) IDD5 1,275 1,175 1,175 1,225 mA 24, 46

tRC = 7.8125µs IDD5A 30 30 30 30 mA 24, 46

SELF REFRESH CURRENT: CKE £ 0.2V IDD6 20 20 20 20 mA 9

OPERATING CURRENT: Four device bank interleaving READs

(BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK

(MIN); Address and control inputs change only during Active

READ or WRITE commands

IDD7 2,200 1,900 1,900 2,000 mA 20, 45

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 14: Capacitance

Note: 11; notes appearon pages 19–22

PARAMETER SYMBOL MIN MAX UNITS

Input/Output Capacitance: DQ, DQS CIO 45 pF

Input Capacitance: Command and Address, S#, CKE CI1 10 15 pF

Input Capacitance: CK0, CK0#, CK1, CK1# CI2 10.6 12.6 pF

Input Capacitance: CK2, CK2# CI2 8.6 9.6 pF

Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-335, -262)

Notes: 1–5, 12-15, 29, 50; notes appear on pages 19–22; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V

AC CHARACTERISTICS -335 -262

UNITS

NOTES

PARAMETER

SYMBOL

MIN MAX MIN MAX

Access window of DQs from CK/CK# tAC -0.7 +0.75 -0.70 +0.70 ns

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 26

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 26

Clock cycle time CL=2.5 tCK (2.5) 6 13 6 13 ns 41, 48

CL=2 tCK (2) 7.5 13 7.5 13 ns 41, 48

DQ and DM input hold time relative to DQS tDH 0.45 0.45 ns 23, 27

DQ and DM input setup time relative to DQS tDS 0.45 0.45 ns 23, 27

DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 ns 27

Access window of DQS from CK/CK# tDQSCK -0.60 +0.60 -0.65 +0.6 ns

DQS input high pulse width tDQSH 0.35 0.35 tCK

DQS input low pulse width tDQSL 0.35 0.35 tCK

DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.45 0.45 ns 22, 23

Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK rising - setup time tDSS 0.2 0.2 tCK

DQS falling edge from CK rising - hold time tDSH 0.2 0.2 tCK

Half clock period tHP tCH, tCL tCH,tCL ns 30

Data-out high-impedance window from CK/CK# tHZ +0.70 +0.7 ns 16, 38

Data-out low-impedance window from CK/CK# tLZ -0.70 -0.7 ns 16, 39

Address and control input hold time (fast slew rate)

tIHF0.75 0.75 ns 12

Address and control input setup time (fast slew rate)

tISF0.75 0.75 ns 12

Address and control input hold time (slow slew rate)

tIHS0.80 0.8 ns 12

Address and control input setup time (slow slew rate)

tISS0.80 0.8 ns 12

LOAD MODE REGISTER command cycle time tMRD 12 15 ns

DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP - tQHS tHP-tQHS ns 22, 23

Data hold skew factor tQHS 0.55 0.75 ns

ACTIVE to PRECHARGE command tRAS 42 70,000 40 120,000 ns 31

ACTIVE to READ with Auto precharge

command

64MB tRAP 18 15 ns 42

128MB 18 15 ns

ACTIVE to ACTIVE/AUTO REFRESH command period

tRC 60 60 ns

AUTO REFRESH command period tRFC 72 75 ns 46

ACTIVE to READ or WRITE delay tRCD 18 15 ns

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

PRECHARGE command period tRP 18 15 ns

DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 38

DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK

ACTIVE bank a to ACTIVE bank b command tRRD 12 15 ns

DQS write preamble tWPRE 0.25 0.25 tCK

DQS write preamble setup time tWPRES 0 0 ns 18, 19

DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK 17

Write recovery time tWR 15 15 ns

Internal WRITE to READ command delay tWTR 1 1 tCK

Data valid output window na tQH - tDQSQ tQH -tDQSQ ns 22

REFRESH to REFRESH command interval 64MB tREFC 140.6 140.6 µs 21

128MB 70.3 70.3 µs 21

Average periodic refresh interval 64MB tREFI 15.6 15.6 µs 21

128MB 7.8 7.8 µs 21

Terminating voltage delay to VDD tVTD 0 0 ns

Exit SELF REFRESH to non-READ command tXSNR 75 75 ns

Exit SELF REFRESH to READ command tXSRD 200 200 tCK

Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-335, -262) (Continued)

Notes: 1–5, 12-15, 29, 50; notes appear on pages 19–22; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V

AC CHARACTERISTICS -335 -262

UNITS

NOTES

PARAMETER

SYMBOL

MIN MAX MIN MAX

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-26A, -265, -202)

Notes: 1–5, 12-15, 29, 50; notes appear on pages 19–22; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V

AC CHARACTERISTICS -26A/-265 -202

UNITS

NOTES

PARAMETER

SYMBOL

MIN MAX MIN MAX

Access window of DQs from CK/CK# tAC -0.75 +0.75 -0.8 +0.8 ns

CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 26

CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 26

Clock cycle time CL=2.5 tCK (2.5) 7.5 13 8 13 ns 41, 48

CL=2 tCK (2) 7.5/10 13 10 13 ns 41, 48

DQ and DM input hold time relative to DQS tDH 0.5 0.6 ns 23, 27

DQ and DM input setup time relative to DQS tDS 0.5 0.6 ns 23, 27

DQ and DM input pulse width (for each input) tDIPW 1.75 2 ns 27

Access window of DQS from CK/CK# tDQSCK -0.75 +0.75 -0.8 +0.8 ns

DQS input high pulse width tDQSH 0.35 0.35 tCK

DQS input low pulse width tDQSL 0.35 0.35 tCK

DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.5 0.6 ns 22, 23

Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK rising - setup time tDSS 0.2 0.2 tCK

DQS falling edge from CK rising - hold time tDSH 0.2 0.2 tCK

Half clock period tHP tCH, tCL tCH, tCL ns 30

Data-out high-impedance window from CK/CK# tHZ +0.75 +0.8 ns 16, 38

Data-out low-impedance window from CK/CK# tLZ -0.75 -0.8 ns 16, 39

Address and control input hold time (fast slew rate)

tIHF0.90 1.1 ns 12

Address and control input setup time (fast slew rate)

tISF0.90 1.1 ns 12

Address and control input hold time (slow slew rate)

tIHS11.1ns12

Address and control input setup time (slow slew rate)

tISS11.1ns12

LOAD MODE REGISTER command cycle time tMRD 15 16 ns

DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP - tQHS tHP - tQHS ns 22, 23

Data hold skew factor tQHS 0.75 1 ns

ACTIVE to PRECHARGE command tRAS 40 120,000 40 120,000 ns 31

ACTIVE to READ with Auto precharge command 64MB tRAP

tRAS(MIN)-(burst length*tCK/2) ns 42

128MB 20 20 ns

ACTIVE to ACTIVE/AUTO REFRESH command period

tRC 65 70 ns

AUTO REFRESH command period tRFC 75 80 ns 46

ACTIVE to READ or WRITE delay tRCD 20 20 ns

PRECHARGE command period tRP 20 20 ns

DQS read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 38

DQS read postamble tRPST 0.4 0.6 0.4 0.6 tCK

ACTIVE bank a to ACTIVE bank b command tRRD 15 15 ns

DQS write preamble tWPRE 0.25 0.25 tCK

DQS write preamble setup time tWPRES 0 0 ns 18, 19

DQS write postamble tWPST 0.4 0.6 0.4 0.6 tCK 17

Write recovery time tWR 15 15 ns

Internal WRITE to READ command delay tWTR 1 1 tCK

Data valid output window na tQH - tDQSQ tQH - tDQSQ ns 22

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

REFRESH to REFRESH command interval 64MB tREFC 140.6 140.6 µs 21

128MB 70.3 70.3 µs 21

Average periodic refresh interval 64MB tREFI 15.6 15.6 µs 21

128MB 7.8 7.8 µs 21

Terminating voltage delay to VDD tVTD 0 0 ns

Exit SELF REFRESH to non-READ command tXSNR 75 80 ns

Exit SELF REFRESH to READ command tXSRD 200 200 tCK

Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-26A, -265, -202) (Continued)

Notes: 1–5, 12-15, 29, 50; notes appear on pages 19–22; 0°C £ TA £ +70°C; VDD = VDDQ = +2.5V ±0.2V

AC CHARACTERISTICS -26A/-265 -202

UNITS

NOTES

PARAMETER

SYMBOL

MIN MAX MIN MAX

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Notes

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and electrical AC and DC

characteristics may be conducted at nominal ref-

erence/supply voltage levels, but the related spec-

ifications and device operation are guaranteed for

the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC timing and IDD tests may use a VIL-to-VIH

swing of up to 1.5V in the test environment, but

input timing is still referenced to VREF (or to the

crossing point for CK/CK#), and parameter speci-

fications are guaranteed for the specified AC input

levels under normal use conditions. The mini-

mum slew rate for the input signals used to test

the device is 1V/ns in the range between VIL (ACV)

and VIH (AC).

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver

will effectively switch as a result of the signal

crossing the AC input level, and will remain in that

state as long as the signal does not ring back

above [below] the DC input LOW [HIGH] level).

6. VREF is expected to equal VDDQ/2 of the transmit-

ting device and to track variations in the DC level

of the same. Peak-to-peak noise (non-common

mode) on VREF may not exceed ±2 percent of the

DC value. Thus, from VDDQ/2, VREF is allowed

±25mV for DC error and an additional ±25mV for

AC noise. This measurement is to be taken at the

nearest VREF by-pass capacitor.

7. VTT is not applied directly to the device. VTT is a

system supply for signal termination resistors, is

expected to be set equal to VREF and must track

variations in the DC level of VREF.

8. IDD is dependent on output loading and cycle

rates. Specified values are obtained with mini-

mum cycle time at CL = 2 for -262, -26A, and -202,

CL = 2.5 for-335 and -265 with the outputs open.

9. Enables on-chip refresh and address counters.

10. IDD specifications are tested after the device is

properly initialized, and is averaged at the defined

cycle rate.

11. This parameter is sampled. VDD = +2.5V ±0.2V,

VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, TA=

25°C, VOUT (DC) = VDDQ/2, VOUT (peak to peak) =

0.2V. DM input is grouped with I/O pins, reflecting

the fact that they are matched in loading.

12. Command/Address input slew rate = 0.5V/ns. For

-335, -262, -26A, and -265 with slew rates 1V/ns

and faster, tIS and tIH are reduced to 900ps. If the

slew rate is less than 0.5V/ ns, timing must be der-

ated: tIS has an additional 50ps per each 100mV/

ns reduction in slew rate from the 500mV/ns,

while tIH remains constant. If the slew rate

exceeds 4.5V/ns, functionality is uncertain.

13. The CK/CK# input reference level (for timing ref-

erenced to CK/CK#) is the point at which CK and

CK# cross; the input reference level for signals

other than CK/CK# is VREF.

14. Inputs are not recognized as valid until VREF stabi-

lizes. Exception: during the period before V

REF

stabilizes, CKE £ 0.3 x VDDQ is recognized as LOW.

15. The output timing reference level, as measured at

the timing reference point indicated in Note 3, is

VTT.

16. tHZ and tLZ transitions occur in the same access

time windows as valid data transitions. These

parameters are not referenced to a specific voltage

level, but specify when the device output is no

longer driving (HZ) or begins driving (LZ).

17. If DQS transitions to HIGH above VIH (DC) MIN,

then it must not transition to LOW below VIH (DC)

MIN prior to tDQSH (MIN).

18. This is not a device limit. The device will operate

with a negative value, but system performance

could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The

case shown (DQS going from High-Z to logic

LOW) applies when no WRITEs were previously in

progress on the bus. If a previous WRITE was in

progress, DQS could be HIGH during this time,

depending on tDQSS.

20. MIN (tRC or tRFC) for IDD measurements is the

smallest multiple of tCK that meets the minimum

absolute value for the respective parameter. tRAS

(MAX) for IDD measurements is the largest multi-

ple of tCK that meets the maximum absolute

value for tRAS.

Output

OUT

)

Reference

Point

Ω

30pF

QFC#

OUT

)

Reference

Point

Ω

15pF

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 7: Derating Data Valid Window

21. The refresh period is 64ms. This equates to an

average refresh rate of 15.625µs (128MB module)

or 7.8125µs (256MB module). However, an AUTO

REFRESH command must be asserted at least

once every 140.6µs (128MB module) or 70.3µs

(256MB module); burst refreshing or posting by

the DRAM controller greater than eight refresh

cycles is not allowed.

22. The valid data window is derived by achieving

other specifications: tHP (tCK/2), tDQSQ, and tQH

(tQH = tHP - tQHS). The data valid window derates

directly porportional with the clock duty cycle

and a practical data valid window can be derived.

The clock is allowed a maximum duty cycle varia-

tion of 45/55, beyond which functionality is

uncertain. Figure 7, Derating Data Valid Window,

shows derating curves for duty cycles between 50/

50 and 45/55.

23. Each byte lane has a corresponding DQS.

24. This limit is actually a nominal value and does not

result in a fail value. CKE is HIGH during RE-

FRESH command period (tRFC [MIN]) else CKE is

LOW (i.e., during standby).

25. To maintain a valid level, the transitioning edge of

the input must:

a. Sustain a constant slew rate from the current

AC level through to the target AC level, VIL (AC)

or VIH (AC).

b. Reach at least the target AC level.

c. After the AC target level is reached, continue to

maintain at least the target DC level, VIL (DC)

or VIH (DC).

26. JEDEC specifies CK and CK# input slew rate must

be ³ 1V/ns (2V/ns differentially).

27. DQ and DM input slew rates must not deviate

from DQS by more than 10 percent. If the DQ/

DM/DQS slew rate is less than 0.5V/ns, timing

must be derated: 50ps must be added to tDS and

tDH for each 100mv/ns reduction in slew rate. If

slew rate exceeds 4V/ns, functionality is uncer-

tain.

28. VDD must not vary more than 4 percent if CKE is

not active while any device bank is active.

29. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same

amount.

30. tHP min is the lesser of tCL minimum and tCH

minimum actually applied to the device CK and

3.750 3.700 3.650 3.600 3.550

3.500 3.450

3.400 3.350 3.300 3.250

3.400 3.350 3.300

3.250

3.200 3.150 3.100 3.050

3.000 2.950 2.900

2.500 2.463 2.425 2.388 2.350 2.313 2.275 2.238 2.200 2.163 2.125

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55

Clock Duty Cycle

-335

-262/-26A/-265 @ tCK = 10ns

-202 @ tCK = 10ns

-262/-26A/-265 @ tCK = 7.5ns

-202 @ tCK = 8ns

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

CK/ inputs, collectively during device bank active.

31. READs and WRITEs with auto precharge are not

allowed to be issued until tRAS(MIN) can be satis-

fied prior to the internal precharge command

being issued.

32. Any positive glitch in the nominal voltage must be

less than 1/3 of the clock and not more than

+400mV or 2.9V maximum, whichever is less. Any

negative glitch must be less than 1/3 of the clock

cycle and not exceed either -300mV or 2.2V mini-

mum, whichever is more positive.

33. Normal Output Drive Curves:

a. The full variation in driver pull-down current

from minimum to maximum process, temper-

ature and voltage will lie within the outer

bounding lines of the V-I curve of Figure 8,

Pull-Down Characteristics.

b. The variation in driver pull-down current

within nominal limits of voltage and tempera-

ture is expected, but not guaranteed, to lie

within the inner bounding lines of the V-I

curve of Figure 8, Pull-Down Characteristics.

c. The full variation in driver pull-up current

from minimum to maximum process, temper-

ature and voltage will lie within the outer

bounding lines of the V-I curve of Figure 9,

Pull-Up Characteristics.

d. The variation in driver pull-up current within

nominal limits of voltage and temperature is

expected, but not guaranteed, to lie within the

inner bounding lines of the V-I curve of Figure

9, Pull-Up Characteristics.

e. The full variation in the ratio of the maximum

to minimum pull-up and pull-down current

should be between 0.71 and 1.4, for device

drain-to-source voltages from 0.1V to 1.0V, and

at the same voltage and temperature.

f. The full variation in the ratio of the nominal

pull-up to pull-down current should be unity

±10 percent, for device drain-to-source volt-

ages from 0.1V to 1.0V.

34. Reduced Output Drive Curves:

a. The full variation in driver pull-down current

from minimum to maximum process, tempera-

ture and voltage will lie within the outer

bounding lines of the V-I curve of Figure 10,

Reduced Output Pull-Down Characteristics, on

page 22.

b. The variation in driver pull-down current

within nominal limits of voltage and tempera-

ture is expected, but not guaranteed, to lie

within the inner bounding lines of the V-I curve

of Figure 10, Reduced Output Pull-Down Char-

acteristics, on page 22.

c. The full variation in driver pull-up current from

minimum to maximum process, temperature

and voltage will lie within the outer bounding

lines of the V-I curve of Figure 11, Reduced

Output Pull-Up Characteristics, on page 22.

d. The variation in driver pull-up current within

nominal limits of voltage and temperature is

expected, but not guaranteed, to lie within the

inner bounding lines of the V-I curve of

Figure 11, Reduced Output Pull-Up Character-

istics, on page 22.

e. The full variation in the ratio of the maximum

to minimum pull-up and pull-down current

should be between 0.71 and 1.4, for device

drain-to-source voltages from 0.1V to 1.0V, and

at the same voltage.

f. The full variation in the ratio of the nominal

pull-up to pull-down current should be unity

±10 percent, for device drain-to-source volt-

ages from 0.1V to 1.0V.

Figure 8: Pull-Down Characteristics Figure 9: Pull-Up Characteristics

160

140

IOUT (mA)

VOUT (V)

Nominal low

Minimum

Nominal high

Maximum

120

100

0.0 0.5 1.0 1.5 2.0 2.5

VOUT (V)

-20

IOUT (mA)

Nominal low

Minimum

Nominal high

Maximum

-40

-60

-80

-100

-120

-140

-160

-180

-200

0.0 0.5 1.0 1.5 2.0 2.5

VDDQ - VOUT (V)

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

35. The voltage levels used are derived from a mini-

mum VDD level and the referenced test load. In

practice, the voltage levels obtained from a prop-

erly terminated bus will provide significantly dif-

ferent voltage values.

36. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a

pulse width £ 3ns and the pulse width can not be

greater than 1/3 of the cycle rate. VIL undershoot:

VIL (MIN) = -1.5V for a pulse width £ 3ns and the

pulse width can not be greater than 1/3 of the

cycle rate.

37. VDD and VDDQ must track each other.

38. This maximum value is derived from the refer-

enced test load. In practice, the values obtained

in a typical terminated design may reflect up to

310ps less for tHZ(MAX) and the last DVW. tHZ

(MAX) will prevail over tDQSCK (MAX) + tRPST

(MAX) condition. tLZ (MIN) will prevail over

tDQSCK (MIN) + tRPRE (MAX) condition.

39. For slew rates greater than 1V/ns the (LZ) transi-

tion will start about 310ps earlier.

40. During initialization, VDDQ, VTT, and VREF must

be equal to or less than VDD + 0.3V. Alternatively,

VTT may be 1.35V maximum during power up,

even if VDD/VDDQ are 0V, provided a minimum of

42W of series resistance is used between the VTT

supply and the input pin.

41. The current Micron part operates below the slow-

est JEDEC operating frequency of 83 MHz. As

such, future die may not reflect this option.

42. tRAP ³ tRCD. Does not apply to -335 speed grade.

43. For -335, -262, -26A, and -265, IDD3N is specified

to be 35mA at 100 MHz.

44. Random addressing changing and 50 percent of

data changing at every transfer.

45. Random addressing changing and 100 percent of

data changing at every transfer.

46. CKE must be active (high) during the entire time a

refresh command is executed. That is, from the

time the AUTO REFRESH command is registered,

CKE must be active at each rising clock edge, until

tREF later.

47. IDD2N specifies the DQ, DQS, and DM to be

driven to a valid high or low logic level. IDD2Q is

similar to IDD2F except IDD2Q specifies the

address and control inputs to remain stable.

Although IDD2F, IDD2N, and IDD2Q are similar,

IDD2F is “worst case.”

48. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset.

This is followed by 200 clock cycles (before READ

commands).

49. Leakage number reflects the worst case leakage

possible through the module pin, not what each

memory device contributes.

50. The -335 module speed grade, using the -6R speed

device, has VDD (MIN) = 2.4V.

Figure 10: Reduced Output Pull-Down

Characteristics

Figure 11: Reduced Output Pull-Up

Characteristics

0.0 0.5 1.0 1.5 2.0 2.

OUT

(V)

OUT

(mA)

Nominal low

Minimum

Nominal high

Maximum

-50

-45

-40

-35

-30

-25

-20

-15

-10

-5

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

Q - V

OUT

(V)

OUT

(mA)

Nominal low

Minimum

Nominal high

Maximum

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions (as

shown in Figure 12, Data Validity, and Figure 13, Defi-

nition of Start and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL

is HIGH. The SPD device continuously monitors the

SDA and SCL lines for the start condition and will not

respond to any command until this condition has been

met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when

SCL is HIGH. The stop condition is also used to place

the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle, the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data (as shown in Fig-

ure 14, Acknowledge Response from Receiver).

The SPD device will always respond with an

acknowledge after recognition of a start condition and

its slave address. If both the device and a WRITE oper-

ation have been selected, the SPD device will respond

with an acknowledge after the receipt of each subse-

quent eight-bit word. In the read mode the SPD device

will transmit eight bits of data, release the SDA line and

monitor the line for an acknowledge. If an acknowl-

edge is detected and no stop condition is generated by

the master, the slave will continue to transmit data. If

an acknowledge is not detected, the slave will termi-

nate further data transmissions and await the stop

condition to return to standby power mode.

Figure 12: Data Validity Figure 13: Definition of Start and Stop

Figure 14: Acknowledge Response from Receiver

SCL

SDA

DATA STABLE DATA STABLEDATA

CHANGE

SCL

SDA

START

BIT

STOP

BIT

SCL from Master

Data Output

from Transmitter

Data Output

from Receiver

Acknowledge

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Figure 15: SPD EEPROM Timing Diagram

Table 17: EEPROM Device Select Code

Most significant bit (b7) is sent first

SELECT CODE DEVICE TYPE IDENTIFIER CHIP ENABLE RW

b7 b6 b5 b4 b3 b2 b1 b0

Memory Area Select Code (two arrays) 1 0 1 0 SA2 SA1 SA0 RW

Protection Register Select Code 0 1 1 0 SA2 SA1 SA0 RW

Table 18: EEPROM Operating Modes

MODE RW BIT WC BYTES INITIAL SEQUENCE

Current Address Read 1V

IH or VIL 1START, Device Select, RW = ‘1’

Random Address Read 0VIH or VIL 1START, Device Select, RW = ‘0’, Address

1VIH or VIL 1reSTART, Device Select, RW = ‘1’

Sequential Read 1VIH or VIL ³ 1 Similar to Current or Random Address Read

Byte Write 0V

IL 1START, Device Select, RW = ‘0’

Page Write 0VIL £ 16 START, Device Select, RW = ‘0’

SCL

SDA IN

SDA OUT

tLOW

tSU:STA tHD:STA

tFtHIGH tR

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the

EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA

remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

Table 19: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS

SUPPLY VOLTAGE VDDSPD 2.3 3.6 V

INPUT HIGH VOLTAGE: Logic 1; All inputs VIH VDDSPD ´ 0.7 VDDSPD + 0.5 V

INPUT LOW VOLTAGE: Logic 0; All inputs VIL -1 VDDSPD ´ 0.3 V

OUTPUT LOW VOLTAGE: IOUT = 3mA VOL –0.4V

INPUT LEAKAGE CURRENT: VIN = GND to VDD ILI –10µA

OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD ILO –10µA

STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD ISB –30µA

POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz ICC –2mA

Table 20: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SCL LOW to SDA data-out valid tAA 0.3 3.5 µs

Time the bus must be free before a new transition can start tBUF 4.7 µs

Data-out hold time tDH 300 ns

SDA and SCL fall time tF 300 ns

Data-in hold time tHD:DAT 0 µs

Start condition hold time tHD:STA 4 µs

Clock HIGH period tHIGH 4 µs

Noise suppression time constant at SCL, SDA inputs tI 100 ns

Clock LOW period tLOW 4.7 µs

SDA and SCL rise time tR1µs

SCL clock frequency tSCL 100 KHz

Data-in setup time tSU:DAT 250 ns

Start condition setup time tSU:STA 4.7 µs

Stop condition setup time tSU:STO 4.7 µs

WRITE cycle time tWRC 10 ms 1

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

Table 21: Serial Presence-Detect Matrix

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear following matrix

BYTE DESCRIPTION ENTRY (VERSION)

MT5VDDT872H MT5VDDT1672H

0Number of SPD Bytes Used by Micron 128 80 80

1Total Number of Bytes in SPD Device 256 08 08

2Fundamental Memory Type DDR SDRAM 07 07

3Number of Row Addresses on Assembly 12,13 0C 0D

4Number of Column Addresses on Assembly 10 09 09

5Number of Physical Ranks on DIMM 10101

6Module Data Width 72 48 48

7Module Data Width (Continued) 00000

8Module Voltage Interface Levels (VDDQ) SSTL 2.5V 04 04

9SDRAM Cycle Time, (tCK) CAS Latency = 2.5

(See note 1)

6ns (-335)

7ns (-262/-26A)

7.5ns (-265)

8ns (-202)

10 SDRAM Access From Clock (tAC) CAS Latency = 2.5 0.7ns (-335)

0.75ns (-262/-26A/-265)

0.8ns (-202)

11 Module Configuration Type ECC 02 02

12 Refresh Rate/Type 15.62µs, 7.8µs/SELF 80 82

13 SDRAM Device Width (Primary DDR SDRAM) 16 10 10

14 Error-checking DDR SDRAM Data Width 16 10 10

15 Minimum Clock Delay, Back-to-Back Random

Column Access

1 clock 01 01

16 Burst Lengths Supported 2, 4, 8 0E 0E

17 Number of Banks on DDR SDRAM Device 40404

18 CAS Latencies Supported 2, 2.5 0C 0C

19 CS Latency 00101

20 WE Latency 10202

21 SDRAM Module Attributes Unbuffered/Diff. Clock 20 20

22 SDRAM Device Attributes: General Fast/Concurrent AP C1 C1

23 SDRAM Cycle Time, (tCK) CAS Latency = 2 7.5ns (-335/-262/-26A)

10ns (-265/-202)

24 SDRAM Access From Clock (tAC) CAS Latency = 2 0.7ns (-335)

0.75ns (-262/-26A/-265)

0.8ns (-202)

25 SDRAM Cycle Time, (tCK) CAS Latency = 1.5 N/A 00 01

26 SDRAM Access from CK , (tAC) CAS Latency = 1.5 N/A 00 01

27 Minimum Row Precharge Time, (tRP) 18ns (-335)

15ns (-262)

20ns (-26A/-265/-202)

28 Minimum Row Active to Row Active, (tRRD) 12ns (-335)

15ns (-262/-26A/-265/-202)

29 Minimum RAS# to CAS# Delay, (tRCD)

18ns (-335)

15ns (

-262)

20ns (-26A/-265/-202)

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

30 Minimum RAS# Pulse Width, (tRAS), (See note 3) 42ns (-335)

45ns (-262/-26A/-265)

40ns (-202)

31 Module Rank Density 64MB, 128MB 10 20

32 Address and Command Setup Time, (tIS),

(See note 4)

0.8ns (-335)

1.0ns (-262/-26A/-265)

1.1ns (-202)

33 Address and Command Hold Time, (tIH),

(See note 4)

0.8ns (-335)

1.0ns (-262/-26A/-265)

1.1ns (-202)

34 Data/Data Mask Input Setup Time, (tDS) 0.45ns (-335)

0.5ns (-262/-26A/-265)

0.6ns (-202)

35 Data/Data Mask Input Hold Time, (tDH) 0.45ns (-335)

0.5ns (-262/-26A/-265)

0.6ns (-202)

36-40 Reserved 00 00

41 Minimum Active Auto Refresh Time (tRC) 60ns (335/-262)

65ns (-26A/-265)

70ns (-202)

42 Minimum Auto Refresh to Active/Auto Refresh

Command Period, (tRFC)

72ns (-335)

75ns (-262/-26A/-265)

80ns (-202)

43 SDRAM Device Max Cycle Time (tCKMAX)12ns (-335)

13ns (-262/-26A/-265/-202)

44 SDRAM Device Max DQS-DQ Skew Time (tDQSQ) 0.45ns (-335)

0.5ns (-262/-26A/-265)

0.6ns (-202)

45 SDRAM Device Max Read Data Hold Skew Factor

(tQHS)

0.55ns (-335)

0.75ns (-262/-26A/-265)

1.0ns (-202)

46 Reserved 00 00

47 DIMM Height 01 01

48–61 Reserved 00 00

62 SPD Revision Release 1.0 10 10

63 Checksum for Bytes 0-62 -335

-262

-26A

-265

-202

64 Manufacturer’s JEDEC ID Code MICRON 2C 2C

65-71 Manufacturer’s JEDEC IDCode (Continued) 00 00

72 Manufacturing Location 01–12 01 - 0C 01 - 0C

73-90 Module Part Number (ASCII) Variable Data Variable Data

91 PCB Identification Code 1-9 01 - 09 01 - 09

92 Identification Code (Continued) 00000

Table 21: Serial Presence-Detect Matrix (Continued)

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear following matrix

BYTE DESCRIPTION ENTRY (VERSION)

MT5VDDT872H MT5VDDT1672H

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice.

NOTE:

1. Value for -26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns.

2. The value of tRAS used for -262/-26A/-265 modules is calculated from tRC - tRP. Actual device spec. value is 40 ns.

3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is

represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-

mum slew rate is met.

93 Year of Manufacture in BCD Variable Data Variable Data

94 Week of Manufacturein BCD Variable Data Variable Data

95-98 Module Serial Number Variable Data Variable Data

99-127 Manufacturer-specific Data (RSVD) ––

Table 21: Serial Presence-Detect Matrix (Continued)

“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear following matrix

BYTE DESCRIPTION ENTRY (VERSION)

MT5VDDT872H MT5VDDT1672H

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

64MB, 128MB (x72, ECC)

200-PIN DDR SDRAM SODIMM

09005aef80a8e767 Micron Technology, Inc., reserves the right to change products or specifications without notice..

Figure 16: 200-Pin SODIMM Dimensions

NOTE:

All dimensions are in inches (millimeters) or typical where noted.

Data Sheet Designation

Released (No Mark): This data sheet contains mini-

mum and maximum limits specified over the complete

power supply and temrperature range for production

devices. Although considered final, these specifica-

tions are subject to change, as further product devel-

opment and data characterization sometimes occur.

U1 U2 U3 U4

0.150 (3.80)

MAX

0.043 (1.10)

0.035 (0.90)

PIN 1

2.666 (67.72)

2.656 (67.45)

0.787 (20.00)

TYP

0.071 (1.80)

(2X)

0.024 (0.60)

TYP

0.018 (0.45)

TYP

0.079 (2.00) R

(2X)

PIN 199

FRONT VIEW

0.085 (2.15)

0.236 (6.00)

2.504 (63.60)

TYP

0.091 (2.30)

0.039 (1.0)

TYP

1.244 (31.60)

1.256 (31.90)

0.449 (11.40)

TYP

1.87 (47.40)

TYP

BACK VIEW

PIN 2

PIN 200

MAX

MIN