Features
•Incorporates the ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-Circuit Emulation)
•8K Bytes On-chip SRAM
– 32-bit Data Bus
– Single-clock Cycle Access
•Fully-programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to 8 Chip Selects
– Software Programmable 8-/16-bit External Data Bus
•8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
•32 Programmable I/O Lines
•3-channel 16-bit Timer/Counter
– 3 External Clock Inputs
– 2 Multi-purpose I/O Pins per Channel
•2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
•Programmable Watchdog Timer
•Advanced Power-saving Features
– CPU and Peripheral Can be Deactivated Individually
•Fully Static Operation: 0 Hz to 40 MHz Internal Frequency Range at 3.0 V, 85°C
•1.8V to 3.6V Operating Range
•Available in a 100-lead TQFP Package
Description
The AT91M40800 microcontroller is a member of the Atmel AT91 16-/32-bit microcon-
troller family, which is based on the ARM7TDMI processor core. This processor has a
high-performance 32-bit RISC architecture with a high-density 16-bit instruction set
and very low power consumption. In addition, a large number of internally banked reg-
isters result in very fast exception handling, making the device ideal for real-time
control applications.
The AT91M40800 microcontroller features a direct connection to off-chip memory,
including Flash, through the fully-programmable External Bus Interface (EBI). An
eight-level priority vectored interrupt controller, in conjunction with the Peripheral Data
Controller, significantly improves the real-time performance of the device.
The device is manufactured using Atmel’s high-density CMOS technology. By combin-
ing the ARM7TDMI processor core with on-chip high-speed memory and a wide range
of peripheral functions on a monolithic chip, the AT91M40800 is a powerful microcon-
troller that offers a flexible, cost-effective solution to many compute-intensive
embedded control applications.
AT91
ARM® Thumb®
Microcontrollers
AT91M40800
Electrical
Characterisitics
1393C–ATARM–19-Nov-04
2 AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Absolute Maximum Ratings*
The following characteristics are applicable to the Operating Temperature range: TA = -40°C to +85°C, unless otherwise
specified and are certified for a Junction Temperature up to TJ = 100°C.
Operating Temperature (Industrial) .. -40°C to + 85°C*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional oper-
ation of the device at these or other conditions beyond
those indicated in the operational sections of this spec-
ification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
Storage Temperature ..................... -60°C to + 150°C
Voltage on Any Input Pin
with Respect to Ground......................-0.5V to + 5.5V
Maximum Operating Voltage ................................4.6V
DC Output Current ..............................................6 mA
Table 1. DC Characteristics
Symbol Parameter Conditions Min Typ Max Units
VDD DC Supply 1.8 3.6 V
VIL Input Low Voltage VDD = 3.3V 0.8 V
VIH Input High Voltage VDD = 3.3V 2.0 V
VOL Output Low Voltage IOL = 2.0 mA, VDD = 3.3V 0.4 V
VOH Output High Voltage IOH = 2.0 mA, VDD = 3.3V 2.4 V
ILEAK Input Leakage Current 4µA
IPULL Input Pull-up Current VDD = 3.6V, VIN = 0V 350 µA
CIN Input Capacitance 6.6 pF
ISC Static Current
VDD = 3.6V; MCKI = 0 Hz
All inputs driven
TMS, TDI, TCK, NRST = 1
TA = 25°C 12.5
µA
TA = 85°C 250
3
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Power Consumption The values in the following tables are measured values in the operating conditions indi-
cated (i.e., VDD = 3.3V or 2.0V, TA = 25°C) on the AT91EB40 Evaluation Board.
Table 2. Power Consumption
Mode Conditions
VDD
Unit2.0V 3.3V
Reset 0.06 0.10
mW/MHz
Normal
Fetch in ARM mode out of internal
SRAM
All peripheral clocks activated
1.38 4.63
Fetch in ARM mode out of internal
SRAM
All peripheral clocks deactivated
1.04 3.44
Idle All peripheral clocks activated 0.61 2.06
All peripheral clocks deactivated 0.19 0.79
Table 3. Power Consumption per Peripheral
Peripheral
VDD
Unit2.0V 3.3V
PIO Controller 0.01 0.16
mW/MHz
Timer/Counter Channel 0.01 0.15
Timer/Counter Block (3 Channels) 0.02 0.35
USART 0.03 0.40
4 AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Thermal and Reliability
Considerations
Thermal Data In Table 4, the device lifetime is estimated with the MIL-217 standard in the “moderately
controlled” environmental model (this model is described as corresponding to an instal-
lation in a permanent rack with adequate cooling air), depending on the device Junction
Temperature. (For details see the section “Junction Temperature” on page 5.)
Note that the user must be extremely cautious with this MTBF calculation: as the MIL-
217 model is pessimistic with respect to observed values due to the way the data/mod-
els are obtained (test under severe conditions). The life test results that have been
measured are always better than the predicted ones.
Table 5 summarizes the thermal resistance data related to the package of interest.
Reliability Data The number of gates and the device die size are provided for the user to calculate reli-
ability data with another standard and/or in another environmental model.
Table 4. MTBF Versus Junction Temperature
Junction Temperature (TJ) (°C) Estimated Lifetime (MTBF) (Year)
100 40
125 22
150 12
175 7
Table 5. Thermal Resistance Data
Symbol Parameter Condition Package Typ Unit
θJA Junction-to-ambient thermal
resistance
Still Air TQFP100 40 °C/
W
θJC Junction-to-case thermal resistance TQFP100 6.4
Table 6. Reliability Data
Parameter Data Unit
Number of Logic Gates 272 K gates
Number of Memory Gates 400 K gates
Device Die Size 17.6 mm2
5
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Junction Temperature The average chip-junction temperature TJ in °C can be obtained from the following:
1.
2.
Where:
•θ
JA
= package thermal resistance, Junction-to-ambient (°C/W), provided in Table 5
on page 4.
•θ
JC
= package thermal resistance, Junction-to-case thermal resistance (°C/W),
provided in Table 5 on page 4.
•θ
HEAT SINK
= cooling device thermal resistance (°C/W), provided in the device
datasheet.
•P
D = device power consumption (W) estimated from data provided in the section
“Power Consumption” on page 3.
•T
A = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and
thereby decide if a cooling device is necessary or not. If a cooling device is to be fitted
on the chip, the second equation should be used to compute the resulting average chip-
junction temperature
TJ
in °C.
TJTAPDθJA
×()+=
TJTAP(Dθ( HEATSINK
×θ
JC))++=
6 AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Conditions
Timing Results The delays are given as typical values in the following conditions:
•
VDD
= 3.3V
• Ambient Temperature = 25°C
• Load Capacitance = 0 pF
• The output level change detection is
0.5 x VDD
• The input level is
0.3 x VDD
for a low-level detection and is
0.7 x VDD
for a high level
detection.
The minimum and maximum values given in the AC characteristics tables of this
datasheet take into account the process variation and the design.
In order to obtain the timing for other conditions, the following equation should be used:
Where:
•
δ
T
°
is the derating factor in temperature given in Figure 1.
•
δ
VDD
is the derating factor for the Power Supply given in Figure 2.
•
tDATASHEET
is the minimum or maximum timing value given in this datasheet for a load
capacitance of 0 pF.
•
CSIGNAL
is the capacitance load on the considered output pin.(1)
•
δ
CSIGNAL
is the load derating factor depending on the capacitance load on the related
output pins given in Min and Max values in this datasheet.
The input delays are given as typical values.
The input delays are given as typical value.
Note: 1. The user must take into account the package capacitance load contribution (CIN)
described in Table 1 on page 2.
Temperature Derating
Factor
Figure 1. Derating Curve for Different Operating Temperatures
t
δ
T
°δ
VDD
×
t
(
DATASHEET
×
CSIGNAL
δ
CSIGNAL
×())
∑
+=
Derating Factor for
Typ Case is 1
1.3
1.2
1.1
1
0.9
0.8
-60 -40 -20 0 20 40 60 80 100 120 140 160
Operating Temperature (˚C)
Derating Factor
7
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Supply Voltage Derating
Factor
Figure 2. Derating Curve for Different Supply Voltages
Note: This derating factor is applicable only to timings related to output pins.
0.90
0.95
1.00
1.05
1.10
1.15
1.20
1.25
1.30
1.35
1.40
1.45
1.50
1.55
1.60
1.65
1.70
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
Supply Voltage (V)
Derating Factor
Typical Derating Factor
for Typ Case is 1
8 AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Clock Waveforms
Figure 3. Clock Waveform
Table 7. Master Clock Waveform Parameters
Symbol Parameter Conditions Min Max Units
1/(tCP) Oscillator Frequency 47.7 MHz
tCP Oscillator Period 21.0 ns
tCH High Half-period 9.1 ns
tCL Low Half-period 9.4 ns
Table 8. Clock Propagation Times
Symbol Parameter Conditions Min Max Units
tCDLH Rising Edge Propagation Time CMCKO = 0 pF 4.2 6.6 ns
CMCKO derating 0.034 0.053 ns/pF
tCDHL Falling Edge Propagation Time CMCKO = 0 pF 4.5 7.1 ns
CMCKO derating 0.042 0.066 ns/pF
tCH
tCL tCP
MCKI
MCKO
tCDLH tCDHL
0.7 VDD 0.3 VDD
0.5 VDD 0.5 VDD
9
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Figure 4. MCKO Relative to NRST
Table 9. NRST to MCKO
Symbol Parameter Min Max Units
tDNRST Rising Edge to MCKO Valid
Time
3(tCP/2) 7(tCP/2) ns
NRST
tD
MCKO
10 AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
AC Characteristics
EBI Signals Relative to MCKI
The following tables show timings relative to operating condition limits defined in the section “Timing Results” on page 6.
See Figure 5 on page 14.
Table 10. General-purpose EBI Signals
Symbol Parameter Conditions Min Max Units
EBI1MCKI Falling to NUB Valid CNUB = 0 pF 5.4 11.7 ns
CNUB derating 0.034 0.066 ns/pF
EBI2MCKI Falling to NLB/A0 Valid CNLB = 0 pF 4.3 8.7 ns
CNLB derating 0.038 0.062 ns/pF
EBI3MCKI Falling to A1 - A23 Valid CADD = 0 pF 4.2 10.0 ns
CADD = derating 0.038 0.066 ns/pF
EBI4
MCKI Falling to Chip Select
Change
CNCS = 0 pF 4.6 10.4 ns
CNCS derating 0.038 0.057 ns/pF
EBI5NWAIT Setup before MCKI Rising 0.6 ns
EBI6NWAIT Hold after MCKI Rising 3.2 ns
11
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Notes: 1. The derating factor should not be applied to tCH or tCP
.
2. n = number of standard wait states inserted.
Table 11. EBI Write Signals
Symbol Parameter Conditions Min Max Units
EBI7MCKI Rising to NWR Active (No Wait States) CNWR = 0 pF 4.3 7.1 ns
CNWR derating 0.042 0.066 ns/pF
EBI8MCKI Rising to NWR Active (Wait States) CNWR = 0 pF 5.0 8.2 ns
CNWR derating 0.042 0.066 ns/pF
EBI9MCKI Falling to NWR Inactive (No Wait States) CNWR = 0 pF 4.9 8.0 ns
CNWR derating 0.034 0.053 ns/pF
EBI10 MCKI Rising to NWR Inactive (Wait States) CNWR = 0 pF 5.0 8.2 ns
CNWR derating 0.034 0.053 ns/pF
EBI11 MCKI Rising to D0 - D15 Out Valid CDATA = 0 pF 4.1 8.6 ns
CDATA derating 00.066 ns/pF
EBI12 NWR High to NUB Change CNUB = 0 pF 3.3 7.6 ns
CNUB derating 0.034 0.066 ns/pF
EBI13 NWR High to NLB/A0 Change CNLB = 0 pF 2.8 4.6 ns
CNLB derating 0.042 0.066 ns/pF
EBI14 NWR High to A1 - A23 Change CADD = 0 pF 2.7 6.5 ns
CADD derating 0.042 0.066 ns/pF
EBI15 NWR High to Chip Select Inactive CNCS = 0 pF 3.2 6.4 ns
CNCS derating 0.034 0.066 ns/pF
EBI16 Data Out Valid before NWR High (No Wait States)(1)
C = 0 pF tCH - 0.9 ns
CDATA derating -0.066 ns/pF
CNWR derating 0.053 ns/pF
EBI17 Data Out Valid before NWR High (Wait States)(1)
C = 0 pF n x tCP - 0.8(2) ns
CDATA derating -0.066 ns/pF
CNWR derating 0.053 ns/pF
EBI18 Data Out Valid after NWR High 2.1 ns
EBI19 NWR Minimum Pulse Width (No Wait States)(1) CNWR = 0 pF tCH + 0.4 ns
CNWR derating -0.013 ns/pF
EBI20 NWR Minimum Pulse Width (Wait States)(1) CNWR = 0 pF n x tCP - 0.4(2) ns
CNWR derating -0.013 ns/pF
12 AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Notes: 1. Early Read Protocol.
2. Standard Read Protocol.
3. The derating factor should not be applied to tCH or tCP
.
4. n = number of standard wait states inserted.
5. Only one of these two timings needs to be met.
Table 12. EBI Read Signals
Symbol Parameter Conditions Min Max Units
EBI21 MCKI Falling to NRD Active(1) CNRD = 0 pF 5.0 9.0 ns
CNRD derating 0.042 0.066 ns/pF
EBI22 MCKI Rising to NRD Active(2) CNRD = 0 pF 4.1 8.6 ns
CNRD derating 0.042 0.066 ns/pF
EBI23 MCKI Falling to NRD Inactive(1) CNRD = 0 pF 5.2 9.4 ns
CNRD derating 0.034 0.053 ns/pF
EBI24 MCKI Falling to NRD Inactive(2) CNRD = 0 pF 4.9 7.7 ns
CNRD derating 0.034 0.053 ns/pF
EBI25 D0 - D15 In Setup before MCKI Falling Edge(5) -0.3 ns
EBI26 D0 - D15 In Hold after MCKI Falling Edge(5) 4.0 ns
EBI27 NRD High to NUB Change CNUB = 0 pF 4.1 8.4 ns
CNUB derating 0.034 0.066 ns/pF
EBI28 NRD High to NLB/A0 Change CNLB = 0 pF 3.3 5.2 ns
CNLB derating 0.042 0.066 ns/pF
EBI29 NRD High to A1 - A23 Change CADD = 0 pF 3.2 7.1 ns
CADD derating 0.042 0.066 ns/pF
EBI30 NRD High to Chip Select Inactive CNCS = 0 pF 3.6 6.9 ns
CNCS derating 0.034 0.066 ns/pF
EBI31 Data Setup before NRD High(5) CNRD = 0 pF 9.0 ns
CNRD derating 0.053 ns/pF
EBI32 Data Hold after NRD High(5) CNRD = 0 pF -2.4 ns
CNRD derating -0.034 ns/pF
EBI33 NRD Minimum Pulse Width(1)(3) CNRD = 0 pF (n +1) tCP - 0.7(4) ns
CNRD derating -0.013 ns/pF
EBI34 NRD Minimum Pulse Width(2)(3) CNRD = 0 pF n x tCP + (tCH - 0.9)(4) ns
CNRD derating -0.013 ns/pF
13
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Notes: 1. If this condition is not met, the action depends on the read protocol intended for use.
• Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle.
• Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state.
2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be
programmed.
Table 13. EBI Read and Write Control Signals. Capacitance Limitation
Symbol Parameter Conditions Min Max Units
TCPLNRD(1) Master Clock Low Due to NRD Capacitance CNRD = 0 pF 10.8 ns
CNRD derating 0.053 ns/pF
TCPLNWR(2) Master CLock Low Due to NWR Capacitance CNWR = 0 pF 8.6 ns
CNWR derating 0.053 ns/pF
14 AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Figure 5. EBI Signals Relative to MCKI
Notes: 1. Early Read Protocol.
2. Standard Read Protocol.
NCS
A1 - A23
NRD(1)
D0 - D15 Read
MCKI
NUB/NLB/A0
NRD(2)
NWAIT
NWR (No Wait States)
D0 - D15 to Write
NWR (Wait States)
No Wait Wait
EBI1/EBI2
EBI3
EBI4
EBI5EBI6
EBI7EBI9
EBI8EBI10
EBI11
EBI21
EBI22
EBI34
EBI26
CS
EBI23 EBI27 - 30
EBI24
EBI12 - 15
EBI16 EBI18
EBI18
EBI4
EBI33
EBI25
EBI32
EBI31
EBI19
EBI17
EBI20
15
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Peripheral Signals
USART Signals The inputs have to meet the minimum pulse width and period constraints shown in
Table 14 and Table 15, and represented in Figure 6.
Figure 6. USART Signals
Table 14. USART Input Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
US1SCK/RXD Minimum Pulse Width 5(tCP/2) ns
Table 15. USART Minimum Input Period
Symbol Parameter Min Input Period Units
US2SCK Minimum Input Period 9(tCP/2) ns
SCK
RXD
US1
US1
US2
16 AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Timer/Counter Signals Due to internal synchronization of input signals, there is a delay between an input event
and a corresponding output event. This delay is 3(tCP) in Waveform Event Detection
mode and 4(tCP) in Waveform Total-count Detection mode. The inputs have to meet the
minimum pulse width and minimum input period shown in Table 16 and Table 17, and
as represented in Figure 7.
Figure 7. Timer Input
Table 16. Timer Input Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
TC1TCLK/TIOA/TIOB Minimum Pulse Width 3(tCP/2) ns
Table 17. Timer Input Minimum Period
Symbol Parameter Min Input Period Units
TC2 TCLK/TIOA/TIOB Minimum Input Period 5(tCP/2) ns
MCKI
TIOA/
TIOB/
TCLK
TC1
3(tCP/2) 3(tCP/2)
TC2
17
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Reset Signals A minimum pulse width is necessary, as shown in Table 18 and as represented in Fig-
ure 8.
Figure 8. Reset Signal
Only the NRST rising edge is synchronized with MCKI. The falling edge is
asynchronous.
Table 18. Reset Minimum Pulse Width
Symbol Parameter Min Pulse-width Units
RST1NRST Minimum Pulse Width 10(tCP)ns
NRST
RST1
18 AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Advanced Interrupt Controller
Signals
Inputs have to meet the minimum pulse width and minimum input period shown in Table
19 and Table 20 and represented in Figure 9.
Figure 9. AIC Signals
Parallel I/O Signals
The inputs have to meet the minimum pulse width shown in
Table 21
and represented in
Fig-
ure 10
.
Figure 10. PIO Signal
Table 19. AIC Input Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
AIC1FIQ/IRQ0/IRQ1/IRQ2/IRQ3 Minimum Pulse Width 3(tCP/2) ns
Table 20. AIC Input Minimum Period
Symbol Parameter Min Input Period Units
AIC2AIC Minimum Input Period 5(tCP/2) ns
MCKI
FIQ/
IRQ0/IRQ1/
IRQ2/IRQ3
Input
AIC1
AIC2
Table 21. PIO Input Minimum Pulse Width
Symbol Parameter Min Pulse Width Units
PIO1PIO Input Minimum Pulse Width 3(tCP/2) ns
PIO
Inputs
PIO
1
19
AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
ICE Interface Signals
Figure 11. ICE Interface Signal
Table 22. ICE Interface Timing Specifications
Symbol Parameter Conditions Min Max Units
ICE0NTRST Minimum Pulse Width 18.8 ns
ICE1NTRST High Recovery to TCK High 1.2 ns
ICE2NTRST High Removal from TCK
High -0.2 ns
ICE3TCK Low Half-period 41.7 ns
ICE4TCK High Half-period 40.9 ns
ICE5TCK Period 82.5 ns
ICE6TDI, TMS Setup before TCK High 0.5 ns
ICE7TDI, TMS Hold after TCK High 0.6 ns
ICE8TDO Hold Time CTDO = 0 pF 5.2 ns
CTDO derating 0 ns/pF
ICE9TCK Low to TDO Valid CTDO = 0 pF 10.2 ns
CTDO derating 0.063 ns/pF
TCK
ICE3ICE4
ICE7
ICE6
ICE9
ICE8
TMS/TDI
TDO
ICE0
ICE5
NTRST
ICE1ICE2
20 AT91M40800 Electrical Characteristics
1393C–ATARM–19-Nov-04
Document Details
Title AT91M40800 Electrical Characteristics
Literature Number Lit# 1393B
Revision History
Version A Publication Date: Sep, 2000
Version B Publication Date: 10-Dec-2001
Revisions Since Previous Version published on Intranet
Page: 1
“Features” “Fully Static Operation: 0 Hz to 40 MHz Internal Frequency Range at 3.0 V,
85°C” ..... frequency and range modified
Page: 4
“Reliability Data” paragraph modified and new table inserted. “Table 6 Reliability Data”
Page: 6
“Timing Results” Cross reference added to CSIGNAL part of equation.
Page: 8
Table 7. Master Clock Waveform Parameters. Values have been changed for Oscillator
Frequency and Oscillator Period. Some master clock parameters deleted.
Page: 10
Table 10. General-purpose EBI Signals. EBI4, Conditions are changed.
Page: 13
New table inserted. Table 13. Read and Write Control Signals. Capacitance Limitation.
This table adds understanding to EBI Signals Relative to MCK.
Version C Publication Date: 19-Nov-2004
Page 8
Changes in Table 7: new figures for tCH and tCL, removed references to tr and tf. Updated
Figure 3 on page 8.
Printed on recycled paper.
1393C–ATARM–19-Nov-04
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