67 RadHard MSI Logic
UT54ACS132/UT54ACTS132
Radiation-Hardened
Quadruple 2-Input NAND Schmitt Triggers Dec. 1, 2003
FEATURES
•1.2µ radiation-hardened CMOS (ACTS 132) and 0.6µ CRH
CMOS process (ACS132)
- Latchup immune
• High speed
• Low power consumption
• Single 5 volt supply
• Available QML Q or V processes
• Flexible package
- 14-pin DIP (not available for the ACS132)
- 14-lead flatpack
DESCRIPTION
The UT54ACS132 and the UT54ACTS132 are 2-input NAND
gates with Schmitt Trigger input levels. A high applied on both
the inputs forces the output to a low state.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
LOGIC SYMBOL
PINOUTS 14-Pin DIP
Top View
14-Lead Flatpack
Top View
LOGIC DIAGRAM
INPUTS OUTPUT
An Bn Yn
L L H
L H H
H L H
H H L
Y1
(3)
(6) Y2
Y3
(8)
(11) Y4
(1)
A1 (2)
B1 (4)
A2 (5)
B2 (9)
A3 (10)
B3 (12)
A4 (13)
B4
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984
and IEC Publication 617-12.
&
A1
B1
Y1
A2
B2
Y2
VSS
VDD
B4
A4
Y4
B3
A3
Y3
114
213
312
411
510
69
78
VDD
B4
A4
Y4
B3
A3
Y3
A1
B1
Y1
A2
B2
Y2
VSS
114
213
312
411
510
69
78
B4
A4 Y4
B3
A3 Y3
A1
B1 Y1
A2
B2 Y2
RadHard MSI Logic 68
UT54ACS132/UT54ACTS132
RADIATION HARDNESS SPECIFICATIONS 1
Notes:
1. Logic will not latchup during radiation ex posure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E6 (ACTS132)
5.0E5 (ACS132) rads(Si)
SEU Thresh old 280 MeV-cm2/mg
SEL Threshold 120 MeV-cm2/mg
Neutron Fluence 1.0E14 n/cm2
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage -0.3 to 7.0 V
VI/O Voltage any pin -.3 to VDD +.3 V
TSTG Storage Temperature range -65 to +150 °C
TJMaximum junction temperature +175 °C
TLS Lead temperature (soldering 5 seconds) +300 °C
ΘJC Thermal resistance junction to case 20 °C/W
IIDC input current ±10 mA
PDMaximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage 4.5 to 5.5 V
VIN Input voltage any pin 0 to VDD V
TCTe mperature range -55 to + 125 °C
69 RadHard MSI Logic
UT54ACS132/UT54ACTS132
DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VT+Schmitt Trigger, positive going 1 threshold
ACTS
ACS 2.25
.7VDD V
VT-Schmitt Trigger, negative going 1 threshold
ACTS
ACS 0.5
.3VDD V
VHSchmitt Trigger, typical range of hysteresis 2
ACTS
ACS 0.3
0.6 0.9
1.5
V
IIN Input leakage current
ACTS/ACS VIN = VDD or VSS -1 1µA
VOL Low-level output voltage 3
ACTS
ACS IOL = 8.0mA
IOL = 100µA0.40
0.25 V
VOH High-level output voltage 3
ACTS
ACS IOH = -8.0mA
IOH = -100µA.7VDD
VDD - 0.25 V
IOS Short-circuit output current 2 ,4
ACTS/ACS VO = VDD and VSS -200 200 mA
IOL Output current10
(Sink)
VIN = VDD or VSS
VOL = 0.4V
8mA
IOH Output current10
(Source)
VIN = VDD or VSS
VOH = VDD - 0.4V
-8 mA
Ptotal Power dissipatio n 2, 8, 9 CL = 50pF 1.9 mW/
MHz
IDDQ Quiescent Supply Cur rent VDD = 5.5V 10 µA
∆IDDQ Quiescent Supply Current Delta
ACTS For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
3.1 mA
CIN Input capacitance 5ƒ = 1MHz @ 0V 15 pF
COUT Output capacitance 5 ƒ = 1MHz @ 0V 15 pF
RadHard MSI Logic 70
UT54ACS132/UT54ACTS132
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; V IL = VIL(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for curr ent density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All ACTS specifications are valid for radiation dose <1E6 rads(Si), and all ACS specifications are valid for radiation dose <5E5 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C)
Notes:
1. Maximum allowable relative shift equals 50mV.
2. For the ACTS version, all specifications are valid for radiation dose <1E6 rads(Si). For the ACS version, all specifications are valid for radiation dose <5E5 rads(Si).
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
tPHL Input to Yn 2 15 ns
tPLH Input to Yn 2 12 ns
