FEATURES
q45ns and 55ns maximum address access time
qAsynchronous operation for compatibility with industry-
standard 4K x 8/9 dual-port static RAM
qCMOS compatible inputs, TTL/CMOS compatible output
levels
qThree-state bidirectional data bus
qLow operating and standby current
qRadiation-hardened process and design; total dose
irradiation testing to MIL-STD-883 Method 1019
- Total-dose: 1.0E6 rads(Si)
- Memory Cell LET threshold: 85 MeV-cm2/mg
- Latchup immune (LET >100 MeV-cm2/mg)
qQML Q and QML V compliant part
qPackaging options:
- 68-lead Flatpack
- 68-pin PGA
q5-volt operation
qStandard Microcircuit Drawing 5962-96845
INTRODUCTION
The UT7C138 and UT7C139 are high-speed radiation-
hardened CMOS 4K x 8 and 4K x 9 dual-port static RAMs.
Arbitration schemes are included on the UT7C138/139 to
handle situations when multiple processors access the same
memory location. Two ports provide independent,
asynchronous access for reads and writes to any location in
memory. The UT7C138/139 can be utilized as a stand-alone
32/36-Kbit dual-port static RAM or multiple devices can be
combined in order to function as a 16/18-bit or wider master/
slave dual-port static RAM. For applications that require
depth expansion, the BUSY pin is open-collector allowing
for wired OR circuit configuration. An M/ S pin is provided
for implementing 16/18-bit or wider memory applications
without the need for separate master and slave devices or
additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications,
and status buffering.
Each port has independent control pins: chip enable (CE),
read or write enable (R/ W), and output enable (OE). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port.
Standard Products
UT7C138/139 4Kx8/9 Radiation-Hardened
Dual-Port Static RAM with Busy Flag
Data Sheet
January 2002
Figure 1. Logic Block Diagram
MEMORY
ARRAY
ROW
SELECT ROW
SELECT
COL
SEL COL
SEL
COLUMN
I/O COLUMN
I/O
R/WL
CE L
OEL
A11L
A10L
A9L
A0L
R/WR
CE R
OER
A11R
A10R
A9R
A0R
I/O 7L
I/O 8L (7C139) I/O7R
I/O8R (7C139)
I/O 0L I/O0R
ARBITRATION
BUSYLBUSYR
M/S
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
7C138/139
Figure 2a. DPRAM Pinout (68-Flatpack)
(top view)
A5L
A4L
A3L
A2L
A1L
A0L
NC
BUSYL
GND
M/S
BUSYR
NC
A0R
A1R
A2R
A3R
A4R
I/O7R
NC(1)
OER
R/WR
NC
CER
NC
NC
GND
NC
A11R
A10R
A9R
A8R
A7R
A6R
A5R
I/O1L
I/O0L
NC(2)
OE
R/WL
NC
CEL
NC
NC
VDD
NC
A11L
A10L
A9L
A8L
A7L
A6L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VDD
GND
I/O0R
I/O1R
I/O2R
VDD
I/O3R
I/O4R
I/O5R
I/O6R
Notes:
1. I/O8R on the7C139
2. I/O8L on the 7C139
3
Figure 2b: DPRAM Pinout (68 PGA)
(top view)
Notes:
1. I/O8R on the7C139
2. I/O8L on the 7C139
PIN NAMES
B11
A5L
C11
A4L
D11
A2L
E11
A0L
F11
BUSYL
G11
M/SH11
NC J11
A1R
K11
A3R
A10
A7L
B10
A6L
C10
A3L
D10
A1L
E10
NC F10
GND G10
BUSYR
H10
A0R
J10
A2R
K10
A4R
L10
A5R
A9
A9L
B9
A8L
K9
A7R
L9
A6R
A8
A11L
B8
A10L
K8
A9R
L8
A8R
A7
VDD
B7
NC K7
A11R
L7
A10R
A6
NC B6
NC K6
GND L6
NC
A5
NC B5
CEL
K5
NC L5
NC
A4
OEL
B4
R/WL
K4
NC L4
CER
A3
I/O0L
B3
NC(2) K3
OER
L3
R/WR
A2
I/O1L
B2
I/O2L
C2
I/O4L
D2
GND E2
I/O7L
F2
GND G2
I/O1R
H2
VDD
J2
I/O4R
K2
I/O7R
L2
NC(1)
B1
I/O3L
C1
I/O5L
D1
I/O6L
E1
VDD
F1
I/O0R
G1
I/O2R
H1
I/O3R
J1
I/O5R
K1
I/O6R
LEFT PORT RIGHT PORT DESCRIPTION
I/O0L-7L(8L) I/O0R-7R(8R) Data Bus Input/Output
A0L-11L A0R-11R Address Lines
CELCERChip Enable
OELOEROutput Enable
R/WLR/WRRead/Write Enable
BUSYLBUSYRBusy Flag Input/Output
M/SMaster or Slave Select
VDD Power
GND Ground
7C138/139
11
10
9
8
7
6
5
4
3
2
1
ABC D EFHJKLG
4
The UT7C138/139 consists of an array of 4K words of 8 or 9
bits of dual-port SRAM cells, I/O and address lines, and control
signals (CE, OE, R/W). These control pins permit independent
access for reads or writes to any location in memory. To handle
simultaneous writes/reads to the same location, a BUSY pin is
provided on each port. With the M/S pin, the UT7C138/139 can
function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). Each port is provided with its own
output enable control (OE), which allows data to be read from
the device.
WRITE CYCLE
A combination of R/W less than VIL (max), and CE less than
VIL (max), defines a write cycle. The state of OE is a “don’t
care” for a write cycle. The outputs are placed in the high-
impedance state when either OE is greater than VIH (min), or
when R/W is less than VIL (max).
WRITE OPERATION
Write Cycle 1, the Write Enable-controlled Access shown in
figure 4a, is defined by a write terminated by R/W going high
with CE active. The write pulse width is defined by tPWE when
the write is initiated by R/W, and by tSCE when the write is
initiated by CE going active. Unless the outputs have been
previously placed in the high-impedance state by OE, the user
must wait tHZOE before applying data to the eight/nine
bidirectional pins I/O(0:7/0:8) to avoid bus contention.
Write Cycle 2, the Chip Enable-controlled Access shown in
figure 4b, is defined by a write terminated by CE going inactive.
The write pulse width is defined by tPWE when the write is
initiated by R/W, and by tSCE when the write is initiated by CE
going active. For the R/ W initiated write, unless the outputs have
been previously placed in the high-impedance state by OE, the
user must wait tHZWE before applying data to the eight/nine
bidirectional pins I/O(0:7/0:8) to avoid bus contention.
If a location is being written by one port and the opposite port
attempts to read that location, a port-to-port flow through delay
must be met before the data is read on the output. Data will be
valid on the port wishing to read the location (tBZA + tBDD) after
the data is written on the other port (see figure 5a).
READ OPERATION
When reading the device, the user must assert both the OE and
CE pins. Data will be available tACE after CE or tDOE after OE
is asserted (see figures 3a and 3b).
MASTER/SLAVE
A M/S pin is provided in order to expand the word width by
configuring the device as either a master or a slave. The BUSY
output of the master is connected to the BUSY input of the slave.
Writing of slave devices must be delayed until after the BUSY
input has settled. Otherwise, the slave chip may begin a write
cycle during a contention situation. When presented as a HIGH
input, the M/S pin allows the device to be used as a master and,
therefore, the BUSY line is an output. BUSY can then be used
to send the arbitration outcome to a slave. When presented as a
LOW input, the M/S pin allows the device to be used as a slave,
and, therefore, the BUSY pin is an input.
Table 1. Non-Contending Read/Write
RADIATION HARDNESS
The UT7C138/139 incorporates special design and layout
features which allow operation in high-level radiation
environments. UTMC has developed special low-temperature
processing techniques designed to enhance the total-dose
radiation hardness of both the gate oxide and the field oxide
while maintaining the circuit density and reliability. For
transient radiation hardness and latchup immunity, UTMC
builds all radiation-hardened products on epitaxial wafers using
an advanced twin-tub CMOS process. In addition, UTMC pays
special attention to power and ground distribution during the
design phase, minimizing dose-rate upset caused by rail
collapse.
Table 2. Radiation Hardness
Design Specifications1
Notes:
1. The DPRAM will not latchup during radiation exposure under recommended
operating conditions.
2. Not tested for CMOS technology.
INPUTS OUTPUTS
CE R/WOE I/O0-7 OPERATION
HXXHigh Z Power Down
XXHHigh Z I/O Lines
Disabled
LHLData Out Read
LLXData In Write
LXX--- Illegal
Condition
Total Dose 1.0E6 rads(Si)
LET Threshold 85 MeV-cm2/mg
Neutron Fluence23.0E14 n/cm2
Memory Device
Cross Section @ LET
= 120MeV-cm2/mg
< 1.376E-2 (4Kx8)
< 1.548E-2 (4Kx9)
cm2
5
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012, infinite heat sink.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS
VDD DC supply voltage -0.5 to 7.0V
VI/O Voltage on any pin -0.5 to (VDD + 0.3)V
TSTG Storage temperature -65 to +150°C
PDMaximum power dissipation 2.0W
TJMaximum junction temperature2+150°C
ΘJC Thermal resistance, junction-to-case33.3°C/W
IIDC input current ±10 mA
SYMBOL PARAMETER LIMITS
VDD Positive supply voltage 4.5 to 5.5V
TCCase temperature range -55 to +125°C
VIN DC input voltage 0V to VDD
6
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(VDD = 5.0V ±10%; -55°C < TC < +125°C)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019.
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. VIH = 5.5V, VIL = 0V.
5. IDD (OP) derates at 6.4mA/MHz.
6. IDD (OP) derates at 3.4mA/MHz.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIH High-level input voltage (CMOS) 0.7VDD V
VIL Low-level input voltage (CMOS) 0.3VDD V
VOL Low-level output voltage IOL = 8mA, VDD = 4.5V (TTL) 0.4 V
VOL Low-level output voltage IOL = 200µA, VDD = 4.5V (CMOS) 0.05 V
VOH High-level output voltage IOH = -4mA, VDD = 4.5V (TTL) 2.4 V
VOH High-level output voltage IOH = -200µA, VDD = 4.5V (CMOS) 4.45 V
CIN1Input capacitance ƒ = 1MHz @ 0V 25 pF
CIO1Bidirectional I/O capacitance ƒ = 1MHz @ 0V 25 pF
IIN Input leakage current VIN = VDD and VSS -10 10 µA
IOZ Three-state output leakage current VO = VDD and VSS
VDD = 5.5V
G = 5.5V
-10 10 µA
IOS2,3 Short-circuit output current VDD = 5.5V, VO = VDD
VDD = 5.5V, VO = 0V -90 90 mA
mA
IDD(OP)4,5 Supply current operating (both ports)
@ 22.2MHz CMOS inputs (IOUT = 0)
VDD = 5.5V
300 mA
IDD(OP)4,6 Supply current operating (single port)
@ 22.2 MHz CMOS inputs (IOUT = 0)
VDD = 5.5V
150 mA
IDD(OP)4,5 Supply current operating (both ports)
@ 18.2MHz CMOS inputs (IOUT = 0)
VDD = 5.5V
275 mA
IDD(OP)4,6 Supply current operating (single port)
@ 18.2 MHz CMOS inputs (IOUT = 0)
VDD = 5.5V
138 mA
IDD(SB)4Supply current standby CMOS inputs (IOUT = 0)
CE = VDD - 0.5, VDD = 5.5V
1mA
7
AC CHARACTERISTICS READ CYCLE 1,2
(VDD = 5.0V±10%)
Notes:
1. Test conditions assume signal transition time of 5ns or less, timing reference levels of VDD/2, input pulse levels of 0.5V to VDD-0.5V, and output
loading of the specified IOL
/IOH and 50-pF load capacitance.
2. AC test conditions use VOH/VOL=VDD/2 + 500mV.
SYMBOL PARAMETER 7C138 - 45
7C139 - 45
MIN MAX
7C138 - 55
7C139 - 55
MIN MAX
UNIT
tRC Read cycle time 45 55 ns
tAA Address to data valid245 55 ns
tOHA Output hold from address change 5 5 ns
tACE CE LOW to data valid245 55 ns
tDOE OE LOW to data valid220 20 ns
tLZOE OE LOW to low Z 0 0 ns
tHZOE OE HIGH to high Z 20 20 ns
tLZCE CE LOW to low Z 0 0 ns
tHZCE CE HIGH to high Z 20 20 ns
8
Figure 3b. Read Cycle 2
CE
OE
Data Out tLZCE
tLZOE
tDOE
tACE
tHZOE
tHZCE
Figure 3c. Read Timing with Port-to-Port Delay
Address
R/WR
DataINR
AddressL
DATAOUTL
tWC
MATCH
tPWE
tSD tHD
VALID
MATCH
VALID
tDDD
tWDD
Assumptions:
1. Address valid prior to or coincident with CE transition LOW
2. R/W is HIGH for read cycle
Assumptions:
1. BUSY = HIGH for the writing port
2. CEL = CER = LOW
Address
Data Out
Figure 3a. Read Cycle 1
tRC
tOHA
tAA
Data Valid
Assumptions:
1.R/W is HIGH for read cycle
2.Device is continuously selected CE=LOW and OE=LOW
Previous Data Valid
9
AC CHARACTERISTICS WRITE CYCLE 1
(VDD = 5.0V±10%)
Notes:
1. For information on part-to-part delay through DPRAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform (see figure 3c).
SYMBOL PARAMETER 7C138 - 45
7C139 - 45
MIN MAX
7C138 - 55
7C139 - 55
MIN MAX
UNIT
tWC Write cycle time 45 55 ns
tSCE CE LOW to write end 40 50 ns
tAW Address set-up to write end 40 50 ns
tHA Address hold from write end 0 0 ns
tSA Address set-up to write start 0 0 ns
tPWE Write pulse width 40 50 ns
tSD Data set-up to write end 40 50 ns
tHD Data hold from write end 0 0 ns
tHZWE R/W LOW to high Z 20 20 ns
tLZWE R/W HIGH to low Z 0 0 ns
tWDD Write pulse to data delay 95 105 ns
tDDD Write data valid to read data valid 95 105 ns
tWHWL Write disable time 5 5 ns
10
Address
CE
R/W
Data in
OE
Data out
tWC
tSCE
tAW
tPWE
tHA
tSA tSD
tHZOE
tLZOE
DATA VALID
HIGH IMPEDANCEHIGH IMPEDANCE
tHD
Assumptions:
1. The internal write time of memory is defined by the overlap of CE
LOW and R/W LOW. Both signals must be LOW to initiate a write,
and either signal can terminate a write by going HIGH. The data input
set-up and hold timing should be referenced to the rising edge of the
signal that terminates the write.
2. If OE is LOW during a R/W controlled write cycle, the write pulse
width must be the larger of tPWE or (t HZWE + tSD ) to allow the I/O
drivers to turn off and data to be placed on the bus for the required tSD.
If OE is HIGH during a R/W controlled write cycle (as in this exam-
ple), this requirement does not apply and the write pulse can be as
short as the specified tPWE.
3. R/W must be HIGH during all address transactions.
Figure 4a. Write Cycle 1: OE Three-States Data I/Os (Either Port)
11
Address
CE
R/W
Data in
tWC
tSCE
tAW tPWE
tSA
tSD
DATA VALID
tHA
tLZWE
tHD
tHZWE HIGH IMPEDANCE
Figure 4b. Write Cycle 2: R/W Three-States Data I/Os (Either Port)
Assumptions:
1. The internal write time of memory is defined by the overlap of CE
LOW and R/W LOW. Both signals must be LOW to initialize a write,
and either signal can terminate a write by going HIGH. The data input
set-up and hold timing should be referenced to the rising edge of the sig-
nal that terminates the write.
2. R/W must be HIGH during all address transactions.
3. Data I/O pins enter high impedance even if OE is held LOW during
write.
Data out
tWHWL
12
AC CHARACTERISTICS BUSY CYCLE 1
(VDD = 5.0V±10%)
Notes:
1. Test conditions assume signal transition time of 5ns or less, timing reference levels of VDD/2, input pulse levels of 0.5V to VDD-0.5V, and output
loading of the specified IOL
/IOH and 50-pF load capacitance.
2. Violation of t PS (with addresses matching) results in at least one of the two busy output signals asserting, only one port remains busy.
3. When violating tPS, the busy signal asserts on one port or the other; there is no guarantee on which port the busy signal asserts.
SYMBOL PARAMETER 7C138 - 45
7C139 - 45
MIN MAX
7C138 - 55
7C139 - 55
MIN MAX
UNIT
tBLA BUSY LOW from address match 25 30 ns
tBZA BUSY HIGH-Z from address mismatch 25 30 ns
tBLC BUSY LOW from CE LOW 25 30 ns
tBZC BUSY HIGH from CE HIGH 25 30 ns
tPS2,3 Port set-up for priority 55 ns
tWB R/W LOW after BUSY LOW 00 ns
tWH R/W HIGH after BUSY HIGH 40 50 ns
tBDD BUSY HIGH to data valid 45 55 ns
13
AddressR
R/WR
Data InR
AddressL
BUSYL
DataOUTL
tWC
tPWE
tSD tHD
tPS
tBLA tBZA
tDDD
tWDD
VALID
MATCH
MATCH
VALID
Figure 5a. Read Timing with BUSY (M/S=HIGH)
Assumptions:
1. CEL = CER = LOW
tBDD
BUSY
R/WtPWE
tWB tWH
Figure 5b. Write Timing with BUSY (M/S=LOW)
14
AddressL,R
CEL
CER
BUSYR
AddressL,R
CER
CEL
BUSYL
ADDRESS MATCH
ADDRESS MATCH
tPS
tBLC tBZC
tPS
tBLC tBZC
Figure 5c. BUSY Timing Diagram No. 1 (CE Arbitration)
CEL Valid First:
CER Valid First:
Assumptions:
1. If tPS is violated, the BUSY signal will be asserted on
one side or the other, but there is no guarantee on which
side BUSY will be asserted.
15
AddressL
AddressR
BUSYR
AddressR
AddressL
BUSYL
ADDRESS MATCH ADDRESS MISMATCH
ADDRESS MATCH ADDRESS MISMATCH
tPS
tBZA
tRC or tWC
tRC or tWC
tPS
tBLA
tBLA tBZA
Figure 5d. BUSY Timing Diagram No. 2 (Address Arbitration)
Right Address Valid First:
Left Address Valid First:
Assumptions:
1. If t
PS is violated, the BUSY signal will be asserted on
one side or the other, but there is no guarantee on which
side BUSY will be asserted.
16
DATA RETENTION CHARACTERISTICS (Pre-Radiation)
(TC = 25°C)
Notes:
1. CE equals VDR, all other inputs equal VDR or VSS.
2. Guaranteed but not tested.
SYMBOL PARAMETER MINIMUM MAXIMUM
VDD @
2.5V
UNIT
VDR VDD for data retention 2.5 -- V
IDDR1Data retention current -- 400 µA
tEFR1,2 Chip deselect to data retention time 0ns
tR1,2 Operation recovery time tWC or tRC ns
VDD
CE
DATA RETENTION MODE
tR
4.5V
4.5V VDR 2.5V
Figure 6. Low VDD Data Retention Waveform
tEFR VDR
VIN < 1.5V CMOS
Notes:
1. 50pF including scope probe and test socket.
2. Measurement of data output occurs at the low to high or high to low transition mid-point
(CMOS input = VDD/2).
90%
Figure 7. AC Test Loads and Input Waveforms
Input Pulses
10%
< 5ns < 5ns
460 ohms
VDD/2
50pF
CMOS
0.5V
VDD-0.5V
17
Figure 8. 68-lead Flatpack
Notes:
1. All package finishes are per MIL-PRF-38535.
2. Letter designations are for cross-reference to MIL-STD-1835.
3. All leads increase max limit by 0.003 measured at the center of the
flat, when lead finish A (solder) is applied.
4. ID mark: Configuration is optional.
5. Lettering is not subject to marking criteria.
6. Total weight is approximately 4.5 grams.
18
L
K
J
H
G
F
E
D
C
B
A1 2 3 4 5 6 7 8 109 11
11 10 9 8 7 6 5 4 23 1
L
K
J
H
G
F
E
D
C
B
A
Figure 9. 68-pin PGA
Notes:
1. All packages finishes are per MIL-PRF-38535.
2. True position applies at base plane (Datum C).
3. True position applies at pin tips.
4. Letter designations are for cross-reference to MIL-STD-1835.
5. Total weight is approximately 7.0 grams.
19
ORDERING INFORMATION
UT7C138/UT7C139 Dual-Port SRAM: SMD
Lead Finish:
(A) = Solder
(C) =Gold
(X) =Optional
Case Outline:
(X) =68-pin PGA
(Y) =68-lead Flatpack
Class Designator:
(Q) =Class Q
(V) =Class V
Device Type
(01) = 4Kx8, CMOS Compatible Inputs, 45ns
(02) = 4Kx9, CMOS Compatible Inputs, 45ns
(03) = 4Kx8, CMOS Compatible Inputs, 55ns
(04) = 4Kx9, CMOS Compatible Inputs, 55ns
Drawing Number: 96845
Total Dose:
(H) =1E6 rads(Si)
(G) =5E5 rads(Si)
(F) =3E5 rads(Si)
(R) =1E5 rads(Si)
Federal Stock Class Designator: No options
5962 * 96845 * * * *
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
20
UT7C138/UT7C139 Dual-Port SRAM
UT **** *** - * * * * * *
Total Dose:
( ) = None
Lead Finish:
(A) =Solder
(C) = Gold
(X) =Optional
Screening:
(C) =Military Temperature Range flow
(P) =Prototype flow
Package Type:
(G) =68-lead PGA
(W) =68-lead Flatpack
Access Time:
(45) = 45ns access time
(55) =55ns access time
Device Type Modifier:
(C) =CMOS-compatible Inputs, 5.0V operation
Device Type:
(7C138) = 4Kx8 Dual-Port SRAM
(7C139) = 4Kx9 Dual-Port SRAM
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Military Temperature Range flow per UTMC Manufacturing Flows Document. Radiation characteristics are neither tested nor guaranteed and may
not be specified.
4. Prototypes are produced to UTMC’s prototype flow and are tested at 25°C only. Radiation characteristics are neither tested nor guaranteed. Lead finish
is GOLD only.
UTMC Main Office European Sales Office Boston Sales Office
4350 Centennial Blvd. 1+719-594-8166 40 Mall Road, Suite 203
Colorado Springs, CO 80907-3486 1+719-594-8468 FAX Burlington, MA 01830
800-MIL-UTMC http://www.utmc.com 781-221-4122
800-645-8862
http://www.utmc.com
Melbourne Sales Office South LA Sales Office
1901 S. Harbor City Blvd., Suite 802 101 Columbia Street, Suite 130
Melbourne, FL 32901 Aliso Viejo, CA 92656
407-951-4164 714-362-2260
DUALPORT-2-12-97
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