CY62157EV30 MoBL®
8 Mbit (512K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document #: 38-05445 Rev. *H Revised December 20, 2010
Features
■Thin small outline package (TSOP) I package configurable as
512K x 16 or 1M x 8 static RAM (SRAM)
■High speed: 45 ns
■Temperature ranges
❐Industrial: –40°C to +85°C
❐Automotive-A: –40°C to +85°C
❐Automotive-E: –40°C to +125°C
■Wide voltage range: 2.20V to 3.60V
■Pin compatible with CY62157DV30
■Ultra low standby power
❐Typical standby current: 2 A
❐Maximum standby current: 8 A (Industrial)
■Ultra low active power
❐ Typical active current: 1.8 mA at f = 1 MHz
■Easy memory expansion with CE1, CE2, and OE features
■Automatic power down when deselected
■Complementary Metal Oxide Semiconductor (CMOS) for
optimum speed and power
■Available in Pb-free and non Pb-free 48-Ball very fine ball grid
array (VFBGA), Pb-free 44-Pin TSOP II and 48-Pin TSOP I
packages
Functional Description
The CY62157EV30 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Place the device
into standby mode when deselected (CE1 HIGH or CE2 LOW or
both BHE and BLE are HIGH). The input or output pins (I/O0
through I/O15) are placed in a high impedance state when the
device is deselected (CE1HIGH or CE2 LOW), the outputs are
disabled (OE HIGH), Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or a write operation is active (CE1
LOW, CE2 HIGH and WE LOW).
To write to the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is
written into the location specified on the address pins (A0 through
A18). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O8 through I/O15) is written into the location specified on the
address pins (A0 through A18).
To read from the device, take Chip Enable (CE1 LOW and CE2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O8 to I/O15. See the Truth Table on page
11 for a complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
512K × 16/1M x 8
RAM Array I/O0–I/O7
ROW DECODER
A 8
A 7
A 6
A 5
A 2
COLUMN DECODER
A11
A12
A13
A14
A15
SENSE AMPS
DATA IN DRIVERS
OE
A 4
A 3I/O8–I/O15
WE
BLE
BHE
A16
A 0
A 1
A17
A 9
A18
A10
Power Down
Circuit BHE
BLE
CE2
CE1CE2
CE1
BYTE
Logic Block Diagram
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CY62157EV30 MoBL®
Document #: 38-05445 Rev. *H Page 2 of 17
Contents
Pin Configuration .............................................................3
Product Portfolio ..............................................................3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics .................................................4
Capacitance ...................................................................... 5
Thermal Resistance ..........................................................5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................6
Switching Characteristics ................................................7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Ordering Information ...................................................... 12
Ordering Code Definitions ......................................... 12
Package Diagrams .......................................................... 13
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 17
Worldwide Sales and Design Support ....................... 17
Products ....................................................................17
PSoC Solutions .........................................................17
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Pin Configuration
Figure 1. 48-Ball VFBGA (Top View) [2] Figure 2. 44-Pin TSOP II (Top View) [3]
Figure 3. 48-Pin TSOP I (512K x 16/1M x 8) (Top View) [2, 4]
WE
VCC
A11
A10
NC
A6
A0
A3CE1
I/O10
I/O8
I/O9
A4
A5
I/O11
I/O13
I/O12
I/O14
I/O15
V
SS
A9
A8
OE
V
SS
A7
I/O0
BHE
CE2
A2
A1
BLE
V
CC
I/O2
I/O1
I/O3
I/O4
I/O5I/O6
I/O7
A15
A14
A13
A12
NC
A18 NC
3
26
5
4
1
D
E
B
A
C
F
G
H
A16
A17
1
2
3
4
5
6
7
8
9
11
14 31
32
36
35
34
33
37
40
39
38
12
13
41
44
43
42
16
15
29
30
18
17
20
19
27
28
25
26
22
21
23
24
10
A
5
A
6
A
7
A
4
A
3
A
2
A
1
A
0
A
17
A
18
A
9
A
10
A
11
A
12
A
15
A
16
A
14
A
13
OE
BHE
BLE
CE
WE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
V
CC
V
CC
V
SS
V
SS
A
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
CE2
NC
BHE
BLE
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
Vss
I/O15/A19
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
Vcc
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
Vss
CE1
A0
Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC, (mA) Standby, ISB2
(A)
f = 1 MHz f = fmax
Min Typ [1] Max Typ [1] Max Typ [1] Max Typ [1] Max
CY62157EV30LL Industrial/
Auto-A
2.2 3.0 3.6 45 1.8 3 18 25 2 8
Auto-E 2.2 3.0 3.6 55 1.8 4 18 35 2 30
Notes
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.
2. NC pins are not connected on the die.
3. The 44-TSOP II package has only one chip enable (CE) pin.
4. The BYTE pin in the 48-TSOP I package must be tied HIGH to use the device as a 512K × 16 SRAM. The 48-TSOP I package can also be used as a 1M × 8
SRAM by tying the BYTE signal LOW. In the 1M x 8 configuration, Pin 45 is A19, while BHE, BLE and I/O8 to I/O14 pins are not used (NC).
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CY62157EV30 MoBL®
Document #: 38-05445 Rev. *H Page 4 of 17
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. User guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied .......................................... –55°C to + 125°C
Supply Voltage to Ground
Potential ................................–0.3V to 3.9V (VCCmax + 0.3V)
DC Voltage Applied to Outputs
in High-Z State [5, 6] ...............–0.3V to 3.9V (VCCmax + 0.3V)
DC Input Voltage [5, 6] ........... –0.3V to 3.9V (VCC max + 0.3V)
Output Current into Outputs (LOW) ............................ 20 mA
Static Discharge Voltage .......................................... > 2001V
(MIL-STD-883, Method 3015)
Latch Up Current ...................................................> 200 mA
Operating Range
Device Range Ambient
Temperature VCC [7]
CY62157EV30LL Industrial/
Auto-A
–40°C to +85°C 2.2V to
3.6V
Auto-E –40°C to +125°C
Electrical Characteristics
Over the Operating Range
Parameter Description Test Conditions 45 ns (Ind’l/Auto-A) 55 ns (Auto-E) Unit
Min Typ [8] Max Min Typ [8] Max
VOH Output HIGH
voltage
IOH = –0.1 mA 2.0 2.0 V
IOH = –1.0 mA, VCC > 2.70V 2.4 2.4 V
VOL Output LOW
voltage
IOL = 0.1 mA 0.4 0.4 V
IOL = 2.1mA, VCC > 2.70V 0.4 0.4 V
VIH Input HIGH
voltage
VCC = 2.2V to 2.7V 1.8 VCC + 0.3 1.8 VCC + 0.3 V
VCC = 2.7V to 3.6V 2.2 VCC + 0.3 2.2 VCC + 0.3 V
VIL Input LOW
voltage
VCC = 2.2V to 2.7V –0.3 0.6 –0.3 0.6 V
VCC = 2.7V to 3.6V –0.3 0.8 –0.3 0.8 V
IIX Input leakage
current
GND < VI < VCC –1 +1 –4 +4 A
IOZ Output leakage
current
GND < VO < VCC, Output Disabled –1 +1 –4 +4 A
ICC VCC operating
supply current
f = fmax = 1/tRC VCC = VCCmax
IOUT = 0 mA
CMOS levels
18 25 18 35
mA
f = 1 MHz 1.8 3 1.8 4
ISB1 Automatic CE
power down
current — CMOS
inputs
CE1 > VCC 0.2V, CE2 < 0.2V
VIN > VCC – 0.2V, VIN < 0.2V)
f = fmax (Address and Data Only),
f = 0 (OE, BHE, BLE and WE),
VCC = 3.60V
28 230A
ISB2 [9] Automatic CE
power down
current — CMOS
inputs
CE1 > VCC – 0.2V or CE2 < 0.2V,
VIN > VCC – 0.2V or VIN < 0.2V,
f = 0, VCC = 3.60V
28 230A
Notes
5. VIL(min) = –2.0V for pulse durations less than 20 ns.
6. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a 100 s ramp time from 0 to Vcc(min) and 200 s wait time after VCC stabilization.
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
9. Chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE (48 TSOP I only) need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can
be left floating.
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CY62157EV30 MoBL®
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Capacitance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions Max Unit
CIN Input capacitance TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
10 pF
COUT Output capacitance 10 pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters.
Parameter Description Test Conditions BGA TSOP I TSOP II Unit
JA Thermal resistance
(Junction to Ambient) Still air, soldered on a 3 × 4.5 inch,
two-layer printed circuit board 72 74.88 76.88 C/W
JC Thermal resistance
(Junction to Case) 8.86 8.6 13.52 C/W
Figure 4. AC Test Loads and Waveforms
Parameters 2.5V 3.0V Unit
R1 16667 1103
R2 15385 1554
RTH 8000 645
VTH 1.20 1.75 V
VCC VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10% 90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THÉ VENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
TH
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CY62157EV30 MoBL®
Document #: 38-05445 Rev. *H Page 6 of 17
Data Retention Characteristics
Over the Operating Range
Parameter Description Conditions Min Typ [10] Max Unit
VDR VCC for data retention 1.5 V
ICCDR Data retention current VCC= 1.5V, CE1 > VCC – 0.2V,
CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V
Industrial/
Auto-A
25A
Auto-E 30
tCDR [11] Chip deselect to data
retention time
0ns
tR [12] Operation recovery time tRC ns
Data Retention Waveform
Figure 5. Data Retention Waveform [13]
VCC(min)
tCDR
VDR >1.5V
DATA RETENTION MODE
tR
VCC(min)
CE1 or
VCC
BHE.BLE
CE
2
or
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
13. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE.
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CY62157EV30 MoBL®
Document #: 38-05445 Rev. *H Page 7 of 17
Switching Characteristics
Over the Operating Range[14, 15]
Parameter Description 45 ns (Ind’l/Auto-A) 55 ns (Auto-E) Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 45 55 ns
tAA Address to data valid 45 55 ns
tOHA Data hold from address change 10 10 ns
tACE CE1 LOW and CE2 HIGH to data valid 45 55 ns
tDOE OE LOW to data valid 22 25 ns
tLZOE OE LOW to LOW-Z[16] 55ns
tHZOE OE HIGH to High-Z[16, 17] 18 20 ns
tLZCE CE1 LOW and CE2 HIGH to Low-Z[16] 10 10 ns
tHZCE CE1 HIGH and CE2 LOW to High-Z[16, 17] 18 20 ns
tPU CE1 LOW and CE2 HIGH to power up 0 0 ns
tPD CE1 HIGH and CE2 LOW to power down 45 55 ns
tDBE BLE/BHE LOW to data valid 45 55 ns
tLZBE BLE/BHE LOW to Low-Z[16, 18] 510ns
tHZBE BLE/BHE HIGH to HIGH-Z[16, 17] 18 20 ns
Write Cycle[19]
tWC Write cycle time 45 55 ns
tSCE CE1 LOW and CE2 HIGH to write end 35 40 ns
tAW Address setup to write end 35 40 ns
tHA Address hold from write end 0 0 ns
tSA Address setup to write start 0 0 ns
tPWE WE pulse width 35 40 ns
tBW BLE/BHE LOW to write end 35 40 ns
tSD Data setup to write end 25 25 ns
tHD Data hold from write end 0 0 ns
tHZWE WE LOW to High-Z[16, 17] 18 20 ns
tLZWE WE HIGH to Low-Z[16] 10 10 ns
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of VCC(typ)/2, input pulse
levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 5.
15. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.
16. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
18. If both byte enables are toggled together, this value is 10 ns.
19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a
write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
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Switching Waveforms
Figure 6 shows Address Transition Controlled read cycle waveforms.[20, 21]
Figure 6. Read Cycle No. 1
Figure 7 shows OE Controlled read cycle waveforms. [21, 22]
Figure 7. Read Cycle No. 2
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tPD
tHZBE
tLZBE
t
HZCE
tDBE
OE
CE1
ADDRESS
CE2
BHE/BLE
DATA OUT
VCC
SUPPLY
CURRENT
HIGH
ICC
ISB
IMPEDANCE
Notes
20. The device is continuously selected. OE, CE1 = VIL, BHE, BLE, or both = VIL, and CE2 = VIH.
21. WE is HIGH for read cycle.
22. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH.
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CY62157EV30 MoBL®
Document #: 38-05445 Rev. *H Page 9 of 17
Figure 8 shows WE Controlled write cycle waveforms.[23, 24, 25]
Figure 8. Write Cycle No. 1
Figure 9 shows CE1 or CE2 Controlled write cycle waveforms.[23, 24, 25]
Figure 9. Write Cycle No. 1
Switching Waveforms (continued)
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
VALID DATA
tBW
NOTE 26
CE1
ADDRESS
CE2
WE
DATA I/O
OE
BHE/BLE
tHD
tSD
tPWE
tHA
tAW
tSCE
tWC
tHZOE
VALID DATA
tBW
tSA
NOTE 26
CE1
ADDRESS
CE2
WE
DATA I/O
OE
BHE/BLE
Notes
23. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a
write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that
terminates the write.
24. Data I/O is high impedance if OE = VIH.
25. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
26. During this period, the I/Os are in output state. Do not apply input signals.
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CY62157EV30 MoBL®
Document #: 38-05445 Rev. *H Page 10 of 17
Figure 10 shows WE Controlled, OE LOW write cycle waveforms.[27]
Figure 10. Write Cycle No. 3
Figure 11 shows BHE/BLE Controlled, OE LOW write cycle waveforms.[27]
Figure 11. Write Cycle No. 4
Switching Waveforms (continued)
VALID DATA
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
tBW
NOTE 28
CE
1
ADDRESS
CE
2
WE
DATA I/O
BHE
/BLE
tHD
tSD
tSA
tHA
tAW
tWC
VALID DATA
tBW
tSCE
tPWE
NOTE 28
CE
1
ADDRESS
CE
2
WE
DATA I/O
BHE
/BLE
Notes
27. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.
28. During this period, the I/Os are in output state. Do not apply input signals.
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CY62157EV30 MoBL®
Document #: 38-05445 Rev. *H Page 11 of 17
Truth Table
CE1CE2WE OE BHE BLE Inputs/Outputs Mode Power
H X[29] X X X X High-Z Deselect/power down Standby (ISB)
X[29] L X X X X High-Z Deselect/power down Standby (ISB)
X[29] X[29] X X H H High-Z Deselect/power down Standby (ISB)
L H H L L L Data Out (I/O0–I/O15)Read Active (ICC)
L H H L H L Data Out (I/O0–I/O7);
High-Z (I/O8–I/O15)
Read Active (ICC)
L H H L L H High-Z (I/O0–I/O7);
Data Out (I/O8–I/O15)Read Active (ICC)
L H H H L H High-Z Output disabled Active (ICC)
L H H H H L High-Z Output disabled Active (ICC)
L H H H L L High-Z Output disabled Active (ICC)
L H L X L L Data In (I/O0–I/O15)Write Active (ICC)
L H L X H L Data In (I/O0–I/O7);
High-Z (I/O8–I/O15)Write Active (ICC)
L H L X L H High-Z (I/O0–I/O7);
Data In (I/O8–I/O15)
Write Active (ICC)
Note
29. The ‘X’ (Don’t care) state for the Chip enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted
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CY62157EV30 MoBL®
Document #: 38-05445 Rev. *H Page 12 of 17
Ordering Information
Speed
(ns) Ordering Code
Package
Diagram Package Type Operating
Range
45 CY62157EV30LL-45BVI 51-85150 48-ball very fine pitch ball grid array Industrial
CY62157EV30LL-45BVXI 51-85150 48-ball very fine pitch ball grid array (Pb-free)
CY62157EV30LL-45ZSXI 51-85087 44-pin thin small outline package type II (Pb-free)
CY62157EV30LL-45ZXI 51-85183 48-pin thin small outline package type I (Pb-free)
CY62157EV30LL-45BVXA 51-85150 48-ball very fine pitch ball grid array (Pb-free) Automotive-A
CY62157EV30LL-45ZSXA 51-85087 44-pin thin small outline package type II (Pb-free)
CY62157EV30LL-45ZXA 51-85183 48-pin thin small outline package type I (Pb-free)
55 CY62157EV30LL-55ZSXE 51-85087 44-pin thin small outline package type II (Pb-free) Automotive-E
CY62157EV30LL-55ZXE 51-85183 48-pin thin small outline package type I (Pb-free)
Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions
Temperature Range: I = Industrial, A = Automotive-A, E = Automotive-E
ZSX = 44-pin TSOP II (Pb-free), BVX = 48-ball VFBGA (Pb-free) Pinout - 1
xx = Speed Grade
Low Power
Voltage
E = Process Technology 90 nm
Buswidth = × 6
Density = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
CY xx xxx
621 57EV30 LL I/A/E
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CY62157EV30 MoBL®
Document #: 38-05445 Rev. *H Page 14 of 17
Figure 13. 44-Pin TSOP II, 51-85087
Package Diagrams (continued)
MAX
MIN.
DIMENSION IN MM (INCH)
(OPTIONAL)
CAN BE LOCATED
ANYWHERE IN THE
BOTTOM PKG
EJECTOR MARK
Z
A
Z
Z
Z
Z
X
A
10.058 (0.396)
10.262 (0.404)
0.597 (0.0235)
0.406 (0.0160)
0.210 (0.0083)
0.120 (0.0047)
TOP VIEW BOTTOM VIEW
PLANE
SEATING
18.517 (0.729)
0.800 BSC
0°-5°
0.400(0.016)
0.300 (0.012)
1.194 (0.047)
0.991 (0.039)
0.150 (0.0059)
0.050 (0.0020)
(0.0315)
18.313 (0.721)
BASE PLANE
0.10 (.004)
11.938 (0.470)
PIN 1 I.D.
44
1
11.735 (0.462)
10.058 (0.396)
10.262 (0.404)
22
23
51-85087-*C
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Document #: 38-05445 Rev. *H Page 16 of 17
Document History Page
Document Title: CY62157EV30 MoBL®, 8 Mbit (512K x 16) Static RAM
Document Number: 38-05445
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 202940 AJU See ECN New Data Sheet
*A 291272 SYT See ECN Converted from Advance Information to Preliminary
Removed 48-TSOP I Package and the associated footnote
Added footnote stating 44 TSOP II Package has only one CE on Page # 2
Changed VCC stabilization time in footnote #7 from 100 s to 200 s
Changed ICCDR from 4 to 4.5 A
Changed tOHA from 6 to 10 ns for both 35 and 45 ns Speed Bins
Changed tDOE from 15 to 18 ns for 35 ns Speed Bin
Changed tHZOE, tHZBE and tHZWE from 12 and 15 ns to 15 and 18 ns for 35 and 45
ns Speed Bins respectively
Changed tHZCE from 12 and 15 ns to 18 and 22 ns for 35 and 45 ns Speed Bins
respectively
Changed tSCE, tAW and tBW from 25 and 40 ns to 30 and 35 ns for 35 and 45 ns Speed
Bins respectively
Changed tSD from 15 and 20 ns to 18 and 22 ns for 35 and 45 ns Speed Bins respectively
Added Lead-Free Package Information
*B 444306 NXR See ECN Converted from Preliminary to Final.
Changed ball E3 from DNU to NC
Removed redundant footnote on DNU.
Removed 35 ns speed bin
Removed “L” bin
Added 48 pin TSOP I package
Added Automotive product information.
Changed the ICC Typ value from 16 mA to 18 mA and ICC Max value from 28 mA
to 25 mA for test condition f = fax = 1/tRC.
Changed the ICC Max value from 2.3 mA to 3 mA for test condition f = 1MHz.
Changed the ISB1 and ISB2 Max value from 4.5 A to 8 A and Typ value from 0.9
A to 2 A respectively.
Modified ISB1 test condition to include BHE, BLE
Updated Thermal Resistance table.
Changed Test Load Capacitance from 50 pF to 30 pF.
Added Typ value for ICCDR .
Changed the ICCDR Max value from 4.5 A to 5 A
Corrected tR in Data Retention Characteristics from 100 s to tRC ns.
Changed tLZOE from 3 to 5
Changed tLZCE from 6 to 10
Changed tHZCE from 22 to 18
Changed tLZBE from 6 to 5
Changed tPWE from 30 to 35
Changed tSD from 22 to 25
Changed tLZWE from 6 to 10
Added footnote #15
Updated the ordering Information and replaced the Package Name column with
Package Diagram.
*C 467052 NXR See ECN Modified Data sheet to include x8 configurability.
Updated the Ordering Information table
*D 925501 VKN See ECN Removed Automotive-E information
Added Preliminary Automotive-A information
Added footnote #10 related to ISB2 and ICCDR
Added footnote #15 related AC timing parameters
*E 1045801 VKN See ECN Converted Automotive-A specs from preliminary to final
Updated footnote #9
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Document #: 38-05445 Rev. *H Revised December 20, 2010 Page 17 of 17
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.
CY62157EV30 MoBL®
© Cypress Semiconductor Corporation, 2004-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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PSoC 1 | PSoC 3 | PSoC 5
*F 2724889 NXR/AESA 06/26/09 Added Automotive-E information
Included -45ZXA/-55ZSXE/-55ZXE parts in the Ordering Information table
*G 2927528 VKN 05/04/2010 Renamed “DNU” pins as “NC” for 48 TSOP I package
Added footnote #24 related to chip enable
Updated Package Diagrams
Added Contents
Updated links in Sales, Solutions, and Legal Information
*H 3110053 12/14/2010 PRAS Changed Table Footnotes to Footnotes.
Added Ordering Code Definitions.
Document Title: CY62157EV30 MoBL®, 8 Mbit (512K x 16) Static RAM
Document Number: 38-05445
Rev. ECN No. Orig. of
Change
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