Parallel NOR Flash Embedded Memory
MT28EW256ABA
Features
• Single-level cell (SLC) process technology
• Density: 256Mb
• Supply voltage
– VCC = 2.7–3.6V (program, erase, read)
– VCCQ = 1.65 - VCC (I/O buffers)
• Asynchronous random/page read
– Page size: 16 words or 32 bytes
– Page access: 20ns
– Random access: 70ns (VCC = VCCQ = 2.7-3.6V)
– Random access: 75ns (VCCQ = 1.65-VCC)
• Buffer program (512-word program buffer)
– 2.0 MB/s (TYP) when using full buffer program
– 2.5 MB/s (TYP) when using accelerated buffer
program (VHH)
• Word/Byte program: 25us per word (TYP)
• Block erase (128KB): 0.2s (TYP)
• Memory organization
– Uniform blocks: 128KB or 64KW each
– x8/x16 data bus
• Program/erase suspend and resume capability
– Read from another block during a PROGRAM
SUSPEND operation
– Read or program another block during an ERASE
SUSPEND operation
• Unlock bypass, block erase, chip erase, and write to
buffer capability
• BLANK CHECK operation to verify an erased block
• CYCLIC REDUNDANCY CHECK (CRC) operation to
verify a program pattern
• VPP/WP# protection
– Protects first or last block regardless of block
protection settings
• Software protection
– Volatile protection
– Nonvolatile protection
– Password protection
• Extended memory block
– 128-word (256-byte) block for permanent, secure
identification
– Programmed or locked at the factory or by the
customer
• JESD47-compliant
– 100,000 (minimum) ERASE cycles per block
– Data retention: 20 years (TYP)
• Package
– 56-pin TSOP, 14 x 20mm (JS)
– 64-ball LBGA, 11 x 13mm (PC)
– 56-ball VFBGA, 7 x 9mm (PN)
• RoHS-compliant, halogen-free packaging
• Operating temperature
– Ambient: –40°C to +85°C
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Features
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© 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Part Numbering Information
For available options, such as packages or high/low protection, or for further information, contact your Micron
sales representative. Part numbers can be verified at www.micron.com. Feature and specification comparison by
device type is available at www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Number Chart
Production Status
Blank = Production
ES = Engineering sample
Operating Temperature
IT = –40°C to +85°C
Special Options
S = Standard
Security Features
0 = Standard default security
1 = OTP configurable
Package Codes
JS = 56-pin TSOP, 14mm x 20mm
PC = 64-ball LBGA, 11mm x 13mm
PN = 56-ball VFBGA, 7mm x 9mm
(All packages are lead-free, halogen-free,
RoHS-compliant)
Block Structure
H = High lock
L = Low lock
Micron Technology
Part Family
28E = Embedded Parallel NOR
Voltage
W = 2.7–3.6V VCC core
Density
128 = 128Mb
256 = 256Mb
512 = 512Mb
01G = 1Gb
02G = 2Gb
Stack
A = Single die
B = Two die
Device Generation
B = 2nd generation
Die Revision
A = Rev A
Configuration
1 = x8, x16
MT 28E W 512 A A B 1
H
JS IT0- S ES
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Features
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Contents
Important Notes and Warnings ......................................................................................................................... 7
General Description ......................................................................................................................................... 8
Signal Assignments ........................................................................................................................................... 9
Signal Descriptions ......................................................................................................................................... 12
Memory Organization .................................................................................................................................... 14
Memory Configuration ............................................................................................................................... 14
Memory Map ............................................................................................................................................. 14
Bus Operations ............................................................................................................................................... 15
Read .......................................................................................................................................................... 15
Write .......................................................................................................................................................... 15
Standby ..................................................................................................................................................... 16
Output Disable ........................................................................................................................................... 16
Reset .......................................................................................................................................................... 16
Registers ........................................................................................................................................................ 17
Data Polling Register .................................................................................................................................. 17
Lock Register .............................................................................................................................................. 22
Standard Command Definitions – Address-Data Cycles .................................................................................... 24
READ and AUTO SELECT Operations .............................................................................................................. 27
READ/RESET Command ............................................................................................................................ 27
READ CFI Command .................................................................................................................................. 27
AUTO SELECT Command ........................................................................................................................... 27
Read Electronic Signature ........................................................................................................................... 28
Cyclic Redundancy Check Operation ............................................................................................................... 29
CYCLIC REDUNDANCY CHECK Command ................................................................................................. 29
Cyclic Redundancy Check Operation Command Sequence .......................................................................... 29
Bypass Operations .......................................................................................................................................... 32
UNLOCK BYPASS Command ...................................................................................................................... 32
UNLOCK BYPASS RESET Command ............................................................................................................ 32
Program Operations ....................................................................................................................................... 33
PROGRAM Command ................................................................................................................................ 33
UNLOCK BYPASS PROGRAM Command ..................................................................................................... 33
WRITE TO BUFFER PROGRAM Command .................................................................................................. 33
UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command ....................................................................... 36
WRITE TO BUFFER PROGRAM CONFIRM Command .................................................................................. 36
BUFFERED PROGRAM ABORT AND RESET Command ................................................................................ 36
PROGRAM SUSPEND Command ................................................................................................................ 36
PROGRAM RESUME Command .................................................................................................................. 37
ACCELERATED BUFFERED PROGRAM Operations .......................................................................................... 37
Erase Operations ............................................................................................................................................ 38
CHIP ERASE Command .............................................................................................................................. 38
UNLOCK BYPASS CHIP ERASE Command ................................................................................................... 38
BLOCK ERASE Command ........................................................................................................................... 38
UNLOCK BYPASS BLOCK ERASE Command ................................................................................................ 39
ERASE SUSPEND Command ....................................................................................................................... 39
ERASE RESUME Command ........................................................................................................................ 40
ACCELERATED CHIP ERASE Operations ......................................................................................................... 40
BLANK CHECK Operation .............................................................................................................................. 41
BLANK CHECK Commands ........................................................................................................................ 41
Device Protection ........................................................................................................................................... 42
Hardware Protection .................................................................................................................................. 42
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Features
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Software Protection .................................................................................................................................... 42
Volatile Protection Mode ............................................................................................................................. 43
Nonvolatile Protection Mode ...................................................................................................................... 43
Password Protection Mode .......................................................................................................................... 43
Block Protection Command Definitions – Address-Data Cycles ........................................................................ 46
Protection Operations .................................................................................................................................... 49
LOCK REGISTER Commands ...................................................................................................................... 49
PASSWORD PROTECTION Commands ....................................................................................................... 49
NONVOLATILE PROTECTION Commands .................................................................................................. 49
NONVOLATILE PROTECTION BIT LOCK BIT Commands ............................................................................ 50
VOLATILE PROTECTION Commands .......................................................................................................... 51
EXTENDED MEMORY BLOCK Commands .................................................................................................. 51
EXIT PROTECTION Command .................................................................................................................... 52
Common Flash Interface ................................................................................................................................ 53
Power-Up and Reset Characteristics ................................................................................................................ 57
Absolute Ratings and Operating Conditions ..................................................................................................... 59
DC Characteristics .......................................................................................................................................... 61
Read AC Characteristics .................................................................................................................................. 63
Write AC Characteristics ................................................................................................................................. 67
Data Polling/Toggle AC Characteristics ............................................................................................................ 74
Program/Erase Characteristics ........................................................................................................................ 76
Package Dimensions ....................................................................................................................................... 78
Revision History ............................................................................................................................................. 81
Rev. G –05/18 ............................................................................................................................................. 81
Rev. F – 11/16 ............................................................................................................................................. 81
Rev. E – 4/16 ............................................................................................................................................... 81
Rev. D – 5/15 .............................................................................................................................................. 81
Rev. C – 4/15 ............................................................................................................................................... 81
Rev. B – 1/15 ............................................................................................................................................... 81
Rev. A – 6/14 ............................................................................................................................................... 81
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Features
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List of Figures
Figure 1: Part Number Chart ............................................................................................................................ 2
Figure 2: Logic Diagram ................................................................................................................................... 8
Figure 3: 56-Pin TSOP (Top View) .................................................................................................................... 9
Figure 4: 64-Ball LBGA (Top View – Balls Down) ............................................................................................. 10
Figure 5: 56-Ball VFBGA (Top View – Balls Down) ........................................................................................... 11
Figure 6: Data Polling Flowchart .................................................................................................................... 19
Figure 7: Toggle Bit Flowchart ........................................................................................................................ 20
Figure 8: Data Polling/Toggle Bit Flowchart .................................................................................................... 21
Figure 9: Lock Register Program Flowchart ..................................................................................................... 23
Figure 10: Boundary Condition of Program Buffer Size .................................................................................... 34
Figure 11: WRITE TO BUFFER PROGRAM Flowchart ...................................................................................... 35
Figure 12: Software Protection Scheme .......................................................................................................... 44
Figure 13: Set/Clear Nonvolatile Protection Bit Algorithm Flowchart ............................................................... 50
Figure 14: Power-Up Timing .......................................................................................................................... 57
Figure 15: Reset AC Timing – No PROGRAM/ERASE Operation in Progress ...................................................... 58
Figure 16: Reset AC Timing During PROGRAM/ERASE Operation .................................................................... 58
Figure 17: AC Measurement Load Circuit ....................................................................................................... 60
Figure 18: AC Measurement I/O Waveform ..................................................................................................... 60
Figure 19: Random Read AC Timing (8-Bit Mode) ........................................................................................... 64
Figure 20: Random Read AC Timing (16-Bit Mode) ......................................................................................... 65
Figure 21: BYTE# Transition Read AC Timing .................................................................................................. 65
Figure 22: Page Read AC Timing (16-Bit Mode) ............................................................................................... 66
Figure 23: WE#-Controlled Program AC Timing (8-Bit Mode) .......................................................................... 68
Figure 24: WE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 69
Figure 25: CE#-Controlled Program AC Timing (8-Bit Mode) ........................................................................... 71
Figure 26: CE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 72
Figure 27: Chip/Block Erase AC Timing (16-Bit Mode) .................................................................................... 73
Figure 28: Accelerated Program AC Timing ..................................................................................................... 73
Figure 29: Data Polling AC Timing .................................................................................................................. 74
Figure 30: Toggle/Alternative Toggle Bit Polling AC Timing .............................................................................. 75
Figure 31: 56-Pin TSOP – 14mm x 20mm (Package Code: JS) ............................................................................ 78
Figure 32: 64-Ball LBGA – 11mm x 13mm (Package Code: PC) ......................................................................... 79
Figure 33: 56-Ball VFBGA – 7mm x 9mm (Package Code: PN) .......................................................................... 80
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Features
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List of Tables
Table 1: Signal Descriptions ........................................................................................................................... 12
Table 2: Blocks[2047:0] .................................................................................................................................. 14
Table 3: Bus Operations ................................................................................................................................. 15
Table 4: Data Polling Register Bit Definitions .................................................................................................. 17
Table 5: Operations and Corresponding Bit Settings ........................................................................................ 18
Table 6: Lock Register Bit Definitions ............................................................................................................. 22
Table 7: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit ............................................. 24
Table 8: Block Protection ............................................................................................................................... 28
Table 9: Read Electronic Signature – 256Mb .................................................................................................... 28
Table 10: Command Sequence – Range of Blocks ............................................................................................ 29
Table 11: Command Sequence – Entire Chip .................................................................................................. 31
Table 12: ACCELERATED PROGRAM Requirements and Recommendations .................................................... 37
Table 13: ACCELERATED CHIP ERASE Requirements and Recommendations ................................................. 41
Table 14: VPP/WP# Functions ......................................................................................................................... 42
Table 15: Block Protection Status ................................................................................................................... 45
Table 16: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit ................................ 46
Table 17: Extended Memory Block Address and Data ...................................................................................... 51
Table 18: Query Structure Overview ............................................................................................................... 53
Table 19: CFI Query Identification String ........................................................................................................ 53
Table 20: CFI Query System Interface Information .......................................................................................... 54
Table 21: Device Geometry Definition ............................................................................................................ 54
Table 22: Primary Algorithm-Specific Extended Query Table ........................................................................... 55
Table 23: Power-Up Specifications ................................................................................................................. 57
Table 24: Reset AC Specifications ................................................................................................................... 58
Table 25: Absolute Maximum/Minimum Ratings ............................................................................................ 59
Table 26: Operating Conditions ...................................................................................................................... 59
Table 27: Input/Output Capacitance .............................................................................................................. 60
Table 28: DC Current Characteristics .............................................................................................................. 61
Table 29: DC Voltage Characteristics .............................................................................................................. 62
Table 30: Read AC Characteristics – VCC= VCCQ = 2.7-3.6V ................................................................................ 63
Table 31: Read AC Characteristics – VCCQ= 1.65V-VCC ...................................................................................... 63
Table 32: WE#-Controlled Write AC Characteristics ......................................................................................... 67
Table 33: CE#-Controlled Write AC Characteristics ......................................................................................... 70
Table 34: Data Polling/Toggle AC Characteristics ............................................................................................ 74
Table 35: Program/Erase Characteristics ........................................................................................................ 76
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Features
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Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-
nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Important Notes and Warnings
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General Description
The device is an asynchronous, uniform block, parallel NOR Flash memory device.
READ, ERASE, and PROGRAM operations are performed using a single low-voltage sup-
ply. Upon power-up, the device defaults to read array mode.
The main memory array is divided into uniform blocks that can be erased independent-
ly so that valid data can be preserved while old data is purged. PROGRAM and ERASE
commands are written to the command interface of the memory. An on-chip program/
erase controller simplifies the process of programming or erasing the memory by taking
care of all special operations required to update the memory contents. The end of a
PROGRAM or ERASE operation can be detected and any error condition can be identi-
fied. The command set required to control the device is consistent with JEDEC stand-
ards.
CE#, OE#, and WE# control the bus operation of the device and enable a simple con-
nection to most microprocessors, often without additional logic.
The device supports asynchronous random read and page read from all blocks of the
array. It also features an internal program buffer that improves throughput by program-
ming 512 words via one command sequence. A 128-word extended memory block over-
laps addresses with array block 0. Users can program this additional space and then
protect it to permanently secure the contents. The device also features different levels of
hardware and software protection to secure blocks from unwanted modification.
Figure 2: Logic Diagram
VCC VCCQ
A[MAX:0]
WE#
VPP/WP#
DQ[14:0]
DQ15/A-1
VSS
15
CE#
OE#
RST#
BYTE#
RY/BY#
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
General Description
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Signal Assignments
Figure 3: 56-Pin TSOP (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A23
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RST#
A21
VPP/WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
RFU
RFU
A24
A25
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
RFU
VCCQ
Notes: 1. A-1 is the least significant address bit in x8 mode.
2. A23 is valid for 256Mb and above; otherwise, it is RFU.
3. A24 is valid for 512Mb and above; otherwise, it is RFU.
4. A25 is valid for 1Gb and above; otherwise, it is RFU.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Signal Assignments
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Figure 4: 64-Ball LBGA (Top View – Balls Down)
A
B
C
D
E
F
G
H
1
NC
NC
NC
NC
NC
VCCQ
NC
NC
2
A3
A4
A2
A1
A0
CE#
OE#
VSS
3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
4
RY/BY#
A18
A20
DQ2
DQ10
DQ11
DQ3
5
WE#
VPP
/WP#
RST#
A21
A19
DQ5
DQ12
VCC
DQ4
6
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
7
A13
A12
A14
A15
A16
BYTE#
D15/A-1
VSS
8
NC
A22
A23
VCCQ
VSS
A24
A25
NC
Notes: 1. A-1 is the least significant address bit in x8 mode.
2. A23 is valid for 256Mb and above; otherwise, it is RFU.
3. A24 is valid for 512Mb and above; otherwise, it is RFU.
4. A25 is valid for 1Gb and above; otherwise, it is RFU.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Signal Assignments
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Figure 5: 56-Ball VFBGA (Top View – Balls Down)
A
B
C
D
E
F
G
H
87654321
A15
A21
A22
A16
A24
VSS
A11
A12
A13
A14
RFU
DQ15
DQ7
DQ14
A8
A19
A9
A10
DQ6
DQ13
DQ12
DQ5
WE#
A23
A20
DQ4
VCCQ
RFU
VPP/WP#
RST#
RY/BY#
DQ3
VCC
DQ11
RFU
RFU
A18
A17
DQ1
DQ9
DQ10
DQ2
A7
A6
A5
A4
VSS
OE#
DQ0
DQ8
A3
A2
A1
A0
CE#
DNU
Notes: 1. A-1 is the least significant address bit in x8 mode.
2. A23 is valid for 256Mb and above; otherwise, it is RFU.
3. A24 is valid for 512Mb and above; otherwise, it is RFU.
4. A25 is valid for 1Gb and above; otherwise, it is RFU.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Signal Assignments
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Signal Descriptions
The signal description table below is a comprehensive list of signals for this device fami-
ly. All signals listed may not be supported on this device. See Signal Assignments for in-
formation specific to this device.
Table 1: Signal Descriptions
Name Type Description
A[MAX:0] Input Address: Selects array cells to access during READ operations. Controls commands sent to
the program/erase controller command interface during WRITE operations.
CE# Input Chip enable: Activates the device, enabling READ and WRITE operations. When CE# is HIGH,
the device goes to standby and data outputs are High-Z.
OE# Input Output enable: Active LOW input. OE# LOW enables data output buffers during READ cy-
cles. When OE# is HIGH, data outputs are High-Z.
WE# Input Write enable: Controls WRITE operations to the device. Address is latched on the falling
edge of WE# and data is latched on the rising edge.
VPP/WP# Input VPP/Write Protect: Provides WRITE PROTECT and VHH functionality, which protects the low-
est or highest block and enables the device to enter unlock bypass mode.
BYTE# Input Byte/word organization select: Selects x8 or x16 bus mode. When BYTE# is LOW, the de-
vice is in x8 mode and when HIGH, the device is in x16 mode. Under byte configuration,
BYTE# should not be toggled during any WRITE operation.
Caution: This pin cannot be floated.
RST# Input Reset: When held LOW for at least tPLPH, applies a hardware reset to the device control log-
ic and places it in standby. After RST# goes HIGH, the device is ready for READ and WRITE
operations; that is, after tPHEL or tPHWL, whichever occurs last.
DQ[7:0] I/O Data I/O: During a READ operation, outputs data stored at the selected address. During a
WRITE operation, represents the commands sent to the command interface.
DQ[14:8] I/O Data I/O: During a READ operation when BYTE# is HIGH, outputs data stored at the selected
address. When BYTE# is LOW, these pins are High-Z and not used. During a WRITE operation,
these bits are not used. When reading the data polling register, these bits should be ignored.
DQ15/A-1 I/O Data I/O or address input: When device is in x16 bus mode, this pin behaves as data I/O,
together with DQ[14:8]. When device is in x8 bus mode, this pin behaves as the least signifi-
cant bit of the address.
Unless explicitly stated elsewhere, DQ15 = data I/O (x16 mode) and A-1 = address input (x8
mode).
RY/BY# Output Ready busy: Open-drain output used to identify when the device is performing a PROGRAM
or ERASE operation. During a PROGRAM or ERASE operation, RY/BY# is LOW. During read,
auto select, and erase suspend modes, RY/BY# is High-Z.
Enables RY/BY# pins from several devices to be connected to a single pull-up resistor which is
connected to VCCQ. Therefore, RYBY# LOW indicates when one or more of the devices are
busy. A 10K Ohm or bigger resistor is recommended as pull-up resistor to achieve 0.1V VOL.
VCC Supply Supply voltage: Provides power supply for READ, PROGRAM, and ERASE operations. When
VCC ≤ VLKO, the device is disabled, any PROGRAM or ERASE operation is aborted, and any al-
tered content will be invalid.
Capacitors of 0.1μF and 0.01µF should be connected between VCC and VSS to decouple the
current surges from the power supply. The PCB track widths must be sufficient to carry the
currents required during PROGRAM and ERASE operations.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Signal Descriptions
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Table 1: Signal Descriptions (Continued)
Name Type Description
VCCQ Supply I/O supply voltage: Provides power supply to the I/O pins and enables all outputs to be
powered independently from VCC.
Capacitors of 0.1μF and 0.01µF should be connected between VCCQ and VSS to decouple the
current surges from the power supply.
VSS Supply Ground: All VSS pins must be connected to system ground.
RFU — Reserved for future use: Reserved by Micron for future device functionality and enhance-
ment. Recommend that these be left floating. May be connected internally, but external con-
nections will not affect operation.
DNU — Do not use: Do not connect to any other signal or power supply; must be left floating.
NC — No connect: No internal connection; can be driven or floated.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Signal Descriptions
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Memory Organization
Memory Configuration
The main memory array is divided into 128KB or 64KW uniform blocks.
Memory Map
Table 2: Blocks[2047:0]
Block
Block
Size
Address Range (x8) Block
Size
Address Range (x16)
Start End Start End
2047 128KB FFE 0000h FFF FFFFh 64KW 7FF 0000h 7FF FFFFh
⋮ ⋮ ⋮ ⋮ ⋮
1023 7FE 0000h 7FF FFFFh 3FF 0000h 3FF FFFFh
⋮ ⋮ ⋮ ⋮ ⋮
511 3FE 0000h 3FF FFFFh 1FF 0000h 1FF FFFFh
⋮ ⋮ ⋮ ⋮ ⋮
255 1FE 0000h 1FF FFFFh 0FF 0000h 0FF FFFFh
⋮ ⋮ ⋮ ⋮ ⋮
127 0FE 0000h 0FF FFFFh 07F 0000h 07F FFFFh
⋮ ⋮ ⋮ ⋮ ⋮
63 07E 0000h 07F FFFFh 03F 0000h 03F FFFFh
⋮ ⋮ ⋮ ⋮ ⋮
0 000 0000h 001 FFFFh 000 0000h 000 FFFFh
Note: 1. 128Mb device = Blocks 0–127; 256Mb device = Blocks 0–255; 512Mb device = Blocks 0–
511; 1Gb device = Blocks 0–1023; 2Gb device = Blocks 0–2047.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Memory Organization
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Bus Operations
Table 3: Bus Operations
Notes 1 and 2 apply to entire table
Operation CE# OE# WE# RST# VPP/WP#
8-Bit Mode 16-Bit Mode
A[MAX:0],
DQ15/A-1 DQ[14:8] DQ[7:0] A[MAX:0]
DQ15/A-1,
DQ[14:0]
READ L L H H X Address High-Z Data output Address Data output
WRITE L H L H H3Command
address
High-Z Data input4Command
address
Data input4
STANDBY H X X H X X High-Z High-Z X High-Z
OUTPUT
DISABLE
L H H H X X High-Z High-Z X High-Z
RESET X X X L X X High-Z High-Z X High-Z
Notes: 1. Typical glitches of less than 3ns on CE#, OE#, and WE# are ignored by the device and do
not affect bus operations.
2. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
3. If WP# is LOW, then the highest or the lowest block remains protected, depending on
line item.
4. Data input is required when issuing a command sequence or when performing data
polling or block protection.
Read
Bus READ operations read from the memory cells, registers, extended memory block, or
CFI space. To accelerate the READ operation, the memory array can be read in page
mode where data is internally read and stored in a page buffer.
Page size is 16 words (32 bytes) and is addressed by address inputs A[3:0] in x16 bus
mode and A[3:0] plus DQ15/A-1 in x8 bus mode. The extended memory blocks and CFI
area support page read mode.
A valid bus READ operation involves setting the desired address on the address inputs,
taking CE# and OE# LOW, and holding WE# HIGH. The data I/Os will output the value.
If CE# goes HIGH and returns LOW for a subsequent access, a random read access is
performed and tACC or tCE is required. (See AC Characteristics for details about when
the output becomes valid).
Write
Bus WRITE operations write to the command interface. A valid bus WRITE operation
begins by setting the desired address on the address inputs. The address inputs are
latched by the command interface on the falling edge of CE# or WE#, whichever occurs
last. The data I/Os are latched by the command interface on the rising edge of CE# or
WE#, whichever occurs first. OE# must remain HIGH during the entire bus WRITE oper-
ation (See AC Characteristics for timing requirement details).
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Bus Operations
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Standby
Driving CE# HIGH in read mode causes the device to enter standby and data I/Os to be
High-Z (See DC Characteristics).
During PROGRAM or ERASE operations, the device will continue to use the program/
erase supply current (ICC3) until the operation completes. The device cannot be placed
into standby mode during a PROGRAM/ERASE operation.
Output Disable
Data I/Os are High-Z when OE# is HIGH.
Reset
During reset mode the device is deselected and the outputs are High-Z. The device is in
reset mode when RST# is LOW. The power consumption is reduced to the standby level,
independently from CE#, OE#, or WE# inputs.
When RST# is HIGH, a time of tPHEL is required before a READ operation can access
the device, and a delay of tPHWL is required before a write sequence can be initiated.
After this wake-up interval, normal operation is restored, the device defaults to read ar-
ray mode, and the data polling register is reset.
If RST# is driven LOW during a PROGRAM/ERASE operation or any other operation that
requires writing to the device, the operation will abort within tPLRH, and memory con-
tents at the aborted block or address are no longer valid.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Bus Operations
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Registers
Data Polling Register
Table 4: Data Polling Register Bit Definitions
Note 1 applies to entire table
Bit Name Settings Description Notes
DQ7 Data polling
bit
0 or 1, depending on
operations
Monitors whether the program/erase controller has successful-
ly completed its operation, or has responded to an ERASE SUS-
PEND operation.
2, 4
DQ6 Toggle bit Toggles: 0 to 1; 1 to 0;
and so on
Monitors whether the program, erase, or blank check control-
ler has successfully completed its operations, or has responded
to an ERASE SUSPEND operation. During a PROGRAM/ERASE/
BLANK CHECK operation, DQ6 toggles from 0 to 1, 1 to 0, and
so on, with each successive READ operation from any address.
3, 4, 5
DQ5 Error bit 0 = Success
1 = Failure
Identifies errors detected by the program/erase controller. DQ5
is set to 1 when a PROGRAM, BLOCK ERASE, or CHIP ERASE op-
eration fails to write the correct data to the memory, or when
a BLANK CHECK or CRC operation fails.
4, 6
DQ3 Erase timer
bit
0 = Erase not in progress
1 = Erase in progress
Identifies the start of program/erase controller operation dur-
ing a BLOCK ERASE command. Before the program/erase con-
troller starts, this bit set to 0, and additional blocks to be
erased can be written to the command interface.
4
DQ2 Alternative
toggle bit
Toggles: 0 to 1; 1 to 0;
and so on
During CHIP ERASE, BLOCK ERASE, and ERASE SUSPEND opera-
tions, DQ2 toggles from 0 to 1, 1 to 0, and so on, with each
successive READ operation from addresses within the blocks
being erased.
3, 4
DQ1 Buffered
program
abort bit
1 = Abort Indicates a BUFFER PROGRAM, EFI BLANK CHECK, or CRC oper-
ation abort. The BUFFERED PROGRAM ABORT and RESET com-
mand must be issued to return the device to read mode (see
WRITE TO BUFFER PROGRAM command).
–
Notes: 1. The data polling register can be read during PROGRAM, ERASE, or ERASE SUSPEND op-
erations; the READ operation outputs data on DQ[7:0].
2. For a PROGRAM operation in progress, DQ7 outputs the complement of the bit being
programmed. For a READ operation from the address previously programmed success-
fully, DQ7 outputs existing DQ7 data. For a READ operation from addresses with blocks
to be erased while an ERASE SUSPEND operation is in progress, DQ7 outputs 0; upon
successful completion of the ERASE SUSPEND operation, DQ7 outputs 1. For an ERASE
operation in progress, DQ7 outputs 0; upon ERASE operation's successful completion,
DQ7 outputs 1. During a BUFFER PROGRAM operation, the data polling bit is valid only
for the last word being programmed in the write buffer.
3. After successful completion of a PROGRAM, ERASE, or BLANK CHECK operation, the de-
vice returns to read mode.
4. During erase suspend mode, READ operations to addresses within blocks not being
erased output memory array data as if in read mode. A protected block is treated the
same as a block not being erased. See the Toggle Flowchart for more information.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Registers
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5. During erase suspend mode, DQ6 toggles when addressing a cell within a block being
erased. The toggling stops when the program/erase controller has suspended the ERASE
operation. See the Toggle Flowchart for more information.
6. When DQ5 is set to 1, a READ/RESET (F0h) command must be issued before any subse-
quent command.
Table 5: Operations and Corresponding Bit Settings
Note 1 applies to entire table
Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/BY# Notes
PROGRAM Any address DQ7# Toggle 0 – – 0 0 2
EFI BLANK CHECK Any address 1 Toggle 0 – – 0 0 3
CRC range of
blocks
Any address 1 Toggle 0 – – 0 0
CRC chip Any address DQ7# Toggle 0 – – 0 0 4
CHIP ERASE Any address 0 Toggle 0 1 Toggle – 0 –
BLOCK ERASE
before time-out
Erasing block 0 Toggle 0 0 Toggle – 0 –
Non-erasing block 0 Toggle 0 0 No toggle – 0 –
BLOCK ERASE Erasing block 0 Toggle 0 1 Toggle – 0 –
Non-erasing block 0 Toggle 0 1 No toggle – 0 –
PROGRAM
SUSPEND
Programming
block
Invalid operation High-Z –
Nonprogramming
block
Outputs memory array data as if in read mode High-Z –
ERASE
SUSPEND
Erasing block 1 No Toggle 0 – Toggle – High-Z –
Non-erasing block Outputs memory array data as if in read mode High-Z –
PROGRAM during
ERASE SUSPEND
Erasing block DQ7# Toggle 0 – Toggle – 0 2
Non-erasing block DQ7# Toggle 0 – No Toggle – 0 2
BUFFERED
PROGRAM ABORT
Any address DQ7# Toggle 0 – – 1 High-Z –
PROGRAM Error Any address DQ7# Toggle 1 – – – High-Z 2
ERASE Error Any address 0 Toggle 1 1 Toggle – High-Z –
EFI BLANK CHECK
Error
Any address 0 Toggle 1 1 Toggle – High-Z –
CRC range of
blocks error
Any address 1 Toggle 1 – – – High-Z –
CRC chip error Any address DQ7# Toggle 1 – – – High-Z 4
Notes: 1. Unspecified data bits should be ignored.
2. DQ7# for buffer program is related to the last address location loaded.
3. EFI = enhanced Flash interface.
4. DQ7# is the reverse DQ7 of the last word or byte loaded before CRC chip confirm com-
mand cycle.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Registers
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Figure 6: Data Polling Flowchart
Start
DQ7 = Data
DQ5 = 1
DQ1 = 1
DQ7 = Data
No
No
No
No
Yes
Yes
Yes
Yes
Read DQ7, DQ5, and DQ1
at valid address1
Read DQ7 at valid address
SuccessFailure 4
32
Notes: 1. Valid address is the last address being programmed or an address within the block being
erased.
2. Failure results: DQ5 = 1 indicates an operation error. A READ/RESET (F0h) command must
be issued before any subsequent command.
3. Failure results: DQ1 = 1 indicates a WRITE TO BUFFER PROGRAM ABORT operation. A
full three-cycle RESET (AAh/55h/F0h) command sequence must be used to reset the abor-
ted device.
4. The data polling process does not support the BLANK CHECK operation. The process
represented in the Toggle Bit Flowchart figure can provide information on the BLANK
CHECK operation.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Registers
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Figure 7: Toggle Bit Flowchart
DQ6 = Toggle
DQ5 = 1
DQ6 = Toggle
No
No
Yes
Yes
Yes
Start
Read DQ6 at valid address
Read DQ6, DQ5, and DQ1
at valid address
Read DQ6 (twice) at valid address
SuccessFailure1
DQ1 = 1
No
Yes
No
Notes: 1. Failure results: DQ5 = 1 indicates an operation error; DQ1 = 1 indicates a WRITE TO BUF-
FER PROGRAM ABORT operation.
2. The toggle bit process supports the BLANK CHECK operation.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Registers
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Figure 8: Data Polling/Toggle Bit Flowchart
WRITE TO BUFFER
PROGRAM
Start
DQ7 = Valid data
DQ5 = 1
Yes
No
No
Yes
Yes
DQ6 = Toggling Yes
No No
No
Yes
PROGRAM operation
No
No
DQ6 = Toggling
No
DQ2 = Toggling
Yes
Yes
Yes
DQ1 = 1
Read 3 correct data?
No
Yes
Read 1
Read 2
Read 2
Read 3
Device busy: Repolling
Device busy: Repolling
Read 3
PROGRAM operation
complete
PROGRAM operation
failure
WRITE TO BUFFER
PROGRAM
abort
Timeout failure
ERASE operation
complete
Erase/suspend mode
Device error
Read2.DQ6 = Read3.DQ6
Read2.DQ2 = Read3.DQ2
Read1.DQ6 = Read2.DQ6
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Registers
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Lock Register
Table 6: Lock Register Bit Definitions
Note 1 applies to entire table
Bit Name Settings Description Notes
DQ2 Password
protection
mode lock bit
0 = Password protection
mode enabled
1 = Password protection
mode disabled (Default)
Places the device permanently in password protection mode. 2
DQ1 Nonvolatile
protection
mode lock bit
0 = Nonvolatile protection
mode enabled with pass-
word protection mode
permanently disabled
1 = Nonvolatile protection
mode enabled (Default)
Places the device in nonvolatile protection mode with pass-
word protection mode permanently disabled. When shipped
from the factory, the device will operate in nonvolatile protec-
tion mode, and the memory blocks are unprotected.
2
DQ0 Extended
memory
block
protection bit
0 = Protected
1 = Unprotected (Default)
If the device is shipped with the extended memory block un-
locked, the block can be protected by setting this bit to 0. The
extended memory block protection status can be read in auto
select mode by issuing an AUTO SELECT command.
–
Notes: 1. The lock register is a 16-bit, one-time programmable register. DQ[15:3] are reserved and
are set to a default value of 1.
2. The password protection mode lock bit and nonvolatile protection mode lock bit cannot
both be programmed to 0. Any attempt to program one while the other is programmed
causes the operation to abort, and the device returns to read mode. The device is ship-
ped from the factory with the default setting.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Registers
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Figure 9: Lock Register Program Flowchart
Start
Success: EXIT PROTECTION
command set
Address/data cycle 1
Address/data cycle 2
Done?
Match expected
value, 0?
No
No
Yes
Yes
Enter LOCK REGISTER command set
Address/data (unlock) cycle 1
Address/data (unlock) cycle 2
Address/data cycle 3
PROGRAM LOCK REGISTER
Address/data cycle 1
Address/data cycle 2
Polling algorithm
Read lock register
Notes: 1. Each lock register bit can be programmed only once.
2. See the Block Protection Command Definitions table for address-data cycle details.
3. DQ5 and DQ1 are ignored in this algorithm flow.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Registers
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Standard Command Definitions – Address-Data Cycles
Table 7: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit
Note 1 applies to entire table
Command and
Code/Subcode
Bus
Size
Address and Data Cycles
Notes
1st 2nd 3rd 4th 5th 6th
A D A D A D A D A D A D
READ and AUTO SELECT Operations
READ/RESET (F0h) x8 X F0 2
AAA AA 555 55 X F0
x16 X F0
555 AA 2AA 55 X F0
READ CFI (98h) x8 AAA 98
x16 555
EXIT READ CFI (F0h) x8 X F0
x16
AUTO SELECT (90h) x8 AAA AA 555 55 AAA 90 Note
3
Note
3
4, 5
x16 555 2AA 555
EXIT AUTO SELECT (F0h) x8 X F0
x16
BYPASS Operations
UNLOCK BYPASS (20h) x8 AAA AA 555 55 AAA 20
x16 555 2AA 555
UNLOCK BYPASS
RESET (90h/00h)
x8 X 90 X 00
x16
PROGRAM Operations
PROGRAM (A0h) x8 AAA AA 555 55 AAA A0 PA PD
x16 555 2AA 555
UNLOCK BYPASS
PROGRAM (A0h)
x8 X A0 PA PD 6
x16
WRITE TO BUFFER
PROGRAM (25h)
x8 AAA AA 555 55 BAd 25 BAd N PA PD 7, 8, 9
x16 555 2AA
UNLOCK BYPASS
WRITE TO BUFFER
PROGRAM (25h)
x8 BAd 25 BAd N PA PD 6
x16
WRITE TO BUFFER
PROGRAM CONFIRM
(29h)
x8 BAd 29 7
x16
BUFFERED PROGRAM
ABORT and RESET (F0h)
x8 AAA AA 555 55 AAA F0
x16 555 2AA 555
PROGRAM SUSPEND
(B0h)
x8 X B0
x16
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Standard Command Definitions – Address-Data Cycles
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Table 7: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit (Continued)
Note 1 applies to entire table
Command and
Code/Subcode
Bus
Size
Address and Data Cycles
Notes
1st 2nd 3rd 4th 5th 6th
A D A D A D A D A D A D
PROGRAM RESUME
(30h)
x8 X 30
x16
ERASE Operations
CHIP ERASE (80/10h) x8 AAA AA 555 55 AAA 80 AAA AA 555 55 AAA 10
x16 555 2AA 555 555 2AA 555
UNLOCK BYPASS
CHIP ERASE (80/10h)
x8 X 80 X 10 6
x16
BLOCK ERASE (80/30h) x8 AAA AA 555 55 AAA 80 AAA AA 555 55 BAd 30 10
x16 555 2AA 555 555 2AA
UNLOCK BYPASS
BLOCK ERASE (80/30h)
x8 X 80 BAd 30 6
x16
ERASE SUSPEND (B0h) x8 X B0
x16
ERASE RESUME (30h) x8 X 30
x16
Enhanced Flash Interface (EFI) BLANK CHECK Operations
EFI BLANK CHECK
SETUP (EB/76h)
x8 AAA AA 555 55 BAd +
00
EB BAd +
00
76 BAd +
00
00 BAd +
00
00
x16 555 2AA
EFI BLANK CHECK
CONFIRM and READ
(29h)
x8 BAd +
00
29
x16
Notes: 1. A = Address; D = Data; X = "Don't Care"; BAd = Any address in the block; N = Number of
bytes (x8) or words (x16) to be programmed; PA = Program address; PD = Program data;
Gray shading = Not applicable. All values in the table are hexadecimal. Some commands
require both a command code and subcode.
2. A full three-cycle RESET command sequence must be used to reset the device in the
event of a buffered program abort error (DQ1 = 1).
3. These cells represent READ cycles (versus WRITE cycles for the others).
4. AUTO SELECT enables the device to read the manufacturer code, device code, block pro-
tection status, and extended memory block protection indicator.
5. AUTO SELECT addresses and data are specified in the Electronic Signature table and the
Extended Memory Block Protection table.
6. For any UNLOCK BYPASS ERASE/PROGRAM command, the first two UNLOCK cycles are
unnecessary.
7. BAd must be the same as the address loaded during the WRITE TO BUFFER PROGRAM
3rd and 4th cycles.
8. WRITE TO BUFFER PROGRAM operation: maximum cycles = 261 (x8) and 517 (x16). UN-
LOCK BYPASS WRITE TO BUFFER PROGRAM operation: maximum cycles = 259 (x8), 515
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Standard Command Definitions – Address-Data Cycles
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(x16). WRITE TO BUFFER PROGRAM operation: N + 1 = bytes (x8) or words (x16) to be
programmed; maximum buffer size = 256 bytes (x8) and 512 words (x16).
9. For x8, A[MAX:7] address pins should remain unchanged while A[6:0] and A-1 pins are
used to select a byte within the N + 1 byte page. For x16, A[MAX:9] address pins should
remain unchanged while A[8:0] pins are used to select a word within the N+1 word
page.
10. BLOCK ERASE address cycles can extend beyond six address-data cycles, depending on
the number of blocks to erase.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Standard Command Definitions – Address-Data Cycles
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READ and AUTO SELECT Operations
READ/RESET Command
The READ/RESET (F0h) command returns the device to read mode and resets the errors
in the data polling register. One or three bus WRITE operations can be used to issue the
READ/RESET command. Note: A full three-cycle RESET command sequence must be
used to reset the device in the event of a buffered program abort error (DQ1 = 1).
Once a PROGRAM, ERASE, or SUSPEND operation begins, RESET commands are ignor-
ed until the operation is complete. Read/reset serves primarily to return the device to
read mode from a failed PROGRAM or ERASE operation. Read/reset may cause a return
to read mode from undefined states that might result from invalid command sequen-
ces. A hardware reset may be required to return to normal operation from some unde-
fined states.
To exit the unlock bypass mode, the system must issue a two-cycle UNLOCK BYPASS
RESET command sequence. A READ/RESET command will not exit unlock bypass
mode.
READ CFI Command
The READ CFI (98h) command puts the device in read CFI mode and is only valid when
the device is in read array or auto select mode. One bus WRITE cycle is required to issue
the command.
Once in read CFI mode, bus READ operations will output data from the CFI memory
area (Refer to the Common Flash Interface for details).
Read CFI mode is exited by performing a reset. The device returns to read mode unless
it entered read CFI mode after an ERASE SUSPEND or PROGRAM SUSPEND command,
in which case it returns to erase or program suspend mode.
AUTO SELECT Command
At power-up or after a hardware reset, the device is in read mode. It can then be put in
auto select mode by issuing an AUTO SELECT (90h) command. Auto select mode ena-
bles the following device information to be read:
• Electronic signature, which includes manufacturer and device code information as
shown in the Electronic Signature table.
• Block protection, which includes the block protection status and extended memory
block protection indicator, as shown in the Block Protection table.
Electronic signature or block protection information is read by executing a READ opera-
tion with control signals and addresses set, as shown in the Read Electronic Signature
table or the Block Protection table, respectively. In addition, this device information can
be read or set by issuing an AUTO SELECT command.
Auto select mode can be used by the programming equipment to automatically match a
device with the application code to be programmed.
Three consecutive bus WRITE operations are required to issue an AUTO SELECT com-
mand. The device remains in auto select mode until a READ/RESET or READ CFI com-
mand is issued.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
READ and AUTO SELECT Operations
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The device cannot enter auto select mode when a PROGRAM or ERASE operation is in
progress (RY/BY# LOW). However, auto select mode can be entered if the PROGRAM or
ERASE operation has been suspended by issuing a PROGRAM SUSPEND or ERASE SUS-
PEND command.
Auto select mode is exited by performing a reset. The device returns to read mode un-
less it entered auto select mode after an ERASE SUSPEND or PROGRAM SUSPEND
command, in which case it returns to erase or program suspend mode.
Table 8: Block Protection
Note 1 applies to entire table
Read Cycle CE# OE# WE#
Address Input Data Input/Output
8-Bit/16-Bit 8-Bit Only 8-Bit Only 16-Bit Only
A[MAX:16] A[15:2] A1 A0 DQ15/A-1 DQ[14:8] DQ[7:0]
DQ15/A-1,
DQ[14:0]
128-bit (0x0~0x7) Factory-Programmable Extended memory protection Indicator (bit DQ7)
Low lock L L H L L H H X X 09h20009h2
89h30089h3
High lock L L H L L H H X X 19h20019h2
99h30099h3
Block protection status
Protected L L H Block base
address
L H L X X 01h 0001h
Unprotected L L H L H L X X 00h 0000h
Notes: 1. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
2. Customer-lockable (default).
3. Micron prelocked.
Read Electronic Signature
Table 9: Read Electronic Signature – 256Mb
Note 1 applies to entire table
READ Cycle CE# OE# WE#
Address Input Data Input/Output
8-Bit/16-Bit 8-Bit Only 8-Bit Only 16-Bit Only
A[MAX:4] A3 A2 A1 A0 DQ15/A-1 DQ[14:8] DQ[7:0]
DQ15/A-1,
DQ[14:0]
Manufacturer code L L H L L L L L X X 89h 0089h
Device code 1 L L H L L L L H X X 7Eh 227Eh
Device code 2 L L H L H H H L X X 22h 2222h
Device code 3 L L H L H H H H X X 01h 2201h
Note: 1. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
READ and AUTO SELECT Operations
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Cyclic Redundancy Check Operation
CYCLIC REDUNDANCY CHECK Command
The CYCLIC REDUNDANCY CHECK (CRC) command is a nonsecure hash function de-
signed to detect accidental changes to raw data. Typically, it is used in digital networks
and storage devices such as hard disk drives. A CRC-enabled device calculates a short,
fixed-length binary sequence known as the CRC code (or CRC). The device CRC opera-
tion will generate the CRC result of the whole device or of an address range specified by
the operation. Then the CRC result is compared with the expected CRC data provided in
the sequence. Finally, the device indicates a pass or fail through the data polling regis-
ter. If the CRC fails, corrective action is possible, such as re-verifying with a normal
READ mode or rewriting the array data.
CRC is a higher performance alternative to reading data directly to verify recently pro-
grammed data, or as a way to periodically check the data integrity of a large block of
data against a stored CRC reference over the life of the product.
CRC helps improve test efficiency for programmer or burn-in stress tests. No system
hardware changes are required to enable CRC.
The CRC-64 operation follows the ECMA standard; the generating polynomial is:
G(x) = x64 + x62 + x57 + x55 + x54 + x53 + x52 + x47 + x46 + x45 + x40 + x39 + x38 + x37 + x35 + x33
+ x32+ x31 + x29 + x27 + x24 + x23 + x22 + x21 + x19 + x17 + x13 + x12 + x10 + x9 + x7 + x4 + x + 1
Note: The data stream sequence is from LSB to MSB and the default initial CRC value is
all zeros.
The CRC command sequences are shown in the tables below, for an entire die or for a
selected range, respectively.
Cyclic Redundancy Check Operation Command Sequence
Table 10: Command Sequence – Range of Blocks
Note 1 and 2 apply to entire table.
Word Mode Byte Mode
Description NotesA[MAX:0] DQ[15:0]
A[MAX:0],
DQ15/A-1 DQ[7:0]
0000555 00AAh 0000AAA AAh UI unlock cycle 1
00002AA 0055h 0000555 55h UI unlock cycle 2
0000000 00EBh 0000000 EBh Extended function interface command
0000000 0027h 0000000 27h CRC sub-op code
0000000 000Ah 0000000 15h N-1 data count
0000000 FFFEh 0000000 FEh CRC operation option data
0000001 FFh
0000001 Data 0000002 Low byte of
the data
1st word of 64-bit expected CRC
0000003 High byte of
the data
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Cyclic Redundancy Check Operation
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Table 10: Command Sequence – Range of Blocks (Continued)
Note 1 and 2 apply to entire table.
Word Mode Byte Mode
Description NotesA[MAX:0] DQ[15:0]
A[MAX:0],
DQ15/A-1 DQ[7:0]
0000002 Data 0000004 Low byte of
the data
2nd word of 64-bit expected CRC
0000005 High byte of
the data
0000003 Data 0000006 Low byte of
the data
3rd word of 64-bit expected CRC
0000007 High byte of
the data
0000004 Data 0000008 Low byte of
the data
4th word of 64-bit expected CRC
0000009 High byte of
the data
0000005 A14-A-1 000000A A6-A-1 Byte address to start 3
0000011 A14-A7
0000006 A30-A15 000000C A22-A15 Byte address to start 3
000000D A30-A23
0000007 Reserved 000000E Reserved Default as 0000h
000000F Reserved
0000008 A14-A-1 0000010 A6-A-1 Byte address to stop 3
0000011 A14-A7
0000009 A30-A15 0000012 A22-A15 Byte address to stop 3
0000013 A30-A23
000000A Reserved 0000014 Reserved Default as 0000h
0000015 Reserved
0000000 0029h 0000000 29h Confirm command
0000000 Read 0000000 Read Continue data polling to wait for device to be
ready
Notes: 1. If the CRC check fails, a check error is generated by setting DQ5 = 1.
2. This is a byte-aligned operation, whether BYTE# is HIGH or LOW.
3. The stop address must be bigger than the start address; otherwise, the algorithm will
take no action.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Cyclic Redundancy Check Operation
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Table 11: Command Sequence – Entire Chip
Word Mode Byte Mode
DescriptionA[MAX:0] DQ[15:0]
A[MAX:0],
DQ15/A-1 DQ[7:0]
0000555 00AAh 0000AAA AAh UI unlock cycle 1
00002AA 0055h 0000555 55h UI unlock cycle 2
0000000 00EBh 0000000 EBh Extended function interface command
0000000 0027h 0000000 27h CRC sub-op code
0000000 0004h 0000000 09h N-1 data count
0000000 FFFFh 0000000 FFh CRC operation option data
0000001 FFh
0000001 Data 0000002 Low byte of
the data
1st word of 64-bit expected CRC
0000003 High byte of
the data
0000002 Data 0000004 Low byte of
the data
2nd word of 64-bit expected CRC
0000005 High byte of
the data
0000003 Data 0000006 Low byte of
the data
3rd word of 64-bit expected CRC
0000007 High byte of
the data
0000004 Data 0000008 Low byte of
the data
4th word of 64-bit expected CRC
0000009 High byte of
the data
0000000 0029h 0000000 0029h Confirm command
0000000 Read 0000000 Read Continue data polling to wait for device to be ready
Note: 1. Applies to entire table: If the CRC check fails, a check error is generated by setting DQ5
= 1.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Cyclic Redundancy Check Operation
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Bypass Operations
UNLOCK BYPASS Command
The UNLOCK BYPASS (20h) command is used to place the device in unlock bypass
mode. Three bus WRITE operations are required to issue the UNLOCK BYPASS com-
mand.
When the device enters unlock bypass mode, the two initial UNLOCK cycles required
for a standard PROGRAM or ERASE operation are not needed, thus enabling faster total
program or erase time.
The UNLOCK BYPASS command is used in conjunction with UNLOCK BYPASS PRO-
GRAM or UNLOCK BYPASS ERASE commands to program or erase the device faster
than with standard PROGRAM or ERASE commands. Using these commands can save
considerable time when the cycle time to the device is long. When in unlock bypass
mode, only the following commands are valid:
• The UNLOCK BYPASS PROGRAM command can be issued to program addresses
within the device.
• The UNLOCK BYPASS BLOCK ERASE command can then be issued to erase one or
more memory blocks.
• The UNLOCK BYPASS CHIP ERASE command can be issued to erase the whole mem-
ory array.
• The UNLOCK BYPASS WRITE TO BUFFER PROGRAM and UNLOCK BYPASS EN-
HANCED WRITE TO BUFFER PROGRAM commands can be issued to speed up the
programming operation.
• The UNLOCK BYPASS RESET command can be issued to return the device to read
mode.
In unlock bypass mode, the device can be read as if in read mode.
In addition to the UNLOCK BYPASS command, when VPP/WP# is raised to VHH, the de-
vice automatically enters unlock bypass mode. When VPP/WP# returns to VIH or VIL, the
device is no longer in unlock bypass mode, and normal operation resumes. The transi-
tions from VIH to VHH and from VHH to VIH must be slower than tVHVPP. (See the Accel-
erated Program, Data Polling/Toggle AC Characteristics.)
Note: Micron recommends entering and exiting unlock bypass mode using the ENTER
UNLOCK BYPASS and UNLOCK BYPASS RESET commands rather than raising VPP/WP#
to VHH. VPP/WP# should never be raised to VPPH from any mode except read mode; oth-
erwise, the device may be left in an indeterminate state. VPP/WP# should not remain at
VHH for than 80 hours cumulative.
UNLOCK BYPASS RESET Command
The UNLOCK BYPASS RESET (90/00h) command is used to return to read/reset mode
from unlock bypass mode. Two bus WRITE operations are required to issue the UN-
LOCK BYPASS RESET command. The READ/RESET command does not exit from un-
lock bypass mode.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Bypass Operations
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Program Operations
PROGRAM Command
The PROGRAM (A0h) command can be used to program a value to one address in the
memory array. The command requires four bus WRITE operations, and the final WRITE
operation latches the address and data in the internal state machine and starts the pro-
gram/erase controller. After programming has started, bus READ operations output the
data polling register content.
Programming can be suspended and then resumed by issuing a PROGRAM SUSPEND
command and a PROGRAM RESUME command, respectively.
If the address falls in a protected block, the PROGRAM command is ignored, and the
data remains unchanged. The data polling register is not read, and no error condition is
given.
After the PROGRAM operation has completed, the device returns to read mode, unless
an error has occurred. When an error occurs, bus READ operations to the device contin-
ue to output the data polling register. A READ/RESET command must be issued to reset
the error condition and return the device to read mode.
The PROGRAM command cannot change a bit set to 0 back to 1, and an attempt to do
so is masked during a PROGRAM operation. Instead, an ERASE command must be used
to set all bits in one memory block or in the entire memory from 0 to 1.
The PROGRAM operation is aborted by performing a hardware reset or by powering
down the device. In this case, data integrity cannot be ensured, and it is recommended
that the words or bytes that were aborted be reprogrammed.
UNLOCK BYPASS PROGRAM Command
When the device is in unlock bypass mode, the UNLOCK BYPASS PROGRAM (A0h)
command can be used to program one address in the memory array. The command re-
quires two bus WRITE operations instead of four required by a standard PROGRAM
command; the final WRITE operation latches the address and data and starts the pro-
gram/erase controller (The standard PROGRAM command requires four bus WRITE op-
erations). The PROGRAM operation using the UNLOCK BYPASS PROGRAM command
behaves identically to the PROGRAM operation using the PROGRAM command. The
operation cannot be aborted. A bus READ operation to the memory outputs the data
polling register.
WRITE TO BUFFER PROGRAM Command
The WRITE TO BUFFER PROGRAM (25h) command makes use of the program buffer to
speed up programming and dramatically reduces system programming time compared
to the standard non-buffered PROGRAM command. This product supports a 512-word
(x16) or 256-byte (x8) maximum program buffer.
When issuing a WRITE TO BUFFER PROGRAM command, V PP/WP# can be held HIGH
or raised to VHH. Also, it can be held LOW if the block is not the lowest or highest block,
depending on the part number.
The following successive steps are required to issue the WRITE TO BUFFER PROGRAM
command:
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Program Operations
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First, two UNLOCK cycles are issued. Next, a third bus WRITE cycle sets up the WRITE
TO BUFFER PROGRAM command. The set-up code can be addressed to any location
within the targeted block. Then, a fourth bus WRITE cycle sets up the number of words/
bytes to be programmed. Value n is written to the same block address, where n + 1 is the
number of words/bytes to be programmed. Value n + 1 must not exceed the size of the
program buffer, or the operation will abort. A fifth cycle loads the first address and data
to be programmed. Last, n bus WRITE cycles load the address and data for each word/
byte into the program buffer. Addresses must lie within the range from the start address
+1 to the start address + (n - 1).
Optimum programming performance and lower power usage are achieved by aligning
the starting address at the beginning of a 512-word boundary (A[8:0] = 0x000h). Any
buffer size smaller than 512 words is allowed within a 512-word boundary, while all ad-
dresses used in the operation must lie within the 512-word boundary. In addition, any
crossing boundary buffer program will result in a program abort. For a x8 application,
maximum buffer size is 256 bytes; for a x16 application, the maximum buffer size is
1024 bytes.
To program the content of the program buffer, this command must be followed by a
WRITE TO BUFFER PROGRAM CONFIRM command.
If an address is written several times during a WRITE TO BUFFER PROGRAM operation,
the address/data counter will be decremented at each data load operation, and the data
will be programmed to the last word loaded into the buffer.
Invalid address combinations or the incorrect sequence of bus WRITE cycles will abort
the WRITE TO BUFFER PROGRAM command.
The data polling register bits DQ1, DQ5, DQ6, DQ7 can be used to monitor the device
status during a WRITE TO BUFFER PROGRAM operation.
The WRITE TO BUFFER PROGRAM command should not be used to change a bit set to
0 back to 1, and an attempt to do so is masked during the operation. Rather than the
WRITE TO BUFFER PROGRAM command, the ERASE command should be used to set
memory bits from 0 to 1.
Figure 10: Boundary Condition of Program Buffer Size
0400h
0000h
512 Words
512 Words
0200h
511 words or less are allowed
in the program buffer
512-word program
buffer is allowed
Any buffer program attempt
is not allowed
512-word program
buffer is allowed
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Program Operations
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Figure 11: WRITE TO BUFFER PROGRAM Flowchart
Abort
WRITE TO BUFFER
Write buffer data,
start address
Start
X = n
Write n,1
block address
Write to a different
block address
X = 0
Write next data,2
program address pair
WRITE TO BUFFER
confirm, block address
X = X - 1
Yes
No
Yes
No
Polling
status = done?
No
Yes
Yes
Error?
No
Yes
WRITE TO BUFFER
command,
block address
Perform polling
algorithm
Buffer program
abort?
No
Failure: Issue RESET
command to return to
read array mode
Success: Return to
read array mode
Failure: Issue BUFFERED
PROGRAM ABORT AND
RESET command
First three cycles of the
WRITE TO BUFFER
PROGRAM command
Notes: 1. n + 1 is the number of addresses to be programmed.
2. The BUFFERED PROGRAM ABORT AND RESET command (3 cycles reset) must be issued to
return the device to read mode.
3. When the block address is specified, any address in the selected block address space is
acceptable. However, when loading program buffer address with data, all addresses
must fall within the selected program buffer page.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Program Operations
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UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command
When the device is in unlock bypass mode, the UNLOCK BYPASS WRITE TO BUFFER
(25h) command can be used to program the device in fast program mode. The com-
mand requires two bus WRITE operations fewer than the standard WRITE TO BUFFER
PROGRAM command.
The UNLOCK BYPASS WRITE TO BUFFER PROGRAM command behaves the same way
as the WRITE TO BUFFER PROGRAM command: the operation cannot be aborted, and
a bus READ operation to the memory outputs the data polling register.
The WRITE TO BUFFER PROGRAM CONFIRM command is used to confirm an UN-
LOCK BYPASS WRITE TO BUFFER PROGRAM command and to program the n + 1
words/bytes loaded in the program buffer by this command.
WRITE TO BUFFER PROGRAM CONFIRM Command
The WRITE TO BUFFER PROGRAM CONFIRM (29h) command is used to confirm a
WRITE TO BUFFER PROGRAM command and to program the n + 1 words/bytes loaded
in the program buffer by this command.
BUFFERED PROGRAM ABORT AND RESET Command
A BUFFERED PROGRAM ABORT AND RESET (F0h) command must be issued to reset
the device to read mode when the BUFFER PROGRAM operation is aborted. The buffer
programming sequence can be aborted in the following ways:
• Load a value that is greater than the page buffer size during the number of locations
to program in the WRITE TO BUFFER PROGRAM command.
• Write to an address in a different block than the one specified during the WRITE BUF-
FER LOAD command.
• Write an address/data pair to a different write buffer page than the one selected by
the starting address during the program buffer data loading stage of the operation.
• Write data other than the CONFIRM command after the specified number of data
load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DQ7# (for the last address location
loaded), DQ6 = toggle, and DQ5 = 0 (all of which are data polling register bits). A BUF-
FERED PROGRAM ABORT and RESET command sequence must be written to reset the
device for the next operation.
Note: The full three-cycle BUFFERED PROGRAM ABORT and RESET command se-
quence is required when using buffer programming features in unlock bypass mode.
PROGRAM SUSPEND Command
The PROGRAM SUSPEND (B0h) command can be used to interrupt a program opera-
tion so that data can be read from another block. When the PROGRAM SUSPEND com-
mand is issued during a program operation, the device suspends the operation within
the program suspend latency time and updates the data polling register bits.
After the program operation has been suspended, data can be read from any address.
However, data is invalid when read from an address where a program operation has
been suspended.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Program Operations
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The PROGRAM SUSPEND command may also be issued during a PROGRAM operation
while an erase is suspended. In this case, data may be read from any address not in
erase suspend or program suspend mode. To read from the extended memory block
area (one-time programmable area), the ENTER/EXIT EXTENDED MEMORY BLOCK
command sequences must be issued.
The system may also issue the AUTO SELECT command sequence when the device is in
program suspend mode. The system can read as many auto select codes as required.
When the device exits auto select mode, the device reverts to program suspend mode
and is ready for another valid operation.
The PROGRAM SUSPEND operation is aborted by performing a device reset or power-
down. In this case, data integrity cannot be ensured, and it is recommended that the
words or bytes that were aborted be reprogrammed.
PROGRAM RESUME Command
The PROGRAM RESUME (30h) command must be issued to exit a program suspend
mode and resume a PROGRAM operation. The controller can use DQ7 or DQ6 data
polling bits to determine the status of the PROGRAM operation. After a PROGRAM RE-
SUME command is issued, subsequent PROGRAM RESUME commands are ignored.
Another PROGRAM SUSPEND command can be issued after the device has resumed
programming.
ACCELERATED BUFFERED PROGRAM Operations
ACCELERATED BUFFER PROGRAM operations provides faster performance than
standard program command sequences. Operations are enabled through VPP/WP# un-
der the VHH voltage supply.
When the system asserts VHH on input, the device automatically enters the UNLOCK
BYPASS mode, which enables the system to use the UNLOCK BYPASS WRITE TO BUF-
FER PROGRAM (25h) command sequence.
Removing VHH from the VPP upon completion of the embedded program operation re-
turns the device to normal operation.
Table 12: ACCELERATED PROGRAM Requirements and Recommendations
Device State Requirements/Recommendations
Device blocks Requirement: Must be unprotected prior to raising VPP/WP# to VHH
VHH applied to VPP/WP# Requirement: Maximum cumulative period of 80 hours.
VPP/WP# Requirement: Must not be at VHH for operations except ACCELERATED BUFFERED PRO-
GRAM and CHIP ERASE; otherwise device can be damaged
Recommendation: Keep stable to VHH during ACCELERATED BUFFERED PROGRAM opera-
tion
Power-up Recommendation: Apply VHH on VPP/WP# after VCC/VCCQ is stable on.
Power-down Recommendation: Adjust VPP/WP# from VHH to VIH/VIL before VCC/VCCQ goes LOW.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
ACCELERATED BUFFERED PROGRAM Operations
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Erase Operations
CHIP ERASE Command
The CHIP ERASE (80/10h) command erases the entire chip. Six bus WRITE operations
are required to issue the command and start the program/erase controller.
Protected blocks are not erased. If all blocks are protected, the data remains unchanged.
No error is reported when protected blocks are not erased.
During the CHIP ERASE operation, the device ignores all other commands, including
ERASE SUSPEND. It is not possible to abort the operation. All bus READ operations dur-
ing CHIP ERASE output the data polling register on the data I/Os. See the Data Polling
Register section for more details.
After the CHIP ERASE operation completes, the device returns to read mode, unless an
error has occurred. If an error occurs, the device will continue to output the data polling
register.
When the operation fails, a READ/RESET command must be issued to reset the error
condition and return to read mode. The status of the array must be confirmed through
the BLANK CHECK operation and the BLOCK ERASE command re-issued to the failed
block.
The CHIP ERASE command sets all of the bits in unprotected blocks of the device to 1.
All previous data is lost.
The operation is aborted by performing a reset or by powering down the device. In this
case, data integrity cannot be ensured, and it is recommended that the entire chip be
erased again.
UNLOCK BYPASS CHIP ERASE Command
When the device is in unlock bypass mode, the UNLOCK BYPASS CHIP ERASE (80/10h)
command can be used to erase all memory blocks at one time. The command requires
only two bus WRITE operations instead of six using the standard CHIP ERASE com-
mand. The final bus WRITE operation starts the program/erase controller.
The UNLOCK BYPASS CHIP ERASE command behaves the same way as the CHIP
ERASE command: the operation cannot be aborted, and a bus READ operation to the
memory outputs the data polling register.
BLOCK ERASE Command
The BLOCK ERASE (80/30h) command erases a list of one or more blocks. It sets all bits
in the selected, unprotected blocks to 1. All previous, selected, unprotected blocks data
in the selected blocks is lost.
Six bus WRITE operations are required to select the first block in the list. Each addition-
al block in the list can be selected by repeating the sixth bus WRITE operation using the
address of the additional block. After the command sequence is written, a block erase
timeout occurs.
During the period specified by the block erase timeout parameter, additional block ad-
dresses and BLOCK ERASE commands can be written. Any command except BLOCK
ERASE or ERASE SUSPEND during this timeout period resets that block to the read
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Erase Operations
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mode. The system can monitor DQ3 to determine if the block erase timer has timed
out.
After the program/erase controller has started, it is not possible to select any more
blocks. Each additional block must therefore be selected within the timeout period of
the last block. The timeout timer restarts when an additional block is selected. After the
sixth bus WRITE operation, a bus READ operation outputs the data polling register. See
the WE#-Controlled Program waveforms for details on how to identify if the program/
erase controller has started the BLOCK ERASE operation.
After the BLOCK ERASE operation completes, the device returns to read mode, unless
an error has occurred. If an error occurs, bus READ operations will continue to output
the data polling register. A READ/RESET command must be issued to reset the error
condition and return to read mode.
If any selected blocks are protected, they are ignored, and all the other selected blocks
are erased. If all selected blocks are protected, the data remains unchanged. No error
condition is given when protected blocks are not erased.
During the BLOCK ERASE operation, the device ignores all commands except the
ERASE SUSPEND command and the READ/RESET command, which is accepted only
during the timeout period. The operation is aborted by performing a hardware reset or
powering down the device. In this case, data integrity cannot be ensured, and it is rec-
ommended that the aborted blocks be erased again.
UNLOCK BYPASS BLOCK ERASE Command
When the device is in unlock bypass mode, the UNLOCK BYPASS BLOCK ERASE
(80/30h) command can be used to erase one or more memory blocks at a time. The
command requires two bus WRITE operations instead of six using the standard BLOCK
ERASE command. The final bus WRITE operation latches the address of the block and
starts the program/erase controller.
To erase multiple blocks (after the first two bus WRITE operations have selected the first
block in the list), each additional block in the list can be selected by repeating the sec-
ond bus WRITE operation using the address of the additional block.
Any command except BLOCK ERASE or ERASE SUSPEND during a timeout period re-
sets that block to the read mode. The system can monitor DQ3 to determine if the block
erase timer has timed out.
The UNLOCK BYPASS BLOCK ERASE command behaves the same way as the BLOCK
ERASE command: the operation cannot be aborted, and a bus READ operation to the
memory outputs the data polling register. See the BLOCK ERASE Command section for
details.
ERASE SUSPEND Command
The ERASE SUSPEND (B0h) command temporarily suspends a BLOCK ERASE opera-
tion. One bus WRITE operation is required to issue the command. The block address is
"Don't Care."
The program/erase controller suspends the ERASE operation within the erase suspend
latency time of the ERASE SUSPEND command being issued. However, when the
ERASE SUSPEND command is written during the block erase timeout, the device im-
mediately terminates the timeout period and suspends the ERASE operation. After the
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Erase Operations
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program/erase controller has stopped, the device operates in read mode, and the erase
is suspended.
During an ERASE SUSPEND operation, it is possible to execute these operations in ar-
rays that are not suspended:
• READ (main memory array)
• PROGRAM
• WRITE TO BUFFER PROGRAM
• AUTO SELECT
• READ CFI
• UNLOCK BYPASS
• Extended memory block commands
• READ/RESET
Reading from a suspended block will output the data polling register. If an attempt is
made to program in a protected or suspended block, the PROGRAM command is ignor-
ed and the data remains unchanged; also, the data polling register is not read and no
error condition is given.
Before the RESUME command is initiated, the READ/RESET command must to issued
to exit AUTO SELECT and READ CFI operations. In addition, the EXIT UNLOCK BYPASS
and EXIT EXTENDED MEMORY BLOCK commands must be issued to exit unlock by-
pass and the extended memory block modes.
An ERASE SUSPEND command is ignored if it is written during a CHIP ERASE opera-
tion.
If the ERASE SUSPEND operation is aborted by performing a device hardware reset or
power-down, data integrity cannot be ensured, and it is recommended that the suspen-
ded blocks be erased again.
ERASE RESUME Command
The ERASE RESUME (30h) command restarts the program/erase controller after an
ERASE SUSPEND operation.
The device must be in read array mode before the RESUME command will be accepted.
An erase can be suspended and resumed more than once.
ACCELERATED CHIP ERASE Operations
The ACCELERATED CHIP ERASE operation provides faster performance than the
standard CHIP ERASE command sequence. Operations are enabled through VPP/WP#
under the VHH voltage supply.
When the system asserts VHH on input, the device automatically enters the UNLOCK
BYPASS mode, which enables the system to use the UNLOCK BYPASS CHIP ERASE
(80/30h) command sequence.
When a block is protected, the CHIP ERASE command skips the protected block and
continues with next block erase. The command algorithm skips a block that failed to
erase and continues with the remaining blocks. The fail flag will be set for the operation.
Removing VHH from the VPP/WP# upon completion of the embedded erase operation
returns the device to normal operation. When an error occurs or when the operation
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
ACCELERATED CHIP ERASE Operations
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fails, the array status should be confirmed through the BLANK CHECK operation and
the BLOCK ERASE command re-issued to the failed block.
Table 13: ACCELERATED CHIP ERASE Requirements and Recommendations
Device Component/State Requirements/Recommendations
VPP/WP# Requirement: Must not be at VHH for operations except ACCELERATED PROGRAM and
CHIP ERASE; otherwise device can be damaged.
VHH applied to VPP/WP# Requirement: Maximum cumulative period of 80 hours.
Power-up Recommendation: Apply VHH on VPP/WP# after VCC/VCCQ is stable on.
Power-down Recommendation: Adjust VPP/WP# from VHH to VIH/VIL before VCC/VCCQ goes LOW.
BLANK CHECK Operation
BLANK CHECK Commands
Two commands are required to execute a BLANK CHECK operation: BLANK CHECK
SETUP (EB/76h) and BLANK CHECK CONFIRM AND READ (29h).
The BLANK CHECK operation determines whether a specified block is blank (that is,
completely erased). It can also be used to determine whether a previous ERASE opera-
tion was successful, including ERASE operations that might have been interrupted by
power loss.
The BLANK CHECK operation checks for cells that are programmed or over-erased. If it
finds any, it returns a failure status, indicating that the block is not blank. If it returns a
passing status, the block is guaranteed blank (all 1s) and is ready to program.
Before executing, the ERASE operation initiates an embedded BLANK CHECK opera-
tion, and if the target block is blank, the ERASE operation is skipped, benefitting overall
cycle performance; otherwise, the ERASE operation continues.
The BLANK CHECK operation can occur in only one block at a time, and during its exe-
cution, reading the data polling register is the only other operation allowed. Reading
from any address in the device enables reading the data polling register to monitor
blank check progress or errors. Operations such as READ (array data), PROGRAM,
ERASE, and any suspended operation are not allowed.
After the BLANK CHECK operation has completed, the device returns to read mode un-
less an error has occurred. When an error occurs, the device continues to output data
polling register data. A READ/RESET command must be issued to reset the error condi-
tion and return the device to read mode.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
BLANK CHECK Operation
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Device Protection
Hardware Protection
The VPP/WP# function provides a hardware method of protecting either the highest or
lowest block. When V PP/WP# is LOW, PROGRAM and ERASE operations on either of
these block options is ignored to provide protection. When V PP/WP# is HIGH, the de-
vice reverts to the previous protection status for the highest or lowest block. PROGRAM
and ERASE operations can modify the data in either of these block options unless block
protection is enabled.
Note: Micron highly recommends driving VPP/WP# HIGH or LOW. If a system needs to
float the VPP/WP# pin, without a pull-up/pull-down resistor and no capacitor, then an
internal pull-up resistor is enabled.
Table 14: VPP/WP# Functions
VPP/WP# Settings Function
VIL Highest or lowest block is protected.
VIH Highest or lowest block is unprotected unless software protection is activated.
Software Protection
The following software protection modes are available:
• Volatile protection
• Nonvolatile protection
• Password protection
The device is shipped with all blocks unprotected. On first use, the device defaults to
the nonvolatile protection mode but can be activated in either the nonvolatile protec-
tion or password protection mode.
The desired protection mode is activated by setting either the nonvolatile protection
mode lock bit or the password protection mode lock bit of the lock register (see the Lock
Register section). Both bits are one-time-programmable and nonvolatile; therefore, af-
ter the protection mode has been activated, it cannot be changed, and the device is set
permanently to operate in the selected protection mode. It is recommended that the
desired software protection mode be activated when first programming the device.
For the highest or lowest block, a higher level of block protection can be achieved by
locking the block using nonvolatile protection mode and holding VPP /WP# LOW.
Blocks with volatile protection and nonvolatile protection can coexist within the memo-
ry array. If the user attempts to program or erase a protected block, the device ignores
the command and returns to read mode.
The block protection status can be read by performing a read electronic signature or by
issuing an AUTO SELECT command (see the Block Protection table).
Refer to the Block Protection Status table and the Software Protection Scheme figure for
details on the block protection scheme. Refer to the Protection Operations section for a
description of the command sets.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Device Protection
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Volatile Protection Mode
Volatile protection enables the software application to protect blocks against inadver-
tent change and can be disabled when changes are needed. Volatile protection bits are
unique for each block and can be individually modified. Volatile protection bits control
the protection scheme only for unprotected blocks whose nonvolatile protection bits
are cleared to 1. Issuing a PROGRAM VOLATILE PROTECTION BIT or CLEAR VOLATILE
PROTECTION BIT command sets to 0 or clears to 1 the volatile protection bits and pla-
ces the associated blocks in the protected (0) or unprotected (1) state, respectively. The
volatile protection bit can be set or cleared as often as needed.
When the device is first shipped, or after a power-up or hardware reset, the volatile pro-
tection bits default to 1 (unprotected).
Nonvolatile Protection Mode
A nonvolatile protection bit is assigned to each block. Each of these bits can be set for
protection individually by issuing a PROGRAM NONVOLATILE PROTECTION BIT com-
mand. Also, each device has one global volatile bit called the nonvolatile protection bit
lock bit; it can be set to protect all nonvolatile protection bits at once. This global bit
must be set to 0 only after all nonvolatile protection bits are configured to the desired
settings. When set to 0, the nonvolatile protection bit lock bit prevents changes to the
state of the nonvolatile protection bits. When cleared to 1, the nonvolatile protection
bits can be set and cleared using the PROGRAM NONVOLATILE PROTECTION BIT and
CLEAR ALL NONVOLATILE PROTECTION BITS commands, respectively.
No software command unlocks the nonvolatile protection bit lock bit unless the device
is in password protection mode; in nonvolatile protection mode, the nonvolatile protec-
tion bit lock bit can be cleared only by taking the device through a hardware reset or
power-up.
Nonvolatile protection bits cannot be cleared individually; they must be cleared all at
once using a CLEAR ALL NONVOLATILE PROTECTION BITS command. They will re-
main set through a hardware reset or a power-down/power-up sequence.
If one of the nonvolatile protection bits needs to be cleared (unprotected), additional
steps are required: First, the nonvolatile protection bit lock bit must be cleared to 1, us-
ing either a power-cycle or hardware reset. Then, the nonvolatile protection bits can be
changed to reflect the desired settings. Finally, the nonvolatile protection bit lock bit
must be set to 0 to lock the nonvolatile protection bits. The device now will operate nor-
mally.
To achieve the best protection, the PROGRAM NONVOLATILE PROTECTION LOCK BIT
command should be executed early in the boot code, and the boot code should be pro-
tected by holding VPP/WP# LOW.
Nonvolatile protection bits and volatile protection bits have the same function when
VPP/WP# is HIGH or when VPP/WP# is at the voltage for program acceleration (VHH ).
Password Protection Mode
The password protection mode provides a higher level of security than the nonvolatile
protection mode by requiring a 64-bit password to unlock the nonvolatile protection bit
lock bit. In addition to this password requirement, the nonvolatile protection bit lock
bit is set to 0 after power-up and reset to maintain the device in password protection
mode.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Device Protection
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Executing the UNLOCK PASSWORD command by entering the correct password clears
the nonvolatile protection bit lock bit, enabling the block nonvolatile protection bits to
be modified. If the password provided is incorrect, the nonvolatile protection bit lock
bit remains locked, and the state of the nonvolatile protection bits cannot be modified.
To place the device in password protection mode, the following two steps are required:
First, before activating the password protection mode, a 64-bit password must be set
and the setting verified. Password verification is allowed only before the password pro-
tection mode is activated. Next, password protection mode is activated by program-
ming the password protection mode lock bit to 0. This operation is irreversible. After the
bit is programmed, it cannot be erased, the device remains permanently in password
protection mode, and the 64-bit password can be neither retrieved nor reprogrammed.
In addition, all commands to the address where the password is stored are disabled.
Note: There is no means to verify the password after password protection mode is ena-
bled. If the password is lost after enabling the password protection mode, there is no
way to clear the nonvolatile protection bit lock bit.
Figure 12: Software Protection Scheme
1 = unprotected (default)
0 = protected
1 = unprotected
0 = protected
(Default setting depends on the product order option)
Volatile protection bit Nonvolatile protection bit
1 = unlocked (default, after power-up or hardware reset)
0 = locked
Nonvolatile protection bit lock bit (volatile)
Nonvolatile protection
mode
Password protection
mode
Volatile
protection
Nonvolatile
protection
Array block
Notes: 1. Volatile protection bits are programmed and cleared individually. Nonvolatile protection
bits are programmed individually and cleared collectively.
2. Once programmed to 0, the nonvolatile protection bit lock bit can be reset to 1 only by
taking the device through a power-up or hardware reset.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Device Protection
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Table 15: Block Protection Status
Nonvolatile
Protection Bit
Lock Bit1
Nonvolatile
Protection
Bit2
Volatile
Protection
Bit3
Block
Protection
Status4Block Protection Status
1 1 1 00h Block unprotected; nonvolatile protection bit changeable.
1 1 0 01h Block protected by volatile protection bit; nonvolatile pro-
tection bit changeable.
1 0 1 01h Block protected by nonvolatile protection bit; nonvolatile
protection bit changeable.
1 0 0 01h Block protected by nonvolatile protection bit and volatile
protection bit; nonvolatile protection bit changeable.
0 1 1 00h Block unprotected; nonvolatile protection bit unchangeable.
0 1 0 01h Block protected by volatile protection bit; nonvolatile pro-
tection bit unchangeable.
0 0 1 01h Block protected by nonvolatile protection bit; nonvolatile
protection bit unchangeable.
0 0 0 01h Block protected by nonvolatile protection bit and volatile
protection bit; nonvolatile protection bit unchangeable.
Notes: 1. Nonvolatile protection bit lock bit: when cleared to 1, all nonvolatile protection bits are
unlocked; when set to 0, all nonvolatile protection bits are locked.
2. Block nonvolatile protection bit: when cleared to 1, the block is unprotected; when set
to 0, the block is protected.
3. Block volatile protection bit: when cleared to 1, the block is unprotected; when set to 0,
the block is protected.
4. Block protection status is checked under AUTO SELECT mode.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Device Protection
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Block Protection Command Definitions – Address-Data Cycles
Table 16: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit
Notes 1 and 2 apply to entire table
Command and
Code/Subcode
Bus
Size
Address and Data Cycles
Notes
1st 2nd 3rd 4th
…
nth
A D A D A D A D A D
LOCK REGISTER Commands
ENTER LOCK
REGISTER
COMMAND SET (40h)
x8 AAA AA 555 55 AAA 40 3
x16 555 AA 2AA 55 555
PROGRAM LOCK
REGISTER (A0h)
x8 X A0 X Data 5
x16
READ LOCK REGISTER x8 X Data 4, 5, 6
x16
EXIT LOCK REGISTER
(90h/00h)
x8 X 90 X 00 3
x16
PASSWORD PROTECTION Commands
ENTER PASSWORD
PROTECTION
COMMAND SET (60h)
x8 AAA AA 555 55 AAA 60 3
x16 555 AA 2AA 55 555
PROGRAM
PASSWORD (A0h)
x8 X A0 PWAn PWDn 7
x16
READ PASSWORD x8 00 PWD0 01 PWD1 02 PWD2 03 PWD3 … 07 PWD
7
4, 6, 8,
9
x16 00 PWD0 01 PWD1 02 PWD2 03 PWD3
UNLOCK PASSWORD
(25h/03h)
x8 00 25 00 03 00 PWD0 01 PWD1 … 00 29 8, 10
x16
EXIT PASSWORD
PROTECTION (90h/00h)
x8 X 90 X 00 3
x16
NONVOLATILE PROTECTION Commands
ENTER NONVOLATILE
PROTECTION
COMMAND SET (C0h)
x8 AAA AA 555 55 AAA C0 3
x16 555 AA 2AA 55 555
PROGRAM
NONVOLATILE
PROTECTION BIT (A0h)
x8 X A0 BAd 00 11
x16
READ NONVOLATILE
PROTECTION BIT
STATUS
x8 BAd READ
(DQ0)
4, 6, 11
x16
CLEAR ALL
NONVOLATILE
PROTECTION
BITS (80h/30h)
x8 X 80 00 30 12
x16
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Block Protection Command Definitions – Address-Data Cycles
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Table 16: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit (Continued)
Notes 1 and 2 apply to entire table
Command and
Code/Subcode
Bus
Size
Address and Data Cycles
Notes
1st 2nd 3rd 4th
…
nth
A D A D A D A D A D
EXIT NONVOLATILE
PROTECTION (90h/00h)
x8 X 90 X 00 3
x16
NONVOLATILE PROTECTION BIT LOCK BIT Commands
ENTER NONVOLATILE
PROTECTION BIT
LOCK BIT
COMMAND SET (50h)
x8 AAA AA 555 55 AAA 50 3
x16 555 AA 2AA 55 555
PROGRAM
NONVOLATILE
PROTECTION BIT
LOCK BIT (A0h)
x8 X A0 X 00 11
x16
READ NONVOLATILE
PROTECTION BIT
LOCK BIT STATUS
x8 X READ
(DQ0)
4, 6, 11
x16
EXIT NONVOLATILE
PROTECTION BIT
LOCK BIT (90h/00h)
x8 X 90 X 00 3
x16
VOLATILE PROTECTION Commands
ENTER VOLATILE
PROTECTION
COMMAND SET (E0h)
x8 AAA AA 555 55 AAA E0 3
x16 555 AA 2AA 55 555
PROGRAM VOLATILE
PROTECTION BIT (A0h)
x8 X A0 BAd 00 11
x16
READ VOLATILE
PROTECTION BIT
STATUS
x8 BAd READ
(DQ0)
4, 6
x16
CLEAR VOLATILE
PROTECTION BIT (A0h)
x8 X A0 BAd 01 11
x16
EXIT VOLATILE
PROTECTION (90h/00h)
x8 X 90 X 00 3
x16
EXTENDED MEMORY BLOCK Operations
ENTER EXTENDED
MEMORY BLOCK (88h)
x8 AAA AA 555 55 AAA 88
x16 555 2AA 555
PROGRAM EXTENDED
MEMORY BLOCK (A0h)
x8 AAA AA 555 55 AAA A0 Word
address
data
x16 555 2AA 555
READ EXTENDED
MEMORY BLOCK
x8 Word
address
data
x16
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Block Protection Command Definitions – Address-Data Cycles
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Table 16: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit (Continued)
Notes 1 and 2 apply to entire table
Command and
Code/Subcode
Bus
Size
Address and Data Cycles
Notes
1st 2nd 3rd 4th
…
nth
A D A D A D A D A D
EXIT EXTENDED
MEMORY BLOCK
(90h/00h)
x8 AAA AA 555 55 555 90 X 00
x16 555 2AA
Notes: 1. Key: A = Address and D = Data; X = "Don’t Care;" BAd = Any address in the block; PWDn
= Password bytes, n = 0 to 7 (×8)/words 0 to 3 (×16); PWAn = Password address, n = 0 to
7 (×8)/0 to 3 (×16); PWDn = Password words, n = 0 to 3 (×16); PWAn = Password address,
n = 0 to 3(×16);Gray = Not applicable. All values in the table are hexadecimal.
2. DQ[15:8] are "Don’t Care" during UNLOCK and COMMAND cycles. A[MAX:16] are
"Don’t Care" during UNLOCK and COMMAND cycles, unless an address is required.
3. The ENTER command sequence must be issued prior to any operation. It disables READ
and WRITE operations from and to block 0. READ and WRITE operations from and to
any other block are allowed. Also, when an ENTER COMMAND SET command is issued,
an EXIT COMMAND SET command must be issued to return the device to READ mode.
4. READ REGISTER/PASSWORD commands have no command code; CE# and OE# are driven
LOW and data is read according to a specified address.
5. Data = Lock register content.
6. All address cycles shown for this command are READ cycles.
7. Only one portion of the password can be programmed or read by each PROGRAM PASS-
WORD command.
8. Each portion of the password can be entered or read in any order as long as the entire
64-bit password is entered or read.
9. For the x8 READ PASSWORD command, the nth (and final) address cycle equals the 8th
address cycle. From the 5th to the 8th address cycle, the values for each address and da-
ta pair continue the pattern shown in the table as follows: for x8, address and data = 04
and PWD4; 05 and PWD5; 06 and PWD6; 07 and PWD7.
10. For the x8 UNLOCK PASSWORD command, the nth (and final) address cycle equals the
11th address cycle. From the 5th to the 10th address cycle, the values for each address
and data pair continue the pattern shown in the table as follows: address and data = 02
and PWD2; 03 and PWD3; 04 and PWD4; 05 and PWD5; 06 and PWD6; 07 and PWD7.
For the x16 UNLOCK PASSWORD command, the nth (and final) address cycle equals the
7th address cycle. For the 5th and 6th address cycles, the values for the address and data
pair continue the pattern shown in the table as follows: address and data = 02 and
PWD2; 03 and PWD3.
11. Both nonvolatile and volatile protection bit settings are as follows: Protected state = 00;
Unprotected state = 01.
12. The CLEAR ALL NONVOLATILE PROTECTION BITS command programs all nonvolatile pro-
tection bits before erasure. This prevents over-erasure of previously cleared nonvolatile
protection bits.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Block Protection Command Definitions – Address-Data Cycles
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Protection Operations
Blocks can be protected individually against accidental PROGRAM or ERASE operations
on both 8-bit and 16-bit configurations. The block protection scheme is shown in the
Software Protection Scheme figure. Memory block and extended memory block protec-
tion is configured through the lock register.
LOCK REGISTER Commands
After the ENTER LOCK REGISTER COMMAND SET (40h) command has been issued, all
bus READ or PROGRAM operations can be issued to the lock register.
The PROGRAM LOCK REGISTER (A0h) command allows the lock register to be config-
ured. The programmed data can then be checked with a READ LOCK REGISTER com-
mand by driving CE# and OE# LOW with the appropriate address data on the address
bus.
PASSWORD PROTECTION Commands
After the ENTER PASSWORD PROTECTION COMMAND SET (60h) command has been
issued, the commands related to password protection mode can be issued to the device.
The PROGRAM PASSWORD (A0h) command is used to program the 64-bit password
used in the password protection mode. To program the 64-bit password, the complete
command sequence must be entered eight times at eight consecutive addresses selec-
ted by A[1:0] plus DQ15/A-1 in 8-bit mode, or four times at four consecutive addresses
selected by A[1:0] in 16-bit mode. By default, all password bits are set to 1. The password
can be checked by issuing a READ PASSWORD command.
Note: A password must be programmed per Flash memory die to enable password pro-
tection.
The READ PASSWORD command is used to verify the password used in password pro-
tection mode. To verify the 64-bit password, the complete command sequence must be
entered eight times at eight consecutive addresses selected by A[1:0] plus DQ15/A-1 in
8-bit mode, or four times at four consecutive addresses selected by A[1:0] in 16-bit
mode. If the password mode lock bit is programmed and the user attempts to read the
password, the device will output 00h onto the I/O data bus.
The UNLOCK PASSWORD (25/03h) command is used to clear the nonvolatile protec-
tion bit lock bit, allowing the nonvolatile protection bits to be modified. The UNLOCK
PASSWORD command must be issued, along with the correct password, and requires a
6μs delay between successive UNLOCK PASSWORD commands in order to prevent
hackers from cracking the password by trying all possible 64-bit combinations. If this
delay does not occur, the latest command will be ignored. Approximately 6μs is re-
quired for unlocking the device after the valid 64-bit password has been provided.
NONVOLATILE PROTECTION Commands
After the ENTER NONVOLATILE PROTECTION COMMAND SET (C0h) command has
been issued, the commands related to nonvolatile protection mode can be issued to the
device.
A block can be protected from program or erase by issuing a PROGRAM NONVOLATILE
PROTECTION BIT (A0h) command, along with the block address. This command sets
the nonvolatile protection bit to 0 for a given block.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Protection Operations
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The status of a nonvolatile protection bit for a given block or group of blocks can be
read by issuing a READ NONVOLATILE MODIFY PROTECTION BIT command, along
with the block address.
The nonvolatile protection bits are erased simultaneously by issuing a CLEAR ALL
NONVOLATILE PROTECTION BITS (80/30h) command. No specific block address is re-
quired. If the nonvolatile protection bit lock bit is set to 0, the command fails.
Figure 13: Set/Clear Nonvolatile Protection Bit Algorithm Flowchart
No
No
Yes
Yes
Success
Done?
Match
expected value?
DQ0 = 1 (clear)
or 0 (set)
ENTER NONVOLATILE
PROTECTION
command set
Start
PROGRAM/CLEAR
NONVOLATILE
PROTECTION BIT
Polling algorithm
READ NONVOLATILE
PROTECTION
BIT STATUS
EXIT PROTECTION
command set
Notes: 1. See the Block Protection Command Definitions table for address-data cycle details.
2. DQ5 and DQ1 are ignored in this algorithm flow.
NONVOLATILE PROTECTION BIT LOCK BIT Commands
After the ENTER NONVOLATILE PROTECTION BIT LOCK BIT COMMAND SET (50h)
command has been issued, the commands that allow the nonvolatile protection bit lock
bit to be set can be issued to the device.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Protection Operations
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The PROGRAM NONVOLATILE PROTECTION BIT LOCK BIT (A0h) command is used to
set the nonvolatile protection bit lock bit to 0, thus locking the nonvolatile protection
bits and preventing them from being modified.
The READ NONVOLATILE PROTECTION BIT LOCK BIT STATUS command is used to
read the status of the nonvolatile protection bit lock bit.
VOLATILE PROTECTION Commands
After the ENTER VOLATILE PROTECTION COMMAND SET (E0h) command has been
issued, commands related to the volatile protection mode can be issued to the device.
The PROGRAM VOLATILE PROTECTION BIT (A0h) command individually sets a vola-
tile protection bit to 0 for a given block. If the nonvolatile protection bit for the same
block is set, the block is locked regardless of the value of the volatile protection bit (see
the Block Protection Status table).
The status of a volatile protection bit for a given block can be read by issuing a READ
VOLATILE PROTECTION BIT STATUS command along with the block address.
The CLEAR VOLATILE PROTECTION BIT (A0h) command individually clears (sets to 1)
the volatile protection bit for a given block. If the nonvolatile protection bit for the same
block is set, the block is locked regardless of the value of the volatile protection bit (see
the Block Protection Status table).
EXTENDED MEMORY BLOCK Commands
The device has one extra 128-word extended memory block that can be accessed only
by the ENTER EXTENDED MEMORY BLOCK (88h) command. The extended memory
block is 128 words (x16) or 256 bytes (x8). It is used as a security block to provide a per-
manent 128-bit secure ID number or to store additional information. The device can be
shipped with the extended memory block prelocked permanently by Micron, including
the 128-bit security identification number. Or, the device can be shipped with the ex-
tended memory block unlocked, enabling customers to permanently program and lock
it (default). (See Lock Register, the AUTO SELECT command, and the Block Protection
table).
Table 17: Extended Memory Block Address and Data
Address Data
x8 x16 Micron prelocked Customer Lockable
000000h–00000Fh 000000h–000007h Secure ID number Determined by
customer (default)
Secure ID number
000010h–0000FFh 000008h–00007Fh Protected and
unavailable
Determined by customer
After the ENTER EXTENDED MEMORY BLOCK command has been issued, the device
enters the extended memory block mode. All bus READ or PROGRAM operations are
conducted on the extended memory block, and the extended memory block is ad-
dressed using the addresses occupied by block 0 in the other operating modes (see the
Memory Map table).
In extended memory block mode, ERASE, CHIP ERASE, ERASE SUSPEND, and ERASE
RESUME commands are not allowed. The extended memory block cannot be erased,
and each bit of the extended memory block can only be programmed once.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Protection Operations
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The extended memory block is protected from further modification by programming
lock register bit 0. Once invoked, this protection cannot be undone.
The device remains in extended memory block mode until the EXIT EXTENDED MEM-
ORY BLOCK (90/00h) command is issued, which returns the device to read mode, or
until power is removed from the device. After a power-up sequence or hardware reset,
the device will revert to reading memory blocks in the main array.
EXIT PROTECTION Command
The EXIT PROTECTION COMMAND SET (90/00h) command is used to exit the lock
register, password protection, nonvolatile protection, volatile protection, and nonvola-
tile protection bit lock bit command set modes and return the device to read mode.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Protection Operations
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Common Flash Interface
The common Flash interface (CFI) is a JEDEC-approved, standardized data structure
that can be read from the Flash memory device. It allows a system's software to query
the device to determine various electrical and timing parameters, density information,
and functions supported by the memory. The system can interface easily with the de-
vice, enabling the software to upgrade itself when necessary.
When the READ CFI command is issued, the device enters CFI query mode and the data
structure is read from memory. The following tables show the addresses (A[7:0], A-1)
used to retrieve the data. The query data is always presented on the lowest order data
outputs (DQ[7:0]), and the other data outputs (DQ[15:8]) are set to 0.
Table 18: Query Structure Overview
Note 1 applies to the entire table
Address
Subsection Name Descriptionx16 x8
10h 20h CFI query identification string Command set ID and algorithm data offset
1Bh 36h System interface information Device timing and voltage information
27h 4Eh Device geometry definition Flash device layout
40h 80h Primary algorithm-specific extended query table Additional information specific to the primary al-
gorithm (optional)
Note: 1. Query data are always presented on the lowest order data outputs (DQ[7:0]). DQ[15:8]
are set to 0.
Table 19: CFI Query Identification String
Note 1 applies to the entire table
Address
Data Description Valuex16 x8
10h 20h 0051h Query unique ASCII string "QRY" "Q"
11h 22h 0052h "R"
12h 24h 0059h "Y"
13h
14h
26h
28h
0002h
0000h
Primary algorithm command set and control interface ID code 16-bit ID
code defining a specific algorithm
–
15h
16h
2Ah
2Ch
0040h
0000h
Address for primary algorithm extended query table (see the Primary Algo-
rithm-Specific Extended Query Table)
P = 40h
17h
18h
2Eh
30h
0000h
0000h
Alternate vendor command set and control interface ID code second ven-
dor-specified algorithm supported
–
19h
1Ah
32h
34h
0000h
0000h
Address for alternate algorithm extended query table –
Note: 1. Query data are always presented on the lowest order data outputs (DQ[7:0]). DQ[15:8]
are set to 0.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Common Flash Interface
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Table 20: CFI Query System Interface Information
Note 1 applies to the entire table
Address
Data Description Valuex16 x8
1Bh 36h 0027h VCC logic supply minimum program/erase voltage
Bits[7:4] BCD value in volts
Bits[3:0] BCD value in 100mV
2.7V
1Ch 38h 0036h VCC logic supply maximum program/erase voltage
Bits[7:4] BCD value in volts
Bits[3:0] BCD value in 100mV
3.6V
1Dh 3Ah 0085h VHH (programming) supply minimum program/erase voltage
Bits[7:4] hex value in volts
Bits[3:0] BCD value in 100mV
8.5V
1Eh 3Ch 0095h VHH (programming) supply maximum program/erase voltage
Bits[7:4] hex value in volts
Bits[3:0] BCD value in 10mV
9.5V
1Fh 3Eh 0005h Typical timeout for single byte/word program = 2nμs 32µs
20h 40h 0009h Typical timeout for maximum size buffer program = 2nμs 512µs
21h 42h 0008h Typical timeout per individual block erase = 2nms 256ms
22h 44h 0010h Typical timeout for full chip erase = 2nms 66s
23h 46h 0003h Maximum timeout for byte/word program = 2n times typical 256µs
24h 48h 0002h Maximum timeout for buffer program = 2n times typical 2048µs
25h 4Ah 0003h Maximum timeout per individual block erase = 2n times typical 2s
26h 4Ch 0003h Maximum timeout for chip erase = 2n times typical 528s
Note: 1. The values in this table are valid for both packages.
Table 21: Device Geometry Definition
Address
Data Description Valuex16 x8
27h 4Eh 0019h Device size = 2n in number of bytes 32MB
28h
29h
50h
52h
0002h
0000h
Flash device interface code description x8, x16
asynchronous
2Ah
2Bh
54h
56h
000xh
0000h
Maximum number of bytes in multi-byte program or page =
2n
X16 mode: 000Ah
X8 mode: 08h
1024 (x16)
256 (x8)
2Ch 58h 0001h Number of erase block regions. It specifies the number of
regions containing contiguous erase blocks of the same size.
1
2Dh
2Eh
5Ah
5Ch
00FFh
0000h
Erase block region 1 information
Number of identical-size erase blocks = 00FFh + 1
256
2Fh
30h
5Eh
60h
0000h
0002h
Erase block region 1 information
Block size in region 1 = 0200h × 256 bytes
128KB
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Common Flash Interface
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Table 21: Device Geometry Definition (Continued)
Address
Data Description Valuex16 x8
31h
32h
33h
34h
62h
64h
66h
68h
0000h
0000h
0000h
0000h
Erase block region 2 information 0
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase block region 3 information 0
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase block region 4 information 0
Table 22: Primary Algorithm-Specific Extended Query Table
Note 1 applies to the entire table
Address
Data Description Valuex16 x8
40h 80h 0050h Primary algorithm extended query table unique ASCII string “PRI” "P"
41h 82h 0052h "R"
42h 84h 0049h "I"
43h 86h 0031h Major version number, ASCII "1"
44h 88h 0033h Minor version number, ASCII "3"
45h 8Ah 001Ch Address sensitive unlock (bits[1:0]):
00 = Required
01 = Not required
Process technology (bits [7:2])
0111b: 2nd Generation
0110b: 1st Generation
Required
46h 8Ch 0002h Erase suspend:
00 = Not supported
01 = Read only
02 = Read and write
2
47h 8Eh 0001h Block protection:
00 = Not supported
x = Number of blocks per group
1
48h 90h 0000h Temporary block unprotect scheme:
00 = Not supported
01 = Supported
Not supported
49h 92h 0008h Protect/unprotect scheme:
08 = Advanced sector protection method
8
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Common Flash Interface
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Table 22: Primary Algorithm-Specific Extended Query Table (Continued)
Note 1 applies to the entire table
Address
Data Description Valuex16 x8
4Ah 94h 0000h Simultaneous operations:
Not supported
–
4Bh 96h 0000h Burst mode:
00 = Not supported
01 = Supported
Not supported
4Ch 98h 0003h Page mode:
00 = Not supported
01 = 4-word page
02 = 8-word page
03 = 16-word page
16-word page
4Dh 9Ah 0085h VHH supply minimum program/erase voltage:
Bits[7:4] hex value in volts
Bits[3:0] BCD value in 100mV
8.5V
4Eh 9Ch 0095h VHH supply maximum program/erase voltage:
Bits[7:4] hex value in volts
Bits[3:0] BCD value in 100mV
9.5V
4Fh 9Eh 00xxh WP# protection:
xx = 04h: Uniform device, HW protection for lowest block
xx = 05h: Uniform device, HW protection for highest block
Uniform +
VPP/WP# protect-
ing highest or
lowest block
50h A0h 0001h Program suspend:
00 = Not supported
01 = Supported
Supported
Note: 1. The values in this table are valid for both packages.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Common Flash Interface
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Power-Up and Reset Characteristics
Table 23: Power-Up Specifications
Note 1 applies to entire table.
Parameter
Symbol
Min Unit NotesLegacy JEDEC
VCC HIGH to VCCQ HIGH – tVCHVCQH 0 µs 2
VCC HIGH to rising edge of RST# tVCS tVCHPH 300 µs 3, 4
VCCQ HIGH to rising edge of RST# tVIOS tVCQHPH 0 µs 3, 4
RST# HIGH to chip enable LOW tRH tPHEL 50 ns
RST# HIGH to write enable LOW – tPHWL 150 ns
Notes: 1. Sampled only; not 100% tested.
2. VCC should attain VCC,min from VSS simultaneously with or prior to applying VCCQ during
power up. VCC should attain VSS during power down.
3. If RST# is not stable for tVCS or tVIOS, the device will not allow any READ or WRITE oper-
ations, and a hardware reset is required.
4. Power supply transitions should only occur when RST# is LOW.
Figure 14: Power-Up Timing
tRH
tVIOS
tVCS
tPHWL
tVCHVCQH
VCCQ
VCC
CE#
RST#
WE#
VSSQ
VSS
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Power-Up and Reset Characteristics
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Table 24: Reset AC Specifications
Condition/Parameter
Symbol
Min Max Unit NotesLegacy JEDEC
RST# LOW to read mode during program or
erase
tREADY tPLRH – 25 µs 1
RST# pulse width tRP tPLPH 100 – ns
RST# HIGH to CE# LOW, OE# LOW tRH tPHEL, tPHGL 50 – ns 1
RST# LOW to standby mode during read mode tRPD – 0 – µs
RST# LOW to standby mode during program or
erase
0 – µs
RY/BY# HIGH to CE# LOW, OE# LOW tRB tRHEL, tRHGL 0 – ns 1
Note: 1. Sampled only; not 100% tested.
Figure 15: Reset AC Timing – No PROGRAM/ERASE Operation in Progress
tRH
RY/BY#
CE#, OE#
RST#
tRP
Figure 16: Reset AC Timing During PROGRAM/ERASE Operation
tRB
RY/BY#
CE#, OE#
RST#
tRP
tRH
tREADY
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Power-Up and Reset Characteristics
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Absolute Ratings and Operating Conditions
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions outside those indicated in the operational sections of this specification is not im-
plied. Exposure to absolute maximum rating conditions for extended periods may ad-
versely affect reliability.
Table 25: Absolute Maximum/Minimum Ratings
Parameter Symbol Min Max Unit Notes
Temperature under bias TBIAS –50 125 °C
Storage temperature TSTG –65 150 °C
Supply voltage VCC –0.6 VCC + 2 V 1, 2
Input/output supply voltage VCCQ –0.6 VCCQ + 2 V 1, 2
Program/erase voltage VPP –0.6 9.5 V 3
Notes: 1. During signal transitions, minimum voltage may undershoot to −2V for periods less than
20ns.
2. During signal transitions, maximum voltage may overshoot to VCC + 2V for periods less
than 20ns.
3. VPP must not remain at 9.5V for more than 80 hours cumulative.
Table 26: Operating Conditions
Parameter Symbol Min Max Unit Notes
Supply voltage VCC 2.7 3.6 V
Input/output supply voltage (VCCQ ≤ VCC) VCCQ 1.65 3.6 V
Accelerated buffered program/chip erase voltage VHH 8.5 9.5 V
Ambient operating temperature TA–40 85 °C
Load capacitance CL30 pF
Input rise and fall times (VIL to VIH) – 0.3 2.5 ns 1, 2
Input pulse voltages – 0 to VCCQ V
Input and output timing reference voltages – VCCQ/2 V
Address to address skew – – 3 ns
Notes: 1. If the rise/fall time is slower than 2.5ns, all timing specs must be derated by 0.5ns for ev-
ery nanosecond push-out in rise/fall time. (Example: for a 10ns rise/fall time, all timing
specs must be derated by (10 - 2.5) × (0.5ns) = 3.75ns.
2. Applies to Address, CE#, OE#, and WE# signals.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Absolute Ratings and Operating Conditions
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Figure 17: AC Measurement Load Circuit
CL
VCCQ
25kΩ
Device
under
test
0.1µF
VCC
25kΩ
Note: 1. CL includes jig capacitance.
Figure 18: AC Measurement I/O Waveform
VCCQ
0V
VCCQ/2
Table 27: Input/Output Capacitance
Parameter Symbol Test Condition Min Max Unit
Input capacitance CIN VIN = 0V 3 11 pF
Output capacitance COUT VOUT = 0V 3 7 pF
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Absolute Ratings and Operating Conditions
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DC Characteristics
Table 28: DC Current Characteristics
Parameter Symbol Conditions Min Typ Max Unit Notes
Input load current ILI 0V ≤ VIN ≤ VCC – – ±1 µA 1
Output leakage current ILO 0V ≤ VOUT ≤ VCC – – ±1 µA
VCC read
current
Random read ICC1 CE# = VIL, OE# = VIH,
f = 5 MHz
– 26 31 mA
Page read CE# = VIL, OE# = VIH,
f = 13 MHz
– 12 16 mA
VCC standby
current (256Mb)
ICC2 CE# = VCCQ ±0.2V,
RST# = VCCQ ±0.2V
– 65 135 µA
VCC program/erase/blank
check current
ICC3 Program/
erase
controller
active
VPP/WP# = VIL
or VIH
– 35 50 mA 2
VPP/WP# = VHH – 35 50 mA
VPP current Read IPP1 VPP/WP# ≤ VCC – 2 15 µA
Standby IPP2 – 0.2 5 µA
PROGRAM operation
ongoing
IPP3 VPP/WP# = VHH – 5 10 mA
VPP/WP# = VCC – 0.05 0.10 mA
ERASE operation
ongoing
IPP4 VPP/WP# = VHH – 5 10 mA
VPP/WP# = VCC – 0.05 0.10 mA
Notes: 1. The maximum input load current is ±5µA on the VPP/WP# pin.
2. Sampled only; not 100% tested.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
DC Characteristics
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Table 29: DC Voltage Characteristics
Parameter Symbol Conditions Min Typ Max Unit Notes
Input LOW voltage VIL VCC ≥ 2.7V –0.5 – 0.8 V
Input HIGH voltage VIH VCC ≥ 2.7V 0.7VCCQ – VCCQ + 0.4 V
Output LOW voltage VOL IOL = 100µA,
VCC = VCC,min,
VCCQ = VCCQ,min
– – 0.15VCCQ V
Output HIGH voltage VOH IOH = 100µA,
VCC = VCC,min,
VCCQ = VCCQ,min
0.85VCCQ – – V
Voltage for VPP/WP# program
acceleration
VPP – 8.5 – 9.5 V 1
Program/erase lockout supply
voltage
VLKO – 2.0 – – V 2, 3
Notes: 1. VPP must not remain at 9.5V for more than 80 hours cumulative.
2. Sampled only; not 100% tested.
3. WRITE operations are not valid when VCC supply drops below VLKO.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
DC Characteristics
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Read AC Characteristics
Table 30: Read AC Characteristics – VCC= VCCQ = 2.7-3.6V
Parameter
Symbol
Condition Min Max Unit NotesLegacy JEDEC
Address valid to next address valid tRC tAVAV CE# = VIL,
OE# = VIL
70 – ns
Address valid to output valid tACC tAVQV CE# = VIL,
OE# = VIL
– 70 ns
Address valid to output valid (page) tPAGE tAVQV1 CE# = VIL,
OE# = VIL
– 20 ns
CE# LOW to output valid tCE tELQV OE# = VIL – 70 ns
OE# LOW to output valid tOE tGLQV CE# = VIL – 25 ns
CE# HIGH to output High-Z tHZ tEHQZ OE# = VIL – 20 ns 1
OE# HIGH to output High-Z tDF tGHQZ CE# = VIL – 15 ns 1
CE# HIGH, OE# HIGH, or address transi-
tion to output transition
tOH tEHQX,
tGHQX,
tAXQX
– 0 – ns
CE# LOW to BYTE# LOW tELFL tELBL – – 10 ns
CE# LOW to BYTE# HIGH tELFH tELBH – – 10 ns
BYTE# LOW to output valid tFLQV tBLQV – – 1 µs
BYTE# HIGH to output valid tFHQV tBHQV – – 1 µs
Note: 1. Sampled only; not 100% tested.
Table 31: Read AC Characteristics – VCCQ= 1.65V-VCC
Parameter
Symbol
Condition Min Max Unit NotesLegacy JEDEC
Address valid to next address valid tRC tAVAV CE# = VIL,
OE# = VIL
75 – ns
Address valid to output valid tACC tAVQV CE# = VIL,
OE# = VIL
– 75 ns
Address valid to output valid (page) tPAGE tAVQV1 CE# = VIL,
OE# = VIL
– 20 ns
CE# LOW to output valid tCE tELQV OE# = VIL – 75 ns
OE# LOW to output valid tOE tGLQV CE# = VIL – 25 ns
CE# HIGH to output High-Z tHZ tEHQZ OE# = VIL – 20 ns 1
OE# HIGH to output High-Z tDF tGHQZ CE# = VIL – 15 ns 1
CE# HIGH, OE# HIGH, or address transi-
tion to output transition
tOH tEHQX,
tGHQX,
tAXQX
– 0 – ns
CE# LOW to BYTE# LOW tELFL tELBL – – 10 ns
CE# LOW to BYTE# HIGH tELFH tELBH – – 10 ns
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Read AC Characteristics
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Table 31: Read AC Characteristics – VCCQ= 1.65V-VCC (Continued)
Parameter
Symbol
Condition Min Max Unit NotesLegacy JEDEC
BYTE# LOW to output valid tFLQV tBLQV – – 1 µs
BYTE# HIGH to output valid tFHQV tBHQV – – 1 µs
Note: 1. Sampled only; not 100% tested.
Figure 19: Random Read AC Timing (8-Bit Mode)
Valid
Valid
tACC
tRC
tOH
tCE
tELFL
tLZ
tOH
tHZ
tOLZ tOH
tOE tDF
A[MAX:0]/A-1
CE#
OE#
DQ[7:0]
BYTE#
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Read AC Characteristics
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Figure 20: Random Read AC Timing (16-Bit Mode)
Valid
Valid
tACC
tRC
tOH
tCE
tELFH
tLZ
tOH
tHZ
tOLZ tOH
tOE tDF
A[MAX:0]
CE#
OE#
DQ[15:0]
BYTE#
Figure 21: BYTE# Transition Read AC Timing
Data-out
Data-out
Valid
Valid
tACC tOH
tFHQV
tBLQX
High-Z
A[MAX:0]
A–1
BYTE#
DQ[7:0]
DQ[15:8] 1
Note: 1. DQ15 transitions to be A-1 when BYTE# is LOW.
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Read AC Characteristics
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Figure 22: Page Read AC Timing (16-Bit Mode)
Valid
Valid Valid Valid ValidValid Valid Valid
tACC
tCE
tPAGE
tOH
tHZ
tOH
tOE
tDF
A[MAX:4]
A[3:0]
CE#
OE#
DQ[15:0] Valid Valid Valid Valid Valid Valid Valid
Note: 1. Page size is 16 words (32 bytes) and is addressed by address inputs A[3:0] in x16 bus
mode and A[3:0] plus DQ15/A−1 in x8 bus mode.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Read AC Characteristics
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Write AC Characteristics
Table 32: WE#-Controlled Write AC Characteristics
Parameter
Symbol
Min Typ Max Unit NotesLegacy JEDEC
WRITE cyle time tWC – 60 – – ns
CE# LOW to WE# LOW tCS tELWL 0 – – ns
WE# LOW to WE# HIGH tWP tWLWH 35 – – ns
Input valid to WE# HIGH tDS tDVWH 30 – – ns 1
WE# HIGH to input transition tDH tWHDX 0 – – ns
WE# HIGH to CE# HIGH tCH tWHEH 0 – – ns
WE# HIGH to WE# LOW tWPH tWHWL 20 – – ns
Address valid to WE# LOW tAS tAVWL 0 – – ns
WE# LOW to address transition tAH tWLAX 45 – – ns
OE# HIGH to WE# LOW – tGHWL 0 – – ns
WE# HIGH to OE# LOW tOEH tWHGL 0 – – ns
Program/erase valid to RY/BY# LOW tBUSY tWHRL – – 90 ns 2
WE# HIGH to OE# valid – tWHQV tAVQV
+ 30
– – ns
VHH rise or fall time on VPP/WP# – tVHVPP 250 – – ns
Notes: 1. The user's write timing must comply with this specification. Any violation of this write
timing specification may result in permanent damage to the NOR Flash device.
2. Sampled only; not 100% tested.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Write AC Characteristics
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Figure 23: WE#-Controlled Program AC Timing (8-Bit Mode)
AAAh PA PA
3rd Cycle 4th Cycle READ CycleData Polling
tWC tWC
tAS
tWP
tDS
tWHWH1 tDF
tWPH
tAH
tCE
tCS
tGHWL tOE
tDH
tOH
tCH
A[MAX:0]/A-1
CE#
OE#
WE#
DQ[7:0] A0h PD DQ7# DOUT DOUT
Notes: 1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-
GRAM command is followed by checking of the data polling register bit and by a READ
operation that outputs the data (DOUT) programmed by the previous PROGRAM com-
mand.
2. PA is the address of the memory location to be programmed. PD is the data to be pro-
grammed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit
[DQ7]).
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
5. For tWHWH1 timing details, see the Program/Erase Characteristics table.
256Mb: x8/x16, 3V, MT28EW Embedded Parallel NOR
Write AC Characteristics
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Figure 24: WE#-Controlled Program AC Timing (16-Bit Mode)
555h PA PA
3rd Cycle 4th Cycle READ CycleData Polling
tWC tWC
tAS
tWP
tDS
tDF
tWHWH1
tWPH
tAH
tCE
tCS
tGHWL tOE
tDH
tOH
tCH
A[MAX:0]
CE#
OE#
WE#
DQ[15:0] A0h PD DQ7# DOUT DOUT
Notes: 1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-
GRAM command is followed by checking of the data polling register bit and by a READ
operation that outputs the data (DOUT) programmed by the previous PROGRAM com-
mand.
2. PA is the address of the memory location to be programmed. PD is the data to be pro-
grammed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit
[DQ7]).
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
5. For tWHWH1 timing details, see the Program/Erase Characteristics table.
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Write AC Characteristics
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Table 33: CE#-Controlled Write AC Characteristics
Parameter
Symbol
Min Typ Max Unit NotesLegacy JEDEC
WRITE cycle time tWC – 60 – – ns
WE# LOW to CE# LOW tWS tWLEL 0 – – ns
CE# LOW to CE# HIGH tCP tELEH 35 – – ns
Input valid to CE# HIGH tDS tDVEH 30 – – ns 1
CE# HIGH to input transition tDH tEHDX 0 – – ns
CE# HIGH to WE# HIGH tWH tEHWH 0 – – ns
CE# HIGH to CE# LOW tCPH tEHEL 20 – – ns
Address valid to CE# LOW tAS tAVEL 0 – – ns
CE# LOW to address transition tAH tELAX 45 – – ns
OE# HIGH to CE# LOW – tGHEL 0 – – ns
VHH rise or fall time on VPP/WP# – tVHVPP 250 – – ns
Program/erase valid to RY/BY# LOW tBUSY tWHRL – – 90 ns 2
WE# HIGH to OE# valid – tWHQV tAVQV +
30
– – ns
Notes: 1. The user's write timing must comply with this specification. Any violation of this write
timing specification may result in permanent damage to the NOR Flash device.
2. Sampled only; not 100% tested.
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Write AC Characteristics
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Figure 25: CE#-Controlled Program AC Timing (8-Bit Mode)
AAAh PA PA
3rd Cycle 4th Cycle Data Polling
tWC
tAS
tCP
tDS
tWHWH1
tCPH
tAH
tWS
tGHEL
tDH
tWH
A[MAX:0]/A-1
WE#
OE#
CE#
DQ[7:0] A0h PD DQ7# DOUT
Notes: 1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-
GRAM command is followed by checking of the data polling register bit.
2. PA is the address of the memory location to be programmed. PD is the data to be pro-
grammed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit
[DQ7]).
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
5. For tWHWH1 timing details, see the Program/Erase Characteristics table.
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Write AC Characteristics
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Figure 26: CE#-Controlled Program AC Timing (16-Bit Mode)
555h PA PA
3rd Cycle 4th Cycle Data Polling
tWC
tAS
tCP
tDS
tWHWH1
tCPH
tAH
tWS
tGHEL
tDH
tWH
A[MAX:0]
WE#
OE#
CE#
DQ[15:0] A0h PD DQ7# DOUT
Notes: 1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-
GRAM command is followed by checking of the data polling register bit.
2. PA is the address of the memory location to be programmed. PD is the data to be pro-
grammed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit
[DQ7]).
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
5. For tWHWH1 timing details, see the Program/Erase Characteristics table.
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Write AC Characteristics
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Figure 27: Chip/Block Erase AC Timing (16-Bit Mode)
555h
tWC
tAS
tWP
tDS
tWPH
tAH
tCS
tGHWL
tDH
tCH
A[MAX:0]
CE#
OE#
WE#
DQ[15:0] AAh
2AAh 555h 555h
BAh1
2AAh555h
55h 55hAAh80h 10h/
30h
Notes: 1. For a CHIP ERASE command, the address is 555h, and the data is 10h; for a BLOCK ERASE
command, the address is BAd, and the data is 30h.
2. BAd is the block address.
3. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
4. For tWHWH1 timing details, see the Program/Erase Characteristics table.
Figure 28: Accelerated Program AC Timing
tVHVPP
tVHVPP
VHH
VIL or VIH
VPP/WP#
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Write AC Characteristics
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Data Polling/Toggle AC Characteristics
Table 34: Data Polling/Toggle AC Characteristics
Note 1 applies to entire table
Parameter
Symbol
Min Max UnitLegacy JEDEC
Address setup time to CE# or OE# LOW tASO tAXGL 15 – ns
Address hold time from OE# or CE# HIGH tAHT tGHAX, tEHAX 0 – ns
CE# HIGH time tEPH tEHEL2 20 – ns
OE# HIGH time tOPH tGHGL2 20 – ns
WE# HIGH to OE# LOW (toggle and data polling) tOEH tWHGL2 10 – ns
Note: 1. Sampled only; not 100% tested.
Figure 29: Data Polling AC Timing
DQ7#Data DQ7# Valid DQ7
Data
Output flagData Output flag
Valid
DQ[6:0] Data
tHZ/tDF
tCE
tOE tOPH
tCH
tBUSY
tOEH
CE#
OE#
WE#
DQ[6:0]
DQ7
RY/BY#
Notes: 1. DQ7 returns a valid data bit when the PROGRAM or ERASE command has completed.
2. See the following tables for timing details: Read AC Characteristics and Data Polling/
Toggle AC Characteristics.
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Data Polling/Toggle AC Characteristics
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Figure 30: Toggle/Alternative Toggle Bit Polling AC Timing
Toggle Toggle ToggleData
Stop
toggling
Output
Valid
tBUSY
tOPH tEPH
tOEH
CE#
WE#
OE#
DQ6/DQ2
RY/BY#
tOPH
tAHT tASO
tAHT
tDH
tASO
A[MAX:0]/
A–1
tOE tCE
Notes: 1. DQ6 stops toggling when the PROGRAM or ERASE command has completed. DQ2 stops
toggling when the CHIP ERASE or BLOCK ERASE command has completed.
2. See the following tables for timing details: Read AC Characteristics and Data Polling/
Toggle AC Characteristics.
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Data Polling/Toggle AC Characteristics
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Program/Erase Characteristics
Table 35: Program/Erase Characteristics
Notes 1 and 2 apply to entire table
Parameter
Buffer
Size Byte Word Min Typ Max Unit Notes
Erase
Block erase (128KB) – – – – 0.2 1.1 s –
Chip erase (256Mb) – – – – 52 – s –
Erase suspend latency time – – – – – 20 µs –
Block erase timeout – – – – – 50 µs –
Erase or erase resume to suspend – – – – 100 – µs 3, 4
Accelerated chip erase – – – – 47 – s –
Program
Single-byte/single-word program – – – – 25 200 µs –
Buffer Program (Byte mode)
Byte write to buffer program (tWHWH1) 64 64 – – 92 460 µs –
128 128 – – 117 600 µs –
256 256 – – 171 900 µs –
Effective write to buffer program per byte
(tWHWH1)
64 1 – – 1.44 7.19 µs –
128 1 – – 0.91 4.69 µs –
256 1 – – 0.67 3.52 µs –
Buffer Program (Word mode)
Word write to buffer program (tWHWH1) 32 – 32 – 92 460 µs –
64 – 64 – 117 600 µs –
128 – 128 – 171 900 µs –
256 – 256 – 285 1500 µs –
512 – 512 – 512 2000 µs –
Effective write to buffer program per word
(tWHWH1)
32 – 1 – 2.88 14.38 µs –
64 – 1 – 1.83 9.38 µs –
128 – 1 – 1.34 7.03 µs –
256 – 1 – 1.11 5.86 µs –
512 – 1 – 1.0 3.9 µs –
Accelerated full buffer program time – – – – 410 – µs –
Program suspend latency time – – – – – 15 µs –
Nonvolatile protection
Set nonvolatile protection bit time – – – – 25 200 µs –
Clear nonvolatile protection bit time – – – – 80 1100 ms –
Blank Check, CRC, and Program/Erase Endurance
Blank check: main block – – – – 3.2 – ms –
CRC check time: main block – – – – 5 – ms –
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Table 35: Program/Erase Characteristics (Continued)
Notes 1 and 2 apply to entire table
Parameter
Buffer
Size Byte Word Min Typ Max Unit Notes
CRC check time: full chip (256Mb) – – – – 2.5 – s –
PROGRAM/ERASE cycles (per block) – – – 100,000 – – cycles –
Notes: 1. Typical values measured at room temperature and nominal voltages(Vcc=3V).
2. Typical and maximum values are sampled, but not 100% tested.
3. Erase to suspend is the time between an initial BLOCK ERASE or ERASE RESUME com-
mand and a subsequent ERASE SUSPEND command.
4. This typical value allows an ERASE operation to progress to completion--it is important
to note that the algorithm might never finish if the ERASE operation is always suspen-
ded less than this specification.
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Program/Erase Characteristics
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Package Dimensions
Figure 31: 56-Pin TSOP – 14mm x 20mm (Package Code: JS)
Detail A
Seating plane
0.6 ±0.1
0.25 Gage plane
0.1 ±0.05
For reference
only
Pin A1 ID
0.1 A
See Detail A
56X 0.1 ±0.05
0.15 ±0.05
56X 0.22 ±0.05 14 ±0.1
18.4 ±0.1
20 ±0.2
1.1 ±0.1
0.5 TYP
16.2 CTR
11.8
CTR
2X Ø1.2
29
56
1
28
A
Notes: 1. All dimensions are in millimeters.
2. Pin A1 ID diameter is 1mm.
3. New package assembly site has effected an ASE process change (original ASE process is
Amkor). The package shows two eject pins on the package mark: one in the corner by
pin 56 and one in the corner by pin 28, each with diameter 2mm x 1.2mm.
4. Package width and length include mold flash.
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Package Dimensions
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Figure 32: 64-Ball LBGA – 11mm x 13mm (Package Code: PC)
0.44 MIN
1.3 ±0.1
7 CTR
11 ±0.1
1 TYP
13 ±0.1
1.0 TYP
Ball A1 ID
Seating plane
0.08 AA
64X Ø0.60
Dimensions apply
to solder balls post-
reflow on Ø0.50 SMD
ball pads.
7 CTR
A
B
C
D
E
F
G
H
234567 18
Note: 1. All dimensions are in millimeters.
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Package Dimensions
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Figure 33: 56-Ball VFBGA – 7mm x 9mm (Package Code: PN)
0.2 MIN
0.9 ±0.1
5.6 CTR
7 ±0.1
0.8 TYP
9 ±0.1
Ball A1 ID
Ball A1 ID
Seating plane
0.08 A
A
56X Ø0.375
Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.
5.6 CTR
0.8 TYP
A
B
C
D
E
F
G
H
12345678
Note: 1. All dimensions are in millimeters.
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Package Dimensions
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Revision History
Rev. G –05/18
• Added Important Notes and Warnings section for further clarification aligning to in-
dustry standards
Rev. F – 11/16
• Updated 56-pin dimension drawing
• Added Note 4 to 56-pin dimension drawing
Rev. E – 4/16
• Added 56-ball VFBGA 7mm x 9mm
Rev. D – 5/15
• Updated document status to Production
Rev. C – 4/15
• Updated block protection bit specification under Registers
• Clarified descriptions for tOH, tELFL, tELFH under Read AC Characteristics
Rev. B – 1/15
• Change status to Preliminary version.
Rev. A – 6/14
• Initial release
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000
www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
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Revision History
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