Data Sheet
27448.003F
A8285/A8287
LNB Supply and Control Voltage Regulator
Intended for analog and digital satellite receivers, the LNB (low noise
block) converter regulator is a monolithic linear and switching voltage
regulator, specifi cally designed to provide power and interface signals
to an LNB downconverter, via coaxial cable.
The device uses a 2-wire bidirectional serial interface, compatible with
the I2C (Inter-C bus) standard, that operates up to 400 kHz.
The A8285 is supplied in a 16-lead plastic power SOIC with internally
fused leads for thermal dissipation. The A8287 is supplied in a 24-lead
plastic power SOIC with internally fused leads. Both devices are also
available in lead (Pb) free versions, with 100% matte tine leadframe
plating.
LNB selection and standby function
Provides up to 500 mA load current
Two-wire serial I2C interface
Built-in tone oscillator, factory-trimmed to 22 kHz; facilitates
DiSEqC™ 2.0 encoding
Auxiliary modulation input
22 kHz tone detector facilitates DiSEqC™ decoding (A8287 only)
Tracking switch-mode power converter for lowest dissipation
LNB overcurrent protection and diagnostics
Internal overtemperature protection
LNB voltages (16 possible levels) compatible with all common
standards
Use the following complete part numbers when ordering:
AB SO LUTE MAX I MUM RAT INGS
8
ADD
4
GND
7EXTM
3IRQ
6
VIN
2
SDA
5
VREG
9 NC
13 GND
10 TCAP
14 LX
11 TOUT
15 BOOST
12 LNB
16 VCP
1
SCL
A8287SlB
SOIC
Part Number Pb-free Package Description
A8285SLB – 16-pin SOIC Tone detect not provided
A8285SLB-T Yes 16-pin SOIC Tone detect not provided
A8287SLB – 24-pin SOIC All features
A8287SLB-T Yes 24-pin SOIC All features
Load Supply Voltage, VIN....................................16 V
Output Current, IOUT ..................Internally Limited*
Output Voltage
LNB, BOOST .....................–0.3 V to 28 V
TOUT................................. –0.3 V to 22 V
Logic Input
EXTM ...................................–0.3 V to 5 V
Other .................................... –0.3 V to 7 V
Logic Output ........................................ –0.3 V to 7 V
Package Power Dissipation ………..See power dis si-
pation information in the Application Information section
Operating Temperature
Ambient, TA.......................–20°C to +85°C
Junction, TJ.......................–20°C to +150°C
Storage,T
S
.......................–55°C to +150°C
* Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specifi ed current
rating or a junction temperature of +150°C.
13 TDI
14 NC
TCAP15
16 TOUT
17 LNB
21 GND
18 GND
22 GND
19 GND
23 BOOS
T
20 LX
24 VCP
12
TDO
11
ADD 10
EXTM 9
VIN
8
V
REG
4
GND
7GND
3IRQ
6
GND
2
SDA
5
GND
1
SCL
A8285SlB
SOIC
FEATURES
Scale 1:1
Scale 1:1
2
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
Functional Block Diagram
22 kHz Tone
Detector
Internal
Regulator
Boost Converter
Charge
Pump
Clock
Divider
22 kHz
Tone
Generator
I C Interface
2Output
Voltage
Select
Fault Monitor
Overcurrent
TSD
Undervoltage
VREG
BOOST
Feedback
33 µH
33 µF
EXTM
VIN
SDA
SCL
ADD
IRQ
100 mV
VIN LX
100 nF
VCP BOOST
OSC In
DISABLE
100 nF
LNB
220 Ω
6.8 nF
33 µH
220 nF
1.5 µF
TCAP
TOUT
TDI
10 nF
VDD
TDO
VDD
OSC
Overcurrent
VPUMP
220 nF
Overcurrent
15 Ω
100 µF
100 nF
C10 C1 L1 D1 C5 C2 C4
C3
R3 R4 R5
R6
C9
R2
C8
D2
C6
C7
L2
R1
Tracking
Regulator
GM
ID Characteristics Suggested Manufacturer
C1 33 μF, 25 V, esr < 200 mΩ, Iripple > 350 mA Nichicon, part number UHC1E330MET
C2, C5,C10 100 nF, 50 V, X5R or X7R
C4 100 μF, 35 V, esr < 75 mΩ, Iripple> 800 mA Nichicon, part number UHC1V101MPT
C3,C6 220 nF, 50 V, X5R or X7R
C7 1.5 μF, 50 V, X5R or X7R
C8 6.8 nF, 50 V; Y5V, X5R, or X7R
C9 10 nF (maximum), 50 V; Y5V, X5R, or X7R
R1 15 Ω, 1%, c W
R2 220 Ω, 1%, 2 W
R3-R6 Value determined by VDD, bus capacitance. etc.
L1 33 μH, IDC > 1.3 A TDK, part number TSL0808-330K1R4
L2 33 μH, IDC > 0.5 A TDK, part number TSL0808-330K1R4
D1 1 A, 35 V or 40 V, Schottky diode Various, part number 1N5819; Sanken, part number AW04
D2 1 A, 100 V, 1N4002
Tone detector and leads TDI and TDO are not provided in 16-pin package (A8285).
3
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Set-point Accuracy, load and line
regulation VO1
Relative to target voltage selected, with:
ILOAD = 0 to 500 mA -4.5 0 4.5 %
Supply Current
ICC ENB = Low, LNB output disabled ––7mA
ICCEN ENB = High, LNB output enabled, ILOAD = 0mA ––
15 mA
Boost Switch-On Resistance RDSBOOST TJ = 25 °C, ILOAD = 500mA –400 500 mΩ
Switching Frequency fo –320 352 384 kHz
Switch Current Limit –VIN = 12 V 2.0 3 4.0 A
Linear Regulator Voltage Drop ΔVREG VBOOST – VLNB, no tone signal, ILOAD = 500 mA 400 600 800 mV
Slew Rate Current on TCAP ICAP Charging –12.5 –10 –7.5 μA
Discharging 7.5 10 12.5 μA
Output Voltage Slew Period tslew VLNB = 13 to 18 V, TCAP = 6.8 nF, ILOAD = 500 mA –500 –μs
Output Reverse Current IOR ENB = Low, VLNB = 28 V with C4 fully charged –15mA
Ripple and Noise on LNB Output VRN See notes 1 and 2 ––
50 mVpp
Protection Circuitry
Overcurrent Limit ILIM
High limit
Low limit
550
400
700
500
850
600
mA
mA
Overcurrent Disable Time tDIS –1.2 –1.7 ms
VIN Undervoltage Threshold UVOFF Guaranteed turn-off 8.65 9.15 9.65 V
VIN Turn-On Threshold UVON Guaranteed turn-on 8.75 9.25 9.75 V
Power-Not-Good Flag Set PNGset –77 85 93 %VLNB
Power-Not-Good Flag Reset PNGreset –82 90 98 %VLNB
Thermal Shutdown Threshold TJSee note 1 –165 –°C
Thermal Shutdown Hysteresis ΔTJSee note 1 –20 –°C
ELECTRICAL CHARACTERISTICS at TA = +25°C, VIN = 10 to 16 V (unless otherwise noted)
Continued on next page
4
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
ELECTRICAL CHARACTERISTICS (continued) at TA = +25°C, VIN = 10 to 16 V (unless otherwise noted)
Characteristics Symbol Test Conditions Min. Typ. Max. Units
Tone Characteristics
Tone Frequency fTONE – 20 22 24 kHz
Tone Pull-Down Current ITONE –304050mA
Tone Turn-On and Turn-Off Delays tDEL Using EXTM pin – – 1 μs
External Tone Logic Input VIH –2––V
VIL – – – 0.8 V
Input Leakage IIL ––1–1μA
Tone Detector Input Amplitude VTDI fIN = 22 kHz 260 – 1000 mV
Tone Detector Frequency Capture fTDI 600 mVpp sinewave 17.6 – 26.4 kHz
Tone Detector Input Impedance ZTDI See note 1 – 8.6 – kΩ
Tone Detector Output Voltage VOL Tone present, ILOAD = 3 mA – – 0.4 V
Tone Detector Output Leakage IOL Tone absent, VO = 7 V – – 10 μA
I2C Interface
Logic Input (SDA,SCL) Low Level VIL – – – 0.8 V
Logic Input (SDA,SCL) High Level VIH –2––V
Input Hysteresis VHYS – – 150 – mV
Logic Input Current IIN VIN = 0 V to 7 V –10 <±1.0 10 μA
Output Voltage (SDA, IRQ) VOL ILOAD = 3 mA – – 0.4 V
Output Leakage (SDA, IRQ) IOL VO = 0 V to 7 V – – 10 μA
SCL Clock Frequency fCLK – 0 – 400 kHz
Output Fall Time tOF VIH to VIL – – 250 ns
Bus Free Time Between Stop and Start tBUF See I2C Interface Timing Diagram 1.3 – – μs
Hold Time for Start Condition tHD:STA See I2C Interface Timing Diagram 0.6 – – μs
Setup Time for Start Condition tSU:STA See I2C Interface Timing Diagram 0.6 – – μs
SCL Low Time tLOW See I2C Interface Timing Diagram 1.3 – – μs
SCL High Time tHIGH See I2C Interface Timing Diagram 0.6 – – μs
Data Setup Time tSU:DAT See note1; I2C Interface Timing Diagram 100 – – ns
Data Hold Time tHD:DAT See I2C Interface Timing Diagram 0 – 900 ns
Setup Time for Stop Condition tSU:STO See I2C Interface Timing Diagram 0.6 – – μs
Continued on next page
5
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
I2C Address Setting
ADD Voltage for Address 0001,000 Address1 –0–0.7 V
ADD Voltage for Address 0001,001 Address2 –1.3 –1.7 V
ADD Voltage for Address 0001,010 Address3 –2.3 –2.7 V
ADD Voltage for Address 0001,011 Address4 –3.3 –5V
1 Guaranteed by design.
2 Use recommended components and adhere to layout guidelines.
ELECTRICAL CHARACTERISTICS (continued) at TA = +25°C, VIN = 10 to 16 V (unless otherwise noted)
Characteristics Symbol Test Conditions Min. Typ. Max. Units
t
SU:STA
t
HD:STA
t
SU:DAT
t
HD:DAT
t
BUF
t
SU:STO
t
HIGH
t
LOW
SDA
SCL
I2C Interface Timing Diagram
6
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
Boost Converter/Linear Regulator. A current-mode
boost converter provides the tracking regulator a supply
voltage that tracks the requested LNB output voltage. The
converter operates at 16 times the internal tone
frequency, 352 kHz nominal.
The tracking regulator provides minimum power dissipation
across the range of output voltages, assuming the input volt-
age is less than the output voltage, by adjusting the BOOST
pin voltage 600 mV nominal above the LNB output voltage
selected. Under conditions where the input voltage is greater
than the output voltage, the tracking regulator must drop the
differential voltage. When operating in this condition, care
must be taken to ensure that the safe operating temperature
range of the A8285/A8287 is not exceeded. For additional
information, see Power Dissipation in the Application Infor-
mation section.
Note: To conserve power at light loads, the boost converter
operates in a pulse-skipping mode.
Overcurrent Protection. The A8285/A8287 is protected
against both overcurrent and short circuit conditions by lim-
iting the output current to ILIM . In the event of an overcur-
rent, the current limit can be applied indefi nitely. Alterna-
tively, if the ODT feature is enabled, and the fault current
appears for longer than the disable time tDIS, then the device
is turned off. The device can be enabled again via the I2C
interface. If the overcurrent is removed before the disable
time has elapsed, the device remains functioning. These set-
tings are made in the Control register and the Status register.
Charge Pump. Generates a supply voltage above the
internal tracking regulator output to drive the linear regula-
tor control.
Slew Rate Control. During either start-up or when the
output voltage on the BOOST pin is being changed, the
output voltage rise and fall times can be programmed by an
external capacitor located on the TCAP pin. Note that during
start-up, the BOOST pin is precharged to the input voltage
minus a diode drop. As a result, the slew rate control occurs
from this point.
The value for TCAP can be calculated using the following
formula:
TCAP = (ICAP × 8) / (ΔV/s)
where ΔV/s is required slew rate. The smallest value for
TCAP is 2.2 nF.
Modulation is unaffected by the choice of TCAP. If limit-
ing LNB output voltage rise and fall times is not required,
the TCAP terminal must have a value of at least a 2.2 nF to
minimize output noise.
External Tone Modulation. To improve design fl exibil-
ity and to allow implementation of proposed LNB remote
control standards, the logic modulation input pin EXTM
is provided. The logic signal supplied to this pin creates a
650 mV ±250 mV tone signal on the TOUT pin by control-
ling a 40 mA current pull-down device through the
DiSEqC™ fi lter. The shape of the tone waveform depends
on the fi lter components used and the LNB/cable capacitance.
Tone Detection. A 22 kHz tone envelope detector is pro-
vided in the A8287 solution. The detector extracts the tone
signal and provides it as an open-collector signal on the TDO
pin. The maximum tone out error is ±1 tone cycle, and the maxi-
mum tone out delay with respect to the input is ±1 tone cycle.
Control Register. The main functions of the A8285/
A8287 are controlled via the I2C interface by writing to the
control register. The power-up states for the control func-
tions are all zero. Control functions include the following:
• Internal Tone Modulation Enable (ENT). When the
ENT bit is set to 1, the internal tone generator controls
a 40 mA pull-down device, thus creating the tone signal
after the DiSEqC™ fi lter in a way identical to the EXTM
scheme. The internal oscillator is factory-trimmed to
provide a tone of 22 ±2 kHz. No further adjustment is
required. Burst coding of the 22 kHz tone is accomplished
due to the fast response of the serial command and rapid
tone response. This allows implementation of the
DiSEqC™ 2.0 protocols.
• Select Output Voltage Amplitude (VSEL0, VSEL1,
VSEL2, VSEL3). The LNB output voltage can be pro-
grammed to a particular voltage according to the Output Volt-
age Amplitude Selection table shown on the following page.
• Enable (ENB). When set to 1, the LNB output is enabled.
When reset to 0, the LNB output is disabled.
• Overcurrent Limit (ILIM). Selects the output overcurrent
limit. When set to 0, the limit is 500 mA. When set to 1, the
limit is 700 mA.
• Overcurrent Disable Time (ODT). When set to 1, in the
event of an overcurrent occuring for a duration exceeding
the disable time, the device is turned off. When set to 0,
Functional Description
7
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
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A8285/A8287
LNB Supply and Control Voltage Regulator
this feature is disabled and the device is not turned off dur-
ing an overcurrent.
Status Register. The status of the A8285/A8287 read reg-
ister can be interrogated by the system master controller via
the I2C interface. Status functions include the following:
• Power Not Good (PNG). When the LNB output is enabled,
and the LNB output is below 85% of the programmed LNB
voltage, the PNG bit is set.
• Disable (DIS). Provides the status of the LNB output.
When set, this indicates that the output is disabled, either
intentionally or by a fault.
• Thermal Shutdown (TSD). When the junction tempera-
ture exceeds the maximum threshold, the thermal shutdown
bit is set, which disables the LNB output. DIS also is set.
• Overcurrent (OCP). This disables LNB output when an
overcurrent appears on the LNB output for a period greater
than the ODT (ODT must be enabled for this feature to take
effect). In addition, the DIS bit is set. Note: If an overcurrent
occurs and ODT is disabled, the A8285/A8287 will operate
in current limit indefi ninitely and the OCP bit will not be set.
• Undervoltage Lockout (VUV). When the input voltage
(VIN) drops below the undervoltage threshold, the undervolt-
age bit VUV is set, disabling the output.
When VIN is initially applied to the A8285/A8285, the VUV bit
is set, indicating that an undervoltage condition has occurred.
IRQ Flag. The IRQ fl ag is activated when any fault con-
dition occurs, including: thermal shutdown, overcurrent,
undervoltage, or the occurrence of a power-up sequence.
Note that the IRQ fl ag is not activated when either (a) the
channel is disabled (DIS), as it may have been disabled
intentionally by the master controller, or (b) if PNG is active,
as the A8285/A8287 may be starting up. Fault conditions are
stored in the status registers. Also note that the IRQ fl ag will
not activate when an overcurrent occurs and ODT is dis-
abled. In this condition, the device operates within ILIM.
When the IRQ fl ag is activated during either of the above
fault conditions, and the system master controller addresses
the A8285/A8287 with the read/write bit set to 1, then the
IRQ fl ag is reset once the A8285/A8287 acknowledges the
address. When the master controller reads the data and is
acknowledged, the status registers are updated. If the fault
is removed, the A8285/A8287 is again ready for operation
(being re-enabled via a write command). Otherwise, the
controller can keep polling the A8285/A8287 until the fault
is removed.
When VIN, is initially applied to the A8285/A8285, the I2C
interface will not function until the internal logic supply VREG
has reached its operating level. Once VREG is within toler-
ance, the VUV bit in the status register is set and the IRQ is
activated to inform the master controller of this condition.
(The IRQ is effectively acting as a power-up fl ag.) The IRQ
is reset when the A8285/A8287 acknowledges the address.
Once the master has read the status registers, the VUV bit is
reset. The device is then ready for operation.
I2C Interface. This is a serial interface that uses two bus
lines, SCL and SDA, to access the internal Control and
Status registers of the A8285/A8287. Data is exchanged
between a microcontroller (master) and the A8285/A8287
(slave). The clock input to SCL is generated by the master,
while SDA functions as either an input or an open drain
output, depending on the direction of the data.
VSEL3 VSEL2 VSEL1 VSEL0 LNB (V)
0 0 0 0 12.709
0 0 0 1 13.042
0 0 1 0 13.375
0 0 1 1 13.709
0 1 0 0 14.042
0 1 0 1 14.375
0 1 1 0 14.709
0 1 1 1 15.042
1 0 0 0 18.042
1 0 0 1 18.375
1 0 1 0 18.709
1 0 1 1 19.042
1 1 0 0 19.375
1 1 0 1 19.709
1 1 1 0 20.042
1 1 1 1 20.375
Output Voltage Amplitude Selection Table
8
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
Timing Considerations
The control sequence of the communication through the I2C
interface is composed of several steps in sequence:
1. Start Condition. Defi ned by a negative edge on the SDA
line, while SCL is high.
2. Address Cycle. 7 bits of address, plus 1 bit to indicate
read (1) or write (0), and an acknowledge bit. The fi rst
fi ve bits of the address are fi xed as: 00010. The four
optional addresses, defi ned by the remaining two bits, are
selected by the ADD input. The address is transmitted
MSB fi rst.
3. Data Cycles. 8 bits of data followed by an acknowledge
bit. Multiple data bytes can be read. Data is transmitted
MSB fi rst.
4. Stop Condition. Defi ned by a positive edge on the SDA
line, while SCL is high.
Except to indicate a Start or Stop condition, SDA must be
stable while the clock is high. SDA can only be changed
while SCL is low. It is possible for the Start or Stop condition
to occur at any time during a data transfer. The A8285/A8287
always responds by resetting the data transfer sequence.
The Read/Write bit is used to determine the data transfer
direction. If the Read/Write bit is high, the master reads one
or more bytes from the A8285/A8287. If the Read/Write bit
is low, the master writes one byte to the A8285/A8287. Note
that multiple writes are not permitted. All write operations
must be preceded with the address.
The Acknowledge bit has two functions. It is used by the
master to determine if the slave device is responding to its
address and data, and it is used by the slave when the master
is reading data back from the slave. When the A8285/A8287
decodes the 7-bit address fi eld as a valid address, it responds
by pulling SDA low during the ninth clock cycle.
During a data write from the master, the A8285/A8287 also
pulls SDA low during the clock cycle that follows the data
byte, in order to indicate that the data has been successfully
received. In both cases, the master device must release the
1 2 3 4 5 6 7 8 9
0 0 0 1 0 A1 A0 0 AK AKD6 D5 D4 D3 D2 D1 D0 D7
Control Data Address Start W Stop
SDA
SCL
acknowledge
from LNBR
acknowledge
from LNBR
0 0 0 1 0 A1 A0 1 AK D6 D5 D4 D3 D2 D1 D0 D7 NAK
Status Data Address Start R Stop
1 2 3 4 5 6 7 8 9
SDA
SCL
no acknowledge
from maste
r
acknowledge
from LNBR
0 0 0 1 0 A1 A0 1 AK D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 AK NAK
Status Data Address Start R StopStatus Data
1 2 3 4 5 6 7 8 9
SDA
SCL
acknowledge
from master
acknowledge
from LNBR
no acknowledge
from maste
r
Writing to the Register
Reading One Byte from the Register
Reading Multiple Bytes from the Register
Application Information
9
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
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A8285/A8287
LNB Supply and Control Voltage Regulator
SDA line before the ninth clock cycle, in order to allow this
handshaking to occur.
During a data read, the A8285/A8287 acknowledges the
address in the same way as in the data write sequence, and
then retains control of the SDA line and send the data to the
master. On completion of the eight data bits, the A8285/
A8287 releases the SDA line before the ninth clock cycle,
in order to allow the master to acknowledge the data. If the
master holds the SDA line low during this Acknowledge bit,
the A8285/A8287 responds by sending another data byte to
the master. Data bytes continue to be sent to the master until
the master releases the SDA line during the Acknowledge bit.
When this is detected, the A8285/A8287 stops sending data
and waits for a stop signal.
Interrupt Request. The A8285/A8287 also provides an
interrupt request pin IRQ, which is an open-drain, active-
low output. This output may be connected to a common
IRQ line with a suitable external pull-up and can be used
with other I2C devices to request attention from the master
controller. The IRQ output becomes active when either the
A8285/A8287 fi rst recognizes a fault condition, or at power-
on when the main supply VIN and the internal logic supply
VREG reach the correct operating conditions. It is only reset
to inactive when the I2C master addresses the A8285/A8287
with the Read/Write bit set (causing a read). Fault conditions
are indicated by the TSD, VUV, and OCP bits in the status
register (see description of OCP for conditions of use). The
DIS and PNG bits do not cause an interrupt. When the mas-
ter recognizes an interrupt, it addresses all slaves connected
to the interrupt line in sequence, and then reads the status
register to determine which device is requesting attention.
The A8285/A8287 latches all conditions in the status regis-
ter until the completion of the data read.
The action at the resampling point is further defi ned in the
description for each of the status bits. The bits in the status
register are defi ned such that the all-zero condition indicates
that the A8285/A8287 is fully active with no fault conditions.
When VIN is initially applied, the I2C interface does not
respond to any requests until the internal logic supply VREG
has reached its operating level. Once VREG has reached this
point, the IRQ output goes active, and the VUV bit is set.
After the A8285/A8287 acknowledges the address, the IRQ
fl ag is reset. Once the master reads the status registers, the
registers are updated with the VUV reset.
Control Register (I2C Write Register). All main func-
tions of the A8285/A8287 are controlled through the I2C
interface via the 8-bit Control register. This register allows
selection of the output voltage and current limit, enabling and
disabling the LNB output, and switching the 22 kHz tone on
and off. The power-up state is 0 for all of the control functions.
Bit 0 (VSEL0), Bit 1 (VSEL1), and Bit 2 (VSEL2). These
provide incremental control over the voltage on the LNB
output. The available voltages provide the necessary levels
for all the common standards plus the ability to add line
compensation in increments of 333 mV. The voltage levels
are defi ned in the Output Voltage Amplitude Selection table.
Bit 3 (VSEL3). Switches between the low-level and high-
level output voltages on the LNB output. A value of 0 selects
the low level voltage and a value of 1 selects the high level.
The low-level center voltage is 12.709 V nominal, and the
high level is 18.042 V nominal. These may be increased, in
increments of 333 mV, by using the VSEL2, VSEL1, and
VSEL0 control register bits.
Bit 4 (ODT). When set to 1, enables the ODT feature
(disables the A8285/A8287 if the overcurrent disable time
is exceeded during an overcurrent condition on the output).
When set to 0, the ODT feature is disabled.
0 0 0 1 0 A1 A0 1 AK D6 D5 D4 D3 D2 D1 D0 D7 NAK
Status Data Address Start R Stop
1 2 3 4 5 6 7 8 9
SDA
SCL
IRQ
Fault
Event
Reload
Status Register
Reading the Register After an Interrupt
10
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
Bit Name Function
0 VSEL0
See Output Voltage Amplitude
Selection Table
1 VSEL1
2 VSEL2
3 VSEL3 0: LNBx = Low range
1: LNBx = High range
4 ODT 0: Overcurrent disable time off
1: Overcurrent disable time on
5 ENB 0: Disable LNB Output
1: Enable LNB Output
6 ILIM 0: Overcurrent Limit = 500mA
1: Overcurrent Limit = 700mA
7 ENT 0: Disable Tone
1: Enable 22KHz internal tone
Bit 5 (ENB). When set to 1, enables the LNB output. When
set to 0, the LNB output is disabled.
Bit 6 (ILIM). Selects the ILIM level. When set to 0, the lower
limit (typically 500 mA) is selected. When set to 1, the
higher limit (typically 700 mA), is selected.
Bit 7 (ENT). When set to 1, enables modulation of the
LNB output with the the internal 22 kHz tone. Since the I2C
interface is compatible with the 400 kHz transfer speed, this
bit may be used to encode DiSEqC™ 2.0 tone bursts for
communication with the LNB or switcher at the far end of
the coaxial cable.
Status Register (I2C Read Register). The main fault
conditions: overcurrent, undervoltage, and overtemperature,
are all indicated by setting the relevant bit in the Status
register. In all fault cases, once the bit is set it is not reset
until the A8285/A8287 is read by the I2C master. The cur-
rent status of the LNB output is also indicated by DIS. DIS
and PNG are the only bits that may be reset without an I2C
read sequence. The normal sequence of the master in a fault
condition is to detect the fault by reading the Status register,
then rereading the Status register until the status bit is reset,
indicating the fault condition has been reset. The fault may
be detected by: continuously polling, responding to an inter-
rupt request (IRQ), or detecting a fault condition externally
and performing a diagnostic poll of all slave devices. Note
that the fully operational condition of the Status register is
all 0s. This simplifi es checking of the status byte.
Bit 0 (TSD). A 1 indicates that the A8285/A8287 has
detected an overtemperature condition and has disabled
the LNB output. DIS is set and the A8285/A8287 does not
re-enable the output until so instructed by writing the rel-
evant bit into the Control register. The status of the overtem-
perature condition is sampled on the rising edge of the ninth
clock pulse in the data read sequence. If the condition is no
longer present, then the TSD bit is reset, allowing the master
to re-enable the LNB output if required. If the condition is
still present, then the TSD bit remains at 1.
Bit 1 (OCP) Overcurrent. If the A8285/A8287 detects an
overcurrent condition for greater than the detection time, and
if ODT is enabled, the LNB output is then disabled. Also, the
OCP bit is set to indicate that an overcurrent has occurred,
and the DIS bit is set. The Status register is updated on the
rising edge of the ninth clock pulse. The OCP bit is reset in
all cases, allowing the master to re-enable the LNB output. If
the overcurrent timer is not enabled, the A8285/A8287 oper-
ates in current limit indefi nitely, and the OCP bit is not set.
Bit 2 and 3. Reserved.
Bit 4 (PNG) Power Not Good. Set to 1 when the LNB
output is enabled and the LNB output volts are below 85%
of the programmed LNB voltage. The PNG is reset when the
LNB volts are within 90% of the programmed LNB voltage.
Bit 5 (DIS) LNB output disabled. DIS is used to indicate
the current condition of the LNB output. At power-on, or if
a fault condition occurs, the disable bit is set. Having this bit
change to 1 does not cause the IRQ to activate because the
LNB output may be disabled intentionally by the I2C master.
This bit also is reset at the end of a write sequence, if the
LNB output is enabled.
Bit 6. Reserved.
Bit 7 (VUV) Undervoltage lockout. Set to 1 to indicate that
the A8285/A8287 has detected that the input supply VIN is, or
has been, below the minimum level and that an undervoltage
lockout has occurred, which has disabled the LNB output.
Bit 5 also is set, and the A8285/A8287 does not re-enable the
output until so instructed (by having the relevant bit written
into the Control register). The status of the undervoltage con-
dition is sampled on the rising edge of the ninth clock pulse
in the data read sequence. If the condition is no longer pres-
ent, the VUV bit is reset, allowing the master to re-enable the
LNB output if required. If the condition is still present, the
VUV bit remains set to 1.
Control (I2C Write) Register Table
11
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
Bit Name Function
0 TSD Thermal Shutdown
1 OCP Overcurrent
2 Reserved
3 Reserved
4 PNG Power Not Good
5 DIS LNB output disabled
6 Reserved
7 VUV VIN Undervoltage
Power Dissipation
To ensure that the device operates within the safe operating
temperature range, several checks should be performed. An
approximate operating junction temperature can be deter-
mined by estimating the power losses and the thermal imped-
ance characteristics of the printed circuit board solution. To
do so, perform the following procedure:
1. Estimate the maximum ambient temperature (TA).
2. Defi ne the maximum running junction temperature (TJ)of
A8285/A8287. Note that the absolute maximum junction
temperature should never exceed 150ºC.
3. Determine worst case power dissipation:
(a) Estimate the duty cycle D:
D = 1 – [VIN / (VOUT + VD + ΔVREG)]
where:
V
D is the voltage drop of the boost diode, and
ΔVREG can be taken from the specifi cation table.
(b) Estimate the peak current in boost stage IPK:
IPK = VOUT
× [ ILOAD / (0.89
× VIN)]
(c) Estimate boost RDS (RDSBOOST ) at maximum running junc-
tion temperature. RDSBOOST is a function of junction tempera-
ture and it rises by 2.7 mΩ/ºC with respect to the specifi ed
fi gure, RDSBOOST(25ºC), when Tj equals 25ºC.
Actual RDSBOOST = RDSBOOST(25ºC) + [(Tj – 25)
× 2.7 mΩ]
(d) Determine losses in each block PTOT; based on the relative
value of VIN, perform either (i) or (ii):
(i) When VIN < VOUT + VD + ΔVREG. Note that worst case dis-
sipation occurs at minimum input voltage.
PTOT = Pd_Rds + Pd_sw + Pd_control + Pd_lin
where
Pd_Rds = I2PK
× RDSBOOST
× D
Pd_control = 15 mA
× VIN
Pd_lin = ΔVREG
× ILOAD
and Pd_sw (switching losses estimate); worst case = 70 mW.
(ii) When VIN > VOUT + VD + ΔVREG. Note that worst case
dissipation in this case occurs at maximum input voltage.
PTOT = Pd_control + Pd_lin
where:
Pd_control = 15 mA
× V IN
Pd_lin = (VIN – VD – VOUT )
× I LOAD
Step 4. Determine the thermal impedance required in the
solution:
RØJA = (TJ – TA) / PTOT
The RØJA for one or two layer PCBs can be estimated from
the RØJA vs. Area charts on the following page.
Note: For maximum effectiveness, the PCB area underneath
the IC should be fi lled copper and connected to pins 4 and
13 for A8285, and pins 6, 7, 18, and 19 for A8287. Where
a PCB with two or more layers is used, apply thermal vias,
placing them adjacent to each of the above pins, and under-
neath the IC.
Status (I2C Read) Register Table
12
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
Example.
Given:
VIN = 12 V
VOUT = 18 V
ILOAD = 500 mA
Two-layer PCB.
Maximum ambient temperature = 70 ºC,
Maximum allowed junction temperature= 110 ºC
Assume:
VD= 0.4 V and select ΔVREG= 0.7 V
D = 1 – (12 / (18 + 0.4 + 0.7) = 0.37
IPK = 18
× 0.5 / (0.89
× 12) = 843 mA
RDSBOOST = 0.5 + (110 – 25)
× 2.7 mΩ= 730 mΩ
Worst case losses can now be estimated:
Pd_Rds = 0.8432
× 0.73
× 0.37 = 192 mW
Pd_sw = 70 mW
Pd_control = 15 mA
× VIN = 180 mW
Pd_lin = 0.7
× 0.5 = 350 mW
and therefore
PTOT = 0.192 + 0.07 + 0.18 + 0.35 = 0.792 W
The thermal resistance required is:
(110 – 70) / 0.792 = 50.5ºC/W
Note: For the case of the A8287, the area of copper required
on each layer is approximately 1.2 in2.
Layout Considerations
Recommended placement of critical components and track-
ing for the A8287 is shown in the PCB Layout digagram on
the following page. It is recommended that the ground plane
be separated into two areas, referred to as switcher and con-
trol, on each layer using a ground plane. With respect to the
input connections, VIN and 0V, the two ground plane areas
are isolated as shown by the dotted line and the ground plane
areas are connected together at pins 6, 7, 18, and 19. This
confi guration minimizes the effects of the noise produced by
the switcher on the noise-sensitive sections of the circuit.
Power-related tracking from INPUT to L1, LNB (pin 17) to
L2 then OUTPUT, LX (pin 20) to D1 and L1, VBOOST (pin
23) to C4 and D1 should be as short and wide as possible.
Power components such as the boost diode D1, inductor
L1, and input/output capacitors C1, C9, and C4, should be
located as close as possible to the IC. The DiSEqC inductor
L2 should be located as far away from the boost inductor L1
to prevent potential magnetic crosstalk.
The fi lter capacitor (VREG), charge pump capacitor (VCP),
ac coupling tone detect capacitor (TDI), tone pull-down
resistor (TOUT), and LNB output capacitor/protection diode
(LNB) should be located directly next to the appropriate pin.
Where a PCB with two or more layers is used, it is recom-
mended that four thermal vias be deployed as shown in the
PCB Layout diagram. Note that adding additional vias does
not enhance the thermal characteristics.
40
50
60
70
80
90
100
01234
Area (in
2
)
Thermal Resistance (
0
C/W)
One side Copper
Two side Copper
40
50
60
70
80
01234
Area (in
2
)
Thermal Resistance (
0
C/W)
One side Copper
Two side Copper
RØJA vs. Area Charts
A8285, 16-Pin SOIC A8287, 24-Pin SOIC
Thermal Resistance
(ºC /W)
Thermal Resistance
(ºC /W)
Area (in.2)Area (in.2)
13
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
Note that to add additional connec-
tions, e.g. SCL, SDA, IRQ, VIN,
EXTM, ADD, TDO, and TDI,
some modifi cations to the control
ground plane will be necessary.
Refer to Functional Block diagram
for circuit connections.
PCB Layout Diagram
Power-on Reset I2C Sequence
ADR READ A AR
S
T
S
PADR WRITE A AW
S
T
S
P
Master Responds to IRQ
Reads Status
VUV = 1
Master Writes
Enables output
SDA
IRQ
VUV
reset
V
REG
V
IN
READ N
VUV = 0
OUTPUT
Thermal Via
Cut in 0 V Plane
++
C1
C5
C2
C8
C7
C6
C4
L1
L2
R1
+
D1
+
D2
13
15
14
18
17
16
22
21
20
19
24
23
VIN
(INPUT)
Tracking
0V Pla ne
C3
Control 0V
Control 0V
Control 0V
Switch er 0V
1
12
4
3
2
7
6
5
10
9
8
11
C9
0V
0V
14
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
Response to Overtemperature fault condition using multiple byte read
Overtemperature and Overcurrent I2C Sequences
Response to Overcurrent fault condition using single byte read
ADR READ A N R
S
T
S
P
ADR READ A N R
S
T
S
P ADR WRITE A A W
S
T
S
P
Master Responds to IRQ
Reads Status
OCP = 1
DIS = 1
Master Polls
Reads Status
OCP = 0
DIS = 0
Master Writes
Re-enables LNB
output
SDA
IRQ
OCP
reset
I
LNB
V
LNB
LNB
ou
t
pu
t
di
sa
bl
e
d
LNB output enable
d
ADR READ A A R
S
T
S
P ADR WRITE A A W
S
T
S
P
Master Responds to IRQ
Reads Status continuously
TSD = 1
DIS = 1
Master Writes
Re-enables LNB
output
READ A READ A READ A READ N
TSD
reset
TSD = 0
DIS = 1
SDA
IRQ
TJMAX
T
JMAX
-ΔT
J
TJ LNB ouput enabled
LNB Output Disabled
Overtemperature
15
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
Pin Name Pin Description A8287SLB
SOIC-24 A8285SLB
SOIC-16
SCL I2C Clock Input 1 1
SDA I2C Data Input/Output 2 2
IRQ Interrupt Request 3 3
GND Ground 4,5,6,7 4
VREG Analog Supply 8 5
VIN Supply Input Voltage 9 6
EXTM External Modulation Input 10 7
ADD Address Select 11 8
TDO Tone Detect Out 12 -
TDI Tone Detect Input 13 -
NC No Connection 14 9
TCAP Capacitor for setting the rise and fall time of the LNB output 15 10
TOUT Tone Generation 16 11
LNB Output voltage to LNB 17 12
GND Ground 18,19 13
LX Inductor drive point 20 14
GND Ground 21,22 -
BOOST Tracking supply voltage to linear regulator 23 15
VCP Gate supply voltage 24 16
Terminal List Table
16
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
A8285SLB 16-Pin Batwing SOIC
NOTES:
1. Exact body and lead confi guration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 49 devices or add “TR” to part number for tape and reel.
.606
.598
15.39
15.19
.299
.291
7.59
7.39
.414
.398
10.52
10.11
.020
.014
0.51
0.36
.026
REF
0.66
.050
BSC
1.27
.012
.004
0.30
0.10
.104
.096
2.64
2.44
.040
.020
1.02
0.51
.011
.009
0.28
0.23
8º
0º
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
2176
24 19 18
A8287SLB 24-Pin Batwing SOIC
.406
.398
10.31
10.11
.299
.291
7.59
7.39
.414
.398
10.52
10.11
.020
.014
0.51
0.36
.026
REF
0.66
.050
BSC
1.27
.012
.004
0.30
0.10
.104
.096
2.64
2.44
.040
.020
1.02
0.51
.011
.009
0.28
0.23
8º
0º
Dimensions in inches
Metric dimensions (mm) in brackets, for reference only
21
16
Leads 4 and 13 are connected inside the device package.
Leads 6, 7, 18 and 19 are connected intside the device package.
17
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
A8285/A8287
LNB Supply and Control Voltage Regulator
The products described here are manufactured under one or
more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time
to time, such de par tures from the detail spec i fi ca tions as may be
required to permit improvements in the per for mance, reliability,
or manufacturability of its products. Before placing an order, the
user is cautioned to verify that the information being relied upon is
current.
Allegro products are not authorized for use as critical compo-
nents in life-support devices or sys tems without express written
approval.
The in for ma tion in clud ed herein is believed to be ac cu rate and
reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon -
si bil i ty for its use; nor for any in fringe ment of patents or other
rights of third parties which may result from its use.
Purchase of I2C components of Allegro MicroSystems or one of its
sublicensed Associated Companies, conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system,
provided that the system conforms to the I2C Standard Specifi cation
as defi ned by Philips.
DiSEqC™ is a registered trademark of Eutelsat S.A.
Copyright©2003 Allegr oMicrosystems, Inc.
