To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. R8C/1A Group, R8C/1B Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. REJ03B0144-0140 Rev.1.40 Dec 08, 2006 Overview These MCUs are fabricated using the high-performance silicon gate CMOS process, embedding the R8C/ Tiny Series CPU core, and is packaged in a 20-pin molded-plastic LSSOP, SDIP or a 28-pin plastic moldedHWQFN. It implements sophisticated instructions for a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed. Furthermore, the R8C/1B Group has on-chip data flash ROM (1 KB x 2 blocks). The difference between the R8C/1A Group and R8C/1B Group is only the presence or absence of data flash ROM. Their peripheral functions are the same. 1.1 Applications Electric household appliances, office equipment, housing equipment (sensors, security systems), portable equipment, general industrial equipment, audio equipment, etc. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 1 of 45 R8C/1A Group, R8C/1B Group 1.2 1. Overview Performance Overview Table 1.1 outlines the Functions and Specifications for R8C/1A Group and Table 1.2 outlines the Functions and Specifications for R8C/1B Group. Table 1.1 CPU Functions and Specifications for R8C/1A Group Item Number of fundamental instructions Minimum instruction execution time Operating mode Address space Memory capacity Ports Specification 89 instructions 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) Single-chip 1 Mbyte See Table 1.3 Product Information for R8C/1A Group Peripheral I/O ports: 13 pins (including LED drive port) Functions Input port: 3 pins LED drive ports I/O ports: 4 pins Timers Timer X: 8 bits x 1 channel, timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel (Input capture and output compare circuits) Serial interfaces 1 channel Clock synchronous serial I/O, UART 1 channel UART Clock synchronous serial interface 1 channel I2C bus Interface(1) Clock synchronous serial I/O with chip select (SSU) A/D converter 10-bit A/D converter: 1 circuit, 4 channels Watchdog timer 15 bits x 1 channel (with prescaler) Reset start selectable, count source protection mode Internal: 11 sources, External: 4 sources, Software: 4 sources, Interrupts Priority levels: 7 levels Clock generation circuits 2 circuits * Main clock oscillation circuit (with on-chip feedback resistor) * On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has a frequency adjustment function Oscillation stop detection function Main clock oscillation stop detection function Voltage detection circuit On-chip Power-on reset circuit On-chip Electric Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) Characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) Current consumption Typ. 9 mA (VCC = 5.0 V, f(XIN) = 20 MHz, A/D converter stopped) Typ. 5 mA (VCC = 3.0 V, f(XIN) = 10 MHz, A/D converter stopped) Typ. 35 A (VCC = 3.0 V, wait mode, peripheral clock off) Typ. 0.7 A (VCC = 3.0 V, stop mode) Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V Programming and erasure 100 times endurance Operating Ambient Temperature -20 to 85C -40 to 85C (D version) -20 to 105C (Y version) (2) Package 20-pin molded-plastic LSSOP 20-pin molded-plastic SDIP 28-pin molded-plastic HWQFN NOTE: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Please contact Renesas Technology sales offices for the Y version. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 2 of 45 R8C/1A Group, R8C/1B Group Table 1.2 CPU 1. Overview Functions and Specifications for R8C/1B Group Item Number of fundamental instructions Minimum instruction execution time Operating mode Address space Memory capacity Ports Specification 89 instructions 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V) 100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V) Single-chip 1 Mbyte See Table 1.4 Product Information for R8C/1B Group Peripheral I/O ports: 13 pins (including LED drive port) Functions Input port: 3 pins LED drive ports I/O ports: 4 pins Timers Timer X: 8 bits x 1 channel, timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel (Input capture and output compare circuits) Serial interfaces 1 channel Clock synchronous serial I/O, UART 1 channel UART Clock synchronous serial interface 1 channel I2C bus Interface(1) Clock synchronous serial I/O with chip select (SSU) A/D converter 10-bit A/D converter: 1 circuit, 4 channels Watchdog timer 15 bits x 1 channel (with prescaler) Reset start selectable, count source protection mode Internal: 11 sources, External: 4 sources, Software: 4 sources, Interrupts Priority levels: 7 levels Clock generation circuits 2 circuits * Main clock generation circuit (with on-chip feedback resistor) * On-chip oscillator (high speed, low speed) High-speed on-chip oscillator has a frequency adjustment function Oscillation stop detection function Main clock oscillation stop detection function Voltage detection circuit On-chip Power on reset circuit On-chip Electric Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz) Characteristics VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz) Current consumption Typ. 9 mA (VCC = 5.0 V, f(XIN) = 20 MHz, A/D converter stopped) Typ. 5 mA (VCC = 3.0 V, f(XIN) = 10 MHz, A/D converter stopped) Typ. 35 A (VCC = 3.0 V, wait mode, peripheral clock off) Typ. 0.7 A (VCC = 3.0 V, stop mode) Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 V Programming and erasure 10,000 times (data flash) endurance 1,000 times (program ROM) Operating Ambient Temperature -20 to 85C -40 to 85C (D version) -20 to 105C (Y version) (2) Package 20-pin molded-plastic LSSOP 20-pin molded-plastic SDIP 28-pin molded-plastic HWQFN NOTE: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. 2. Please contact Renesas Technology sales offices for the Y version. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 3 of 45 R8C/1A Group, R8C/1B Group 1.3 1. Overview Block Diagram Figure 1.1 shows a Block Diagram. I/O ports 8 4 Port P1 Port P3 1 3 Port P4 Peripheral Functions Timers A/D converter (10 bits x 4 channels) Timer X (8 bits) Timer Z (8 bits) Timer C (16 bits) UART or clock synchronous serial I/O (8 bits x 1 channel) System clock generator XIN-XOUT High-speed on-chip oscillator Low-speed on-chip oscillator SSU (8 bits x 1 channel) or I2C bus UART (8 bits x 1 channel) Watchdog timer (15 bits) R8C/Tiny Series CPU core R0H R1H R0L R1L R2 R3 SB ROM(1) USP ISP INTB A0 A1 FB Memory RAM(2) PC FLG Multiplier NOTES: 1. ROM size varies with MCU type. 2. RAM size varies with MCU type. Figure 1.1 Block Diagram Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 4 of 45 R8C/1A Group, R8C/1B Group 1.4 1. Overview Product Information Table 1.3 lists Product Information for R8C/1A Group and Table 1.4 lists Product Information for R8C/1B Group. Table 1.3 Product Information for R8C/1A Group Type No. R5F211A1SP R5F211A2SP R5F211A3SP R5F211A4SP R5F211A1DSP R5F211A2DSP R5F211A3DSP R5F211A4DSP R5F211A1DD R5F211A2DD R5F211A3DD R5F211A4DD R5F211A2NP R5F211A3NP R5F211A4NP R5F211A1XXXSP ROM Capacity 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 4 Kbytes RAM Capacity 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 512 bytes 768 bytes 1 Kbyte 384 bytes R5F211A2XXXSP R5F211A3XXXSP R5F211A4XXXSP R5F211A1DXXXSP R5F211A2DXXXSP R5F211A3DXXXSP R5F211A4DXXXSP R5F211A1XXXDD R5F211A2XXXDD R5F211A3XXXDD R5F211A4XXXDD R5F211A2XXXNP R5F211A3XXXNP R5F211A4XXXNP 8 Kbytes 12 Kbytes 16 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 512 bytes 768 bytes 1 Kbyte Package Type Remarks PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A D version PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PRDP0020BA-A PRDP0020BA-A PRDP0020BA-A PRDP0020BA-A PWQN0028KA-B PWQN0028KA-B PWQN0028KA-B PLSP0020JB-A Factory programming product (1) PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A D version PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PRDP0020BA-A Factory programming product (1) PRDP0020BA-A PRDP0020BA-A PRDP0020BA-A PWQN0028KA-B PWQN0028KA-B PWQN0028KA-B NOTE: 1. The user ROM is programmed before shipment. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 5 of 45 Current of October 2006 R8C/1A Group, R8C/1B Group Type No. 1. Overview R 5 F 21 1A 4 D XXX SP Package type: SP: PLSP0020JB-A DD: PRDP0020BA-A NP: PWQN0028KA-B ROM number Classification D: Operating ambient temperature -40C to 85C No Symbol: Operating ambient temperature -20C to 85C Y: Operating ambient temperature -20C to 105C (Note) ROM capacity 1: 4 KB 2: 8 KB 3: 12 KB 4: 16 KB R8C/1A Group R8C/Tiny Series Memory type F: Flash memory version Renesas MCU Renesas semiconductors NOTE: Please contact Renesas Technology sales offices for the Y version. Figure 1.2 Type Number, Memory Size, and Package of R8C/1A Group Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 6 of 45 R8C/1A Group, R8C/1B Group Table 1.4 1. Overview Product Information for R8C/1B Group Type No. R5F211B1SP R5F211B2SP R5F211B3SP R5F211B4SP R5F211B1DSP R5F211B2DSP R5F211B3DSP R5F211B4DSP R5F211B1DD R5F211B2DD R5F211B3DD R5F211B4DD R5F211B2NP R5F211B3NP R5F211B4NP R5F211B1XXXSP R5F211B2XXXSP R5F211B3XXXSP R5F211B4XXXSP R5F211B1DXXXSP R5F211B2DXXXSP R5F211B3DXXXSP R5F211B4DXXXSP R5F211B1XXXDD R5F211B2XXXDD R5F211B3XXXDD R5F211B4XXXDD R5F211B2XXXNP R5F211B3XXXNP R5F211B4XXXNP ROM Capacity Program ROM Data Flash 4 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 4 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 4 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 4 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 4 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 4 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 RAM Capacity 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 384 bytes 512 bytes 768 bytes 1 Kbyte 512 bytes 768 bytes 1 Kbyte NOTE: 1. The user ROM is programmed before shipment. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 7 of 45 Current of October 2006 Package Type PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PRDP0020BA-A PRDP0020BA-A PRDP0020BA-A PRDP0020BA-A PWQN0028KA-B PWQN0028KA-B PWQN0028KA-B PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PRDP0020BA-A PRDP0020BA-A PRDP0020BA-A PRDP0020BA-A PWQN0028KA-B PWQN0028KA-B PWQN0028KA-B Remarks D version Factory programming product (1) D version Factory programming product (1) R8C/1A Group, R8C/1B Group Type No. 1. Overview R 5 F 21 1B 4 D XXX SP Package type: SP: PLSP0020JB-A DD: PRDP0020BA-A NP: PWQN0028KA-B ROM number Classification D: Operating ambient temperature -40C to 85C No Symbol: Operating ambient temperature -20C to 85C Y: Operating ambient temperature -20C to 105C (Note) ROM capacity 1: 4 KB 2: 8 KB 3: 12 KB 4: 16 KB R8C/1B Group R8C/Tiny Series Memory Type F: Flash memory version Renesas MCU Renesas semiconductors NOTE: Please contact Renesas Technology sales offices for the Y version. Figure 1.3 Type Number, Memory Size, and Package of R8C/1B Group Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 8 of 45 R8C/1A Group, R8C/1B Group 1.5 1. Overview Pin Assignments Figure 1.4 shows Pin Assignments for PLSP0020JB-A Package (Top View), Figure 1.5 shows Pin Assignments for PRDP0020BA-A Package (Top View) and Figure 1.6 shows Pin Assignments for PWQN0028KA-B Package (Top View). PIN assignments (top view) 1 20 P3_4/SCS/SDA/CMP1_1 P3_7/CNTR0/SSO/TXD1 2 19 P3_3/TCIN/INT3/SSI00/CMP1_0 RESET 3 18 P1_0/KI0/AN8/CMP0_0 XOUT/P4_7(1) 4 17 P1_1/KI1/AN9/CMP0_1 VSS/AVSS 5 16 P4_2/VREF XIN/P4_6 6 15 P1_2/KI2/AN10/CMP0_2 VCC/AVCC 7 14 P1_3/KI3/AN11/TZOUT MODE 8 13 P1_4/TXD0 P4_5/INT0/RXD1 9 12 P1_5/RXD0/CNTR01/INT11 10 11 P1_6/CLK0/SSI01 P1_7/CNTR00/INT10 R8C/1A Group R8C/1B Group P3_5/SSCK/SCL/CMP1_2 NOTE: 1. P4_7 is an input-only port. Package: PLSP0020JB-A (20P2F-A) Figure 1.4 Pin Assignments for PLSP0020JB-A Package (Top View) Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 9 of 45 R8C/1A Group, R8C/1B Group 1. Overview PIN assignments (top view) 1 20 P3_4/SCS/SDA/CMP1_1 P3_7/CNTR0/SSO/TXD1 2 19 P3_3/TCIN/INT3/SSI00/CMP1_0 RESET 3 18 P1_0/KI0/AN8/CMP0_0 XOUT/P4_7(1) 4 17 P1_1/KI1/AN9/CMP0_1 VSS/AVSS 5 16 P4_2/VREF XIN/P4_6 6 15 P1_2/KI2/AN10/CMP0_2 VCC/AVCC 7 14 P1_3/KI3/AN11/TZOUT MODE 8 13 P1_4/TXD0 P4_5/INT0/RXD1 9 12 P1_5/RXD0/CNTR01/INT11 10 11 P1_6/CLK0/SSI01 P1_7/CNTR00/INT10 R8C/1A Group R8C/1B Group P3_5/SSCK/SCL/CMP1_2 NOTE: 1. P4_7 is an input-only port. Package: PRDP0020BA-A (20P4B) Figure 1.5 Pin Assignments for PRDP0020BA-A Package (Top View) Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 10 of 45 R8C/1A Group, R8C/1B Group 1. Overview NC P1_3/AN11/KI3/TZOUT P1_2/AN10/KI2/CMP0_2 NC NC P4_2/VREF NC PIN Assignment (top view) 21 20 19 18 17 16 15 P1_1/AN9/KI1/CMP0_1 22 14 P1_4/TXD0 P1_0/AN8/KI0/CMP0_0 23 13 P1_5/RXD0/CNTR01/INT11 P3_3/TCIN/INT3/SSI00/CMP1_0 24 12 P1_6/CLK0/SSI01 P3_4/SCS/SDA/CMP1_1 25 11 P1_7/CNTR00/INT10 P3_5/SSCK/SCL/CMP1_2 26 10 P4_5/INT0/RXD1 P3_7/CNTR0/SSO/TXD1 27 9 MODE RESET 28 8 VCC/AVCC R8C/1A Group R8C/1B Group 4 5 6 (1) VSS/AVSS NC NC XIN/P4_6 NC 3 XOUT/P4_7 2 NC 7 1 NOTES: 1. P4_7 is a port for the input. Package: PWQN0028KA-B(28PJW-B) Figure 1.6 Pin Assignments for PWQN0028KA-B Package (Top View) Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 11 of 45 R8C/1A Group, R8C/1B Group 1.6 1. Overview Pin Functions Table 1.5 lists Pin Functions, Table 1.6 lists Pin Name Information by Pin Number of PLSP0020JB-A, PRDP0020BA-A Packages and Table 1.7 lists Pin Name Information by Pin Number of PWQN0028KAB Package. Table 1.5 Pin Functions Type Symbol I/O Type Description Power Supply Input VCC, VSS I Apply 2.7 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin. Analog Power Supply Input AVCC, AVSS I Power supply for the A/D converter Connect a capacitor between AVCC and AVSS. Reset Input RESET I Input "L" on this pin resets the MCU. MODE MODE I Connect this pin to VCC via a resistor. Main Clock Input XIN I Main Clock Output XOUT O These pins are provided for main clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an external clock, input it to the XIN pin and leave the XOUT pin open. INT Interrupt INT0, INT1, INT3 I INT interrupt input pins Key Input Interrupt KI0 to KI3 I Key input interrupt input pins Timer X CNTR0 I/O Timer X I/O pin CNTR0 O Timer X output pin Timer Z TZOUT O Timer Z output pin Timer C TCIN I Timer C input pin CMP0_0 to CMP0_2, CMP1_0 to CMP1_2 O Timer C output pins CLK0 I/O Transfer clock I/O pin Serial Interface RXD0, RXD1 I Serial data input pins TXD0, TXD1 O Serial data output pins I/O Data I/O pin. I/O Chip-select signal I/O pin I/O Clock I/O pin SSO I/O Data I/O pin SCL I/O Clock I/O pin SDA I/O Data I/O pin Clock synchronous SSI00, SSI01 serial I/O with chip SCS select (SSU) SSCK I2C bus Interface Reference Voltage Input VREF I Reference voltage input pin to A/D converter A/D Converter AN8 to AN11 I Analog input pins to A/D converter I/O Port P1_0 to P1_7, P3_3 to P3_5, P3_7, P4_5 Input Port P4_2, P4_6, P4_7 I: Input O: Output Rev.1.40 Dec 08, 2006 REJ03B0144-0140 I/O I I/O: Input and output Page 12 of 45 CMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually. Any port set to input can be set to use a pull-up resistor or not by a program. P1_0 to P1_3 also function as LED drive ports. Input-only ports R8C/1A Group, R8C/1B Group Table 1.6 Pin Number Pin Name Information by Pin Number of PLSP0020JB-A, PRDP0020BA-A Packages Control Pin 1 2 3 4 5 6 7 8 9 1. Overview Port Interrupt P3_5 P3_7 RESET XOUT VSS/AVSS XIN VCC/AVCC MODE I/O Pin Functions for Peripheral Modules Clock Synchronous I2C bus Serial A/D Timer Interface Serial I/O with Interface Converter Chip Select CMP1_2 SSCK SCL TXD1 SSO CNTR0 P4_7 P4_6 P4_5 INT0 10 P1_7 INT10 CNTR00 11 12 P1_6 P1_5 INT11 CNTR01 13 14 P1_4 P1_3 KI3 TZOUT AN11 15 P1_2 KI2 CMP0_2 AN10 P4_2 P1_1 KI1 CMP0_1 AN9 18 P1_0 KI0 CMP0_0 AN8 19 P3_3 INT3 20 P3_4 TCIN/ CMP1_0 CMP1_1 16 17 VREF Rev.1.40 Dec 08, 2006 REJ03B0144-0140 RXD1 CLK0 RXD0 SSI01 TXD0 Page 13 of 45 SSI00 SCS SDA R8C/1A Group, R8C/1B Group Table 1.7 Pin Number 1 2 3 4 5 6 7 8 9 10 1. Overview Pin Name Information by Pin Number of PWQN0028KA-B Package Control Pin NC XOUT VSS/AVSS NC NC XIN NC VCC/AVCC MODE Port Interrupt I/O Pin Functions for Peripheral Modules Clock Serial Synchronous I2C bus A/D Timer Interface Serial I/O with Interface Converter Chip Select P4_7 P4_6 P4_5 INT0 11 P1_7 INT10 CNTR00 12 13 P1_6 P1_5 INT11 CNTR01 14 15 16 P1_4 RXD1 CLK0 RXD0 SSI01 TXD0 NC P1_3 KI3 TZOUT AN11 P1_2 KI2 CMP0_2 AN10 P1_1 KI1 CMP0_1 AN9 23 P1_0 KI0 CMP0_0 AN8 24 P3_3 INT3 TCIN/CMP1_0 SSI00 25 P3_4 CMP1_1 26 27 P3_5 P3_7 CMP1_2 SCS SSCK SSO 17 18 19 20 21 22 28 NC NC VREF NC P4_2 RESET Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 14 of 45 CNTR0 TXD1 SDA SCL R8C/1A Group, R8C/1B Group 2. 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank. b31 b15 R2 R3 b8b7 b0 R0H (high-order of R0) R0L (low-order of R0) R1H (high-order of R1) R1L (low-order of R1) Data registers (1) R2 R3 A0 A1 FB b19 b15 Address registers (1) Frame base register (1) b0 Interrupt table register INTBL INTBH The 4 high order bits of INTB are INTBH and the 16 low bits of INTB are INTBL. b19 b0 Program counter PC b15 b0 USP User stack pointer ISP Interrupt stack pointer SB Static base register b15 b0 FLG b15 b8 IPL b7 Flag register b0 U I O B S Z D C Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved bit Processor interrupt priority level Reserved bit NOTE: 1. These registers comprise a register bank. There are two register banks. Figure 2.1 CPU Register Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 15 of 45 R8C/1A Group, R8C/1B Group 2.1 2. Central Processing Unit (CPU) Data Registers (R0, R1, R2, and R3) R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32bit data register (R2R0). R3R1 is analogous to R2R0. 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer and arithmetic and logic operations. A1 is analogous to A0. A1 can be combined with A0 and used as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register that indicates the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is 20 bits wide indicates the address of the next instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointer (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register for SB relative addressing. 2.8 Flag Register (FLG) FLG is an 11-bit register indicating the CPU state. 2.8.1 Carry Flag (C) The C flag retains a carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit. 2.8.2 Debug Flag (D) The D flag is for debugging only. Set it to 0. 2.8.3 Zero Flag (Z) The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0. 2.8.4 Sign Flag (S) The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0. 2.8.5 Register Bank Select Flag (B) Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1. 2.8.6 Overflow Flag (O) The O flag is set to 1 when the operation results in an overflow; otherwise to 0. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 16 of 45 R8C/1A Group, R8C/1B Group 2.8.7 2. Central Processing Unit (CPU) Interrupt Enable Flag (I) The I flag enables maskable interrupts. Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1. The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has higher priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit If necessary, set to 0. When read, the content is undefined. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 17 of 45 R8C/1A Group, R8C/1B Group 3. 3. Memory Memory 3.1 R8C/1A Group Figure 3.1 is a Memory Map of R8C/1A Group. The R8C/1A Group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 16Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 1Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users. 00000h SFR (See 4. Special Function Registers (SFRs)) 002FFh 00400h Internal RAM 0XXXXh 0FFDCh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer*oscillation stop detection*voltage monitor 2 0YYYYh Address break (Reserved) Reset Internal ROM 0FFFFh 0FFFFh Expanded area FFFFFh NOTE: 1. The blank regions are reserved. Do not access locations in these regions. Internal ROM Part Number Internal RAM Size Address 0YYYYh Size Address 0XXXXh 16 Kbytes 0C000h 1 Kbyte 007FFh 12 Kbytes 0D000h 768 bytes 006FFh 8 Kbytes 0E000h 512 bytes 005FFh 4 Kbytes 0F000h 384 bytes 0057Fh R5F211A4SP, R5F211A4DSP, R5F211A4DD, R5F211A4NP, R5F211A4XXXSP, R5F211A4DXXXSP, R5F211A4XXXDD, R5F211A4XXXNP R5F211A3SP, R5F211A3DSP, R5F211A3DD, R5F211A3NP, R5F211A3XXXSP, R5F211A3DXXXSP, R5F211A3XXXDD, R5F211A3XXXNP R5F211A2SP, R5F211A2DSP, R5F211A2DD, R5F211A2NP, R5F211A2XXXSP, R5F211A2DXXXSP, R5F211A2XXXDD, R5F211A2XXXNP R5F211A1SP, R5F211A1DSP, R5F211A1DD, R5F211A1XXXSP, R5F211A1DXXXSP, R5F211A1XXXDD Figure 3.1 Memory Map of R8C/1A Group Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 18 of 45 R8C/1A Group, R8C/1B Group 3.2 3. Memory R8C/1B Group Figure 3.2 is a Memory Map of R8C/1B Group. The R8C/1B Group has 1 Mbyte of address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM area is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses 02400h to 02BFFh. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1Kbyte internal RAM area is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged. Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users. 00000h SFR (See 4. Special Function Registers (SFRs)) 002FFh 00400h Internal RAM 0XXXXh 02400h 02BFFh Internal ROM (data Flash)(1) 0FFDCh Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer * oscillation stop detection * voltage monitor 2 0YYYYh Address break (Reserved) Reset Internal ROM (program ROM) 0FFFFh 0FFFFh Expanded area FFFFFh NOTES: 1. Data flash block A (1 Kbyte) and B (1 Kbyte) are shown. 2. The blank regions are reserved. Do not access locations in these regions. Internal ROM Part Number Internal RAM Size Address 0YYYYh Size Address 0XXXXh 16 Kbytes 0C000h 1 Kbyte 007FFh 12 Kbytes 0D000h 768 bytes 006FFh 8 Kbytes 0E000h 512 bytes 005FFh 4 Kbytes 0F000h 384 bytes 0057Fh R5F211B4SP, R5F211B4DSP, R5F211B4DD, R5F211B4NP, R5F211B4XXXSP, R5F211B4DXXXSP, R5F211B4XXXDD, R5F211B4XXXNP R5F211B3SP, R5F211B3DSP, R5F211B3DD, R5F211B3NP, R5F211B3XXXSP, R5F211B3DXXXSP, R5F211B3XXXDD, R5F211B3XXXNP R5F211B2SP, R5F211B2DSP, R5F211B2DD, R5F211B2NP, R5F211B2XXXSP, R5F211B2DXXXSP, R5F211B2XXXDD, R5F211B2XXXNP R5F211B1SP, R5F211B1DSP, R5F211B1DD, R5F211B1XXXSP, R5F211B1DXXXSP, R5F211B1XXXDD Figure 3.2 Memory Map of R8C/1B Group Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 19 of 45 R8C/1A Group, R8C/1B Group 4. 4. Special Function Registers (SFRs) Special Function Registers (SFRs) An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.4 list the special function registers. Table 4.1 SFR Information (1)(1) Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh Register Symbol After reset Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 PM0 PM1 CM0 CM1 00h 00h 01101000b 00100000b Address Match Interrupt Enable Register Protect Register AIER PRCR 00h 00h Oscillation Stop Detection Register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 OCD WDTR WDTS WDC RMAD0 00000100b XXh XXh 00X11111b 00h 00h X0h Address Match Interrupt Register 1 RMAD1 00h 00h X0h Count Source Protection Mode Register CSPR 00h INT0 Input Filter Select Register INT0F 00h High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 HRA0 HRA1 HRA2 00h When shipping 00h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h Voltage Detection Register 1(2) Voltage Detection Register 2(2) VCA1 VCA2 00001000b 0033h 0034h 0035h 0036h Voltage Monitor 1 Circuit Control Register (2) VW1C Voltage Monitor 2 Circuit Control Register (5) VW2C 0000X000b(3) 0100X001b(4) 00h 001Fh 0020h 0021h 0022h 0023h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect this register. 3. After hardware reset. 4. After power-on reset or voltage monitor 1 reset. 5. Software reset, watchdog timer reset, and voltage monitor 2 reset do not affect b2 and b3. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 20 of 45 00h(3) 01000000b(4) R8C/1A Group, R8C/1B Group Table 4.2 Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 4. Special Function Registers (SFRs) SFR Information (2)(1) Register Symbol After reset Key Input Interrupt Control Register A/D Conversion Interrupt Control Register SSU/IIC Interrupt Control Register(2) Compare 1 Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register UART1 Transmit Interrupt Control Register UART1 Receive Interrupt Control Register KUPIC ADIC SSUAIC/IIC2AIC CMP1IC S0TIC S0RIC S1TIC S1RIC XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b Timer X Interrupt Control Register TXIC XXXXX000b Timer Z Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register Timer C Interrupt Control Register Compare 0 Interrupt Control Register INT0 Interrupt Control Register TZIC INT1IC INT3IC TCIC CMP0IC INT0IC XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. Selected by the IICSEL bit in the PMR register. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 21 of 45 R8C/1A Group, R8C/1B Group Table 4.3 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh 4. Special Function Registers (SFRs) SFR Information (3)(1) Timer Z Mode Register Register Symbol TZMR After reset 00h Timer Z Waveform Output Control Register Prescaler Z Register Timer Z Secondary Register Timer Z Primary Register PUM PREZ TZSC TZPR 00h FFh FFh FFh Timer Z Output Control Register Timer X Mode Register Prescaler X Register Timer X Register Timer Count Source Setting Register TZOC TXMR PREX TX TCSS 00h 00h FFh FFh 00h Timer C Register TC 00h 00h External Input Enable Register INTEN 00h Key Input Enable Register KIEN 00h Timer C Control Register 0 Timer C Control Register 1 Capture, Compare 0 Register TCC0 TCC1 TM0 Compare 1 Register TM1 UART0 Transmit/Receive Mode Register UART0 Bit Rate Generator UART0 Transmit Buffer Register U0MR U0BRG U0TB UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register U0C0 U0C1 U0RB UART1 Transmit/Receive Mode Register UART1 Bit Rate Generator UART1 Transmit Buffer Register U1MR U1BRG U1TB UART1 Transmit/Receive Control Register 0 UART1 Transmit/Receive Control Register 1 UART1 Receive Buffer Register U1C0 U1C1 U1RB UART Transmit/Receive Control Register 2 UCON 00h 00h 0000h(2) FFFFh(3) FFh FFh 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h XXh XXh XXh 00001000b 00000010b XXh XXh 00h SS Control Register H / IIC bus Control Register 1(4) SS Control Register L / IIC bus Control Register 2(4) SS Mode Register / IIC bus Mode Register(4) SS Enable Register / IIC bus Interrupt Enable Register(4) SS Status Register / IIC bus Status Register(4) SS Mode Register 2 / Slave Address Register(4) SS Transmit Data Register / IIC bus Transmit Data Register(4) SS Receive Data Register / IIC bus Receive Data Register(4) SSCRH / ICCR1 SSCRL / ICCR2 SSMR / ICMR SSER / ICIER SSSR / ICSR SSMR2 / SAR SSTDR / ICDRT SSRDR / ICDRR 00h 01111101b 00011000b 00h 00h / 0000X000b 00h FFh FFh X: Undefined NOTES: 1. The blank regions are reserved. Do not access locations in these regions. 2. In input capture mode. 3. In output compare mode. 4. Selected by the IICSEL bit in the PMR register. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 22 of 45 R8C/1A Group, R8C/1B Group Table 4.4 Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh 4. Special Function Registers (SFRs) SFR Information (4)(1) A/D Register Register Symbol AD After reset XXh XXh A/D Control Register 2 ADCON2 00h A/D Control Register 0 A/D Control Register 1 ADCON0 ADCON1 00000XXXb 00h Port P1 Register P1 XXh Port P1 Direction Register PD1 00h Port P3 Register P3 XXh Port P3 Direction Register Port P4 Register PD3 P4 00h XXh Port P4 Direction Register PD4 00h Port Mode Register PMR 00h Pull-Up Control Register 0 Pull-Up Control Register 1 Port P1 Drive Capacity Control Register Timer C Output Control Register PUR0 PUR1 DRR TCOUT 00XX0000b XXXXXX0Xb 00h 00h 01B3h 01B4h 01B5h 01B6h 01B7h Flash Memory Control Register 4 FMR4 01000000b Flash Memory Control Register 1 FMR1 1000000Xb Flash Memory Control Register 0 FMR0 00000001b 0FFFFh Optional Function Select Register OFS (2) X: Undefined NOTES: 1. Blank regions, 0100h to 01B2h and 01B8h to 02FFh are all reserved. Do not access locations in these regions. 2. The OFS register cannot be changed by a user program. Use a flash programmer to write to it. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 23 of 45 R8C/1A Group, R8C/1B Group 5. 5. Electrical Characteristics Electrical Characteristics Please contact Renesas Technology sales offices for the electrical characteristics in the Y version (Topr = -20C to 105C ). Table 5.1 Absolute Maximum Ratings Rated Value Unit VCC Symbol Supply voltage Parameter VCC = AVCC Condition -0.3 to 6.5 V AVCC Analog supply voltage VCC = AVCC -0.3 to 6.5 V V VI Input voltage -0.3 to VCC+0.3 VO Output voltage -0.3 to VCC+0.3 V Pd Power dissipation 300 mW Topr Operating ambient temperature -20 to 85 / -40 to 85 (D version) C Tstg Storage temperature -65 to 150 C Table 5.2 Topr = 25C Recommended Operating Conditions Symbol Parameter Conditions Standard Min. Typ. Max. Unit VCC Supply voltage 2.7 - 5.5 AVCC Analog supply voltage - VCC - V VSS Supply voltage - 0 - V AVSS Analog supply voltage - 0 - V VIH Input "H" voltage 0.8VCC - VCC V VIL Input "L" voltage 0 - 0.2VCC V IOH(sum) Peak sum output "H" current - - -60 mA IOH(peak) Peak output "H" current - - -10 mA IOH(avg) Average output "H" current - - -5 mA IOL(sum) Peak sum output "L" currents Sum of all pins IOL (peak) - - 60 mA IOL(peak) Peak output "L" currents Except P1_0 to P1_3 IOL(avg) f(XIN) - Average output "L" current Sum of all pins IOH (peak) P1_0 to P1_3 - 10 mA - - 30 mA Drive capacity LOW - - 10 mA - - 5 mA Drive capacity HIGH - - 15 mA Drive capacity LOW - - 5 mA 3.0 V VCC 5.5 V 0 - 20 MHz 2.7 V VCC < 3.0 V 0 - 10 MHz OCD2 = 0 Main clock selected 3.0 V VCC 5.5 V 0 - 20 MHz 2.7 V VCC < 3.0 V 0 - 10 MHz OCD2 = 1 On-chip oscillator clock selected HRA01 = 0 Low-speed on-chip oscillator clock selected - 125 - kHz HRA01 = 1 High-speed on-chip oscillator clock selected - 8 - MHz Main clock input oscillation frequency System clock - Drive capacity HIGH Except P1_0 to P1_3 P1_0 to P1_3 NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. Typical values when average output current is 100 ms. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 V Page 24 of 45 R8C/1A Group, R8C/1B Group Table 5.3 5. Electrical Characteristics A/D Converter Characteristics Symbol Parameter - Resolution - Absolute accuracy Rladder Resistor ladder tconv Conversion time Conditions Standard Min. Typ. Max. Unit Vref = VCC - - 10 Bits 10-bit mode AD = 10 MHz, Vref = VCC = 5.0 V - - 3 LSB 8-bit mode AD = 10 MHz, Vref = VCC = 5.0 V - - 2 LSB 10-bit mode AD = 10 MHz, Vref = VCC = 3.3 V(3) - - 5 LSB 8-bit mode AD = 10 MHz, Vref = VCC = 3.3 V(3) - - 2 LSB Vref = VCC 10 - 40 k 10-bit mode AD = 10 MHz, Vref = VCC = 5.0 V 3.3 - - s 8-bit mode AD = 10 MHz, Vref = VCC = 5.0 V 2.8 - - s 2.7 - Vcc V 0 - AVcc V 0.25 - 10 MHz 1 - 10 MHz Vref Reference voltage VIA Analog input voltage(4) - A/D operating clock frequency(2) Without sample and hold With sample and hold NOTES: 1. VCC = AVCC = 2.7 to 5.5 V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. If f1 exceeds 10 MHz, divide f1 and ensure the A/D operating clock frequency (AD) is 10 MHz or below. 3. If AVcc is less than 4.2 V, divide f1 and ensure the A/D operating clock frequency (AD) is f1/2 or below. 4. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in 8-bit mode. P1 P3 P4 Figure 5.1 Port P1, P3, and P4 Measurement Circuit Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 25 of 45 30pF R8C/1A Group, R8C/1B Group Table 5.4 Flash Memory (Program ROM) Electrical Characteristics Symbol - 5. Electrical Characteristics Parameter Program/erase endurance(2) Conditions Standard Unit Min. Typ. Max. R8C/1A Group 100(3) - - times R8C/1B Group 1,000(3) - - times s - Byte program time - 50 400 - Block erase time - 0.4 9 s td(SR-SUS) Time delay from suspend request until suspend - - 97+CPU clock x 6 cycles s - Interval from erase start/restart until following suspend request 650 - - s - Interval from program start/restart until following suspend request 0 - - ns - Time from suspend until program/erase restart - - 3+CPU clock x 4 cycles s - Program, erase voltage 2.7 - 5.5 V - Read voltage 2.7 - 5.5 V - Program, erase temperature 0 - 60 C - Data hold time(8) 20 - - year Ambient temperature = 55 C NOTES: 1. VCC = 2.7 to 5.5 V at Topr = 0 to 60 C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. If emergency processing is required, a suspend request can be generated independent of this characteristic. In that case the normal time delay to suspend can be applied to the request. However, we recommend that a suspend request with an interval of less than 650 s is only used once because, if the suspend state continues, erasure cannot operate and the incidence of erasure error rises. 5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. In addition, averaging the number of erase operations between block A and block B can further reduce the effective number of rewrites. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring programming/erasure failure rate information should contact their Renesas technical support representative. 8. The data hold time includes time that the power supply is off or the clock is not supplied. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 26 of 45 R8C/1A Group, R8C/1B Group Table 5.5 5. Electrical Characteristics Flash Memory (Data flash Block A, Block B) Electrical Characteristics Symbol Parameter Conditions Standard Min. Typ. Max. Unit 10,000(3) - - times Byte program time (Program/erase endurance 1,000 times) - 50 400 s - Byte program time (Program/erase endurance > 1,000 times) - 65 - s - Block erase time (Program/erase endurance 1,000 times) - 0.2 9 s - Block erase time (Program/erase endurance > 1,000 times) - 0.3 - s td(SR-SUS) Time Delay from suspend request until suspend - - 97+CPU clock x 6 cycles s - Interval from erase start/restart until following suspend request 650 - - s - Interval from program start/restart until following suspend request 0 - - ns - Time from suspend until program/erase restart - - 3+CPU clock x 4 cycles s - Program, erase voltage 2.7 - 5.5 V - Read voltage 2.7 - 5.5 V - Program, erase temperature -20(8) - 85 C - Data hold time(9) 20 - - year - Program/erase endurance(2) - Ambient temperature = 55 C NOTES: 1. VCC = 2.7 to 5.5 V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. Definition of programming/erasure endurance The programming and erasure endurance is defined on a per-block basis. If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024 1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance still stands at one. However, the same address must not be programmed more than once per erase operation (overwriting prohibited). 3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed). 4. If emergency processing is required, a suspend request can be generated independent of this characteristic. In that case the normal time delay to suspend can be applied to the request. However, we recommend that a suspend request with an interval of less than 650 s is only used once because, if the suspend state continues, erasure cannot operate and the incidence of erasure error rises. 5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example, when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the number of erase operations to a certain number. 6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase command at least three times until the erase error does not occur. 7. Customers desiring programming/erasure failure rate information should contact their Renesas technical support representative. 8. -40 C for D version. 9. The data hold time includes time that the power supply is off or the clock is not supplied. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 27 of 45 R8C/1A Group, R8C/1B Group 5. Electrical Characteristics Suspend request (maskable interrupt request) FMR46 Clockdependent time Fixed time (97 s) Access restart td(SR-SUS) Figure 5.2 Table 5.6 Transition Time to Suspend Voltage Detection 1 Circuit Electrical Characteristics Symbol Parameter Vdet1 Voltage detection level(3) - Voltage detection circuit self power consumption td(E-A) Waiting time until voltage detection circuit operation starts(2) Vccmin MCU operating voltage minimum value Condition VCA26 = 1, VCC = 5.0 V Standard Unit Min. Typ. Max. 2.70 2.85 3.00 V - 600 - nA - - 100 s 2.7 - - V NOTES: 1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40C to 85 C. 2. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2 register to 0. 3. Ensure that Vdet2 > Vdet1. Table 5.7 Voltage Detection 2 Circuit Electrical Characteristics Symbol Parameter Vdet2 Voltage detection level(4) - Voltage monitor 2 interrupt request generation time(2) - Voltage detection circuit self power consumption td(E-A) Waiting time until voltage detection circuit operation starts(3) Condition VCA27 = 1, VCC = 5.0 V Standard Unit Min. Typ. Max. 3.00 3.30 3.60 V - 40 - s - 600 - nA - - 100 s NOTES: 1. The measurement condition is VCC = 2.7 V to 5.5 V and Topr = -40C to 85 C. 2. Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2. 3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA27 bit in the VCA2 register to 0. 4. Ensure that Vdet2 > Vdet1. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 28 of 45 R8C/1A Group, R8C/1B Group Table 5.8 5. Electrical Characteristics Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset) Symbol Parameter Condition Standard Min. Power-on reset valid voltage Vpor2 tw(Vpor2-Vdet1) Supply voltage rising time when power-on reset is deasserted(1) Unit Typ. Max. -20C Topr 85C - - Vdet1 V -20C Topr 85C, tw(por2) 0s(3) - - 100 ms NOTES: 1. This condition is not applicable when using with Vcc 1.0 V. 2. When turning power on after the time to hold the external power below effective voltage (Vpor1) exceeds10 s, refer to Table 5.9 Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset). 3. tw(por2) is the time to hold the external power below effective voltage (Vpor2). Table 5.9 Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset) Symbol Parameter Condition Standard Min. Typ. Unit Max. Vpor1 Power-on reset valid voltage -20C Topr 85C - - 0.1 V tw(Vpor1-Vdet1) Supply voltage rising time when power-on reset is deasserted 0C Topr 85C, tw(por1) 10 s(2) - - 100 ms tw(Vpor1-Vdet1) Supply voltage rising time when power-on reset is deasserted -20C Topr < 0C, tw(por1) 30 s(2) - - 100 ms tw(Vpor1-Vdet1) Supply voltage rising time when power-on reset is deasserted -20C Topr < 0C, tw(por1) 10 s(2) - - 1 ms tw(Vpor1-Vdet1) Supply voltage rising time when power-on reset is deasserted 0C Topr 85C, tw(por1) 1 s(2) - - 0.5 ms NOTES: 1. When not using voltage monitor 1, use with Vcc 2.7 V. 2. tw(por1) is the time to hold the external power below effective voltage (Vpor1). Vdet1(3) Vdet1(3) Vccmin Vpor2 Vpor1 tw(por1) tw(Vpor1-Vdet1) Sampling time(1, 2) tw(por2) tw(Vpor2-Vdet1) Internal reset signal ("L" valid) 1 x 32 fRING-S 1 x 32 fRING-S NOTES: 1. Hold the voltage inside the MCU operation voltage range (Vccmin or above) within the sampling time. 2. The sampling clock can be selected. Refer to 7. Voltage Detection Circuit for details. 3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 7. Voltage Detection Circuit for details. Figure 5.3 Reset Circuit Electrical Characteristics Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 29 of 45 R8C/1A Group, R8C/1B Group Table 5.10 5. Electrical Characteristics High-Speed On-Chip Oscillator Circuit Electrical Characteristics Symbol Parameter Condition Standard Min. Typ. Max. Unit - High-speed on-chip oscillator frequency when the reset is deasserted VCC = 5.0 V, Topr = 25 C - 8 - MHz - High-speed on-chip oscillator frequency temperature * supply voltage dependence(2) 0 to +60 C/5 V 5 %(3) 7.76 - 8.24 MHz -20 to +85 C/2.7 to 5.5 V(3) 7.68 - 8.32 MHz -40 to +85 C/2.7 to 5.5 V(3) 7.44 - 8.32 MHz NOTES: 1. The measurement condition is VCC = 5.0 V and Topr = 25 C. 2. Refer to 10.6.4 High-Speed On-Chip Oscillator Clock for notes on high-speed on-chip oscillator clock. 3. The standard value shows when the HRA1 register is assumed as the value in shipping and the HRA2 register value is set to 00h. Table 5.11 Power Supply Circuit Timing Characteristics Symbol Parameter Condition Standard Min. Typ. Max. Unit td(P-R) Time for internal power supply stabilization during power-on(2) 1 - 2000 s td(R-S) STOP exit time(3) - - 150 s NOTES: 1. The measurement condition is VCC = 2.7 to 5.5 V and Topr = 25 C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until CPU clock supply starts after the interrupt is acknowledged to exit stop mode. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 30 of 45 R8C/1A Group, R8C/1B Group Table 5.12 5. Electrical Characteristics Timing Requirements of Clock Synchronous Serial I/O with Chip Select(1) Symbol Parameter Conditions Standard Min. Typ. Max. Unit tSUCYC SSCK clock cycle time 4 - - tCYC(2) tHI SSCK clock "H" width 0.4 - 0.6 tSUCYC tLO SSCK clock "L" width tRISE SSCK clock rising time 0.4 - 0.6 tSUCYC Master - - 1 tCYC(2) Slave - - 1 s Master - - 1 tCYC(2) s tFALL SSCK clock falling time - - 1 tSU SSO, SSI data input setup time 100 - - ns tH SSO, SSI data input hold time 1 - - tCYC(2) tLEAD Slave SCS setup time Slave 1tCYC+50 - - ns tLAG SCS hold time Slave 1tCYC+50 - - ns tOD SSO, SSI data output delay time - - 1 tCYC(2) tSA SSI slave access time - - 1.5tCYC+100 ns tOR SSI slave out open time - - 1.5tCYC+100 ns NOTES: 1. VCC = 2.7 to 5.5V, VSS = 0V at Ta = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. 1tCYC = 1/f1(s) Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 31 of 45 R8C/1A Group, R8C/1B Group 5. Electrical Characteristics 4-Wire Bus Communication Mode, Master, CPHS = 1 VIH or VOH SCS (output) VIH or VOH tHI tFALL tRISE SSCK (output) (CPOS = 1) tLO tHI SSCK (output) (CPOS = 0) tLO tSUCYC SSO (output) tOD SSI (input) tSU tH 4-Wire Bus Communication Mode, Master, CPHS = 0 VIH or VOH SCS (output) VIH or VOH tHI tFALL tRISE SSCK (output) (CPOS = 1) tLO tHI SSCK (output) (CPOS = 0) tLO tSUCYC SSO (output) tOD SSI (input) tSU tH CPHS, CPOS: Bits in SSMR register Figure 5.4 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master) Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 32 of 45 R8C/1A Group, R8C/1B Group 5. Electrical Characteristics 4-Wire Bus Communication Mode, Slave, CPHS = 1 VIH or VOH SCS (input) VIH or VOH tLEAD tHI tFALL tRISE tLAG SSCK (input) (CPOS = 1) tLO tHI SSCK (input) (CPOS = 0) tLO tSUCYC SSO (input) tSU tH SSI (output) tSA tOD tOR 4-Wire Bus Communication Mode, Slave, CPHS = 0 VIH or VOH SCS (input) VIH or VOH tHI tLEAD tFALL tRISE tLAG SSCK (input) (CPOS = 1) tLO tHI SSCK (input) (CPOS = 0) tLO tSUCYC SSO (input) tSU tH SSI (output) tSA tOD tOR CPHS, CPOS: Bits in SSMR register Figure 5.5 I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave) Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 33 of 45 R8C/1A Group, R8C/1B Group 5. Electrical Characteristics tHI VIH or VOH SSCK VIH or VOH tLO tSUCYC SSO (output) tOD SSI (input) tSU Figure 5.6 tH I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous Communication Mode) Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 34 of 45 R8C/1A Group, R8C/1B Group Table 5.13 5. Electrical Characteristics Timing Requirements of I2C bus Interface (1) Symbol Parameter Condition tSCL SCL input cycle time tSCLH SCL input "H" width tSCLL SCL input "L" width tsf tSP SCL, SDA input fall time SCL, SDA input spike pulse rejection time tBUF Standard Typ. (2) - 12tCYC+600 (2) - 3tCYC+300 Min. Max. - - Unit ns ns 5tCYC+300(2) - - - - ns - 300 - SDA input bus-free time 5tCYC(2) - 1tCYC(2) - ns ns tSTAH Start condition input hold time 3tCYC(2) - - ns tSTAS Retransmit start condition input setup time 3tCYC(2) - - ns tSTOS Stop condition input setup time 3tCYC(2) - - ns tSDAS Data input setup time - - ns tSDAH Data input hold time 1tCYC+20(2) 0 - - ns NOTES: 1. VCC = 2.7 to 5.5 V, VSS = 0 V and Ta = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. 1tCYC = 1/f1(s) VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P(2) S(1) tsf Sr(3) tSCLL tSDAS tSCL NOTES: 1. Start condition 2. Stop condition 3. Retransmit start condition Figure 5.7 I/O Timing of I2C bus Interface Rev.1.40 Dec 08, 2006 REJ03B0144-0140 P(2) Page 35 of 45 tSDAH ns R8C/1A Group, R8C/1B Group Table 5.14 Electrical Characteristics (1) [VCC = 5 V] Symbol VOH 5. Electrical Characteristics IOH = -1 mA Standard Min. Typ. VCC - 2.0 - VCC - 0.3 - VCC - 2.0 - Max. VCC VCC VCC IOH = -500 A VCC - 2.0 - VCC V - - - - IOL = 15 mA - - 2.0 0.45 2.0 V V V IOL = 5 mA - - 2.0 V IOL = 200 A - - 0.45 V IOL = 1 mA - - 2.0 V IOL = 500 A - - 2.0 V INT0, INT1, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RXD0 0.2 - 1.0 V RESET 0.2 - 2.2 V - - - 30 - 40 2.0 50 1.0 125 - 5.0 -5.0 167 - 250 - A - Parameter Output "H" voltage Except XOUT XOUT VOL Output "L" voltage Except P1_0 to P1_3, XOUT P1_0 to P1_3 XOUT VT+-VT- IIH IIL RPULLUP RfXIN fRING-S VRAM Hysteresis Input "H" current Input "L" current Pull-up resistance Feedback resistance XIN Low-speed on-chip oscillator frequency RAM hold voltage Condition IOH = -5 mA IOH = -200 A Drive capacity HIGH Drive capacity LOW IOL = 5 mA IOL = 200 A Drive capacity HIGH Drive capacity LOW Drive capacity LOW Drive capacity HIGH Drive capacity LOW VI = 5 V VI = 0 V VI = 0 V During stop mode NOTE: 1. VCC = 4.2 to 5.5 V at Topr = -20 to 85 C / -40 to 85 C, f(XIN) = 20 MHz, unless otherwise specified. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 36 of 45 Unit V V V A k M kHz V R8C/1A Group, R8C/1B Group Table 5.15 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (2) [Vcc = 5 V] (Topr = -40 to 85 C, unless otherwise specified.) Parameter Condition Power supply current High-speed (VCC = 3.3 to 5.5 V) mode Single-chip mode, output pins are open, other pins are VSS, A/D converter is stopped Mediumspeed mode High-speed on-chip oscillator mode Low-speed on-chip oscillator mode Wait mode Wait mode Stop mode Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 37 of 45 XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 Main clock off High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz No division Main clock off High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 FMR47 = 1 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = 0 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = 0 Main clock off, Topr = 25 C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = 0 Min. - Standard Typ. 9 Max. 15 - 8 14 mA - 5 - mA - 4 - mA - 3 - mA - 2 - mA - 4 8 mA - 1.5 - mA - 110 300 A - 40 80 A - 38 76 A - 0.8 3.0 A Unit mA R8C/1A Group, R8C/1B Group 5. Electrical Characteristics Timing Requirements (Unless otherwise specified: VCC = 5 V, VSS = 0 V at Ta = 25 C) [ VCC = 5 V ] Table 5.16 XIN Input Symbol tc(XIN) tWH(XIN) tWL(XIN) Standard Min. Max. 50 - 25 - 25 - Parameter XIN input cycle time XIN input "H" width XIN input "L" width Unit ns ns ns VCC = 5 V tc(XIN) tWH(XIN) XIN input tWL(XIN) Figure 5.8 Table 5.17 XIN Input Timing Diagram when VCC = 5 V CNTR0 Input, CNTR1 Input, INT1 Input Symbol tc(CNTR0) tWH(CNTR0) tWL(CNTR0) Standard Min. Max. 100 - 40 - 40 - Parameter CNTR0 input cycle time CNTR0 input "H" width CNTR0 input "L" width Unit ns ns ns VCC = 5 V tc(CNTR0) tWH(CNTR0) CNTR0 input tWL(CNTR0) Figure 5.9 Table 5.18 CNTR0 Input, CNTR1 Input, INT1 Input Timing Diagram when VCC = 5 V TCIN Input, INT3 Input tc(TCIN) TCIN input cycle time Standard Min. Max. - 400(1) tWH(TCIN) TCIN input "H" width 200(2) - ns tWL(TCIN) TCIN input "L" width 200(2) - ns Symbol Parameter Unit ns NOTES: 1. When using timer C input capture mode, adjust the cycle time to (1/timer C count source frequency x 3) or above. 2. When using timer C input capture mode, adjust the pulse width to (1/timer C count source frequency x 1.5) or above. VCC = 5 V tc(TCIN) tWH(TCIN) TCIN input tWL(TCIN) Figure 5.10 TCIN Input, INT3 Input Timing Diagram when VCC = 5 V Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 38 of 45 R8C/1A Group, R8C/1B Group Table 5.19 5. Electrical Characteristics Serial Interface Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Standard Min. Max. 200 - 100 - 100 - - 50 0 - 50 - 90 - Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Unit ns ns ns ns ns ns ns i = 0 or 1 VCC = 5 V tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 1 Figure 5.11 Table 5.20 Serial Interface Timing Diagram when VCC = 5 V External Interrupt INT0 Input INT0 input "H" width Standard Min. Max. - 250(1) INT0 input "L" width 250(2) Symbol tW(INH) tW(INL) Parameter - Unit ns ns NOTES: 1. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. 2. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater. VCC = 5 V tW(INL) INT0 input tW(INH) Figure 5.12 External Interrupt INT0 Input Timing Diagram when VCC = 5 V Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 39 of 45 R8C/1A Group, R8C/1B Group Table 5.21 Electrical Characteristics (3) [VCC = 3V] Symbol VOH VOL 5. Electrical Characteristics Parameter Output "H" voltage Output "L" voltage Except XOUT XOUT Except P1_0 to P1_3, XOUT P1_0 to P1_3 XOUT VT+-VT- Hysteresis IIH IIL RPULLUP RfXIN fRING-S VRAM RESET Input "H" current Input "L" current Pull-up resistance Feedback resistance XIN Low-speed on-chip oscillator frequency RAM hold voltage IOH = -0.1 mA Standard Min. Typ. VCC - 0.5 - VCC - 0.5 - Max. VCC VCC IOH = -50 A VCC - 0.5 - VCC V - - 0.5 V IOL = 2 mA - - 0.5 V IOL = 1 mA - - 0.5 V IOL = 0.1 mA - - 0.5 V IOL = 50 A - - 0.5 V 0.2 - 0.8 V 0.2 - 1.8 V - - A - 66 - 40 2.0 - 160 3.0 125 - 4.0 -4.0 500 - 250 - Condition IOH = -1 mA Drive capacity HIGH Drive capacity LOW IOL = 1 mA Drive capacity HIGH Drive capacity LOW Drive capacity HIGH Drive capacity LOW INT0, INT1, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RXD0 VI = 3 V VI = 0 V VI = 0 V During stop mode NOTE: 1. VCC = 2.7 to 3.3 V at Topr = -20 to 85 C / -40 to 85 C, f(XIN) = 10 MHz, unless otherwise specified. Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 40 of 45 Unit V V A k M kHz V R8C/1A Group, R8C/1B Group Table 5.22 Symbol ICC 5. Electrical Characteristics Electrical Characteristics (4) [Vcc = 3 V] (Topr = -40 to 85 C, unless otherwise specified.) Parameter Condition Power supply current High-speed (VCC = 2.7 to 3.3 V) mode Single-chip mode, output pins are open, other pins are VSS, A/D converter is stopped Mediumspeed mode High-speed on-chip oscillator mode Low-speed on-chip oscillator mode Wait mode Wait mode Stop mode Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 41 of 45 XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz No division XIN = 20 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 16 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 XIN = 10 MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 Main clock off High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz No division Main clock off High-speed on-chip oscillator on = 8 MHz Low-speed on-chip oscillator on = 125 kHz Divide-by-8 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz Divide-by-8 FMR47 = 1 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock operation VCA27 = VCA26 = 0 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on = 125 kHz While a WAIT instruction is executed Peripheral clock off VCA27 = VCA26 = 0 Main clock off, Topr = 25 C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA27 = VCA26 = 0 Min. - Standard Typ. 8 Max. 13 - 7 12 mA - 5 - mA - 3 - mA - 2.5 - mA - 1.6 - mA - 3.5 7.5 mA - 1.5 - mA - 100 280 A - 37 74 A - 35 70 A - 0.7 3.0 A Unit mA R8C/1A Group, R8C/1B Group 5. Electrical Characteristics Timing requirements (Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Ta = 25 C) [VCC = 3 V] Table 5.23 XIN Input Symbol tc(XIN) tWH(XIN) tWL(XIN) Standard Min. Max. 100 - 40 - 40 - Parameter XIN input cycle time XIN input "H" width XIN input "L" width Unit ns ns ns VCC = 3 V tc(XIN) tWH(XIN) XIN input tWL(XIN) Figure 5.13 Table 5.24 XIN Input Timing Diagram when VCC = 3 V CNTR0 Input, CNTR1 Input, INT1 Input Symbol tc(CNTR0) tWH(CNTR0) tWL(CNTR0) Standard Min. Max. 300 - 120 - 120 - Parameter CNTR0 input cycle time CNTR0 input "H" width CNTR0 input "L" width Unit ns ns ns VCC = 3 V tc(CNTR0) tWH(CNTR0) CNTR0 input tWL(CNTR0) Figure 5.14 Table 5.25 CNTR0 Input, CNTR1 Input, INT1 Input Timing Diagram when VCC = 3 V TCIN Input, INT3 Input Symbol Standard Min. Max. - 1,200(1) Parameter Unit tc(TCIN) TCIN input cycle time tWH(TCIN) TCIN input "H" width 600(2) - ns tWL(TCIN) TCIN input "L" width 600(2) - ns ns NOTES: 1. When using the timer C input capture mode, adjust the cycle time to (1/timer C count source frequency x 3) or above. 2. When using the timer C input capture mode, adjust the width to (1/timer C count source frequency x 1.5) or above. VCC = 3 V tc(TCIN) tWH(TCIN) TCIN input tWL(TCIN) Figure 5.15 TCIN Input, INT3 Input Timing Diagram when VCC = 3 V Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 42 of 45 R8C/1A Group, R8C/1B Group Table 5.26 5. Electrical Characteristics Serial Interface Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Standard Min. Max. 300 - 150 - 150 - - 80 0 - 70 - 90 - Parameter CLKi input cycle time CLKi input "H" width CLKi input "L" width TXDi output delay time TXDi hold time RXDi input setup time RXDi input hold time Unit ns ns ns ns ns ns ns i = 0 or 1 VCC = 3 V tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TXDi td(C-Q) tsu(D-C) th(C-D) RXDi i = 0 or 1 Figure 5.16 Table 5.27 Serial Interface Timing Diagram when VCC = 3 V External Interrupt INT0 Input INT0 input "H" width Standard Min. Max. - 380(1) INT0 input "L" width 380(2) Symbol tW(INH) tW(INL) Parameter - Unit ns ns NOTES: 1. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input HIGH width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater 2. When selecting the digital filter by the INT0 input filter select bit, use an INT0 input LOW width of either (1/digital filter clock frequency x 3) or the minimum value of standard, whichever is greater VCC = 3 V tW(INL) INT0 input tW(INH) Figure 5.17 External Interrupt INT0 Input Timing Diagram when VCC = 3 V Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 43 of 45 R8C/1A Group, R8C/1B Group Package Dimensions Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website. JEITA Package Code P-LSSOP20-4.4x6.5-0.65 RENESAS Code PLSP0020JB-A Previous Code 20P2F-A 11 *1 E 20 HE MASS[Typ.] 0.1g NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. F 1 10 Index mark c A1 Reference Dimension in Millimeters Symbol D D E A2 A A1 bp c A L *2 A2 *3 e bp Detail F y HE e y L RENESAS Code PRDP0020BA-A Previous Code 20P4B Nom Max 6.5 6.6 4.4 4.5 1.15 1.45 0.1 0.2 0 0.17 0.22 0.32 0.13 0.15 0.2 0 10 6.2 6.4 6.6 0.53 0.65 0.77 0.10 0.3 0.5 0.7 MASS[Typ.] 1.0g 11 1 10 c *1 E 20 e1 JEITA Package Code P-SDIP20-6.3x19-1.78 Min 6.4 4.3 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. D A A2 *2 L A1 Reference Symbol *3 b 3 e SEATING PLANE bp e1 D E A A1 A2 bp b3 c e L Rev.1.40 Dec 08, 2006 REJ03B0144-0140 Page 44 of 45 Dimension in Millimeters Min Nom Max 7.32 7.62 7.92 18.8 19.0 19.2 6.15 6.3 6.45 4.5 0.51 3.3 0.38 0.48 0.58 0.9 1.0 1.3 0.22 0.27 0.34 15 0 1.528 1.778 2.028 3.0 R8C/1A Group, R8C/1B Group JEITA Package Code P-HWQFN28-5x5-0.50 Package Dimensions RENESAS Code PWQN0028KA-B *1 Previous Code 28PJW-B MASS[Typ.] 0.05g D 15 21 21 15 22 14 14 22 E1 *2 E D2 8 28 Lp 28 8 7 7 1 e bp 1 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. x y Rev.1.40 Dec 08, 2006 REJ03B0144-0140 A1 F Page 45 of 45 Detail F A A2 Reference Symbol D E A2 A A1 bp e Lp x y D2 E1 Dimension in Millimeters Min Nom Max 4.9 5.0 5.1 4.9 5.0 5.1 0.75 0.8 0 0 0.05 0.15 0.2 0.25 0.5 0.5 0.6 0.7 0.05 0.05 2.0 2.0 REVISION HISTORY REVISION HISTORY Description Rev. Date 0.10 Feb 18, 2005 - 0.20 Jun 01, 2005 2, 3 0.30 Jul 04, 2005 R8C/1A Group, R8C/1B Group Datasheet R8C/1A Group, R8C/1B Group Datasheet Page Summary First Edition issued Tables 1.1, 1.2: Item name changed 9 Table 1.5: Timer C's Pin name revised, Reference Voltage Input Description revised 16 Table 4.1 the value after reset revised; 0009h address "XXXXXX00b" "00h", 000Ah address "00XXX000b" "00h", 001Eh address "XXXXX000b" "00h". 17 Table 4.2 004Fh address; "SSU/IIC Interrupt Control Register, SSUAIC/ IIC2AIC, XXXXX000b" added 18 Table 4.3 the value after reset revised; 00BCh address "00h" "00h / 0000X000b" 20 to 39 5. Electrical Characteristics added 1.00 Sep 01, 2005 all pages "Under development" deleted 3 Table 1.2 Performance Outline of the R8C/1B Group; Flash Memory: (Data area) (Data flash) (Program area) (Program ROM) revised 4 Figure 1.1 Block Diagram; "Peripheral Function" added, "System Clock Generation" "System Clock Generator" revised 5 Table 1.3 Product Information of R8C/1A Group; "(D)" and "(D): Under development" deleted 6 Table 1.4 Product Information of R8C/1B Group; "(D)" and "(D): Under development" deleted ROM capacity: (Program area) (Program ROM), (Data area) (Data flash) revised 9 Table 1.5 Pin Description; Power Supply Input: "VCC/AVCC" "VCC", "VSS/AVSS" "VSS" revised Analog Power Supply Input: added 11 Figure 2.1 CPU Register; "Reserved Area" "Reserved Bit" revised 13 2.8.10 Reserved Area; "Reserved Area" "Reserved Bit" revised 15 3.2 R8C/1B Group, Figure 3.2 Memory Map of R8C/1B Group; "Data area" "Data flash", "Program area" "Program ROM" revised A-1 REVISION HISTORY Rev. Date 1.00 Sep 01, 2005 1.10 1.20 1.30 Dec 16, 2005 Mar 31, 2006 Oct 03, 2006 R8C/1A Group, R8C/1B Group Datasheet Description Page Summary 18 Table 4.3 SFR Information(3); 0085h: "Prescaler Z" "Prescaler Z Register" 0086h: "Timer Z Secondary" "Timer Z Secondary Register" 0087h: "Timer Z Primary" "Timer Z Primary Register" 008Ch: "Prescaler X" "Prescaler X Register" 008Dh: "Timer X" "Timer X Register" 0090h, 0091h: "Timer C" "Timer C Register" revised 21 Table 5.3 A/D Converter Characteristics; Vref and VIA: Standard value, NOTE4 revised 22 Table 5.4 Flash Memory (Program ROM) Electrical Characteristics; NOTES3 and 5 revised, NOTE8 deleted 23 Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics; NOTES1 and 3 revised 25 Table 5.8 Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset); NOTE2 revised 26 Table 5.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics; "High-Speed On-Chip Oscillator ..." "High-Speed On-Chip Oscillator Frequency ..." revised, NOTE2 added 33 Table 5.15 Electrical Characteristics (2) [Vcc = 5V]; NOTE1 deleted 37 Table 5.22 Electrical Characteristics (4) [Vcc = 3V]; NOTE1 deleted - Products of PWQN0028KA-B package included 5, 6 Table 1.3, Table 1.4 revised 24 Table 5.4 Flash Memory (Program ROM) Electrical Characteristics; NOTE 8 added, Topr Ambient temperature 25 Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics; NOTE 9 added, Topr Ambient temperature 28 Table 5.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics; NOTE 3 added 29 Table 5.12; tSA and tOR revised, NOTE: 1. VCC = 2.2 to 2.7 to 33 Table 5.13; NOTE: 1. VCC = 2.2 to 2.7 to 35, 39 Table 5.15, Table 5.22; The title revised, Condition of Stop Mode added 37, 41 Table 5.19, Table 5.26; td(C-Q) and tsu(D-C) revised 42, 43 Package Dimensions revised 5, 6 Table 1.3, Table 1.4; Type No. added, deleted 16, 17 Figure 3.1, Figure 3.2; Part Number added, deleted 24, 25 Table 5.4, Table 5.5; Conditions: VCC = 5.0 V at Topr = 25 C deleted, all pages Y version added Factory programming product added A-2 REVISION HISTORY Rev. Date 1.30 Oct 03, 2006 1.40 Dec 08, 2006 R8C/1A Group, R8C/1B Group Datasheet Description Page 1 Summary 1.1 "portable equipment" added 2, 3 Table 1.1, Table 1.2; Specification Interrupts: "Internal: 9 sources" "Internal: 11 sources" 24 Table 5.2; Parameter: System clock added 45 Package Dimensions; PWQN0028KA-B revised 20 Table 4.1; 000Fh: After reset "000XXXXXb" "00X11111b" 24 Table 19.2; Parameter: OCD2 = 1 On-chip oscillator clock selected revised A-3 Sales Strategic Planning Div. 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