1.6 V to 16.5 V Hot Swap Controller
with Soft Start
Data Sheet
ADM1170
Rev. A Document Feedback
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FEATURES
Controls supply rails from 1.6 V to 16.5 V
Supply voltage range from 2.7 V to 16.5 V
Allows protected board removal and insertion to a live
backplane
External sense resistor provides adjustable analog current
limit with circuit breaker
Soft start controls inrush current profile
Peak fault current limited with fast response
Charge pumped gate drive for external N-FET switch
Automatic retry or latch-off during current fault
Undervoltage lockout
8-lead, TSOT package
APPLICATIONS
Hot swap board insertion: line cards, raid systems
Industrial high-side switches/circuit breakers
Electronic circuit breakers
GENERAL DESCRIPTION
The ADM1170 is a hot swap controller that safely enables a
printed circuit board to be removed and inserted to a live
backplane. This is achieved using an external N-channel power
MOSFET with a current control loop that monitors the load
current through a sense resistor. An internal charge pump is
used to enhance the gate of the N-channel FET. When an
overcurrent condition is detected, the gate voltage of the FET is
reduced to limit the current flowing through the sense resistor.
The ADM1170 operates with a supply voltage ranging from
2.7 V to 16.5 V. By using independent SENSE pins from VCC,
the ADM1170 allows for the hot swap of supplies ranging down
to 1.6 V. During an overcurrent condition, the TIMER pin
capacitor determines the amount of time the FET remains at
a current limiting mode of operation until it is shut down. The
ON (ON-CLR) pin is the enable input for the device and can be
used to monitor the input supply voltage. The ADM1170 also
features soft start to provide the user with a capacitor program-
mable ramping reference to the internal current sense comparator.
This provides a linearly increasing current limit at startup at a
rate set by CSS. This helps to reduce and limit large inrush
currents.
This device is available in two options: the ADM1170-1 with
automatic retry for overcurrent fault and the ADM1170-2 with
latch-off for an overcurrent fault. Toggling the ON (ON-CLR)
pin resets a latched fault. The ADM1170 is packaged in an
8-lead TSOT.
FUNCTIONAL BLOCK DIAGRAM
LONG
V
IN
= 1.8V V
OUT
= 1.8V
SENSE+
R
SENSE
Q
1
C
TIMER
LONG
SHORT
LONG SENSE–
GATE
ON
V
CC
TIMER
SS
ADM1170-1
GND
GND GND
V
IN
= 3.3V AUX
R
ON1
R
ON2
C
LOAD
C
SS
05124-001
Figure 1.
ADM1170 Data Sheet
Rev. A | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Characteristics .............................................................. 4
ESD Caution .................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 11
Overview ...................................................................................... 11
UVLO ........................................................................................... 11
ON (ON-CLR) Pin ..................................................................... 11
GATE ........................................................................................... 11
Current Limit Function ............................................................. 11
Calculating the Current Limit .................................................. 11
Circuit Breaker Function ........................................................... 11
Timer Function ........................................................................... 12
Power-Up Timing Cycle ............................................................ 12
Circuit Breaker Timing Cycle ................................................... 12
Automatic Retry or Latched Off ............................................... 13
Soft Start ...................................................................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 14
REVISION HISTORY
1/13—Rev. 0 to Rev. A
Changes to Figure 36 ...................................................................... 13
Changes to Ordering Guide .......................................................... 14
7/06—Revision 0: Initial Version
Data Sheet ADM1170
Rev. A | Page 3 of 16
SPECIFICATIONS
VCC = 2.7 V to 16.5 V, T A = −40°C to +85°C, typical values at TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Conditions
VCC PIN
Operating Voltage Range VCC 2.7 16.5 V
Supply Current ICC 0.65 0.8 mA
Undervoltage Lockout VUVLO 2.4 2.525 2.65 V VCC rising
Undervoltage Lockout Hysteresis VUVLOHYS 40 mV
ON (ON-CLR) PIN
Input Current IINON −1 0 +1 µA
Threshold VON 1.22 1.3 1.38 V ON rising
Threshold Hysteresis VONHYST 50 mV
SENSE PINS (SENSE+/SENSE−)
Hot Swap Operating Range 1.6 16.5 V
Input Current IINSENSE −160 −65 +13 µA VSENSE+ = 1.6 V
Input Current
I
INSENSE
5
10
15
µA
V
SENSE+
≥ 2.2 V
Circuit Breaker Limit Voltage VCB 26 50 77 mV VCB = (VSENSE+ – VSENSE−), VSENSE+ = 1.6 V
Circuit Breaker Limit Voltage VCB 44 50 56 mV VCB = (VSENSE+ – VSENSE−), VSENSE+ ≥ 2.2 V
GATE PIN
Drive Voltage VGAT E 4.6 7.5 10 V VGAT E − VCC, VCC = 3.0 V
6.0 8 12 V VGATE − VCC, VCC = 3.3 V
8.75 10 12 V VGATE − VCC, VCC = 5 V
7.5 9 12 V VGAT E − VCC, VCC = 12 V
5.56 8 12 V VGATE − VCC, VCC = 15 V
Pull-Up Current −6.5 −12 −14.5 μA VG ATE = 0 V
Pull-Down Current 4 mA VGAT E = 3 V, VCC = 5 V, ON (ON-CLR) = low
Pull-Down Current 25 mA VGATE = 3 V, VCC < UVLO
TIMER PIN
Pull-Up Current ITIMERUP −2 −5 −8.5 µA Initial cycle, VTIMER = 1 V
−25 −60 −100 µA During current fault, VTIMER = 1 V
Pull-Down Current ITIMERDN 2 3.5 µA After Cct breaker tip, VTIMER = 1 V
100 µA Normal operation, VTIMER = 1 V
Threshold High VTIMERH 1.22 1.3 1.38 V TIMER rising
Threshold Low VTIMERL 0.15 0.2 0.25 V TIMER falling
SS PIN
Soft Start Pull-Up Current 10 µA
Current Setting Gain 20 V/V VSS/VSENSE
Soft Start Completion Voltage 1 V
Pull-Down Current 50 µA During fault
tOFF
Turn-Off Time (TIMER Rise to GATE Fall) 2 µs VTIMER = 0 V to 2 V step, VCC = VON = 5 V
Turn-Off Time (ON Fall to GATE Fall) 40 µs VON = 5 V to 0 V step, VCC = 5 V
Turn-Off Time (VCC Fall to IC Reset) 40 µs VCC = 5 V to 2 V step, VON = 5 V
ADM1170 Data Sheet
Rev. A | Page 4 of 16
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VCC Pin −0.3 V to +20 V
SENSE+ Pin/SENSE− Pin −0.3 V to +20 V
SENSE+ Pin − SENSE− Pin ±5 V
TIMER Pin −0.3 V to (VCC + 0.3 V)
ON (ON-CLR) Pin −0.3 V to +20 V
SS Pin –0.3 V to (VCC + 0.3 V)
GATE Pin −0.3 V to (VCC + 11 V)
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA Unit
8-Lead TSOT 152.9 °C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Data Sheet ADM1170
Rev. A | Page 5 of 16
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TIMER
1
GND
2
SS
3
ON
4
V
CC
8
SENSE+
7
SENSE–
6
GATE
5
ADM1170-1AUJ
TOP VIEW
(Not t o Scal e)
05124-006
Figure 2. Pin Configuration, 1AUJ Model
ON-CLR
TIMER
1
GND
2
SS
3
4
V
CC
8
SENSE+
7
SENSE–
6
GATE
5
ADM1170-2AUJ
TOP VIEW
(Not t o Scal e)
05124-007
Figure 3. Pin Configuration, 2AUJ Model
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 TIMER Timer Input Pin. The initial and circuit breaker timing cycles are set by this external capacitor. The initial timing
delay is 272.9 ms/μF, and 21.7 ms/µF for a circuit breaker delay. When the TIMER pin is pulled beyond the
upper threshold, the GATE turns off.
2 GND Chip Ground Pin.
3
SS
Soft Start Pin. An external capacitor between the SS pin and GND sets the ramp rate of the current limit
reference.
4 ON (ON-CLR) Input Pin. The ON (ON-CLR) pin is an input to a comparator that has a low-to-high threshold of 1.3 V with
80 mV hysteresis and a glitch filter. The ADM1170 is reset when the ON (ON-CLR) pin is low. When the ON
(ON-CLR) pin is high, the ADM1170 is enabled. A rising edge on this pin has the added function of clearing a
fault and restarting the device on the latched off model, the ADM1170-2.
5
GATE
Gate Output Pin. An internal charge pump provides a 12 µA pull-up current to drive the gate of an N-channel
MOSFET. In an overcurrent condition, the ADM1170 controls the external FET to maintain a constant load
current.
6, 7 SENSE−, SENSE+ Current Limit Sense Input Pins. The current limit is set via a sense resistor between the SENSE+ and SENSE−
pins. In an overcurrent condition, the gate of the FET is controlled to maintain the SENSE voltage at 50 mV.
When this limit is reached, the TIMER circuit breaker mode is activated. The circuit breaker limit can be
disabled by connecting the SENSE+ and SENSE− pins together.
8 VCC Positive Supply Input Pin. The ADM1170 operates between 2.7 V to 16.5 V. An undervoltage lockout (UVLO)
circuit with a glitch filter resets the ADM1170 when the supply voltage drops below the specified UVLO limit.
ADM1170 Data Sheet
Rev. A | Page 6 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
0.50
0018
SUPPLY VOLT AGE (V)
SUPP LY CURRENT ( mA)
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
246810 12 14 16
05124-023
Figure 4. Supply Current vs. Supply Voltage (GATE off)
0.8
0018
SUPPLY VOLT AGE (V)
SUPP LY CURRENT ( mA)
246810 12 14 16
0.7
0.6
0.5
0.4
0.3
0.2
0.1
05124-024
Figure 5. Supply Current vs. Supply Voltage (GATE on)
1.0
0
–50 150
TEMPERATURE (°C)
SUPP LY CURRENT ( mA)
0.8
0.6
0.4
0.2
–25 025 50 75 100 125
V
CC
= 15V
V
CC
= 12V
V
CC
= 5V V
CC
= 3V
0.9
0.7
0.5
0.3
0.1
05124-033
Figure 6. Supply Current vs. Temperature
2.65
2.45
–50 150
TEMPERATURE (°C)
UVL O THRES HOLD ( V )
V
CC
= 5V
–25 025 50 75 100 125
2.63
2.61
2.59
2.57
2.55
2.53
2.51
2.49
2.47
V
CC
FALLING
V
CC
RIS ING
05124-046
Figure 7. UVLO Threshold vs. Temperature
25
0018
SUPPLY VOLT AGE (V)
GATE VOLTAGE (V)
2 4 6 8 10 12 14 16
20
15
10
5
05124-013
Figure 8. GATE Voltage vs. Supply Voltage
25
0
–50 150
TEMPERATURE (°C)
GATE VOLTAGE (V)
20
15
10
5
–25 025 50 75 100 125
V
CC
= 15V
V
CC
= 12V
V
CC
= 5V
V
CC
= 3V
05124-015
Figure 9. GATE Voltage vs. Temperature
Data Sheet ADM1170
Rev. A | Page 7 of 16
10
0018
SUPPLY VOLT AGE (V)
DELTA GATE VOLTAGE (V)
246810 12 14 16
9
8
7
6
5
4
3
2
1
05124-014
Figure 10. Delta GATE Voltage vs. Supply Voltage
10
0
–50 150
TEMPERATURE (°C)
DELTA GATE VOLTAGE (V)
–25 025 50 75 100 125
V
CC
= 15V
V
CC
= 12V V
CC
= 5V
V
CC
= 3V
9
8
7
6
5
4
3
2
1
05124-016
Figure 11. Delta GATE Voltage vs. Temperature
0
–10 018
SUPPLY VOLT AGE (V)
I
TIMERUP
(µA)
2 4 6 8 10 12 14 16
T
A
= 25° C
–1
–2
–3
–4
–5
–6
–7
–8
–9
05124-035
Figure 12. ITIMERUP (in Initial Cycle) vs. Supply Voltage
0
–10
–50 150
TEMPERATURE (°C)
I
TIMERUP
(µA)
V
CC
= 5V
–1
–2
–3
–4
–5
–6
–7
–8
–9
–25 025 50 75 100 125
05124-038
Figure 13. ITIMERUP (in Initial Cycle) vs. Temperature
–20
–100 018
SUPPLY VOLT AGE (V)
I
TIMERUP
(µA)
2 4 6 8 10 12 14 16
T
A
= 25° C
–30
–40
–50
–60
–70
–80
–90
05124-036
Figure 14. ITIMERUP (During Cct Breaker Delay) vs. Supply Voltage
–20
–100
–50 150
TEMPERATURE (°C)
I
TIMERUP
(µA)
V
CC
= 5V
–25 025 50 75 100 125
–30
–40
–50
–60
–70
–80
–90
05124-039
Figure 15. ITIMERUP (During Cct Breaker Delay) vs. Temperature
ADM1170 Data Sheet
Rev. A | Page 8 of 16
3.0
1.0 018
SUPPLY VOLT AGE (V)
I
TIMERDN
(µA)
2 4 6 8 10 12 14 16
T
A
= 25° C
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
05124-034
Figure 16. ITIMERDN (in Cool-Off Cycle) vs. Supply Voltage
3.0
1.0
–50 150
TEMPERATURE (°C)
I
TIMERDN
(µA)
V
CC
= 5V
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
–25 025 50 75 100 125
05124-037
Figure 17. ITIMERDN (in Cool-Off Cycle) vs. Temperature
1.38
1.22 018
SUPPLY VOLT AGE (V)
TIMER HI GH THRE S HOLD ( V )
246810 12 14 16
T
A
= 25° C
1.36
1.34
1.32
1.30
1.28
1.26
1.24
05124-042
Figure 18. TIMER High Threshold vs. Supply Voltage
1.38
1.22
–50 150
TEMPERATURE (°C)
TIMER HI GH THRE S HOLD ( V )
V
CC
= 5V
–25 025 50 75 100 125
1.36
1.34
1.32
1.30
1.28
1.26
1.24
05124-044
Figure 19. TIMER High Threshold vs. Temperature
0.24
0.16 018
SUPPLY VOLT AGE (V)
TIMER LOW THRESHOLD (V)
2 4 6 8 10 12 14 16
T
A
= 25° C
0.23
0.22
0.21
0.20
0.19
0.18
0.17
05124-043
Figure 20. TIMER Low Threshold vs. Supply Voltage
0.24
0.16
–50 150
TEMPERATURE (°C)
TIMER LOW THRESHOLD (V)
V
CC
= 5V
–25 025 50 75 100 125
0.23
0.22
0.21
0.20
0.19
0.18
0.17
05124-045
Figure 21. TIMER Low Threshold vs. Temperature
Data Sheet ADM1170
Rev. A | Page 9 of 16
1.45
1.05 018
SUPPLY VOLTAGE (V)
ON ( ON-CLR) P IN THRE SHOLD ( V )
2 4 6 8 10 12 14 16
T
A
= 25° C
1.40
1.35
1.30
1.25
1.20
1.15
1.10
LOW T HRESHOL D
HIG H T HRES HO L D
05124-040
Figure 22. ON (ON-CLR) Pin Threshold vs. Supply Voltage
1.45
1.05
–50 150
TEM P ERATURE (°C)
ON ( ON-CLR) P IN THRE SHOLD ( V )
V
CC
= 5V
–25 0 25 50 75 100 125
1.40
1.35
1.30
1.25
1.20
1.15
1.10
HIG H THRESHO LD
LOW THRESHOLD
05124-041
Figure 23. ON (ON-CLR) Pin Threshold vs. Temperature
80
0018
SUPPLY VOLTAGE (V)
t
OFF(ONLOW)
(µs)
2 4 6 8 10 12 14 16
T
A
= 25° C
70
60
50
40
30
20
10
05124-047
Figure 24. tOFF(ONLOW) vs. Supply Voltage
80
0
–50 150
TEM P ERATURE (°C)
t
OFF(ONLOW)
(µs)
–25 0 25 50 75 100 125
V
CC
= 15V
V
CC
= 12V
V
CC
= 5V
V
CC
= 3V
70
60
50
40
30
20
10
05124-048
Figure 25. tOFF(ONLOW) vs. Temperature
50
40018
SUPPLY VOLTAGE (V)
V
CB
(mV)
49
48
47
46
45
44
43
42
41
2 4 6 8 10 12 14 16
05124-049
Figure 26. Cct Breaker Voltage vs. Supply Voltage
50
0
–50 150
TE M P ERATURE (°C)
V
CB
(mV)
–25 0 25 50 75 100 125
45
40
35
30
25
20
15
10
5
05124-021
Figure 27. Cct Breaker Voltage vs. Temperature
ADM1170 Data Sheet
Rev. A | Page 10 of 16
12
0018
SUPPLY VOLTAGE (V)
GAT E CURRE NT (m A)
10
8
6
4
2
2 4 6 8 10 12 14 16
05124-008
Figure 28. GATE Current (Down) vs. Supply Voltage
–
8
–14 018
SUPPLY VOLTAGE (V)
GAT E CURRENT (µA)
–9
–10
–11
–12
–13
2 4 6 8 10 12 14 16
05124-009
Figure 29. GATE Current (up) vs. Supply Voltage
–
11.0
–13.0
–50 150
TEM P ERATURE (°C)
GAT E CURRENT (µA)
–25 0 25 50 75 100 125
V
CC
= 15V
V
CC
= 12V
V
CC
= 5V V
CC
= 3V
–11.2
–11.4
–11.6
–11.8
–12.0
–12.2
–12.4
–12.6
–12.8
05124-017
Figure 30. GATE Current (up) vs. Temperature
–
10.4
–11.0
–50 150
TEM P ERATURE (°C)
SOFT S TART CURRENT (µA)
–25 0 25 50 75 100 125
V
CC
= 15V
V
CC
= 12V
V
CC
= 5V
V
CC
= 3V
–10.5
–10.6
–10.7
–10.8
–10.9
05124-018
Figure 31. Soft Start Current vs. Temperature
50
001.2
SOFT START VOLTAGE (V)
CCT BREAKER V OLT AGE ( mV)
45
40
35
30
25
20
15
10
5
0.2 0.4 0.6 0.8 1.0
05124-020
Figure 32. Circuit Breaker Voltage vs. Soft Start Voltage
Data Sheet ADM1170
Rev. A | Page 11 of 16
THEORY OF OPERATION
Many systems require the insertion or removal of circuit boards
to live backplanes. During this event, the supply bypass and hold-
up capacitors can require substantial transient currents from the
backplane power supply as they charge. These currents can
cause permanent damage to connector pins or undesirable glitches
and resets to the system.
The ADM1170 is intended to control the powering of a system
(on and off) in a controlled manner, allowing the board to be
removed from, or inserted into, a live backplane by protecting it
from excess currents. The ADM1170 can reside either on the
backplane or on the removable board.
OVERVIEW
The ADM1170 operates over a supply range of 2.7 V to 16.5 V.
As the supply voltage is coming up, an undervoltage lockout
circuit checks if sufficient supply voltage is present for proper
operation. During this period, the FET is held off by the GATE
pin being held to GND. When the supply voltage reaches a level
above UVLO and the ON (ON-CLR) pin is high, an initial timing
cycle ensures that the board is fully inserted in the backplane
before turning on the FET. The TIMER pin capacitor sets the
periods for all of the TIMER pin functions. After the initial
timing cycle, the ADM1170 monitors the inrush current
through an external sense resistor. Overcurrent conditions are
actively limited to 50 mV/RSENSE for the circuit breaker timer
limit. The ADM1170-1 automatically retries after a current limit
fault and the ADM1170-2 latches off. The retry duty cycle on
the ADM1170-1 timer function is limited to 3.8% for FET
cooling.
UVLO
If the VCC supply is too low for normal operation, an under-
voltage lockout circuit holds the ADM1170 in reset. The GATE
pin is held to GND during this period. When the supply reaches
this UVLO voltage, the ADM1170 starts when the ON (ON-CLR)
pin condition is satisfied.
ON (ON-CLR) PIN
The ON (ON-CLR) pin is the enable pin. It is connected to a
comparator that has a low-to-high threshold of 1.3 V with 80 mV
hysteresis and a glitch filter. The ADM1170 is reset when the
ON (ON-CLR) pin is low. When the ON (ON-CLR) pin is high,
the ADM1170 is enabled. A rising edge on this pin has the
added function of clearing a fault and restarting the device on
the latched off model, the ADM1170-2. A low input on the ON
(ON-CLR) pin turns off the external FET by pulling the GATE
pin to ground and resets the timer. An external resistor divider at
the ON (ON-CLR) pin can be used to program an undervoltage
lockout value higher than the internal UVLO circuit. There is a
glitch filter delay of approximately 3 μs on rising allowing the
addition of an RC filter at the ON (ON-CLR) pin to increase the
delay time at card insertion. If using a short pin system to
enable the device, a pull-down resistor should be used to hold
the device prior to insertion.
GATE
Gate drive for the external N-channel MOSFET is achieved
using an internal charge pump. The gate driver consists of a
12 μA pull-up from the internal charge pump. There are various
pull-down devices on this pin. At a hotswap condition the board
is hot inserted to the supply bus. During this event, it is possible
for the external FET GATE capacitance to be charged up by the
sudden presence of the supply voltage. This can cause
uncontrolled inrush currents. An internal strong pull-down
circuit holds GATE low while in UVLO. This reduces current
surges at insertion. After the initial timing cycle, the GATE is
then pulled high. During an overcurrent condition, the
ADM1170 servos the GATE pin in an attempt to maintain a
constant current to the load until the circuit breaker timeout
completes. In the event of a timeout, the GATE pin abruptly
shuts down using the 4 mA pull-down device. Care must be
taken not to load the GATE pin resistively because this reduces
the gate drive capability.
CURRENT LIMIT FUNCTION
The ADM1170 features a fast response current control loop that
actively limits the current by reducing the gate voltage of the
external FET. This current is measured by monitoring the
voltage drop across an external sense resistor. The ADM1170
tries to regulate the gate of the FET to achieve a 50 mV voltage
drop across the sense resistor.
CALCULATING THE CURRENT LIMIT
The sense resistor connected between SENSE+ and the SENSE−
pin is used to determine the nominal fault current limit. This is
given by the following equation:
ILIMITNOM = VCBNOM/RSENSENOM (1)
The minimum load current is given by Equation 2
ILIMITMIN = VCBMIN/RSENSEMAX (2)
The maximum load current is given by Equation 3.
ILIMITMAX = VCBMAX/RSENSEMIN (3)
For proper operation, the minimum current limit must exceed
the circuit maximum operating load current with margin. The
sense resistor power rating must exceed
(VCBMAX)2/RSENSEMIN
CIRCUIT BREAKER FUNCTION
When the supply experiences a sudden current surge, such as a
low impedance fault on load, the bus supply voltage can drop
significantly to a point where the power to an adjacent card is
affected, potentially causing system malfunctions. The
ADM1170 limits the current drawn by the fault by reducing the
ADM1170 Data Sheet
Rev. A | Page 12 of 16
gate voltage of the external FET. This minimizes the bus supply
voltage drop caused by the fault and protects neighboring cards.
As the voltage across the sense resistor approaches the current
limit, a timer activates. This timer resets again if the sense
voltage returns below this level. If the sense voltage is any
voltage below 44 mV, the timer is guaranteed to be off. Should
the current continue to increase, the ADM1170 tries to regulate
the gate of the FET to achieve a limit of 50 mV across the sense
resistor. However, if the device is unable to regulate the fault
current and the sense voltage further increases, a larger pull-
down, in the order of milliamperes, is enabled to compensate
for fast current surges. If the sense voltage is any voltage greater
than 56 mV, this pull-down is guaranteed to be on. When the
timer expires, the GATE pin shuts down.
TIMER FUNCTION
The TIMER pin is responsible for several key functions on the
ADM1170. A capacitor controls the initial power on reset time
and the amount of time an overcurrent condition lasts before
the FET shuts down. On the ADM1170-1, the timer pin also
controls the time between auto retry pulses. There are pull-up
and pull-down currents internally available to control the timer
functions. The voltage on the TIMER pin is compared with two
threshold voltages: COMP1 (0.2 V) and COMP2 (1.3 V). The
four timing currents are listed in Table 5.
Table 5.
Timing Current Level (μA)
Pull-up 5
Pull-up 60
Pull-down 2
Pull-down 100
POWER-UP TIMING CYCLE
The ADM1170 is in reset when the ON (ON-CLR) pin is held
low. The GATE pin is pulled low and the TIMER pin is pulled
low with a 100 μA pull-down. At Time Point 2 in Figure 33, the
ON (ON-CLR) pin is pulled high. For the device to startup
correctly, the supply voltage must be above UVLO, the ON
(ON-CLR) pin must be above 1.3 V, and the TIMER pin voltage
must be less than 0.2 V. The initial timing cycle begins when these
three conditions are met, and the TIMER pin is pulled high with
5 μA. At Time Point 3, the TIMER reaches the COMP2 threshold.
This is the end of the first section of the initial cycle. The 100 μA
current source then pulls down the TIMER pin until it reaches
0.2 V at Time Point 4. The initial cycle delay (Time Point 2 to
Time Point 4) relates to CTIMER by equation
tINITIAL = 1.3 × CTIMER/5 μA (4)
When the initial cycle ends, a start-up cycle activates and the
GATE pin is pulled high; the TIMER pin continues to pull down.
1
2
NORMAL
CYCLE
INITIAL
CYCLE
START-UP
CYCLE
RESET
MODE
3
4
V
IN
V
ON
V
TIMER
V
GATE
V
OUT
05124-002
Figure 33. Power-Up Timing
2µA
5µA 60µA
100µA
V
IN
V
ON
V
TIMER
V
GATE
V
OUT
I
RSENSE
NORMAL
CYCLE
INITIAL
CYCLE START-UP
CYCLE
RESET
MODE
05124-003
Figure 34. Power-Up into Capacitor
CIRCUIT BREAKER TIMING CYCLE
When the voltage across the sense resistor exceeds the circuit
breaker trip voltage, the 60 μA timer pull-up current is activated.
If the sense voltage falls below this level before the TIMER pin
reaches 1.3 V, the 60 μA pull-up is disabled and the 2 μA pull-
down is enabled. This is likely to happen if the overcurrent fault
is only transient, such as an inrush current. This is shown in
Figure 34. However, if the overcurrent condition is continuous
and the sense voltage remains above the circuit breaker trip
voltage, the 60 μA pull-up remains active. This allows the TIMER
pin to reach the high trip point of 1.3 V and initiate the GATE
shutdown. On the ADM1170-2, the TIMER pin continues pulling
up but switches to the 5 μA pull-up when it reaches the 1.3 V
Data Sheet ADM1170
Rev. A | Page 13 of 16
threshold. The device can be reset by toggling the ON-CLR pin
or by manually pulling the TIMER pin low. On the ADM1170-1,
the TIMER pin activates the 2 µA pull-down once the 1.3 V
threshold is reached, and continues to pull down until it reaches
the 0.2 V threshold. At this point, the 100 µA pull-down is
activated and the GATE pin is enabled. The device keeps
retrying in the manner as shown in Figure 35.
The duty cycle of this automatic retry cycle is set to the ratio of
2 µA/60 µA, which approximates 3.8% on. The value of the
timer capacitor determines the on time of this cycle. This time
is calculated as follows:
tON = 1.3 × CTIMER/60 A
tOFF = 1.1 × CTIMER/2 A
2µA
COMP1COMP2
SHORT-
CIRCUIT
EVENT
60µA
100µA
VTIMER
VOUT
VGSFET
IRSENSE
FAULT
CYCLE
FAULT
CYCLE
0
5124-004
Figure 35. ADM1170-1 Automatic Retry During Overcurrent Fault
AUTOMATIC RETRY OR LATCHED OFF
The ADM1170 is available in two models. The ADM1170-1
has an automatic retry system whereby when a current fault is
detected, the FET is shut down after a time determined by the
timer capacitor, and it is switched on again in a controlled con-
tinuous cycle to determine if the fault remains (see Figure 35
for details). The period of this cycle is determined by the timer
capacitor at a duty cycle of 3.8% on and 96.2% off.
The ADM1170-2 model has a latch off system whereby when a
current fault is detected, the GATE is switched off after a time
determined by the timer capacitor (see Figure 36 for details).
Toggling the ON-CLR pin, or pulling the TIMER pin to GND
for a brief period, resets this condition.
5µA
COMP2
SHORT-
CIRCUIT
EVENT
60µA
V
TIMER
V
OUT
V
GSFET
I
RSENSE
05124-005
Figure 36. ADM1170-2 Latch Off After Overcurrent Fault
SOFT START
The inrush current profile is controlled using an external
capacitor on the soft start (SS) pin. During power on reset, the
SS pin is held at GND. When the pass FET begins to conduct
current, a pull-up current source is initiated on the SS pin and
charges the voltage on the soft start capacitor in a linear fashion.
The current limit of the device is porportional to the voltage on
the SS pin until it reaches 1 V. When the voltage on the SS pin
reaches 1 V the current limit reaches the normal operating
condition of VSENSE = 50 mV. The voltage on the SS pin
continues to rise past the 1 V level with no effect on the current
limit. The reference voltage for the GATE linear control
amplifier is derived from the soft start voltage, such that the
inrush linear current limit is defined as
ILIMIT = VSS/(20 × RSENSE)
This provides a limit of 50 mV across RSENSE when VSS is at 1 V.
Therefore, the value for the SS capacitor is chosen as follows:
CSS = ISS × t
where ISS = 10 A and t is the time required for the current limit
to ramp up.
ADM1170 Data Sheet
Rev. A | Page 14 of 16
OUTLINE DIMENSIONS
13
56
2
8
4
7
2.90 BSC
PIN 1
INDICATOR
1.60 BSC
1.95
BSC
0.65 BSC
0.38
0.22
0.10 MAX
*0.90
0.87
0.84
SEATING
PLANE
*1.00 MAX 0.20
0.08 0.60
0.45
0.30
8°
4°
0°
2.80 BSC
*COMPLIANT TO JEDEC STANDARDS MO-193-BA WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 37. 8-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Branding
ADM1170-1AUJZ-RL7 −40°C to +85°C 8-Lead TSOT UJ-8 M1H
ADM1170-2AUJZ-RL7 −40°C to +85°C 8-Lead TSOT UJ-8 M1J
EVAL-ADM1170EBZ Evaluation Board
1 Z = RoHS Compliant Part.
Data Sheet ADM1170
Rev. A | Page 15 of 16
NOTES
ADM1170 Data Sheet
Rev. A | Page 16 of 16
NOTES
©2006–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05124-0-1/13(A)
