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Features
•Dual Optical Isolator
•Buffers Two Independent Signals
•Power-Down to Hi-Z Doesn't Load Outputs
•Low-Power CMOS Reduces Supply Current
•Output operates Over 2.7V < VDD < 5.5V
•LED Drive Current Only 1.5mA
•High Speed: 10Mbaud Typical
•3750Vrms Galvanic Isolation
•Single 8-Pin DIP or Surface Mount Package
Applications
•Test and Measurement
•A/D and D/A Isolation
•Power Converter Isolation
•Medical
•Ground Loop Elimination
•I2C Bus Isolation
•Computer Bus Isolation
•Isolated Line Receiver
Approvals
•UL Recognized Component: File E76270
•EN/IEC 60950 Certified Component:
TUV Certificate: B 11 10 49410 007
Description
The CPC5002 is a dual high speed optical logic
isolator with open-drain outputs providing 3750Vrms of
galvanic isolation between the inputs and the outputs.
Activating the input LED causes the open-drain output
to turn on, pulling the voltage of the external pullup
resistor towards ground. Utilizing CMOS technology
enables the output stage’s high-gain circuitry to
operate with a miserly power consumption of <5mW
(typical) when operated with a 3.3V supply voltage
and a low input LED drive current of 1.5mA.
Because optical isolators pass logic levels directly
there is no internal state refresh clock to maintain a
non-changing input. Additionally, the CPC5002 will
always return the buffered signals to their proper value
after a transient interruption at either side.
Ordering Information
Figure 1. CPC5002 Functional Block Diagram
RoHS
2002/95/EC
e3
Pb
Part Description
CPC5002G 8-Pin DIP (50 / Tube)
CPC5002GS 8-Pin Surface Mount (50 / Tube)
CPC5002GSTR 8-Pin Surface Mount Tape & Reel (1000 / Reel)
LED
LED
1
2
3
4
8
7
6
5
V
DD
OUT1
OUT2
GND
A1
K1
K2
A2
Dual High-Speed Open-Drain
Digital Optical Isolator
CPC5002
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1. Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.4 ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.5 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.6 General Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.7 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.8 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.9 Switching Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.10 Propagation Delay Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.11 Typical Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2. Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3 Output Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Power Supply Decoupling and Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4. Circuit Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Inverting and Non-Inverting Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5. Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 ESD Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3 Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4 Board Wash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.5 Mechanical Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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1 Specifications
1.1 Package Pinout 1.2 Pin Description
1.3 Absolute Maximum Ratings
Voltages at Output Side nodes are with respect to GND=0V
Absolute maximum electrical ratings are at 25°C. Power specifications: no derating required to 85°C.
Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device.
Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not
implied.
1.4 ESD Rating
1
2
3
4
8
7
6
5
Pin# Name Description
1A1
LED Anode, Channel 1
2K1
LED Cathode, Channel 1
3K2
LED Cathode, Channel 2
4A2
LED Anode, Channel 2
5GND
Ground, Output Side Supply Return
6OUT2
Output, Channel 2
7OUT1
Output, Channel 1
8VDD Supply Voltage, Output Side
Parameter Symbol Rating Units
LED Forward Current
Continuous IF
20 mA
Peak 40
LED Input Power (Each) PIN 72 mW
LED Reverse Voltage VR6.5 V
Supply Voltage, Output Side VDD -0.3 to 6.5 V
Output Voltage VOUT -0.3 to 6.5 V
Output Current IOUT 10 mA
Output Power (Each Output) POUT 65 mW
Isolation Voltage (Input to Output) VISO 3750 Vrms
Operating Temperature T
A-40 to 85 °C
Operating Relative Humidity RH 5 to 85 %
Storage Temperature TSTG -50 to 125 °C
ESD Rating (Human Body Model)
4000V
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1.5 Recommended Operating Conditions
1.6 General Conditions
Specifications cover the operating temperature range TA = -40°C to +85°C and supply range VDD = 2.7V to 5.5V.
Unless otherwise specified, minimum and maximum values are guaranteed by production testing. Typical values are
the result of engineering evaluations and are characteristic of the device at TA = 25°C and VDD = 3.3V; they are
provided for information purposes only and are not verified by manufacturing testing.
1.7 Electrical Specifications
1.8 Thermal Characteristics
Parameter Symbol Min Typ Max Units
Supply Voltage VDD 2.7 - 5.5 V
LED Forward Current IF1.4 1.5 10 mA
Output Drive ISINK 6mA
Operating Ambient Temperature T
A-40 +85 °C
Parameter Conditions Symbol Min Typ Max Units
Input Specifications
LED Input Threshold Current - ITH 0.16 0.55 1 mA
LED Forward Voltage
IF=1.5mA, TA=25°C VF
0.98 1.2 1.41 V
IF=10mA 1.0 1.3 1.8
LED Reverse Breakdown Voltage IR=5AV
R6--V
LED Capacitance VF=0V, f=1MHz CIN -50-pF
Output Specifications
Output Drive VDD=2.7V, ISINK=3mA
VOL
- 0.21 0.35
V
VDD=2.7V, ISINK=6mA -0.420.7
VDD=3.3V, ISINK=6mA -0.38-
High Level Leakage Current VOUT=VDD=5.5V IOHL -0.110A
Supply Specifications
Supply Current VDD=3.3V, ISINK=0mA IDD
-1.4-mA
VDD=5.5V, ISINK=0mA, TA=25°C -2.13
Parameter Conditions Symbol Typ Units
Thermal Resistance, Junction to Ambient Free Air RJA 114 °C/W
LED Temperature Coefficient IF=1.5mA -1.3 mV/°C
Output Voltage Temperature Coefficient ISINK=6mA 1.2 mV/°C
dVF
dT
----------
dVOUT
dT
-----------------
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1.9 Switching Specifications
1Falling propagation delay can be reduced by increasing instantaneous LED current drive, typically by increasing CFWD .
2Rising propagation delay depends on RPU , CL , and IF .
Increasing IF above 2 • ITH (by reducing RS) increases the rising propagation delay.
3Propagation Delay Skew is the worst case difference propagation delay, High to Low and Low to High between the two channels of a CPC5002
when measured using the test circuit shown below, which is tuned for approximately even rising and falling delays.
1.10 Propagation Delay Test Circuit
Parameter Conditions Symbol Min Typ Max Units
Timing Specifications
Clock Frequency ISINK=6mA, CL=20pF fMAX -10-MHz
Propagation Delay
Output Falling 1, 3
IF=1.5mA, VDD=3.3V,
RPU=499, CL=20pF,
0.5VIN to 0.5VDD_OUT
tPHL 35 81 120 ns
Output Rising 2, 3 tPLH 35 81 120
Pulse Width Distortion: |tPLH - tPLH| As per tPHL and tPLH PWD 85 ns
Propagation Delay Skew 3As per tPHL and tPLH tPSK - - 50 ns
Output Fall Time, 90% to 10% IF=1.5mA, VDD=3.3V,
RPU=499, CL=20pF tf10 15 - ns
Common Mode Specifications
Common Mode Transient Immunity VCM=20VP-P , VDD=3.3V, TA=25°C
VOUT = High VOUT>2V CMH5--
kV/s
VOUT = Low VOUT<0.8V CML7--
2kΩ
27pF 3.3V
RPU
499Ω
CL
20pF
VDD
VOUT
½ CPC5002
IF
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1.11 Typical Switching Waveforms
Ty p i c a l @ V DD = 3.3V, IF = 1.5mA, RPU = 499, CL = 20pF
V
IN
V
OUT
0 100n 200n 300n 400n 500n
Time (s)
1.0
0.0
2.0
3.0
4.0
1.0
0.0
2.0
3.0
4.0
(V)(V)
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2 Performance Characteristics
Temperature (ºC)
-50 -30 -10 10 30 50 70 90 110
LED Forward Voltage (V)
1.10
1.12
1.14
1.16
1.18
1.20
1.22
1.24
1.26
1.28
1.30
1.32
LED Forward Voltage
vs. Temperature
IF=2mA
IF=1.5mA
LED Forward Current (mA)
012345678910
LED Forward Voltage (V)
1.19
1.20
1.21
1.22
1.23
1.24
1.25
1.26
1.27
Typical LED Forward Voltage
vs. LED Forward Current
(TA=25ºC)
Temperature (ºC)
-50 -30 -10 10 30 50 70 90 110
LED Current (mA)
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Typical LED Logic Threshold Current
vs. Temperature
ITH_HI
ITH_HI_Typ
ITH_TYP
ITH_LO_Typ
ITH_LO
LED Current (mA)
1.0 1.5 2.0 2.5 3.0 3.5
Delay Time (ns)
40
50
60
70
80
90
100
110
Delay Times vs. LED Current
(CFWD=0pF, VDD=3.3V, RPU=499Ω, CL=20pF)
t
PHL
t
PLH
CFWD (pF)
0 5 10 15 20 25 30
Delay Time (ns)
30
40
50
60
70
80
90
100
110
Delay Times vs. CFEEDFWD
(ILED=1.5mA, VDD=3.3V, RPU=499Ω, CL=20pF)
tPHL
tPLH
Temperature (ºC)
-50 -30 -10 10 30 50 70 90 110
Supply Current (mA)
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
Typical Supply Current
vs. Temperature
VDD=5.5V
VDD=3.3V
VDD=2.7V
Temperature (ºC)
-50 -30 -10 10 30 50 70 90 110
V
OL
(V)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
Typical VOL vs. Temperature
(ISINK=6mA)
V
DD
=2.7V
V
DD
=3.3V
V
DD
=5.5V
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3 Functional Description
3.1 Introduction
The CPC5002 provides two independent galvanically
isolated high speed open-drain output optical isolators
in a single 8-pin package. It exhibits excellent isolation
(3750Vrms) and speed (10Mbps typical), and operates
over a wide range of supply voltages (2.7V to 5.5V).
Because the active circuits have been fabricated in a
CMOS process, the device requires much less supply
current (1.4mA typical with VDD = 3.3V) and can run at
much lower LED currents (1.4mA minimum) than
similar devices fabricated with bipolar processes.
3.2 Functional Description
An open-drain output of the CPC5002 will activate and
sink current when the light generated by the LED and
passed across the barrier to the photodetector is
sufficient. The minimum level of input current
necessary to initiate this behavior is referred to as the
LED Input Threshold Current (ITH) and is a function of
the optical current transfer ratio of the device.
To provide consistent performance over the LED Input
Threshold Current range, the recommended typical
LED drive current (IF) over temperature and all
operating conditions, is 1.5mA. This recommendation
is provided to offer a balance in the propagation
delays on both the falling and rising edges of the
signal pulse being buffered across the barrier. The
absolute value of the mismatch in the delay of these
two edges is Pulse Width Distortion. In the
specifications these delays are identified as tPHL and
tPLH while the distortion is PWD.
In general, choosing a higher LED drive current will
decrease tPHL, the propagation time for the output to
go from high to low. This is mostly due to the LED
generating more light more quickly as it turns on.
However, if IF is more than 2 x ITH then increasing the
LED drive current further will cause tPLH, the
propagation time for the output to go from low to high,
to increase.
Excess levels of IF makes the difference between tPLH
and tPHL (also known as pulse width distortion)
greater. Pulse width distortion is often of interest when
the signal being isolated is a clock. Keeping the LED
drive current near 1.5mA and using the minimum RPU
and CL at the output reduces the worst case pulse
width distortion and is thus recommended for best
waveform fidelity.
When using 1.5mA of LED drive current and when the
CPC5002 is driving a fast output bus (one with
minimum RPU and CL), the average tPHL will usually
be slightly longer than the average tPLH. In this case,
reduction of average pulse width distortion can be
accomplished by using a small feed forward capacitor.
The capacitor boosts the instantaneous current
applied to the LED at turn-on (reducing tPHL) while
leaving the applied DC input current at 1.5mA (tPLH
unchanged). Examples of the feed forward capacitor
(CFWD) are shown in "Figure 1. Inverting
Configuration” on page 9 and "Figure 2.
Non-Inverting Configuration” on page 9.
Increasing the value of the feed forward capacitor
causes tPHL to decrease. For a 499 pullup into a
20pF load capacitance (CL), a 10pF capacitor across
the series resistor will minimize pulse width distortion
of an average unit.
When parallel digital signals are to be isolated,
propagation delay skew (tPSK) becomes important. It
is defined as the absolute value of the difference
between the maximum and minimum propagation
delays (i.e. the worse of tPLH or tPHL) for any group
of optical isolator channels operating under the same
conditions. For the CPC5002, the delay tPLH has a
wider variation with differing optical current transfer
ratios than the delay tPHL. Additionally, tPLH will exhibit
variation due to RPU and CL differences between
channels. If one channel is to be used as a clock and
another for data, it is recommended to use the
CPC5002 output falling edge to latch the data as this
edge will exhibit less channel-to-channel or
part-to-part timing variation and thus will reduce worst
case timing skew.
In general the current transfer ratio matching between
the two channels in a single CPC5002 is better than
the ratio matching between multiple parts. Thus the
channel to channel skew for two signals isolated
through the same CPC5002 will be statistically better
than skew measured between signals isolated through
multiple parts.
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3.3 Output Drivers
Designed specifically for data and clock busses, the
output drivers have been configured for optimal
performance and behavior.
To reduce RF emissions and ringing on the output
lines the active low output drivers are slew limited. In
addition to limiting emissions, the slew limited outputs
reduce the need for external output series resistors.
Whenever the outputs are in the deasserted logic high
state, the open-drain outputs exhibit low leakage
performance while presenting a high impedance
(Hi-Z) to the load. Additionally, during power-up and
with the loss of VDD, the outputs default to the Hi-Z
deasserted state thereby ensuring signal integrity of
any bussed, open-drain signals connected to the
output pins
To maximize system design flexibility, the outputs are
tolerant of pull-up voltages greater than the CPC5002
supply voltage, VDD, provided the pull-up voltage
remains within the output’s specified voltage limits. For
example, using a 3.3V supply to power the CPC5002,
it’s outputs may be safely operated into a pull up
resistor to a supply voltage of 6.5V.
3.4 Power Supply Decoupling and Noise
Reduction
There are no special power supply decoupling
requirements for the CPC5002.
In addition, since the CPC5002 uses optical coupling
to transfer information across the barrier, no internal
clocking circuits are utilized to maintain the proper
output state. This negates the need to implement the
required special layout or noise reduction techniques
necessary to maintain EMI or RFI compliance.
4 Circuit Examples
4.1 Inverting and Non-Inverting Configurations
Shown below are typical inverting and non-inverting
circuit examples with the optional feed forward
capacitors used for high speed signals.
These designs assume a combined voltage drop of
3.3V across the input resistor and the LED with a
nominal input current of 1.5mA.
Figure 1. Inverting Configuration
CFWD increases instantaneous IF at LED turn-on to
reduce tPHL at VOUT .
Figure 2. Non-Inverting Configuration
For applications where the nominal total voltage drop
across the input resistor and the LED is not 3.3V it will
be necessary to adjust the input resistor’s value.
Examples of this would be different pull-up voltage
supplies and VIN sources that do not drive completely
to the supply rails.
RPU
499Ω
3.3V
VIN
CFWD
10pF
VOUT
1.4k
1/2 CPC5002
Inverting: VIN to VOUT
CL
20pF
3.3V
VIN
VOUT
1.4k
1/2 CPC5002
Non-Inverting: VIN to VOUT
V+
RPU
499Ω
CFWD
10pF
CL
20pF
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4.2 Application Example
Shown below is an example of an isolated POE Controller SMBus where the SDA signal has been split into separate
SDAIN and SDOUT signals on the isolated slave side of the barrier. In this example, the low power SMBus master, not
shown, requires a buffer (U3) capable of driving the CPC5002 input LEDs. Although selection of the appropriate
buffer is determined by the product definition and the ability to drive the LED’s, it is recommended the buffer have
Schmitt trigger inputs to ensure clean bounce-free LED drive signals. A high power SMBus master with the ability to
sink 4mA of pullup current may not require a buffer to drive the CPC5002 inputs. In this example, the POE Controllers
are specified as SMBus high power and I2C compatible. This enables the POE Controllers to drive the CPC5002
LEDs directly without the need of an external buffer.
Circuit design of the SMBus physical layer using the CPC5002 consists of two parts, one being the LED input drive
current and the other being the buffered galvanically isolated logic output signals.
The following design constraints are assumed for this example:
•Supply Voltages: VDDx = 3.0V to 3.6V
•Ambient Temperature: TA = 0°C to 70°C
•VOL 0.4V for U3 and the POE Controllers
•IOL 4mA for U3 and the POE Controllers
•Resistors:
•Tolerance = 1%
•Temperature Coefficient = 100ppm
Figure 3. Optically isolated SMBus for POE Controllers with Separate SDAIN and SDAOUT Pins
To minimize pulse width distortion of the output signal, the input LED drive current needs to be set at the lower end of
it’s operational range. Because the forward voltage of the LED has a negative temperature coefficient this will occur at
the minimum operating temperature point with the minimum supply voltage. With VDD = 3.0V and VF= 1.442V at
TA= 0°C and IF= 1.4mA, the calculated maximum value for the series input resistor RS is 826.8. Taking tolerance
and value change due to temperature into account, the nearest E96 standard value sets RS= 806. Using
VOL_Nominal = 0.25V and VOL_Minimum = 0.1V and calculating for the LED current range over the specified operating
conditions with RS= 806, the LED input current IF will be 1.455mA to 3.212mA. At nominal operating conditions with
TA= 25°C, the nominal LED input current is: IF_Nominal = 2.28mA.
SCLM
SDAM
INTM
SCL
SDAIN
SDAOUT
SMBus
POE
Controllers
1
2
3
4
8
7
6
5
CPC5002
3.3VDDS
3.3VDDS
3.3VDDS
3.3VDDS
GNDMGNDS
3.3VDDM
3.3VDDM
3.3VDDM
1
2
3
4
8
7
6
5
CPC5002
R1
806Ω
3.3VDDM
3.3VDDM
GNDS
GNDM
3.3VDDS
3.3VDDS
3.3VDDS
3.3VDDS
0.1μF
0.1μF
0.1μF
0.1μF
3.3VDDM
U3
U1
R2
806Ω
U2
R3
806Ω
R4
806Ω
R9*
R10*
INT
SCL
SDAIN
SDAOUT
INT
R9 and R10 are not required for this design.
See text for explanation.
*
R6
511Ω
R5
511Ω
R7
10k
R8
10k
INTEGRATED CIRCUITS DIVISION
CPC5002
R03 www.ixysic.com 11
For the outputs, the CPC5002 is compatible with both SMBus and Fast-mode I2C compatible devices. As with all
mixed type devices on a bus, the weakest driver on that bus determines the minimum value of the pullup resistor.
When the CPC5002 is the only device driving the bus as shown with U1, the minimum E96 standard value for pullup
resistors R5 and R6 will be 511. For bus loading up to 400pF, this pullup resistor value will provide for Fast-mode
compliant I2C bus speeds. At lower data rates or with less capacitive bus loading, the actual resistor value selected
can be higher.
When the CPC5002 shares a bus with another device as is the case with U2, the weakest driver sets the conditions
for selecting the correct resistor value. As stated earlier, the SMBus master is rated as a Low-power device and
therefore is only capable of sinking 350uA to an output low voltage level of 0.4V. A pullup resistor attached to the
maximum supply voltage level of 3.6V and pulled down by this low power driver limits the minimum pullup resistor
value to 9.14k. After considering tolerance and temperature effects the nearest E96 standard value is 9.31k. Most
applications will typically select the more common 10k value for R7 and R8, which allows for a 5% resistor tolerance.
Although shown but not needed in this example are pullup resistors R9 and R10. These resistors, not needed by the
CPC5002 at U2, are utilized whenever the busses they are attached to are also connected to device(s) having logic
level inputs. With heavy loading or excessive leakage on the bus the resistors provide supplementary bias to improve
pullup transition performance and to increase the output logic high level without impacting the LED input current bias
level.
The CPC5002 can be utilized to provide digital isolated buffering in a variety of unique applications. Design support is
available by contacting IXYS Integrated Circuits Division’s Applications.
INTEGRATED CIRCUITS DIVISION
12 www.ixysic.com R03
CPC5002
5 Manufacturing Information
5.1 Moisture Sensitivity
All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated
Circuits Division classified all of its plastic encapsulated devices for moisture sensitivity according to the
latest version of the joint industry standard, IPC/JEDEC J-STD-020, in force at the time of product
evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee
proper operation of our devices when handled according to the limitations and information in that standard as well as
to any limitations set forth in the information or standards referenced below.
Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced
product performance, reduction of operable life, and/or reduction of overall reliability.
This product carries a Moisture Sensitivity Level (MSL) rating as shown below, and should be handled according to
the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033.
5.2 ESD Sensitivity
This product is ESD Sensitive, and should be handled according to the industry standard
JESD-625.
5.3 Reflow Profile
This product has a maximum body temperature and time rating as shown below. All other guidelines of
J-STD-020 must be observed.
5.4 Board Wash
IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. However, board washing to
remove flux residue is acceptable. Since IXYS Integrated Circuits Division employs the use of silicone coating as an
optical waveguide in many of its optically isolated products, the use of a short drying bake may be necessary if a wash
is used after solder reflow processes. Chlorine-based or Fluorine-based solvents or fluxes should not be used.
Cleaning methods that employ ultrasonic energy should not be used.
Device Moisture Sensitivity Level (MSL) Rating
CPC5002G / CPC5002GS MSL 1
Device Maximum Temperature x Time
CPC5002G / CPC5002GS 250°C for 30 seconds
RoHS
2002/95/EC
e3
Pb
INTEGRATED CIRCUITS DIVISION
CPC5002
R03 www.ixysic.com 13
5.5 Mechanical Information
5.5.1 8-Pin DIP Package
5.5.2 8-Pin Surface Mount Package
Dimensions
mm
(inches)
PCB Hole Pattern
2.540 ± 0.127
(0.100 ± 0.005)
6.350 ± 0.127
(0.250 ± 0.005)
9.144 ± 0.508
(0.360 ± 0.020)
0.457 ± 0.076
(0.018 ± 0.003)
9.652 ± 0.381
(0.380 ± 0.015)
7.239 TYP.
(0.285)
7.620 ± 0.254
(0.300 ± 0.010)
4.064 TYP
(0.160)
0.889 ± 0.102
(0.035 ± 0.004)
8-0.800 DIA.
(8-0.031 DIA.) 2.540 ± 0.127
(0.100 ± 0.005)
7.620 ± 0.127
(0.300 ± 0.005)
7.620 ± 0.127
(0.300 ± 0.005)
6.350 ± 0.127
(0.250 ± 0.005)
3.302 ± 0.051
(0.130 ± 0.002)
0.254 TYP
(0.01)
Pin 1
Dimensions
mm
(inches)
PCB Land Pattern
2.540 ± 0.127
(0.100 ± 0.005)
9.652 ± 0.381
(0.380 ± 0.015)
6.350 ± 0.127
(0.250 ± 0.005)
9.525 ± 0.254
(0.375 ± 0.010)
0.457 ± 0.076
(0.018 ± 0.003)
0.813 ± 0.120
(0.032 ± 0.004)
4.445 ± 0.127
(0.175 ± 0.005)
7.620 ± 0.254
(0.300 ± 0.010)
0.635 ± 0.127
(0.025 ± 0.005)
0.254 ± 0.0127
(0.010 ± 0.0005)
2.54
(0.10)
8.90
(0.3503)
1.65
(0.0649)
0.65
(0.0255)
3.302 ± 0.051
(0.130 ± 0.002)
Pin 1
INTEGRATED CIRCUITS DIVISION
14 www.ixysic.com R03
CPC5002
5.5.3 Tape & Reel Packaging
Dimensions
mm
(inches)
User Direction of Feed
NOTES:
1. Dimensions carry tolerances of EIA Standard 481-2
2. Tape complies with all “Notes” for constant dimensions listed on page 5 of EIA-481-2
Embossment
Embossed Carrier
Top Cover
Tape Thickness
0.102 MAX.
(0.004 MAX.)
330.2 DIA.
(13.00 DIA.)
K1
=4.20
(0.165)
0
K =4.90
(0.193)
P=12.00
(0.472)
W=16.00
(0.63)
Bo=10.30
(0.406)
Ao=10.30
(0.406)
For additional information please visit our website at: www.ixysic.com
IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated
Circuits Division’s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its
products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other
applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division’s product may result in direct physical harm, injury, or death to a person or severe
property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice.
Specification: DS-CPC5002-R03
©Copyright 2012, IXYS Integrated Circuits Division
All rights reserved. Printed in USA.
9/4/2012
