© 1999 Fairchild Semiconductor Corporation DS009928 www.fairchildsemi.com
November 1988
Revised November 1999
74AC153 • 74ACT153 Dual 4-Input Multiplexer
74AC153 74ACT153
Dual 4-Input Multiplexer
General Description
The AC/ACT153 is a high-speed dual 4-input multiplexer
with comm on select inpu ts and in dividu al enab le inputs f or
each section. It can select two lines of data from four
sources. T he t wo buffered outpu ts pre sent d ata in the true
(non-inverted) form. In addition to multiplexer operation,
the AC/ACT153 can act as a function generator and gener-
ate any two functions of three variables.
Features
ICC reduced by 50%
Outputs source/sink 24 mA
ACT153 has TTL-compatible inputs
Ordering Code:
Device a ls o av ailable in Tape and Reel. Specify by a ppending s uffix let te r “X” to the or dering co de.
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74AC153SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Body
74AC153SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC153MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC153PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACT153SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Body
74ACT153MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pin Names Description
I0aI3a Side A Data Inputs
I0bI3b Side B Data Inputs
S0, S1 Common Select Inputs
Ea Side A Enable Input
Eb Side B Enable Input
Za Side A Output
Zb Side B Output
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74AC153 74ACT153
Functional Description
The AC /ACT153 is a dual 4-input multiplexe r. It can select
two bits of data from up to four sources under the control of
the common Select inputs (S0, S1). The two 4-input mu lti-
plex er cir c ui ts ha v e in di vi d ua l ac t i ve- L OW En ab les ( E a, Eb)
which can be used to strobe the outputs independently.
When the Enables (Ea, Eb) are HIGH, the corresponding
outputs Za, Zb) are forced LOW. The AC/ACT153 is the
logic implementation of a 2-pole, 4-position switch, where
the posi tion of the swit ch is determined b y the logic levels
supplied to the Select inputs. The logic equations for the
outputs are shown bel o w.
Za = Ea (I0a S1 S0 + I1a S1 S0 +
I2a S1 S0 + I3a S1 S0)
Zb = Eb (I0b S1 S0 + I1b S1 S0 +
I2b S1 S0 + I3b S1 S0)
Truth Table
H = HIGH Voltage Lev el
L = LOW Voltage Level
X = Immaterial
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Select Inputs (a or b) Output
Inputs
S0S1EI0I1I2I3Z
XXHXXXX L
LLLLXXX L
LLLHXXX H
HLLX LXX L
HLL X HXX H
LHLX XLX L
LHLX XHX H
HHLX XXL L
HHLX XXH H
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74AC153 74ACT153
Absolute Maximum Ratings(Note 1) Recommended Operating
Conditions
Note 1: Absol ut e ma x i mu m rat ings are thos e v alue s beyond wh ich damage
to the dev ice may occ ur. The databoo k specific ations sh ould be m et, with-
out exc eption, to e nsure that the system des ign is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside da t abook spe c if ic at ions.
DC Electrical Characteristics for AC
Note 2: All outputs lo aded; thre sholds on input as s oc iated with outpu t un der test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are gu aranteed to be less t han or equa l t o th e respectiv e limit @ 5.5V VCC.
Supply Voltage ( VCC) 0.5V to +7.0V
DC Input Diode Current (IIK)
V
I = 0.5V 20 mA
V
I = VCC + 0.5V +20 mA
DC Input Vo ltage (VI) 0.5V to VCC + 0.5V
DC Output Diode Current (IOK)
V
O = 0.5V 20 mA
V
O = VCC + 0.5V +20 mA
DC Output Voltage (VO) 0.5V to VCC + 0.5V
DC Output Source
or Sink Current (IO) ±50 mA
DC VCC or Ground Curre nt
per Output Pin (ICC or IGND) ±50 mA
Storage Temperature (TSTG) 65°C to +150°C
Junction Temperature (TJ)
PDIP 140°C
Supply Voltage (VCC)
AC 2.0V to 6.0V
ACT 4.5V to 5.5V
Input Voltage (VI) 0V to VCC
Output Voltage (VO) 0V to VCC
Operating Temperature (TA) 40°C to +85°C
Minimum Input Edge Rate (V/t)
AC Devices
V
IN from 30% to 70% of VCC
V
CC @ 3.3V, 4.5V, 5.5V 125 mV/ns
Minimum Input Edge Rate (V/t)
ACT Devices
V
IN from 0.8V to 2.0V
V
CC @ 4.5V, 5.5V 125 mV/ns
Symbol Parameter VCC TA = +25°CT
A = 40°C to +85°CUnits Conditions
(V) Typ Guaranteed Limits
VIH Minimum HIGH Level 3.0 1.5 2.1 2.1 VOUT = 0.1V
Input Voltage 4.5 2.25 3.15 3.15 V or VCC 0.1V
5.5 2.75 3.85 3.85
VIL Maximum LOW Level 3.0 1.5 0.9 0.9 VOUT = 0.1V
Input Voltage 4.5 2.25 1.35 1.35 V or VCC 0.1V
5.5 2.75 1.65 1.65
VOH Minimum HIGH Level 3.0 2.99 2.9 2.9
Output Voltage 4.5 4.49 4.4 4.4 V IOUT = 50 µA
5.5 5.49 5.4 5.4 VIN = VIL or VIH
3.0 2.56 2.46 IOH = 12 mA
4.5 3.86 3.76 V IOH = 24 mA
5.5 4.86 4.76 IOH = 24 mA (Note 2)
VOL Maximum LOW Level 3.0 0.002 0.1 0.1
Output Voltage 4.5 0.001 0.1 0.1 V IOUT = 50 µA
5.5 0.001 0.1 0.1 VIN = VIL or VIH
3.0 0.36 0.44 IOL = 12 mA
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 2)
IIN Maximum Input 5.5 ±0.1 ±1.0 µAV
I = VCC, GND
(Note 4) Leakage Current
IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max
IOHD Output Current (Note 3) 5.5 75 mA VOHD = 3.85V Min
ICC Maximum Quiescent 5.5 4.0 40.0 µAVIN = VCC
(Note 4) Supply Current or GND
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74AC153 74ACT153
DC Electrical Characteristics for ACT
Note 5: All outputs loaded; th resholds on input associate d w it h output under tes t.
Note 6: Maximum test du ration 2.0 m s, one out put loaded a t a tim e.
AC Electrical Characteristics for AC
Note 7: Voltage Range 3.3 is 3.3V ± 0 3V
Voltage Range 5. 0 is 5. 0V ± 0.5V
Symbol Parameter VCC TA = +25°CT
A = 40°C to +85°CUnits Conditions
(V) Typ Guaranteed Limits
VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 V VOUT = 0.1V
Input Voltage 5.5 1.5 2.0 2.0 or VCC 0.1V
VIL Maximum LOW Level 4.5 1.5 0.8 0.8 V VOUT = 0.1V
Input Voltage 5.5 1.5 0.8 0.8 or VCC 0.1V
VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 V I
OUT = 50 µA
Output Voltage 5.5 5.49 5.4 5.4 VIN = VIL or VIH
4.5 3.86 3.76 V IOH = 24 mA
5.5 4.86 4.76 IOH = 24 mA (Note 5)
VOL Maximum LOW Level 4.5 0.001 0.1 0.1 V I
OUT = 50 µA
Output Voltage 5.5 0.001 0.1 0.1 VIN = VIL or VIH
4.5 0.36 0.44 V IOL = 24 mA
5.5 0.36 0.44 IOL = 24 mA (Note 5)
IIN Maximum Input 5.5 ±0.1 ±1.0 µA V
I = VCC, GND
Leakage Current
ICCT Maximum 5.5 0.6 1.5 mA VI = VCC 2.1V
ICC/Input
IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max
IOHD Output Current (Note 6) 5.5 75 mA VOHD = 3.85V Min
ICC Maximum Quiescent 5.5 4.0 40.0 µA VIN = VCC
Supply Current or GND
VCC TA = +25°CT
A = 40°C to +85°C
Symbol Parameter (V) CL = 50 pF CL = 50 pF Units
(Note 7) Min Typ Max Min Max
tPLH Propagation Delay 3.3 2.5 9.5 15.0 2.5 17.5 ns
Sn to Z n 5.0 2.0 6.5 11.0 2.0 12.5
tPHL Propagation Delay 3.3 3.0 8.5 14.5 2.5 16.5 ns
Sn to Z n 5.0 2.5 6.5 11.0 2.0 12.0
tPLH Propagation Delay 3.3 2.5 8.0 13.5 2.0 16.0 ns
E to Zn 5.0 1.5 5.5 9.5 1.5 11.0
tPHL Propagation Delay 3.3 2.5 7.0 11.0 2.0 12.5 ns
E to Zn 5.0 2.0 5.0 8.0 1.5 9.0
tPLH Propagation Delay 3.3 2.5 7.5 12.5 2.0 14.5 ns
In to Zn 5.0 1.5 5.5 9.0 1.5 10.5
tPHL Propagation Delay 3.3 1.5 7.0 11.5 1.5 13.0 ns
In to Zn 5.0 1.5 5.0 8.5 1.5 10.0
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74AC153 74ACT153
AC Electrical Characteristics for ACT
Note 8: Vo lt age Range 5.0 is 5.0V ± 0.5V
Capacitance
VCC TA = +25°CT
A = 40°C to +85°C
Symbol Parameter (V) CL = 50 pF CL = 50 pF Units
(Note 8) Min Typ Max Min Max
tPLH Propagation Delay 5.0 3.0 7.0 11.5 2.0 13.5 ns
Sn to Zn
tPHL Propagation Delay 5.0 3.0 7.0 11.5 2.5 13.5 ns
Sn to Zn
tPLH Propagation Delay 5.0 2.0 6.5 10.5 2.0 12.5 ns
En to Zn
tPHL Propagation Delay 5.0 3.0 6.0 9.5 2.5 11.0 ns
En to Zn
tPLH Propagation Delay 5.0 2.5 5.5 9.5 2.0 11.0 ns
In to Zn
tPHL Propagation Delay 5.0 2.0 5.5 9.5 2.0 11.0 ns
In to Zn
Symbol Parameter Typ Units Conditions
CIN Input Capacitance 4.5 pF VCC = OPEN
CPD Power Dissipation Capacitance 65.0 pF VCC = 5.0V
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74AC153 74ACT153
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Out line Integrated Circuit (SOIC), JEDEC MS-012, 0. 150 Narrow Body
Package Number M16A
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74AC153 74ACT153
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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74AC153 74ACT153
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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74AC153 74ACT153 Dual 4-Input Multiplexer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-L ead P lastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume an y responsibility for u se of any circuitry descr ibed, no circuit pat ent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use pr ovi de d in the l abe ling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A crit ical componen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause th e fa i lure of the l ife s upport
device or system, or to affect its safety or effectiveness.
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