MC14632.7680KA-A0:ROHS - EPSON ELECTRONICS AMERICA

FEATURES

DESCRIPTION/ORDERING INFORMATION

TL16C550D , , TL16C550DI

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

ASYNCHRONOUS COMMUNICATIONS ELEMENTWITH AUTOFLOW CONTROL

•Programmable Auto- RTS and Auto- CTS •Standard Asynchronous Communication Bits(Start, Stop, and Parity) Added to or Deleted•In Auto- CTS Mode, CTS Controls Transmitter

From the Serial Data Stream•In Auto- RTS Mode, RCV FIFO Contents and

•5-V, 3.3-V, and 2.5-V OperationThreshold Control RTS

•Independent Receiver Clock Input•Serial and Modem Control Outputs Drive aRJ11 Cable Directly When Equipment Is on the •Transmit, Receive, Line Status, and Data SetSame Power Drop Interrupts Independently Controlled•Capable of Running With All Existing •Fully Programmable Serial InterfaceTL16C450 Software Characteristics:•After Reset, All Registers Are Identical to the – 5-, 6-, 7-, or 8-Bit CharactersTL16C450 Register Set

– Even-, Odd-, or No-Parity Bit Generation•Up to 24-MHz Clock Rate for up to 1.5-Mbaud and DetectionOperation With V

= 5 V

– 1-, 1 ＝-, or 2-Stop Bit Generation•Up to 20-MHz Clock Rate for up to 1.25-Mbaud

– Baud Generation (dc to 1 Mbit/s)Operation With V

= 3.3 V

•False-Start Bit Detection•Up to 48-MHz Clock Rate for up to 3-Mbaud

•Complete Status Reporting CapabilitiesOperation with V

= 3.3 V (ZQS Package Only,

•3-State Output TTL Drive Capabilities forDivisor = 1)

Bidirectional Data Bus and Control Bus•Up to 40-MHz Clock Rate for up to 2.5-Mbaud

•Line Break Generation and DetectionOperation with V

= 3.3 V (ZQS Package Only,

•Internal Diagnostic Capabilities:Divisor ≥2)

– Loopback Controls for Communications•Up to 16-MHz Clock Rate for up to 1-Mbaud

Link Fault IsolationOperation With V

= 2.5 V

– Break, Parity, Overrun, and Framing Error•In the TL16C450 Mode, Hold and Shift

SimulationRegisters Eliminate the Need for PreciseSynchronization Between the CPU and Serial •Fully Prioritized Interrupt System ControlsData

•Modem Control Functions ( CTS, RTS, DSR,•Programmable Baud Rate Generator Allows DTR, RI, and DCD)Division of Any Input Reference Clock by 1 to

•Available in 48-Pin PT, 48-Pin PFB, 32-Pin(2

– 1) and Generates an Internal 16 × Clock

RHB, and 24-Pin ZQS Packages

The TL16C550D and the TL16C550DI are speed and operating voltage upgrades (but functional equivalents) ofthe TL16C550C asynchronous communications element (ACE), which in turn is a functional upgrade of theTL16C450. Functionally equivalent to the TL16C450 on power up (character or TL16C450 mode), theTL16C550D and the TL16C550DI, like the TL16C550C, can be placed in an alternate FIFO mode. This relievesthe CPU of excessive software overhead by buffering received and transmitted characters. The receiver andtransmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiverFIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce softwareoverload and increase system efficiency by automatically controlling serial data flow using RTS output and CTSinput signals.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2004 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.

NC - No internal connection

RD1

VSS

WR1

XOUT

XIN

DSR

DCD

VCC

RHB PACKAGE

(TOP VIEW)

23 22 21 20 19

24 18

CTS

DTR

RTS

INTRPT

2 3 4 5 6 7 8

SOUT

CS2

SIN

NC - No internal connection

14 15

OUT1

DTR

RTS

OUT2

INTRPT

RXRDY

RCLK

SIN

SOUT

CS0

CS1

CS2

BAUDOUT

17 18 19 20

PT/PFB PACKAGE

(TOP VIEW)

DCD

DSR

CTS

47 46 45 44 4348 42

DDIS

TXRDY

ADS

XOUT

WR1

WR2

RD1

RD2

40 39 3841

21 22 23 24

VCC

XIN

VSS

ZQS PACKAGE

(TOP VIEW)

1 2 345

TL16C550D , , TL16C550DI

SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 ..................................................................................................................................................

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The TL16C550D and TL16C550DI perform serial-to-parallel conversions on data received from a peripheraldevice or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read the ACEstatus at any time. The ACE includes complete modem control capability and a processor interrupt system thatcan be tailored to minimize software management of the communications link.

Both the TL16C550D and the TL16C550DI ACE include a programmable baud rate generator capable of dividinga reference clock by divisors from 1 to 65535 and producing a 16 × reference clock for the internal transmitterlogic. Provisions are included to use this 16 × clock for the receiver logic. The ACE accommodates up to a1.5-Mbaud serial rate (24-MHz input clock) so that a bit time is 667 ns and a typical character time is 6.7 µs (startbit, 8 data bits, stop bit).

Two of the TL16C450 terminal functions on the TL16C550D and the TL16C550DI have been changed to TXRDYand RXRDY, which provide signaling to a DMA controller.

The TL16C550D is being made available in a reduced pin count package, the 32-pin RHB package. This isaccomplished by eliminating some signals that are not required for some applications. These include the CS0,CS1, ADS, RD2, WR2, and RCLK input signals and the DDIS, TXRDY, RXRDY, OUT1, OUT2, and BAUDOUToutput signals. There is an internal connection between BAUDOUT and RCLK.

All of the functionality of the TL16C550D is maintained in the RHB package.

TERMINAL ASSIGNMENTS(24-Ball ZQS Package) (continued)

(24-Ball ZQS Package)

1 2 3 4 5

AD5 D4 D2 D0 V

BD7 D3 D1 MR

CSIN SOUT D6 CTS RTS

DCS2 WR1 RD1 INTRPT A0

EXIN XOUT V

A2 A1

TERMINAL ASSIGNMENTS

Product Folder Link(s): TL16C550D TL16C550DI

DETAILED DESCRIPTION

Autoflow Control (see Figure 1 )

Auto- RTS (see Figure 1 )

Auto- CTS (see Figure 1 )

TL16C550D , , TL16C550DI

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

The TL16C550D is being made available in a reduced pin count package, the 24-pin ZQS package. This isaccomplished by eliminating some signals that are not required for some applications. These include the CS0,CS1, ADS, RD2, WR2, DSR, RI, DCD, and RCLK input signals and the DDIS, TXRDY, RXRDY, OUT1, OUT2,DTR, and BAUDOUT output signals. There is an internal connection between BAUDOUT and RCLK.

Most of the functionality of the TL16C550D is maintained in the ZQS package, except that which involves theeliminated signals.

Autoflow control comprises auto- CTS and auto- RTS. With auto- CTS, the CTS input must be active before thetransmitter FIFO can emit data. With auto- RTS, RTS becomes active when the receiver needs more data andnotifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless thereceiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from aTLC16C550D with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceedsthe receiver FIFO read latency.

Figure 1. Autoflow Control (Auto- RTS and Auto- CTS) Example

Auto- RTS data flow control originates in the receiver timing and control block (see functional block diagram) andis linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of1, 4, or 8 (see Figure 3 ), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send anadditional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because itmay not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS isautomatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.

When the trigger level is 14 (see Figure 4 ), RTS is deasserted after the first data bit of the 16th character ispresent on the SIN line. RTS is reasserted when the RCV FIFO has at least one available byte space.

The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the nextbyte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the laststop bit that is currently being sent (see Figure 2 ). The auto- CTS function reduces interrupts to the host system.When flow control is enabled, CTS level changes do not trigger host interrupts because the device automaticallycontrols its own transmitter. Without auto- CTS, the transmitter sends any data present in the transmit FIFO and areceiver overrun error may result.

Product Folder Link(s): TL16C550D TL16C550DI

Enabling Autoflow Control and Auto- CTS

Auto- CTS and Auto- RTS Functional Timing

Byte 18

TL16C550D , , TL16C550DI

SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 ..................................................................................................................................................

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Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 ( RTS) to a 1.Autoflow incorporates both auto- RTS and auto- CTS. When only auto- CTS is desired, bit 1 in the modem controlregister must be cleared (this assumes that a control signal is driving CTS).

A. When CTS is low, the transmitter keeps sending serial data out.B. If CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the currentbyte but it does not send the next byte.C. When CTS goes from high to low, the transmitter begins sending data again.

Figure 2. CTS Functional Timing Waveforms

The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figure 3 and Figure 4 .

A. N = RCV FIFO trigger level (1, 4, or 8 bytes)B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the precedingauto- RTS section.

Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes

A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full afterfinishing the sixteenth byte.B. RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing orthere is more than one byte of space available.C. When the receive FIFO is full, the first receive buffer register read reasserts RTS.

Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes

Product Folder Link(s): TL16C550D TL16C550DI

Receiver

Buffer

Divisor

Latch (LS)

Divisor

Latch (MS)

Baud

Generator

Receiver

FIFO

Line

Status

Transmitter

Holding

Modem

Control

Modem

Status

Line

Control

Transmitter

FIFO

Interrupt

Enable

Interrupt

Identification

FIFO

Control

Select

and

Control

Logic

Interrupt

Control

Logic

Data

Bus

Buffer

BAUDOUT

SIN

RCLK

SOUT

CTS

DTR

DSR

DCD

OUT1

OUT2

INTRPT

A0 28

D(7- 0)

4-2

47-43

Internal

Data Bus

CS0

CS1

CS2

ADS

RD1

RD2

WR1

WR2

DDIS

TXRDY

XIN

XOUT

RXRDY

Receiver

Shift

Receiver

Timing and

Control

Transmitter

Timing and

Control

Transmitter

Shift

Modem

Control

Logic

VCC

VSS

Power

Supply

RTS

Autoflow Control

(AFE)

TL16C550D , , TL16C550DI

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

FUNCTIONAL BLOCK DIAGRAM (For PT and PFB Packages)

Product Folder Link(s): TL16C550D TL16C550DI

Receiver

Buffer

Divisor

Latch (LS)

Divisor

Latch (MS)

Baud

Generator

Receiver

FIFO

Line

Status

Transmitter

Holding

Modem

Control

Modem

Status

Line

Control

Transmitter

FIFO

Interrupt

Enable

Interrupt

Identification

FIFO

Control

Select

and

Control

Logic

Interrupt

Control

Logic

Data

Bus

Buffer

SIN

SOUT

CTS

DTR

DSR

DCD

INTRPT

A0 19

D(7- 0)

5-3

32-29

Internal

Data Bus

CS2

RD1

WR1

XIN

XOUT

Receiver

Shift

Receiver

Timing and

Control

Transmitter

Timing and

Control

Transmitter

Shift

Modem

Control

Logic

VCC

VSS

Power

Supply

RTS

Autoflow

Control

(AFE)

TL16C550D , , TL16C550DI

SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 ..................................................................................................................................................

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FUNCTIONAL BLOCK DIAGRAM (For RHB Package)

Product Folder Link(s): TL16C550D TL16C550DI

Receiver

Buffer

Divisor

Latch (LS)

Divisor

Latch (MS)

Baud

Generator

Receiver

FIFO

Line

Status

Transmitter

Holding

Modem

Control

Modem

Status

Line

Control

Transmitter

FIFO

Interrupt

Enable

Interrupt

Identification

FIFO

Control

Select

and

Control

Logic

Interrupt

Control

Logic

Data

Bus

Buffer

SIN

SOUT

CTS

INTRPT

A0 D5

D(7- 0)

5-3

32-29

Internal

Data Bus

CS2

RD1

WR1

XIN

XOUT

Receiver

Shift

Receiver

Timing and

Control

Transmitter

Timing and

Control

Transmitter

Shift

Modem

Control

Logic

VCC

VSS

Power

Supply

RTS

Autoflow

Control

(AFE)

TL16C550D , , TL16C550DI

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

FUNCTIONAL BLOCK DIAGRAM (For ZQS Package)

Product Folder Link(s): TL16C550D TL16C550DI

TL16C550D , , TL16C550DI

SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 ..................................................................................................................................................

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TERMINAL FUNCTIONS (FOR PT/PFB PACKAGES)

TERMINAL

I/O DESCRIPTIONNAME NO.

A0 28

to read from or write to. See Table 1 for register addresses, and see the ADS description.A2 26

Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1, and CS2 drive theADS 24 I internal select logic directly; when ADS is high, the register select and chip select signals areheld at the logic levels they were in when the low-to-high transition of ADS occurred.Baud out. BAUDOUT is a 16 × clock signal for the transmitter section of the ACE. The clockrate is established by the reference oscillator frequency divided by a divisor specified by theBAUDOUT 12 O

baud generator divisor latches. BAUDOUT may also be used for the receiver section by tyingthis output to RCLK.CS0 9

Chip select. When CS0 and CS1 are high and CS2 is low, these three inputs select the ACE.CS1 10 I

When any of these inputs are inactive, the ACE remains inactive (see the ADS description).CS2 11

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4( CTS) of the modem status register. Bit 0 ( ΔCTS) of the modem status register indicates thatCTS 38 I CTS has changed states since the last read from the modem status register. If the modemstatus interrupt is enabled when CTS changes levels and the auto- CTS mode is not enabled,an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter.D0 43D1 44D2 45D3 46 Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control,I/OD4 47 and status information between the ACE and the CPU.D5 2D6 3D7 4

Data carrier detect. DCD is a modem status signal. Its condition can be checked by readingbit 7 ( DCD) of the modem status register. Bit 3 ( ΔDCD) of the modem status registerDCD 40 I

indicates that DCD has changed states since the last read from the modem status register. Ifthe modem status interrupt is enabled when DCD changes levels, an interrupt is generated.Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDISDDIS 22 O

can disable an external transceiver.Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5( DSR) of the modem status register. Bit 1 ( ΔDSR) of the modem status register indicatesDSR 39 I

DSR has changed levels since the last read from the modem status register. If the modemstatus interrupt is enabled when DSR changes levels, an interrupt is generated.Data terminal ready. When active (low), DTR informs a modem or data set that the ACE isready to establish communication. DTR is placed in the active level by setting the DTR bit ofDTR 33 O

the modem control register. DTR is placed in the inactive level either as a result of a masterreset, during loop mode operation, or clearing the DTR bit.Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to beserviced. Four conditions that cause an interrupt to be issued are: a receiver error, receivedINTRPT 30 O data that is available or timed out (FIFO mode only), an empty transmitter holding register, oran enabled modem status interrupt. INTRPT is reset (deactivated) either when the interruptis serviced or as a result of a master reset.Master reset. When active (high), MR clears most ACE registers and sets the levels ofMR 35

various output signals (see Table 2).1,6,13,NC 21, 25, 36, I No connection37, 48

Outputs 1 and 2. These are user-designated output terminals that are set to the active (low)OUT1 34 level by setting respective modem control register (MCR) bits ( OUT1 and OUT2). OUT1 andOOUT2 31 OUT2 are set to inactive the (high) level as a result of master reset, during loop modeoperations, or by clearing bit 2 ( OUT1) or bit 3 ( OUT2) of the MCR.RCLK 5 I Receiver clock. RCLK is the 16 × baud rate clock for the receiver section of the ACE.Read inputs. When either RD1 or RD2 is active (low or high, respectively) while the ACE isRD1 19 selected, the CPU is allowed to read status information or data from a selected ACE register.IRD2 20 Only one of these inputs is required for the transfer of data during a read operation; the otherinput must be tied to its inactive level (i.e., RD2 tied low or RD1 tied high).

Product Folder Link(s): TL16C550D TL16C550DI

TL16C550D , , TL16C550DI

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

TERMINAL FUNCTIONS (FOR PT/PFB PACKAGES) (continued)

TERMINAL

I/O DESCRIPTIONNAME NO.

Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6( RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that RIRI 41 I has transitioned from a low to a high level since the last read from the modem statusregister. If the modem status interrupt is enabled when this transition occurs, an interrupt isgenerated.

Request to send. When active, RTS informs the modem or data set that the ACE is ready toreceive data. RTS is set to the active level by setting the RTS modem control register bit andRTS 32 O is set to the inactive (high) level either as a result of a master reset or during loop modeoperations or by clearing bit 1 ( RTS) of the MCR. In the auto- RTS mode, RTS is set to theinactive level by the receiver threshold control logic.Receiver ready. Receiver direct memory access (DMA) signaling is available with RXRDY.When operating in the FIFO mode, one of two types of DMA signaling can be selected usingthe FIFO control register bit 3 (FCR3). When operating in the TL16C450 mode, only DMAmode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is madebetween CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers aremade continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 orRXRDY 29 O

FCR0 = 1, FCR3 = 0), when there is at least one character in the receiver FIFO or receiverholding register, RXRDY is active (low). When RXRDY has been active but there are nocharacters in the FIFO or holding register, RXRDY goes inactive (high). In DMA mode 1(FCR0 = 1, FCR3 = 1), when the trigger level or the time-out has been reached, RXRDYgoes active (low); when it has been active but there are no more characters in the FIFO orholding register, it goes inactive (high).SIN 7 I Serial data input. SIN is serial data input from a connected communications device.Serial data output. SOUT is composite serial data output to a connected communicationSOUT 8 O

device. SOUT is set to the marking (high) level as a result of master reset.Transmitter ready. Transmitter DMA signaling is available with TXRDY. When operating inthe FIFO mode, one of two types of DMA signaling can be selected using FCR3. Whenoperating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supportsTXRDY 23 O

single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supportsmultitransfer DMA in which multiple transfers are made continuously until the transmit FIFOhas been filled.V

42 2.25-V to 5.5-V power supply voltageV

18 Supply common

Write inputs. When either WR1 or WR2 is active (low or high, respectively) and while theWR1 16 ACE is selected, the CPU is allowed to write control words or data into a selected ACEIWR2 17 register. Only one of these inputs is required to transfer data during a write operation; theother input must be tied to its inactive level (i.e., WR2 tied low or WR1 tied high).XIN 14 External clock. XIN and XOUT connect the ACE to the main timing reference (clock orI/OXOUT 15 crystal).

Product Folder Link(s): TL16C550D TL16C550DI

TL16C550D , , TL16C550DI

SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 ..................................................................................................................................................

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TERMINAL FUNCTIONS (FOR RHB PACKAGE)

TERMINAL

I/O DESCRIPTIONNAME NO.

A0 19

to read from or write to. See Table 1 for register addresses, and see the ADS description.A2 17

Chip select. When CS0 and CS1 are high and CS2 is low, these three inputs select the ACE.CS2 8 I

When any of these inputs are inactive, the ACE remains inactive (see the ADS description).Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4( CTS) of the modem status register. Bit 0 ( ΔCTS) of the modem status register indicates thatCTS 24 I CTS has changed states since the last read from the modem status register. If the modemstatus interrupt is enabled when CTS changes levels and the auto- CTS mode is not enabled,an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter.D0 29D1 30D2 31D3 32 Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control,I/OD4 1 and status information between the ACE and the CPU.D5 3D6 4D7 5

Data carrier detect. DCD is a modem status signal. Its condition can be checked by readingbit 7 ( DCD) of the modem status register. Bit 3 ( ΔDCD) of the modem status registerDCD 26 I

indicates that DCD has changed states since the last read from the modem status register. Ifthe modem status interrupt is enabled when DCD changes levels, an interrupt is generated.Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5( DSR) of the modem status register. Bit 1 ( ΔDSR) of the modem status register indicatesDSR 39 I

various output signals (see Table 2).2,9,NC I No connection15, 16,

Read inputs. When either RD1 or RD2 is active (low or high, respectively) while the ACE isRD1 14 I

selected, the CPU is allowed to read status information or data from a selected ACE register.Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6( RI) of the modem status register. Bit 2 (TERI) of the modem status register indicates that RIRI 27 I has transitioned from a low to a high level since the last read from the modem statusregister. If the modem status interrupt is enabled when this transition occurs, an interrupt isgenerated.

device. SOUT is set to the marking (high) level as a result of master reset.V

28 2.25-V to 5.5-V power supply voltageV

13 Supply common

Write inputs. When either WR1 or WR2 is active (low or high, respectively) and while theWR1 12 I ACE is selected, the CPU is allowed to write control words or data into a selected ACEregister.

Product Folder Link(s): TL16C550D TL16C550DI

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

TERMINAL FUNCTIONS (FOR RHB PACKAGE) (continued)

TERMINAL

I/O DESCRIPTIONNAME NO.

XIN 10 External clock. XIN and XOUT connect the ACE to the main timing reference (clock orI/OXOUT 11 crystal).

Product Folder Link(s): TL16C550D TL16C550DI

TL16C550D , , TL16C550DI

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TERMINAL FUNCTIONS (FOR ZQS PACKAGE)

TERMINAL

I/O DESCRIPTIONNAME NO.

A0 D5

to read from or write to. See Table 1 for register addresses, and see the ADS description.A2 E4

Chip select. When CS2 is low, the ACE is selected. When CS2 is high, the ACE remainsCS2 D1 I

inactive.

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4( CTS) of the modem status register. Bit 0 ( ΔCTS) of the modem status register indicates thatCTS C4 I CTS has changed states since the last read from the modem status register. If the modemstatus interrupt is enabled when CTS changes levels and the auto- CTS mode is not enabled,an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter.D0 A4D1 B4D2 A3D3 B3 Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control,I/OD4 A2 and status information between the ACE and the CPU.D5 A1D6 C3D7 B1

Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to beserviced. Four conditions that cause an interrupt to be issued are: a receiver error, receivedINTRPT D4 O data that is available or timed out (FIFO mode only), an empty transmitter holding register, oran enabled modem status interrupt. INTRPT is reset (deactivated) either when the interruptis serviced or as a result of a master reset.Master reset. When active (high), MR clears most ACE registers and sets the levels ofMR B5

various output signals (see Table 2).Read input. When RD1 is active (low) while the ACE is selected, the CPU is allowed to readRD1 D3 I

status information or data from a selected ACE register.Request to send. When active, RTS informs the modem or data set that the ACE is ready toreceive data. RTS is set to the active level by setting the RTS modem control register bit andRTS C5 O is set to the inactive (high) level either as a result of a master reset or during loop modeoperations or by clearing bit 1 ( RTS) of the MCR. In the auto- RTS mode, RTS is set to theinactive level by the receiver threshold control logic.SIN C1 I Serial data input. SIN is serial data input from a connected communications device.Serial data output. SOUT is composite serial data output to a connected communicationSOUT C2 O

device. SOUT is set to the marking (high) level as a result of master reset.V

A5 2.25-V to 5.5-V power supply voltageV

E3 Supply common, groundWrite input. When WR1 is active (low) and while the ACE is selected, the CPU is allowed toWR1 D2 I

write control words or data into a selected ACE register.XIN E1 External clock. XIN and XOUT connect the ACE to the main timing reference (clock orI/OXOUT E2 crystal).

Product Folder Link(s): TL16C550D TL16C550DI

ABSOLUTE MAXIMUM RATINGS

(1)

RECOMMENDED OPERATING CONDITIONS

3.3 V ± 10%

TL16C550D , , TL16C550DI

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Supply voltage range

(2)

– 0.5 7 VV

Input voltage range at any input – 0.5 7 VV

Output voltage range – 0.5 7 VTL16C550D 0 70T

Operating free-air temperature range ° CTL16C550DI – 40 85T

stg

Storage temperature range – 65 150 ° CLead temperature 1.6 mm (1/16 inch) from case for 10 seconds PT/PFB packages 260 ° C

(1) Stresses beyond those listed under " absolute maximum ratings " may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under " recommended operatingconditions " is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) All voltage values with respect to V

2.5 V ± 10%

MIN NOM MAX UNIT

Supply voltage 2.25 2.5 2.75 VV

Input voltage 0 V

High-level input voltage 1.8 2.75 VV

Low-level input voltage – 0.3 0.6 VV

Output voltage 0 V

High-level output current (all outputs) 1 mAI

Low-level output current (all outputs) 2 mAOscillator/clock speed 16 MHz

MIN NOM MAX UNIT

Supply voltage 3 3.3 3.6 VV

Input voltage 0 V

High-level input voltage 0.7 × V

Low-level input voltage 0.3 × V

Output voltage 0 V

High-level output current (all outputs) 1.8 mAI

Low-level output current (all outputs) 3.2 mAOscillator/clock speed 20 MHzOscillator/clock speed (ZQS package only) 48 MHz

Product Folder Link(s): TL16C550D TL16C550DI

5 V ± 10%

ELECTRICAL CHARACTERISTICS

TL16C550D , , TL16C550DI

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MIN NOM MAX UNIT

Supply voltage 4.5 5 5.5 VV

Input voltage 0 V

VExcept XIN 2V

High-level input voltage VXIN 0.7 × V

Except XIN 0.8V

Low-level input voltage V0.3 ×XIN

Output voltage 0 V

High-level output current (all outputs) 4 mAI

Low-level output current (all outputs) 4 mAOscillator/clock speed 24 MHz

2.5 V Nominal

over operating ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

High-level output voltage

(2)

= – 1 mA 1.8 VV

Low-level output voltage

(2)

= 2 mA 0.5 VV

= 3.6 V, V

= 0,I

Input current V

= 0 to 3.6 V, All other terminals 10 µAfloatingV

= 3.6 V, V

= 0,High-impedance-state output

= 0 to 3.6 V,I

± 20 µAcurrent

Chip selected in write mode or chip deselectV

= 3.6 V, T

= 25 ° C,SIN, DSR, DCD, CTS, and RI at 2 V,I

Supply current 8 mAAll other inputs are 0.8 V, XTAL1 at 4 MHz,No load on outputs, Baud rate = 50 kbit/sC

i(CLK)

Clock input capacitance 15 20 pFV

= 0,C

o(CLK)

Clock output capacitance 20 30 pFf = 1 MHz, V

= 0,All other terminals T

= 25 ° CC

Input capacitance 6 10 pFgroundedC

Output capacitance 10 10 pF

(1) All typical values are at V

= 2.5 V and T

= 25 ° C.(2) These parameters apply for all outputs except XOUT.

Product Folder Link(s): TL16C550D TL16C550DI

3.3 V Nominal

5 V Nominal

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

over operating ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

High-level output voltage

(2)

= – 1 mA 2.4 VV

Low-level output voltage

(2)

= 2 mA 0.5 VV

= 3.6 V, V

= 0,I

Input current V

= 0 to 3.6 V, All other terminals 10 µAfloatingV

= 3.6 V, V

= 0,High-impedance-state output

= 0 to 3.6 V,I

± 20 µAcurrent

Chip selected in write mode or chip deselectV

= 3.6 V, T

= 25 ° C,SIN, DSR, DCD, CTS, and RI at 2 V,I

Supply current 8 mAAll other inputs are 0.8 V, XTAL1 at 4 MHz,No load on outputs, Baud rate = 50 kbit/sC

i(CLK)

Clock input capacitance 15 20 pFV

= 0,C

o(CLK)

Clock output capacitance 20 30 pFf = 1 MHz, V

= 0,All other terminals T

= 25 ° CC

Input capacitance 6 10 pFgroundedC

Output capacitance 10 20 pF

(1) All typical values are at V

= 3.3 V and T

= 25 ° C.(2) These parameters apply for all outputs except XOUT.

over operating ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

(1)

MAX UNIT

High-level output voltage

(2)

= – 1 mA 4.0 VV

Low-level output voltage

(2)

= 2 mA 0.4 VV

= 3.6 V, V

= 0,I

Input current V

= 0 to 3.6 V, All other terminals 10 µAfloatingV

= 3.6 V, V

= 0,High-impedance-state output

= 0 to 3.6 V,I

± 20 µAcurrent

Chip selected in write mode or chip deselectV

= 3.6 V, T

= 25 ° C,SIN, DSR, DCD, CTS, and RI at 2 V,I

Supply current 10 mAAll other inputs are 0.8 V, XTAL1 at 4 MHz,No load on outputs, Baud rate = 50 kbit/sC

i(CLK)

Clock input capacitance 15 20 pFV

= 0,C

o(CLK)

Clock output capacitance 20 30 pFf = 1 MHz, V

= 0,All other terminals T

= 25 ° CC

Input capacitance 6 10 pFgroundedC

Output capacitance 10 20 pF

(1) All typical values are at V

= 5 V and T

= 25 ° C.(2) These parameters apply for all outputs except XOUT.

Product Folder Link(s): TL16C550D TL16C550DI

SYSTEM TIMING REQUIREMENTS

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over recommended ranges of supply voltage and operating free-air temperature

ALT. SYMBOL TEST CONDITIONS MIN MAX UNIT

Cycle time, read (t

+ t

) RC 87 nst

Cycle time, write (t

+ t

) WC 87 nsf = 16 MHz Max, V

= 2.5 V,

25See Figure 5f = 20 MHz Max, V

= 3.3 V,

20See Figure 5t

Pulse duration, clock high t

nsf = 24 MHz Max, V

= 5 V,

18See Figure 5f = 48 MHz Max, V

= 3.3 V,See Figure 5 8(ZQS package only)f = 16 MHz Max, V

= 2.5 V,

25See Figure 5f = 20 MHz Max, V

= 3.3 V,

20See Figure 5t

Pulse duration, clock low t

nsf = 24 MHz Max, V

= 5 V,

18See Figure 5f = 48 MHz Max, V

= 3.3 V,See Figure 5 8(ZQS package only)t

Pulse duration, ADS low tADS See Figure 6 and Figure 7 9 nst

Pulse duration, WR t

See Figure 6 40 nst

Pulse duration, RD t

See Figure 7 40 nst

Pulse duration, MR t

1µst

su1

Setup time, address valid before ADS↑t

See Figure 6 and Figure 7 8 nst

su2

Setup time, CS valid before ADS↑t

su3

Setup time, data valid before WR1↑or WR2 ↓tDS See Figure 6 15 nst

su4

Setup time, CTS↑before midpoint of stop bit See Figure 17 10 nst

Hold time, address low after ADS↑t

See Figure 6 and Figure 7 0 nst

Hold time, CS valid after ADS↑t

Hold time, CS valid after WR1 ↑or WR2 ↓t

WCS

See Figure 6 10 nst

Hold time, address valid after WR1↑or WR2 ↓t

Hold time, data valid after WR1↑or WR2 ↓t

See Figure 6 5 nst

Hold time, CS valid after RD1↑or RD2 ↓t

RCS

See Figure 7 10 nst

Hold time, address valid after RD1↑or RD2 ↓t

See Figure 6 20 nst

Delay time, CS valid before WR1↓or WR2 ↑

(1)

CSW

See Figure 6 7 nst

Delay time, address valid before WR1↓or WR2 ↑

(1)

Delay time, write cycle, WR1↑or WR2 ↓to ADS↓t

See Figure 6 40 nst

Delay time, CS valid to RD1↓or RD2 ↑

(1)

tCSR

See Figure 7 7 nst

Delay time, address valid to RD1↓or RD2 ↑

(1)

Delay time, read cycle, RD1↑or RD2 ↓ to ADS↓t

See Figure 7 40 nst

d10

Delay time, RD1↓or RD2 ↑ to data valid t

RVD

= 75 pF, Figure 7 45 nst

d11

Delay time, RD1↑or RD2 ↓ to floating data t

= 75 pF, See Figure 7 20 ns

(1) Only applies when ADS is low.

Product Folder Link(s): TL16C550D TL16C550DI

SYSTEM SWITCHING CHARACTERISTICS

(1)

BAUD GENERATOR SWITCHING CHARACTERISTICS

RECEIVER SWITCHING CHARACTERISTICS

(1)

TRANSMITTER SWITCHING CHARACTERISTICS

(1)

TL16C550D , , TL16C550DI

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

over recommended ranges of supply voltage and operating free-air temperature

PARAMETER ALT. SYMBOL TEST CONDITIONS MIN MAX UNIT

dis(R)

Disable time, RD1↓ ↑ or RD2 ↑ ↓ to DDIS ↑ ↓ t

RDD

= 75 pF, Figure 7 20 ns

(1) Charge and discharge are determined by V

, V

, and external loading.

over recommended ranges of supply voltage and operating free-air temperature, C

= 75 pF (For PT and PFB packages only)

PARAMETER ALT. SYMBOL TEST CONDITIONS MIN MAX UNIT

Pulse duration, BADOUT low t

f = 24 MHz, CLK ÷ 2, V

= 5 V,

35 nsSee Figure 5t

Pulse duration, BADOUT high t

Delay time, XIN ↑to BADOUT↑t

BLD

See Figure 5 45 nst

Delay time, XIN ↑ ↓ to BADOUT↓t

BHD

See Figure 5 45 ns

over recommended ranges of supply voltage and operating free-air temperature

PARAMETER ALT. SYMBOL TEST CONDITIONS MIN MAX UNIT

d12

Delay time, RCLK to sample t

SCD

See Figure 8 10 nsSee Figure 5 ,Figure 9 , RCLDelay time, stop to set INTRPT or readt

d13

SINT

Figure 10 ,Figure 11 , 1 KRBR to lSI interrupt or stop to RXRDY↓

Figure 12 cycleC

= 75 pF,See Figure 5 ,Figure 9 ,t

d14

Delay time, read RBR/LSR to reset INTRPT t

RINT

70 nsFigure 10 ,Figure 11 ,Figure 12

(1) In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt identificationregister or line status register).

over recommended ranges of supply voltage and operating free-air temperature

PARAMETER ALT. SYMBOL TEST CONDITIONS MIN MAX UNIT

baudoutt

d15

Delay time, initial write to transmit start t

IRS

See Figure 13 8 24

cycles

baudoutt

d16

Delay time, start to INTRPT t

STI

See Figure 13 8 10

cyclesC

= 75 pF,t

d17

Delay time, WR1 (WR THR) to reset INTRPT t

50 nsSee Figure 13

baudoutt

d18

Delay time, initial write to INTRPT (THRE

(1)

) t

See Figure 13 16 34

cyclesC

= 75 pF,t

d19

Delay time, read IIR

(2)

to reset INTRPT (THRE

(1)

) t

35 nsSee Figure 13C

= 75 pF,t

d20

Delay time, write to TXRDY inactive t

WXI

35 nsSee Figure 14 and Figure 15C

= 75 pF, baudoutt

d21

Delay time, start to TXRDY active t

SXA

9See Figure 14 and Figure 15 cycles

(1) THRE = transmitter holding register empty(2) IIR = Interrupt identification register

Product Folder Link(s): TL16C550D TL16C550DI

MODEM CONTROL SWITCHING CHARACTERISTICS

(1)

PARAMETER MEASUREMENT INFORMATION

TL16C550D , , TL16C550DI

SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 ..................................................................................................................................................

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over recommended ranges of supply voltage and operating free-air temperature, C

= 75 pF

PARAMETER ALT. SYMBOL TEST CONDITIONS MIN MAX UNIT

d22

Delay time, WR2 MCR to output t

MDO

See Figure 15 50 nst

d23

Delay time, modem interrupt to set INTRPT t

SIM

See Figure 16 35 nst

d24

Delay time, RD2 MSR to reset INTRPT t

RIM

See Figure 16 40 nsbaudoutt

d25

Delay time, CTS low to SOUT ↓See Figure 17 24

cycles

baudoutt

d26

Delay time, RCV threshold byte to RTS↑See Figure 18 2

cycles

baudoutt

d27

Delay time, read of last byte in receive FIFO to RTS↓See Figure 18 2

cycles

baudoutt

d28

Delay time, first data bit of 16th character to RTS↑See Figure 19 2

cycles

baudoutt

d29

Delay time, RBRRD low to RTS↓See Figure 19 2

cycles

(1) THRE = transmitter holding register empty

Figure 5. Baud Generator Timing Waveforms (for PT and PFB Packages Only)

Product Folder Link(s): TL16C550D TL16C550DI

ADS

tw5

th1

th2

tsu3 th5

th3

Valid Data

Valid Valid

Active

A0- A2

CS0, CS1,

(see Note B)

CS2

WR1, WR2

D7- D0

50%50%

50% 50%50%

50% 50%

50%

tsu1

tsu2

tw6

td4

td5

th4

td6

(see Note A)

(See Note B)

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

PARAMETER MEASUREMENT INFORMATION (continued)

A. Applicable only when ADS is lowB. The ADS, CSO, CS1, and WR2 signals are applicable only to the PT and PFB packages.

Figure 6. Write Cycle Timing Waveforms

Product Folder Link(s): TL16C550D TL16C550DI

ADS

(see Note A)

Valid

tw5

th1

th2

tsu2

th6

Valid Data

Valid

Active

A0- A2

CS0, CS1,

(see Note B)

CS2

RD1, RD2

(see Note B)

DDIS

(see Note B)

D7- D0

tdis(R)

50%50% 50%

50%

50% 50%

tsu1

td8A

td7Atw7

th7A

td9

td10 td11

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PARAMETER MEASUREMENT INFORMATION (continued)

A. Applicable only when ADS is lowB. The ADS, CSO, CS1, and WR2 signals are applicable only to the PT and PFB packages.

Figure 7. Read Cycle Timing Waveforms

Product Folder Link(s): TL16C550D TL16C550DI

td13

RD1, RD2‡

(read RBR)

RCLK

td14

td12

Parity StopStart Data Bits 5- 8

Sample Clock

TL16C450 Mode:

Sample Clock

SIN

INTRPT

(data ready)

INTRPT

(RCV error)

RD1, RD2‡

(read LSR)

50%

50% 50%

Active

50%

50% 50%

50%

8 CLKs

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

PARAMETER MEASUREMENT INFORMATION (continued)

A. The RD2 signal is applicable only to the PT and PFB packages.

Figure 8. Receiver Timing Waveforms

Product Folder Link(s): TL16C550D TL16C550DI

(FIFO at or above

trigger level)

(FIFO below

trigger level)

(see Note A)

(FIFO below

trigger level)

(FIFO at or above

trigger level)

(see Note B)

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PARAMETER MEASUREMENT INFORMATION (continued)

A. For a time-out interrupt, t

d13

= 9 RCLKs.

Figure 9. Receive FIFO First Byte (Sets DR Bit) Waveforms

A. The RD2 signal is applicable only to the PT and PFB packages.B. For a time-out interrupt, t

d13

= 9 RCLKs.

Figure 10. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms

Product Folder Link(s): TL16C550D TL16C550DI

td13

td14

Stop

SampleClock

SIN

(firstbyte)

Active

RD1

(RDRBR)

RXRDY

50%

(seeNote A)

(seeNoteC)

(seeNoteB)

td13

(seeNoteC)

(seeNoteB)

std14

SampleClock

SIN

(firstbytethatreaches

thetriggerlevel)

Active

RD1

(RDRBR)

RXRDY

(seeNote A)

50%

50%50%

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

PARAMETER MEASUREMENT INFORMATION (continued)

A. The RXRDY signal is applicable only to the PT and PFB packages.B. This is the reading of the last byte in the FIFO.C. For a time-out interrupt, t

d13

= 9 RCLKs.

Figure 11. Receiver Ready ( RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)

A. The RXRDY signal is applicable only to the PT and PFB packages.B. This is the reading of the last byte in the FIFO.C. For a time-out interrupt, t

d13

= 9 RCLKs.

Figure 12. Receiver Ready ( RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)

Product Folder Link(s): TL16C550D TL16C550DI

(see Note A)

WR1

(WR THR)

Parity Stop

Data

Start

Byte 16

SOUT

FIFO Full

td20 td21

50%

TXRDY

(see Note A)

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PARAMETER MEASUREMENT INFORMATION (continued)

Figure 13. Transmitter Timing Waveforms

A. The TXRDY signal is applicable only to the PT and PFB packages.

Figure 14. Transmitter Ready ( TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)

A. The TXRDY signal is applicable only to the PT and PFB packages.

Figure 15. Transmitter Ready ( TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)

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(see Note A)

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

PARAMETER MEASUREMENT INFORMATION (continued)

A. The OUT1, OUT2, RD2, and WR2 signals are applicable only to the PT and PFB packages.

Figure 16. Modem Control Timing Waveforms

Figure 17. CTS and SOUT Autoflow Control Timing (Start and Stop) Waveforms

Figure 18. Auto- RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms

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PARAMETER MEASUREMENT INFORMATION (continued)

Figure 19. Auto- RTS Timing for RCV Threshold of 14 Waveforms

Product Folder Link(s): TL16C550D TL16C550DI

APPLICATION INFORMATION

D7- D0

MEMR or I/OR

MEMW or I/ON

INTR

RESET

EIA-232-D

Drivers

and Receivers

XOUT

XIN

RCLK

BAUDOUT

CTS

DCD

DSR

DTR

RTS

SOUT

SIN

INTRPT

D7- D0

RD1

WR1

ADS

WR2

RD2

CS2

CS1

CS0

TL16C550D

(ACE)

3.072 MHz

D7- D0

MEMR or I/OR

MEMW or I/ON

INTR

RESET

EIA-232-D

Drivers

and Receivers

XOUT

XIN

CTS

DCD

DSR

DTR

RTS

SOUT

SIN

INTRPT

D7- D0

RD1

WR1

CS2

TL16C550D

(ACE)

3.072 MHz

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Figure 20. Basic TL16C550D Configuration (for PT and PFB Packages)

Figure 21. Basic TL16C550D Configuration (for RHB Package)

Product Folder Link(s): TL16C550D TL16C550DI

D7- D0

MEMR or I/OR

MEMW or I/ON

INTR

RESET

EIA-232-D

Drivers

and Receivers

XOUT

XIN

CTS

RTS

SOUT

SIN

INTRPT

D7- D0

RD1

WR1

CS2

TL16C550D

(ACE)

3.072 MHz

Receiver Disable

Microcomputer

System Data Bus Data Bus

Driver Disable

8-Bit

Bus Transceiver

WR WR1

D7- D0

DDIS

TL16C550D

(ACE)

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Figure 22. Basic TL16C550D Configuration (for ZQS Package)

Figure 23. Typical Interface for a High-Capacity Data Bus

Product Folder Link(s): TL16C550D TL16C550DI

Buffer

Address

Decoder

A16–A23 A16–A23

ADS

AD0–AD15

RSI/ABT

PHI1 PHI2

PHI1 PHI2 ADS

ADS

CPU

RSTO

CS0

CS1

CS2

A0–A2

D0–D7

AD0–AD7

RD1

WR1

RD2

WR2

XIN

XOUT

BAUDOUT

RCLK

DTR

RTS

OUT1

OUT2

DCD

DSR

CTS

SIN

SOUT

INTRPT

TXRDY

DDIS

RXRDY

GND

(VSS)VCC

18 42

Alternate

CrystalControl

TL16C550D

EIA-232-D

Connector

2917

TCU

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

Figure 24. Typical TL16C550D Connection to a CPU (for PT and PFB Packages)

Product Folder Link(s): TL16C550D TL16C550DI

Buffer

Address

Decoder

A16- A23

ADS

AD0- AD15

RSI/ABT

PHI1 PHI2

PHI1 PHI2 ADS

CPU

RSTO

A16- A23

A0- A2

D0- D7

AD0- AD7

RD1

WR1

AD0- AD15

XIN

XOUT

DTR

RTS

DCD

DSR

CTS

SIN

SOUT

INTRPT

GND

(VSS)VCC

13 28

Alternate

Crystal Control

TL16C550D

EIA-232-D

Connector

CS2

TCU

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Figure 25. Typical TL16C550D Connection to a CPU (for RHB Package)

Product Folder Link(s): TL16C550D TL16C550DI

Buffer

Address

Decoder

A16- A23

ADS

AD0- AD15

RSI/ABT

PHI1 PHI2

PHI1 PHI2 ADS

CPU

RSTO

A16- A23

A0- A2

D0- D7

AD0- AD7

RD1

WR1

AD0- AD15

XIN

XOUT

RTS

CTS

SIN

SOUT

INTRPT

GND

(VSS)VCC

E3 A5

Alternate

Crystal Control

TL16C550D

EIA-232-D

Connector

CS2

TCU

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

Figure 26. Typical TL16C550D Connection to a CPU (for ZQS Package)

Product Folder Link(s): TL16C550D TL16C550DI

PRINCIPLES OF OPERATION

Accessible Registers

TL16C550D , , TL16C550DI

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Table 1. Register Selection

DLAB

(1)

A2 A1 A0 REGISTER

0 L L L Receiver buffer (read), transmitter holding register (write)0 L L H Interrupt enable registerX L H L Interrupt identification register (read only)X L H L FIFO control register (write)X L H H Line control registerX H L L Modem control registerX H L H Line status registerX H H L Modem status registerX H H H Scratch register1 L L L Divisor latch (LSB)1 L L H Divisor latch (MSB)

(1) The divisor latch access bit (DLAB) is the most significant bit (MSB) of the line control register. TheDLAB signal is controlled by writing to this bit location (see Table 4 ).

Table 2. ACE Reset Functions

Interrupt enable register Master reset All bits cleared (0 −3 forced and 4 −7 permanent)Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bitsInterrupt identification register Master reset

4−5 are permanently clearedFIFO control register Master reset All bits clearedLine control register Master reset All bits clearedModem control register Master reset All bits cleared (6 −7 permanent)Line status register Master reset Bits 5 and 6 are set; all other bits are clearedModem status register Master reset Bits 0 −3 are cleared; bits 4 −7 are input signalsSOUT Master reset HighINTRPT (receiver error flag) Read LSR/MR LowINTRPT (received data available) Read RBR/MR LowINTRPT (transmitter holding register empty) Read IR/write THR/MR LowINTRPT (modem status changes) Read MSR/MR LowOUT2 Master reset HighRTS Master reset HighDTR Master reset HighOUT1 Master reset HighScratch register Master reset No effectDivisor latch (LSB and MSB) registers Master reset No effectReceiver buffer register Master reset No effectTransmitter holding register Master reset No effectRCVR FIFO MR/FCR1 – FCR0/ ΔFCR0 All bits clearedXMIT FIFO MR/FCR2 – FCR0/ ΔFCR0 All bits cleared

The system programmer, using the CPU, has access to and control over any of the ACE registers that aresummarized in Table 2 . These registers control ACE operations, receive data, and transmit data. Descriptions ofthese registers follow Table 3 .

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FIFO Control Register (FCR)

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.................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008

Table 3. Summary of Accessible RegistersREGISTER ADDRESS

0DLAB =

0DLAB = 0 1DLAB = 0 2 2 3 4 5 6 7 0DLAB = 1 1DLAB = 10

Receiver

BIT

Transmitter Interrupt FIFOBuffer Interrupt Line Modem ModemNO.

Holding Indent. Control Line Status Scratch Divisor LatchRegister Enable Control Control StatusRegister Register Register Register Register Latch (LSB) (MSB)(Read Register Register Register Register(Write Only) (Read Only) (Write Only)Only)

RBR THR IER IIR FCR LCR MCR LSR MSR SCR DLL DLM

Enable

Received Word

Delta ClearData Bit Data 0 if Interrupt Length Data Terminal Data Ready0 Data Bit 0 FIFO Enable to Send Bit 0 Bit 0 Bit 80

(1)

Available Pending Select Bit Ready (DR)

(ΔCTS)Interrupt 0 (WLS0)(ERBI)

Enable

Transmitter

WordHolding Delta DataInterrupt ID Receiver Length Request to Overrun1 Data Bit 1 Data Bit 1 Register Set Ready Bit 1 Bit 1 Bit 9Bit 1 FIFO Reset Select Bit Send (RTS) Error (OE)Empty ( ΔDSR)1 (WLS1)Interrupt

(ETBEI)

Enable

TrailingReceiver Number ofInterrupt ID Transmitter Parity Error Edge Ring2 Data Bit 2 Data Bit 2 Line Status Stop Bits OUT1 Bit 2 Bit 2 Bit 10Bit 2 FIFO Reset (PE) IndicatorInterrupt (STB)

(TERI)(ELSI)

Enable

Delta DataModem ParityInterrupt ID DMA Mode Framing Carrier3 Data Bit 3 Data Bit 3 Status Enable OUT2 Bit 3 Bit 3 Bit 11Bit 3

(2)

Select Error (FE) DetectInterrupt (PEN)

(ΔDCD)(EDSSI)

Even

Parity Break Clear to4 Data Bit 4 Data Bit 4 0 0 Reserved Loop Bit 4 Bit 4 Bit 12Select Interrupt Send (CTS)(EPS)

TransmitterAutoflow Data SetStick Holding5 Data Bit 5 Data Bit 5 0 0 Reserved Control Enable Ready Bit 5 Bit 5 Bit 13Parity Register(AFE) (DSR)(THRE)

Receiver Transmitter RingFIFOs Break6 Data Bit 6 Data Bit 6 0 Trigger 0 Empty Indicator Bit 6 Bit 6 Bit 14Enabled

(2)

Control(LSB) (TEMT) (RI)

DivisorReceiver Error in Data CarrierLatch7 Data Bit 7 Data Bit 7 0 Trigger 0 RCVR Detect Bit 7 Bit 7 Bit 15Access Bit(MSB) FIFO

(2)

(DCD)(DLAB)

(1) Bit 0 is the least significant bit. It is the first bit serially transmitted or received.(2) These bits are always 0 in the TL16C450 mode.

The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enablesand clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signaling.•Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bitsare written to or they are not programmed. Changing this bit clears the FIFOs.•Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is notcleared. The 1 that is written to this bit position is self-clearing.•Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is notcleared. The 1 that is written to this bit position is self-clearing.•Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.•Bits 4 and 5: These two bits are reserved for future use.•Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 4 ).

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FIFO Interrupt Mode Operation

FIFO-Polled Mode Operation

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Table 4. Receiver FIFO Trigger Level

RECEIVER FIFOBIT 7 BIT 6

TRIGGER LEVEL (BYTES)

0 0 010 1 041 0 081 1 14

When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interruptoccurs as follows:1. The received data available interrupt is issued to the microprocessor when the FIFO has reached itsprogrammed trigger level. It is cleared when the FIFO drops below its programmed trigger level.2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like theinterrupt, it is cleared when the FIFO drops below the trigger level.3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04)interrupt.

4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO. Itis cleared when the FIFO is empty.

When the receiver FIFO and receiver interrupts are enabled:1. FIFO time-out interrupt occurs if the following conditions exist:a. At least one character is in the FIFO.b. The most recent serial character was received more than four continuous character times ago (if twostop bits are programmed, the second one is included in this time delay).c. The most recent microprocessor read of the FIFO has occurred more than four continuous charactertimes before. This causes a maximum character received command to interrupt an issued delay of 160ms at a 300-baud rate with a 12-bit character.2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional tothe baud rate).3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor readsone character from the receiver FIFO.4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received orafter the microprocessor reads the receiver FIFO.

When the transmitter FIFO and THRE interrupts are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur asfollows:

1. The transmitter-holding-register-empty interrupt [IIR (3 −0) = 2] occurs when the transmit FIFO is empty. It iscleared [IIR (3 −0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFOwhile servicing this interrupt) or the IIR is read.2. The transmitter-holding-register-empty interrupt is delayed one character time minus the last stop bit timewhen there have not been at least two bytes in the transmitter FIFO at the same time since the last time thatthe FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.

With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 putsthe ACE in the FIFO-polled mode of operation. Because the receiver and transmitter are controlled separately,either one or both can be in the polled mode of operation.

In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:•LSR0 is set as long as one byte is in the receiver FIFO.•LSR1 through LSR4 specify which error(s) have occurred. Character error status is handled the same way aswhen in the interrupt mode; the IIR is not affected since IER2 = 0.•LSR5 indicates when the THR is empty.

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Interrupt Enable Register (IER)

Interrupt Identification Register (IIR)

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•LSR6 indicates that both the THR and TSR are empty. LSR7 indicates whether any errors are in the receiverFIFO.

There is no trigger level reached or time-out condition indicated in the FIFO-polled mode. However, the receiverand transmitter FIFOs are still fully capable of holding characters.

The IER enables each of the five types of interrupts (see Table 5 ) and enables INTRPT in response to aninterrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents ofthis register are summarized in Table 3 and are described in the following bullets.•Bit 0: When set, this bit enables the received data available interrupt.•Bit 1: When set, this bit enables the THRE interrupt.•Bit 2: When set, this bit enables the receiver line status interrupt.•Bit 3: When set, this bit enables the modem status interrupt.•Bits 4 through 7: These bits are not used (always cleared).

The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with themost popular microprocessors.

The ACE provides four prioritized levels of interrupts:•Priority 1 −Receiver line status (highest priority)•Priority 2 −Receiver data ready or receiver character time-out•Priority 3 −Transmitter holding register empty•Priority 4 −Modem status (lowest priority)

When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt inits three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 anddescribed in Table 5 . Detail on each bit is as follows:•Bit 0: This bit is used either in a hardwire-prioritized or polled-interrupt system. When bit 0 is cleared, aninterrupt is pending. If bit 0 is set, no interrupt is pending.•Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 3 .•Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that atime-out interrupt is pending.•Bits 4 and 5: These two bits are not used (always cleared).•Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO controlregister is set.

Table 5. Interrupt Control Functions

INTERRUPT IDENTIFICATION

PRIORITY INTERRUPT RESETREGISTER

INTERRUPT TYPE INTERRUPT SOURCELEVEL METHODBIT 3 BIT 2 BIT 1 BIT 0

0 0 0 1 None None None NoneOverrun error, parity error,0 1 1 0 1 Receiver line status framing error, or break Read the line status registerinterrupt

Receiver data available in theReceived data TL16C450 mode or trigger Read the receiver buffer0 1 0 0 2

available level reached in the FIFO registermode

No characters have beenremoved from or input to theCharacter time-out receiver FIFO during the last Read the receiver buffer1 1 0 0 2

indication four character times, and there registeris at least one character in itduring this time

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Line Control Register (LCR)

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Table 5. Interrupt Control Functions (continued)

INTERRUPT IDENTIFICATION

PRIORITY INTERRUPT RESETREGISTER

INTERRUPT TYPE INTERRUPT SOURCELEVEL METHODBIT 3 BIT 2 BIT 1 BIT 0

Read the interruptTransmitter holding Transmitter holding register identification register (if source0 0 1 0 3

Read the modem status0 0 0 0 4 Modem status ring indicator, or data carrier

registerdetect

The system programmer controls the format of the asynchronous data communication exchange through theLCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminatesthe need for separate storage of the line characteristics in system memory. The contents of this register aresummarized in Table 3 and described in the following bulleted list.•Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. Thesebits are encoded as shown in Table 6 .

Table 6. Serial Character

Word Length

BIT 1 BIT 0 WORD LENGTH

0 0 5 bits0 1 6 bits1 0 7 bits1 1 8 bits

•Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated isdependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit regardlessof the number of stop bits selected. The number of stop bits generated in relation to word length and bit 2 areshown in Table 7 .

Table 7. Number of Stop Bits Generated

WORD LENGTH

NUMBER OF STOPBIT 2 SELECTED

BITS GENERATEDBY BITS 1 AND 2

0 Any word length 11 5 bits 1 ＝

1 6 bits 21 7 bits 21 8 bits 2

•Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data betweenthe last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 iscleared, no parity is generated or checked.•Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity (aneven number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared,odd parity (an odd number of logic 1s) is selected.•Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked ascleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. If bit 5is cleared, stick parity is disabled.•Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT isforced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no effecton the transmitter logic; it only effects SOUT.

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Line Status Register (LSR)

(1)

Modem Control Register (MCR)

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•Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the baudgenerator during a read or write. Bit 7 must be cleared during a read or write to access the receiver buffer,the THR, or the IER.

The LSR provides information to the CPU concerning the status of data transfers. The contents of this registerare summarized in Table 3 and described in the following bulleted list.•Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set whenever a complete incomingcharacter has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of thedata in the RBR or the FIFO.•Bit 1

(2)

: This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in theRBR was read, it was overwritten by the next character transferred into the register. OE is cleared every timethe CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the triggerlevel, an overrun error occurs only after the FIFO is full, and the next character has been completely receivedin the shift register. An overrun error is indicated to the CPU as soon as it happens. The character in the shiftregister is overwritten, but it is not transferred to the FIFO.•Bit 2

(3)

: This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the receiveddata character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU readsthe contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO towhich it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.•Bit 3: This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character didnot have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the FIFOmode, this error is associated with the particular character in the FIFO to which it applies. This error isrevealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to resynchronizeafter a framing error. To accomplish this, it is assumed that the framing error is due to the next start bit. TheACE samples this start bit twice and then accepts the input data.•Bit 4: This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input washeld low for longer than a full-word transmission time. A full-word transmission time is defined as the totaltime to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU reads the contents ofthe LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which itapplies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When abreak occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after SINgoes to the marking state for at least two RCLK samples and then receives the next valid start bit.•Bit 5: This bit is the THRE indicator. THRE is set when the THR is empty, indicating that the ACE is ready toaccept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated. THREis set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the loadingof the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared whenat least one byte is written to the transmit FIFO.•Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are bothempty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode,TEMT is set when the transmitter FIFO and shift register are both empty.•Bit 7: In the TL16C550D mode, this bit is always cleared. In the TL16C450 mode, this bit is always cleared. Inthe FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is clearedwhen the microprocessor reads the LSR and there are no subsequent errors in the FIFO.

The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that isemulating a modem. The contents of this register are summarized in Table 3 and are described in the followingbulleted list.•Bit 0: This bit (DTR) controls the DTR output.•Bit 1: This bit (RTS) controls the RTS output.•Bit 2: This bit (OUT1) controls OUT1, a user-designated output signal.

(1) The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testingenvironment.

(2) Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.(3) Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.

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Modem Status Register (MSR)

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•Bit 3: This bit (OUT2) controls OUT2, a user-designated output signal.

When any of bits 0 through 3 are set, the associated output is forced low. When any of these bits are cleared,the associated output is forced high.•Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP is set,the following occurs:– The transmitter SOUT is set high.– The receiver SIN is disconnected.– The output of the TSR is looped back into the receiver shift register input.– The four modem control inputs ( CTS, DSR, DCD, and RI) are disconnected.– The four modem control outputs ( DTR, RTS, OUT1, and OUT2) are internally connected to the fourmodem control inputs.– The four modem control outputs are forced to the inactive (high) levels.•Bit 5: This bit (AFE) is the autoflow control enable. When set, the autoflow control as described in the detaileddescription is enabled.In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verifythe transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.The modem control interrupts are also operational, but the modem control interrupt's sources are now thelower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by theIER.

The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8 .

Table 8. ACE Flow Configuration

MCR BIT 5 MCR BIT 1

ACE FLOW CONFIGURATION(AFE) (RTS)

1 1 Auto- RTS and auto- CTS enabled (autoflow control enabled)1 0 Auto- CTS only enabled0 X Auto- RTS and auto- CTS disabled

The MSR is an 8-bit register that provides information about the current state of the control lines from themodem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide changeinformation; when a control input from the modem changes state, the appropriate bit is set. All four bits arecleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and aredescribed in the following bulleted list.•Bit 0: This bit is the change in clear-to-send ( ΔCTS) indicator. ΔCTS indicates that the CTS input haschanged state since the last time it was read by the CPU. When ΔCTS is set (autoflow control is not enabledand the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control isenabled ( ΔCTS is cleared), no interrupt is generated.•Bit 1: This bit is the change in data set ready ( ΔDSR) indicator. ΔDSR indicates that the DSR input haschanged state since the last time it was read by the CPU. When ΔDSR is set and the modem status interruptis enabled, a modem status interrupt is generated.•Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that the RI input to thechip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, amodem status interrupt is generated.•Bit 3: This bit is the change in data carrier detect ( ΔDCD) indicator. ΔDCD indicates that the DCD input to thechip has changed state since the last time it was read by the CPU. When ΔDCD is set and the modem statusinterrupt is enabled, a modem status interrupt is generated.•Bit 4: This bit is the complement of the clear-to-send ( CTS) input. When the ACE is in the diagnostic testmode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).•Bit 5: This bit is the complement of the data set ready ( DSR) input. When the ACE is in the diagnostic testmode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).•Bit 6: This bit is the complement of the ring indicator ( RI) input. When the ACE is in the diagnostic test mode(LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1).

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•Bit 7: This bit is the complement of the data carrier detect ( DCD) input. When the ACE is in the diagnostic testmode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).

The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHzand divides it by a divisor in the range between 1 and (2

– 1). The output frequency of the baud generator issixteen times (16 × ) the baud rate. The formula for the divisor is:

divisor = XIN frequency input ÷ (desired baud rate × 16)

Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches mustbe loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When eitherof the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.

Table 9 and Table 10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is small. The accuracy of theselected baud rate is dependent on the selected crystal frequency (see Figure 27 for examples of typical clockcircuits).

Table 9. Baud Rates Using a 1.8432-MHz Crystal

DIVISOR USED PERCENT ERRORDESIRED

TO GENERATE DIFFERENCE BETWEENBAUD RATE

16 × CLOCK DESIRED AND ACTUAL

50 230475 1536110 1047 0.026134.5 857 0.058150 768300 384600 1921200 961800 642000 58 0.692400 483600 324800 247200 169600 1219200 638400 356000 2 2.86

Table 10. Baud Rates Using a 3.072-MHz Crystal

DIVISOR USED PERCENT ERRORDESIRED

TO GENERATE DIFFERENCE BETWEENBAUD RATE

16 × CLOCK DESIRED AND ACTUAL

50 384075 2560110 1745 0.026134.5 1428 0.034150 1280300 640600 3201200 160

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TYPICAL CRYSTAL OSCILLATOR NETWORK

CRYSTAL

3.072 MHz 1 MΩ1.5 kΩ10 – 30 pF 40 – 60 pF

1.8432 MHz 1 MΩ1.5 kΩ10 – 30 pF 40 – 60 pF

16 MHz 1 MΩ0 Ω 33 pF 33 pF

RpRX2 C1 C2

Receiver Buffer Register (RBR)

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Table 10. Baud Rates Using a 3.072-MHzCrystal (continued)

DIVISOR USED PERCENT ERRORDESIRED

TO GENERATE DIFFERENCE BETWEENBAUD RATE

16 × CLOCK DESIRED AND ACTUAL

1800 107 0.3122000 962400 803600 53 0.6284800 407200 27 1.239600 2019200 1038400 5

Figure 27. Typical Clock Circuits

The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byteFIFO. Timing is supplied by the 16 ＝receiver clock (RCLK). Receiver section control is a function of the ACEline control register.

The ACE RSR receives serial data from SIN. The RSR then concatenates the data and moves it into the RBRFIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt isenabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. Inthe FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.

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Scratch Register

Transmitter Holding Register (THR)

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The scratch register is an 8-bit register that is intended for the programmer's use as a scratchpad in the sensethat it temporarily holds the programmer's data without affecting any other ACE operation.

The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a16-byte FIFO. Timing is supplied by BAUDOUT. Transmitter section control is a function of the ACE line controlregister.

The ACE THR receives data off the Internal data bus and when the shift register is idle, moves it into the TSR.The TSR serializes the data and outputs it at SOUT. In the TL16C450 mode, if the THR is empty and thetransmitter-holding-register-empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This interruptis cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated based onthe control setup in the FIFO control register.

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Revision History

Changes from Revision D (May 2006) to Revision E ...................................................................................................... Page

•Added " Up to 48-MHz Clock Rate for up to 3-Mbaud Operation with V

= 3.3 V (ZQS Package Only, Divisor = 1) " ........ 1•Added " Up to 40-MHz Clock Rate for up to 2.5-Mbaud Operation with V

= 3.3 V (ZQS Package Only, Divisor = 2) " ..... 1•Added 24-pin ZQS package .................................................................................................................................................. 1•Added ZQS package drawing ................................................................................................................................................ 2•Added ZQS package terminal assignments table.................................................................................................................. 2•Added ZQS package functional block diagram...................................................................................................................... 7•Added ZQS package terminal functions table ..................................................................................................................... 12•Added oscillator/clock speed for ZQS package ................................................................................................................... 13•Added ZQS t

, t

specification .......................................................................................................................................... 16•Added ZQS t

, t

specification .......................................................................................................................................... 16•Added basic TL16C550D configuration for ZQS package ................................................................................................... 28•Added typical TL16C550D connection to a CPU for ZQS package .................................................................................... 31

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PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TL16C550DIPFB ACTIVE TQFP PFB 48 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DIPFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DIPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DIPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DIPT ACTIVE LQFP PT 48 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

TL16C550DIPTG4 ACTIVE LQFP PT 48 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

TL16C550DIPTR ACTIVE LQFP PT 48 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

TL16C550DIPTRG4 ACTIVE LQFP PT 48 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

TL16C550DIRHB ACTIVE QFN RHB 32 73 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DIRHBG4 ACTIVE QFN RHB 32 73 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DIRHBR ACTIVE QFN RHB 32 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DIRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DIZQS PREVIEW BGA MI

CROSTA

R JUNI

ZQS 24 250 TBD Call TI Call TI

TL16C550DIZQSR ACTIVE BGA MI

CROSTA

R JUNI

ZQS 24 2500 Green (RoHS &

no Sb/Br) SNAGCU Level-1-260C-UNLIM

TL16C550DPFB ACTIVE TQFP PFB 48 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DPFBG4 ACTIVE TQFP PFB 48 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DPFBR ACTIVE TQFP PFB 48 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DPFBRG4 ACTIVE TQFP PFB 48 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DPT ACTIVE LQFP PT 48 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

TL16C550DPTG4 ACTIVE LQFP PT 48 250 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

TL16C550DPTR ACTIVE LQFP PT 48 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

TL16C550DPTRG4 ACTIVE LQFP PT 48 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-3-260C-168 HR

TL16C550DRHB ACTIVE QFN RHB 32 73 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

PACKAGE OPTION ADDENDUM

www.ti.com 20-Feb-2009

Addendum-Page 1

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

TL16C550DRHBG4 ACTIVE QFN RHB 32 73 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DRHBR ACTIVE QFN RHB 32 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DRHBRG4 ACTIVE QFN RHB 32 3000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

TL16C550DZQSR ACTIVE BGA MI

CROSTA

R JUNI

ZQS 24 2500 Green (RoHS &

no Sb/Br) SNAGCU Level-1-260C-UNLIM

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 20-Feb-2009

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm) W

(mm) Pin1

Quadrant

TL16C550DIPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2

TL16C550DIPTR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2

TL16C550DIRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

TL16C550DIZQSR BGA MI

CROSTA

R JUNI

ZQS 24 2500 330.0 12.4 3.3 3.3 1.6 8.0 12.0 Q1

TL16C550DPFBR TQFP PFB 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2

TL16C550DPTR LQFP PT 48 1000 330.0 16.4 9.6 9.6 1.9 12.0 16.0 Q2

TL16C550DRHBR QFN RHB 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2

TL16C550DZQSR BGA MI

CROSTA

R JUNI

ZQS 24 2500 330.0 12.4 3.3 3.3 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 8-Jan-2009

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TL16C550DIPFBR TQFP PFB 48 1000 346.0 346.0 33.0

TL16C550DIPTR LQFP PT 48 1000 346.0 346.0 33.0

TL16C550DIRHBR QFN RHB 32 3000 346.0 346.0 29.0

TL16C550DIZQSR BGA MICROSTAR

JUNIOR ZQS 24 2500 340.5 338.1 20.6

TL16C550DPFBR TQFP PFB 48 1000 346.0 346.0 33.0

TL16C550DPTR LQFP PT 48 1000 346.0 346.0 33.0

TL16C550DRHBR QFN RHB 32 3000 346.0 346.0 29.0

TL16C550DZQSR BGA MICROSTAR

JUNIOR ZQS 24 2500 340.5 338.1 20.6

PACKAGE MATERIALS INFORMATION

www.ti.com 8-Jan-2009

Pack Materials-Page 2

MECHANICAL DATA

MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PT (S-PQFP-G48) PLASTIC QUAD FLATPACK

4040052/C 11/96

0,13 NOM

0,17

0,27

6,80

7,20

5,50 TYP

0,25

0,45

0,75

0,05 MIN

9,20

8,80

1,35

1,45

1,60 MAX

Gage Plane

Seating Plane

0,10

0°–7°

0,50 M

0,08

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

D. This may also be a thermally enhanced plastic package with leads conected to the die pads.

MECHANICAL DATA

MTQF019A – JANUARY 1995 – REVISED JANUARY 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK

4073176/B 10/96

Gage Plane

0,13 NOM

0,25

0,45

0,75

Seating Plane

0,05 MIN

0,17

0,27

7,20

6,80

5,50 TYP

8,80

9,20

1,05

0,95

1,20 MAX 0,08

0,50 M

0,08

0°–7°

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

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