1/20
L6225
September 2003
■
OPERATING SUPPLY VOLTAGE FROM 8 TO 52V
■2.8A OUTPUT PEAK CURRENT (1.4A DC)
■RDS(ON) 0.73Ω TYP. VALU E @ Tj = 25 °C
■OPERA TING FREQUENCY UP T O 100KHz
■NON DISSIPATIVE OVERCURRENT
PROTECTION
■
PARALLELED OPERATION
■CROSS CONDUCTION PROTECTION
■THERMAL SHUTDOWN
■UNDER VOLTAG E LOCKOUT
■
INTEGRATED FAST FREE WHEELING DIODES
TYPICAL APPLICATIONS
■BIPOLAR STEPPER MOTOR
■DUAL OR QUAD DC MOT OR
DESCRIPTION
The L6225 is a DMOS Dual Full Bridge designed for
motor control applications, realized in MultiPower-
BCD technology, which combines isolated DMOS
Power Transistors with CMOS and bipolar c ircuits on
the same chip. Available in PowerDIP20 (16+2+2),
PowerSO20 and SO20(16+2+2) packages, the
L6225 features a non-dissipative protection of the
high side PowerMOSFETs and thermal shutdown.
BLOCK DIAGRAM
D99IN1091A
GATE
LOGIC
OVER
CURRENT
DETECTION
OVER
CURRENT
DETECTION
GATE
LOGIC
VCP
VBOOT
EN
A
IN1
A
IN2
A
EN
B
IN1
B
IN2
B
V
BOOT
5V
10V
VS
A
V
S
B
OUT1
A
OUT2
A
OUT1
B
OUT2
B
SENSE
A
CHARGE
PUMP
VOLTAGE
REGULATOR
THERMAL
PROTECTION
V
BOOT
V
BOOT
10V 10V
BRIDGE A
BRIDGE B
SENSE
B
OCD
A
OCD
B
ORDERING NUMBERS:
L6225N (Pow erDIP 20)
L6225PD (PowerSO20)
L6225D (SO2 0)
PowerDIP20
(16+2+2) PowerSO20 SO20
(16+2+2)
DMOS DUAL FULL BRIDGE DRIVER
L6225
2/20
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Test conditions Value Unit
VSSupply Voltage
V
SA
=
VSB =
VS60 V
VOD Differential Voltage between
VS
A
, OUT1
A
, OUT2
A
, SEN SE
A
and
VSB, OUT1B, OUT2B, SENS EB
V
SA
=
VSB =
VS = 60V;
V
SENSEA
= V
SENSEB = GND 60 V
VBOOT Bootstrap Peak Voltage
V
SA
=
VSB =
VSVS + 10 V
VIN,VEN Input and Enable Voltage Range -0.3 to +7 V
VSENSEA,
VSENSEB Voltage Range at pins SENSEA
and SENSEB -1 to +4 V
IS(peak) Pulsed Supply Current (for each
VS pin), internally limited by the
overcurrent protection
V
SA
=
VSB =
VS;
tPULSE < 1ms 3.55 A
ISRMS Supply Current (for each
VS pin)
V
SA
=
VSB =
VS1.4 A
Tstg, TOP Storage and Operating
Temperature Range -40 to 150 °C
Symbol Parameter Test Conditions MIN MAX Unit
VSSupply Voltage
V
SA
=
VSB =
VS852V
V
OD Differential Voltage Between
VS
A
, OUT1
A
, OUT2
A
, SEN SE
A
and
VSB, OUT1B, OUT2B, SENS EB
V
SA
=
VSB =
VS;
V
SENSEA
= V
SENSEB 52 V
VSENSEA,
VSENSEB Voltage Range at pins SENSEA
and SENSEB(pulsed tW < trr)
(DC) -6
-1 6
1V
V
IOUT RMS Output Current 1.4 A
TjOperating Junction Temperature -25 +125 °C
fsw Switching Frequency 100 KHz
3/20
L6225
THE RMAL DA TA
PIN CONNECTIONS (Top View)
(5) The slug is internally connected to pins 1, 10,11 and 20 (GND pins).
Symbol Description PowerDIP20 SO20 PowerSO20 Unit
Rth-j-pins MaximumThermal Resistance Junction-Pins 13 15 - °C/W
Rth-j-case Maximum Thermal Resistance Junction-Case - - 2 °C/W
Rth-j-amb1 MaximumThermal Resistance Junction-Ambient 1
(1) Mounted on a m ul ti-layer FR4 PCB with a di ss i pating copper surface on the bot tom side of 6cm2 (with a thickness of 35µm).
41 52 - °C/W
Rth-j-amb1 Maximum Thermal Resistance Junction-Ambient 2
(2) Mounted on a m ul ti-layer FR4 PCB with a di ss i pating copper surface on the top side of 6cm2 (with a thicknes s of 35µm).
--36°C/W
Rth-j-amb1 MaximumThermal Resistance Junction-Ambient 3
(3) Mounted on a multi-layer FR4 PCB with a dissipating copper surface on the top side of 6cm2 (with a thickness of 35µm), 16 via holes
and a ground l ayer.
--16°C/W
Rth-j-amb2 Maximum Thermal Resistance Junction-Ambient 4
(4) Mounted on a m ul ti-layer FR4 PCB without any heat s i nking surf ace on th e board.
57 78 63 °C/W
PowerDIP20/SO20 PowerSO 20 (5)
GND
OUT1
A
SENSE
A
IN2
A
IN1
A
VCP
EN
A
OUT2
A
VS
A
VS
B
OUT2
B
VBOOT
IN2
B
EN
B
IN1
B
SENSE
B
OUT1
B
GND10
8
9
7
6
5
4
3
2
13
14
15
16
17
19
18
20
12
1
11
GND GND
D99IN1092A
GND
OUT1
B
SENSE
B
IN1
B
IN2
B
1
3
2
4
5
6
7
8
9
EN
B
VBOOT
OUT2
B
VS
B
GND15
14
13
12
11
D99IN1093A
10
20
19
18
17
16
IN1
A
IN2
A
SENSE
A
OUT1
A
GND GND
VS
A
OUT2
A
VCP
EN
A
L6225
4/20
(6) Also connected at the o utput dra i n of th e Overcur rent and Thermal prot ection M OS F ET. Therefore, it has t o be driven putting in series a
res istor with a value in the range of 2.2kΩ - 180KΩ, reco m m e nded 100kΩ
PIN DESCRIPTION
PACKAGE
Name Type Function
SO20/
PowerDIP20
PowerSO20
PIN # PIN #
1 6 IN1ALogic Input Bridge A Logic Input 1.
2 7 IN2ALogic Input Bridge A Logic Input 2.
3 8 SENSEAP ower Supply Bridge A Source Pin. This pin must be connected to Po wer
Ground directly or through a sensing power resistor.
4 9 OUT1APower Output Bridge A Output 1.
5, 6, 15, 16 1, 10, 11,
20 GND GND Signal Ground terminals. In PowerDIP and SO packages,
these pins are also used for heat dissipation toward the
PCB.
7 12 OUT1BPower Output Bridge B Output 1.
8 13 SENSEBP ower Supply Bridge B Source Pin. This pin must be connected to Po wer
Ground directly or through a sensing power resistor.
9 14 IN1BLogic Input Bridge B Logic Input 1.
10 15 IN2BLogic Input Bridge B Logic Input 2.
11 16 ENBLogic Input (6) Bridge B Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge B. This pin is also connected to the
collector of the Overcurrent and Thermal Protection
transistor to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.
12 17 VBOOT Supply
Voltage Bootstrap Voltage needed for driving the upper
PowerMOSFETs of both Bridge A and Bridge B.
13 18 OUT2BPower Output Bridge B Output 2.
14 19 VSBPower Supply Bridge B Power Supply Voltage. It must be connected to
the supply voltage together with pin VSA.
17 2 VSAPower Supply Bridge A Power Supply Voltage. It must be connected to
the supply voltage together with pin VSB.
18 3 OUT2APower Output Bridge A Output 2.
19 4 VCP Output Charge Pump Oscillator Output.
20 5 ENALogic Input (6) Bridge A Enable. LOW logic level switches OFF all Power
MOSFETs of Bridge A. This pin is also connected to the
collector of the Overcurrent and Thermal Protection
transistor to implement over current protection.
If not used, it has to be connected to +5V through a
resistor.
5/20
L6225
ELECTRICAL CHARACTERISTICS
(Tamb = 25 °C, Vs = 48V, unless otherwise specified)
Symbol Parameter Test Conditions Min Typ Max Unit
VSth(ON) Turn-on Threshold 5.8 6.3 6.8 V
VSth(OFF) Turn-off Threshold 5 5.5 6 V
ISQuiescent Supply Current All Bridges OFF;
Tj = -25°C to 125°C (7) 510mA
T
j(OFF) Thermal Shutdown Temperature 165 °C
Output DMOS Transist ors
RDS(ON) High-Side + Low-Side Switch ON
Resistance Tj = 25 °C 1.47 1.69 Ω
Tj =125 °C (7) 2.35 2.70 Ω
IDSS Leakage Current EN = Low; OUT = VS2mA
EN = Low; OUT = GND -0.3 mA
Source Drain Diodes
VSD Forward ON Voltage ISD = 1.4A, EN = LOW 1.15 1.3 V
trr Reverse Recove r y Time If = 1.4A 300 ns
tfr Forward Recovery Time 200 ns
Logic Input
VIL Low level logic input voltage -0.3 0.8 V
VIH High level logic input voltage 2 7 V
IIL Low Level Logic Input Current GND Logic Input Voltage -10 µA
IIH High Level Logic Input Current 7V Logic Input Voltage 10 µA
Vth(ON) Turn-on Input Threshold 1.8 2.0 V
Vth(OFF) Turn-off Input Threshold 0.8 1.3 V
Vth(HYS) Input Threshold Hysteresis 0.25 0.5 V
Switching Characteristics
tD(on)EN
Enable to out turn O N delay time
(8)
ILOAD =1.4A, Resistive Load 500 800 ns
tD(on)IN Input to out turn ON delay time ILOAD =1.4A, Resistive Load
(dead time included) 1.9 µs
tRISE Output rise time(8) ILOAD =1.4A, Resistive Load 40 250 ns
tD(off)EN
Enable to out turn OFF delay time
(8)
ILOAD =1.4A, Resistive Load 500 800 1000 ns
tD(off)IN
Input to out turn OFF delay time
ILOA D =1.4A, Resistive Load 500 800 1000 ns
tFALL Output Fall Time (8) ILOAD =1.4A, Resistive Load 40 250 ns
L6225
6/20
(7) Tested at 25°C in a restricted range and guaranteed by characterization.
(8) See Fig. 1.
(9) See Fig. 2.
Figure 1. Switching Characteristi c Definition
tdt Dead Time Protection 0.5 1 µs
fCP Charge pump frequency -25°C<Tj <125°C 0.6 1 MHz
Over Current Protection
ISOVER Input Supply Overcurrent
Protection Threshold Tj = -25°C to 125°C (7) 2 2.8 3.55 A
ROPDR Open Drain ON Resistance I = 4mA 40 60 Ω
tOCD(ON) OCD Turn-on Delay Time (9) I = 4mA; CEN < 100pF 200 ns
tOCD(OFF) OCD Turn-off Delay Time (9) I = 4mA; CEN < 100pF 100 ns
ELECTRICAL CHARACTERISTICS (continued)
(Tamb = 25 °C, Vs = 48V, unless otherwise specified)
Symbol Parameter Test Conditions Min Typ Max Unit
V
th(ON)
V
th(OFF)
90%
10%
EN
I
OUT
t
t
t
FALL
t
D(OFF)EN
t
RISE
t
D(ON)EN
D01IN1316
7/20
L6225
Figu re 2. Overcurre nt D et ect i on Tim i ng Defi ni tio n
ISOVER
90%
10%
IOUT
VEN
tOCD(OFF)
tOCD(ON)
D02IN1399
ON
OFF
BRIDGE
L6225
8/20
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMP
The L6225 integrates two independent Power MOS
Full Bridges. Each Power MOS has an Rd-
son=0.73ohm (typical value @25°C), with intrinsic
fast freewheeling diode. Cross conduc tion protection
is achieved using a dead time (td = 1
µ
s typical) be-
tween the switch off and switch on of two Pow er MOS
in one leg of a bridge.
Using N Channel Power MOS for the upper transis-
tors in the bridge requires a gate drive vol tage above
the power supply voltage. The Bootstrapped (Vboot)
supply is obtained through an internal Oscillator and
few external components to realize a charge pump
circuit as shown in Figure 3. The oscillator output
(VCP) is a square wave at 600kHz (typical) with 10V
amplitude. Recommended values/part numbers for
the charge pump circuit are shown in Table1.
Table 1. Charge Pump External Components
Values
Figu re 3. Charge Pum p Circ u it
LOGIC INPUTS
Pins IN1
A
, IN2
A
, IN1
B
and IN2
B
are TTL/CMOS and
µ
C compatible logic inputs. The internal structure is
shown in Fi g. 4. Typical value for turn- on and turn-off
thresholds are respectively Vthon=1.8V and
Vthoff=1.3V.
Pins EN
A
and EN
B
have identica l input str ucture w ith
the exception that the drains of the Overcurrent and
thermal protection MOSFETs (one for the Bridge A
and one for the Bridge B) ar e also connected to these
pins. Due to these connections some care needs to
be taken in driving these pins. The EN
A
and EN
B
in-
puts may be driven in one of two configurations as
shown in figures 5 or 6. If driven by an open drain
(collector) structure, a pull-up resistor R
EN
and a ca-
pacitor C
EN
are connected as shown in Fig. 5. If the
driver is a standard Push-Pull structure the resistor
R
EN
and the capacitor C
EN
are connected as shown
in Fig. 6. The resistor R
EN
should be chosen in the
range from 2.2k
Ω
to 180K
Ω
. Recommended values
for R
EN
and C
EN
are respectively 100K
Ω
and 5.6nF.
More information on selecting the values is found in
the Overcurrent Protection section.
Figu re 4. Lo gi c Inp uts I nte rn al S truc ture
Figure 5. EN
A
and EN
B
Pins Open Collector
Driving
Figure 6. EN
A
and EN
B
Pins Push-Pull Driving
TRUTH TABLE
X = Don' t care
High Z = High Impedance Output
CBOOT 220nF
CP10nF
RP100Ω
D1 1N4148
D2 1N4148
D2 CBOOT
D1
RP
CP
VS
VSA
VCP VBOOT VSB
D01IN1328
INPUTS OUTPUTS
EN IN1 IN2 OUT1 OUT2
L X X High Z High Z
H L L GND GND
H H L Vs GND
HLHGNDVs
HHHVsVs
5V
D01IN1329
ESD
PROTECTION
5V
5V
OPEN
COLLECTOR
OUTPUT
REN
CEN
ENA or ENB
D02IN134
9
5V
PUSH-PULL
OUTPUT
REN
CEN
ENA or ENB
D02IN135
0
9/20
L6225
NON-DISSIPATIVE OVERCURRENT PROTECTION
The L6225 integrates an Overcurrent Detection Circuit (OCD). This circuit provides protection against a short
cir cuit to gr ound or between two phases of the br idge. With this internal over current detection, the external cur -
rent sens e resistor nor mally used and i t s assoc iated power dissipation ar e elimi nated. Figure 7 shows a simp li-
fied schematic of the overcurrent detection circuit.
To implement the over current detection, a sens ing element that deli vers a small but preci se fraction of the out-
put current is implemented with each high side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference cur-
rent I
REF
. When the output current in one bridge reaches the detection threshold (typically 2.8A) the relative
OCD compar ator signals a fault condi tion. When a fault condition is detec ted, the EN pin is pulled belo w the tur n
off threshold (1.3V typical) by an internal open drain MOS with a pull dow n capability of 4mA . B y using an ex-
ternal R-C on the EN pin, the off time before recovering normal operation can be easil y program med by m eans
of the accurate thresholds of the logic inputs.
Figure 7. Overcur rent Protection Simpl ified Schema tic
F ig ure 8 s hows the O v erc u r ren t Detectio n o pe ration. T he D i sa bl e T im e t
DISABLE
be for e recove rin g n o rm al op era-
tion can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected whether by
C
EN
and R
EN
values and its magnitude is reported in Figure 9. The Delay Time t
DELAY
befo re t urnin g off th e br idge
when an overcurrent has been detected depends only by C
EN
va lue. Its m agnitude is reported i n Figure 10.
C
EN
is also used for providing immunity to pin EN against fast transient noises. Therefore the value of C
EN
should be c hosen as big as possi ble acc or ding to the maximum tolerable D elay Time and th e R
EN
value should
be chosen according to the desired Disable Time.
The res istor R
EN
should be chosen in the range from 2.2K
Ω
to 180K
Ω
. Recom mended val ues for R
EN
and C
EN
are respectively 100K
Ω
and 5.6nF that allow obtaining 200
µ
s Disable Time.
+
OVER TEMPERATURE
I
REF
(I
1A
+I
2A
) / n
I
1A
/ n
POWER SENSE
1 cell
POWER SENSE
1 cell
POWER DMOS
n cells
POWER DMOS
n cells
HIGH SIDE DMOSs OF
THE BRIDGE A
OUT1
A
OUT2
A
VS
A
I
1A
I
2A
I
2A
/ n
OCD
COMPARATOR
TO GATE
LOGIC
INTERNAL
OPEN-DRAIN
R
DS(ON)
40Ω TYP.
C
EN
R
EN
EN
A
+5V
µC or LOGIC
D02IN1353
L6225
10/20
Figure 8. Overcur rent Protection Wavefor m s
ISOVER
IOUT
Vth(ON)
Vth(OFF) VEN(LOW)
VDD
tOCD(ON) tD(ON)EN
tEN(FALL) tEN(RISE)
tDISABLE
tDELAY
tOCD(OFF)
tD(OFF)EN
VEN
BRIDGE
ON
OFF
OCD
ON
OFF
D02IN1400
11/20
L6225
Figure 9. tDISABLE versus CEN and REN (VDD = 5V).
Figure 10. tDELAY versus CEN (VDD = 5V ).
THERMAL PROTECTION
In addition to the Ovecurrent Protection, the L6225 integrates a Thermal Protection for preventing the device
destruction in case of junction over temperature. It works sensing the die temperature by means of a sensible
element integrated in the die. The device switch-off when the junction temperature reaches 165°C (typ. value)
with 15°C hysteresis (typ. value).
1 10 100
1
10
100
1.103
CEN [nF]
tDISABLE [µs]
REN = 220 kΩREN = 100 kΩREN = 47 kΩ
REN = 33 kΩ
REN = 10 kΩ
1 10 100
1
10
100
1.103
CEN [nF]
tDISABLE [µs]
REN = 220 kΩREN = 100 kΩREN = 47 kΩ
REN = 33 kΩ
REN = 10 kΩ
1 10 100
0.1
1
10
Cen [n F]
tdelay [µs]
L6225
12/20
APPLICATION INFORMATION
A typical application using L6225 is shown in Fig. 11. Typical component values for the application are shown
in Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the pow er
pins ( VS
A
and VS
B
) and ground near the L6225 to improve the high frequenc y fil tering on the power supply and
reduc e high frequency transients ge nerate d by the switchi ng. The capaci tors connected from the EN
A
and EN
B
inputs to ground set the shut down time for the Brgidge A and Bridge B r espectively when an over current is
detected (see O vercurrent Protection). The two current sources (SENSE
A
and SENSE
B
) should be connected
to Power Ground with a trace length as short as possi ble in the layout. To increase noise immunity, unused logic
pins (except E N
A
and EN
B
) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin
description). It is recommended to keep Power Ground and Signal Ground separated on PCB.
Table 2. Component Valu es for Typ ical Application
Figure 11. Typical Appli cation
C1100uF D11N4148
C2100nF D21N4148
CBOOT 220nF RENA 100KΩ
CP10nF RENB 100KΩ
CENA 5.6nF RP100Ω
CENB 5.6nF
OUT1
A
4
18
16
157
13
OUT2
A
GND
GND
GND
GND
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
VS
B
VCP
VBOOT
C
P
C
BOOT
R
P
D
2
D
1
C
1
C
2
SENSE
A
17
6
5
EN
B
C
ENB
R
ENB
ENABLE
B
11
14
3
12
19
SENSE
B
LOAD
A
LOAD
B
8
EN
A
C
ENA
R
ENA
ENABLE
A
20
D02IN1345
1IN1
A
IN2
A
IN1
A
IN2
A
2
IN2
B
10
IN1
B
IN2
B
IN1
B
9
13/20
L6225
PARALLELED OPERATION
The outputs of the L6225 can be paralleled to increase the output current capability or reduce the power dissi-
pation in the device at a given current level. It must be noted, however, that the internal wire bond connections
from the die to the power o r sense pins of the pa ckage m ust carry curr ent in both of the as sociated half bri dges.
When the two halves of one full bridge (for example OUT1
A
and OUT2
A
) are connected in parallel, the peak
current rating is not increased since the total current must still flow through one bond wire on the power supply
or sense pin. In addition, the over current detection senses the sum of the current in the upper devices of each
bridge (A or B) so connecting the two halves of one bridge in parallel does not increase the over current detec-
tion threshold.
For most applications the recommended configuration is Half Bridge 1 of Bridge A paralleled with the Half Bridge
1 of the Bridge B, and the same for the Half Bridges 2 as shown in Figure 12. The current in the two devices
connected in parallel will share very well since the R
DS(ON)
of the devices on the same die is well matched.
In this configuration the resulting Bridge has the following characteristics.
- Equivalent Device: FULL BRIDGE
- R
DS(ON)
0.37
Ω
Typ. Value @ T
J
= 25°C
- 2.8A max RMS Load Current
- 5.6A OCD Threshold
Figure 12. Parallel connection for higher current
To operate the device in parallel and maintain a lower over current threshol d, Half Bridge 1 and the Half B ridge
2 of the Bridge A can be connected in parallel and the same done for the B ridge B as shown in Figure 13. In
this c onfiguration, the peak current for eac h hal f br idge is stil l l imited by the bond wi res for the s upply and s ense
pins so the dissipation in the device will be reduced, but the peak current rating is not increased. This configu-
ration, the resulting bridge has the following characteristics.
- Equivalent Device: FULL BRIDGE
- R
DS(ON)
0.37
Ω
Typ. Value @ T
J
= 25°C
- 1.4A max RMS Load Current
- 2.8A OCD Threshold
OUT1
A
4
7
16
15
18
13
OUT1
B
GND
GND
GND
GNDOUT2
B
OUT2
A
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
VS
B
VCP
VBOOT
C
1
SENSE
A
17
6
5
EN
B
11
14
3
12
19
SENSE
B
LOAD
8
EN
A
C
EN
R
EN
EN20
D02IN1359
1
IN2
IN1
A
IN2
B
10
IN1
B
9
IN2
A
IN1
2
C
P
C
BOOT
R
P
D
2
D
1
C
2
L6225
14/20
Figure 13. Paral le l connec tion with low er Over curr ent Th resho ld
It is also possible to paral lel the four H alf Bridges to obtain a simple Half B ridge as shown in Fig. 14 The resulting
half bridge has the following characteristics.
- Equivalent Device: HALF BRIDGE
- R
DS(ON)
0.18
Ω
Typ. Value @ T
J
= 25°C
- 2.8A max RMS Load Current
- 5.6A OCD Threshold
Figure 14. Paralleling the four Half Bridges
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
4
18 16
157
13
OUT2
A
GND
GND
GND
GND
OUT2
B
OUT1
B
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
VS
B
VCP
VBOOT
C
1
SENSE
A
17
6
5
14
3
12
19
SENSE
B
LOAD
8
D02IN1360
10
IN
A
IN2
B
IN2
A
2
IN1
A
1
IN1
B
IN
B
9
EN
B
EN
A
C
EN
R
EN
EN11
20
C
P
C
BOOT
R
P
D
2
D
1
C
2
OUT1
A
4
7
16
15
18
13
OUT1
B
GND
GND
GND
GND
OUT2
B
OUT2
A
VS
A
POWER
GROUND
SIGNAL
GROUND
+
-
VS
8-52V
DC
VS
B
VCP
VBOOT
C
1
SENSE
A
17
6
5
EN
B
1114
3
12
19
SENSE
B
8
EN
A
C
EN
R
EN
EN20
D02IN1366
1IN1
A
IN2
B
10
IN1
B
9
IN2
A
2
LOAD
IN
15/20
L6225
OUTPUT CURRENT CAPABILITY AND IC POWER DISSIPATION
In Fi g. 15 and Fig. 16 are show n the approxi mate relation between th e output curr ent and the IC power dis sipa-
tion using PWM current control driving two loads, for two different driving types:
– One Full Bridge ON at a time (Fig. 15) in which only one load at a time i s energ ized.
– Two Full Bridges ON at the sam e time (Fig. 16) in which two loads at the same time are e nergized.
For a given output current and driving type the power dissipated by the IC can be easily evaluated, in order to
establish which package should be used and how large must be the on-board copper dissipating area to guar-
antee a safe operating junction temperature (125°C maximum).
Figure 15. IC Power Dis sipation versu s Outp ut Current wi th One Full Bridge ON at a tim e.
Figure 16. IC P ower Dissipation versus Ou tput Curren t wi th Two Full Bridges ON at the same time.
THERMAL MANAGEMENT
In m ost applications the power dissi pation in the IC is the m ain f actor that sets the maximum current that can be de-
li ver by the dev ice in a saf e operating condit ion. Ther efore, it ha s to be taken i nto account very car ef ully. Besides the
a vai la ble space on the PCB, the r ight pack age should be chose n considering t he power di ssipati on. Heat sinking c an
be achieved using copper on the PCB with proper area and thickness. Figures 18, 19 and 20 show the Junction-to-
Ambient Thermal Resistance values for the PowerSO20, PowerDIP20 and SO20 packages.
For instance, using a PowerS O package with copper slug soldered on a 1.5 mm copper thickness F R4 board
with 6cm
2
dissipati ng footpr int (cop per thicknes s of 35µ m), the R
th j-amb
is about 35° C/W. Fig. 17 shows mount-
ing methods for this pack age. Using a multi-layer board wi th vias to a ground plane, thermal impeda nce can be
reduced dow n to 15°C/W.
No PWM
f
SW
= 30 kHz (slow decay)
Test Conditions:
Supply Voltage = 24V
IA
IB
IOUT
IOUT
ONE FULL BRIDGE ON AT A TIME
PD [W]
IOUT [A]
0 0.25 0.5 0.75 1 1.25 1.5
0
2
4
6
8
10
No PWM
f
SW
= 30 kHz (slow decay)
Test Conditions:
Supply Voltage = 24 V
IA
IB
IOUT
IOUT
PD [W]
IOUT [A]
TWO FULL BRIDGES ON AT THE SAME TIME
0 0.25 0.5 0.75 1 1.25 1.5
0
2
4
6
8
10
L6225
16/20
Figure 17. Mou nting the PowerS O pack age.
Figure 18. Pow erSO20 Junction-Am bient thermal resistance versus on -board co pp er area.
Figure 19. PowerDIP20 Junction-Ambient thermal resistance versus on-board copper area.
Figure 20. SO20 Ju nction -Am bient thermal resistance ve rsus on -board co pp er area.
Sl ug soldered
to PC B with
dissipating area
Sl ug soldered
to PC B with
dissipating area
plus ground layer
Slug soldered to PCB with
dissipating area plus ground layer
contacted through via holes
13
18
23
28
33
38
43
12345678910111213
Without Ground Layer
With Ground Layer
With Ground Layer+16 via
Holes
sq. cm
ºC / W
On-Board Copper Area
sq . cm
ºC / W
On-Board Copper Area
Copper Area is on Bottom Side
Copper Area is on Top Side
33
34
35
36
37
38
39
40
41
42
123456789101112
48
50
52
54
56
58
60
62
64
66
68
123456789101112
Copper Area is on Top Side
sq. cm
ºC / W On-Board Copper Area
17/20
L6225
OUTLINE AN D
M E CHANICAL DA T A
e
a2 A
Ea1
PSO20MEC
DETAIL A
T
D
110
1120
E1
E2
h x 45
DETAIL A
lead
slug
a3
S
Gage Plane 0.35
L
DETAIL B
R
DETAIL B
(COPLANARITY)
GC
- C -
SEATING PLANE
e3
b
c
NN
H
BO TTOM VIEW
E3
D1
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 3.6 0.142
a1 0.1 0.3 0.004 0.012
a2 3.3 0.130
a3 0 0.1 0.000 0.004
b 0.4 0.53 0.016 0.021
c 0.23 0.32 0.009 0.013
D (1) 15.8 16 0.622 0.630
D1 9.4 9.8 0.370 0.386
E 13.9 14.5 0.547 0.570
e 1.27 0.050
e3 11.43 0.450
E1 (1) 10.9 11.1 0.429 0.437
E2 2.9 0.114
E3 5.8 6.2 0.228 0.244
G 0 0.1 0.000 0.004
H 15.5 15.9 0.610 0.626
h 1.1 0.043
L 0.8 1.1 0.031 0.043
N 8˚ (typ.)
S 8˚ (max.)
T 10 0.394
(1) “D and E1” do not include mold flash or protusions.
- Mo l d flash or protusio ns shall not exceed 0.15mm (0.006”)
- Critical dime nsio ns: “E”, “G” an d “a3”.
PowerSO20
0056635
JEDEC MO-166
Weight:
1.9gr
L6225
18/20
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
a1 0.51 0.020
B 0.85 1.40 0.033 0.055
b 0.50 0.020
b1 0.38 0.50 0.015 0.020
D 24.80 0.976
E 8.80 0.346
e 2.54 0.100
e3 22.86 0.900
F 7.10 0.280
I 5.10 0.201
L 3.30 0.130
Z 1.27 0.050
Powerdip 20
OUTLINE AND
MECHANICAL DAT A
19/20
L6225
110
1120
A
e
B
D
E
L
KH
A1 C
SO20MEC
h x 45˚
SO20
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A 2.35 2.65 0.093 0.104
A1 0.1 0.3 0.004 0.012
B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009 0.013
D 12.6 13 0.496 0.512
E 7.4 7.6 0.291 0.299
e 1.27 0.050
H 10 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.4 1.27 0.016 0.050
K 0˚ (min.)8˚ (max.)
OUTLINE AND
MECHANICAL DATA
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no r esponsibility for the consequences
of use of such information nor for any inf ringement of patents or other rights of third parties which may result from its use. No license is granted
by i m pl i cation or oth erwise under any pat ent or paten t rights of STMi croelectronic s. Specifications m entioned in this publicati on are subject
to change without notice. This publication supersedes and replaces all information previous ly supplied. STMicroelectronics products ar e not
authorized f or use as c ri tical com ponents in lif e support devices or systems wi t hout exp ress writ ten approval of STM i croelectronics.
Th e ST logo is a register ed tradem ark of STM i croel ectronic s.
All o th er names are the propert y of their re spectiv e owners
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20/20
L6225
