SG6741ASY - Fairchild - Datasheet.Directory

October 2008

SG6741A • Rev. 1.0.1

SG6741A — Highly Integrated Green-Mode PWM Controller

SG6741A

Highly Integrated Green-Mode PWM Controller

Features

 High-Voltage Startup

 Low Operating Current: 4mA

 Linearly Decreasing PWM Frequency to 18kHz

 Frequency Hopping to Reduce EMI Emissions

 Peak-Current-Mode Control

 Cycle-by-Cycle Current Limiting

 Leading-Edge Blanking (LEB)

 Synchronized Slope Compensation

 GATE Output Maximum Voltage Clamp: 18V

 VDD Over-Voltage Protection (Auto Restart)

 VDD Under-Voltage Lockout (UVLO)

 Internal Open-Loop Protection

 Constant Power Limit (Full AC Input Range)

Applications

General-purpose switch-mode power supplies and

flyback power converters, including:

 Power Adapters

 Open-Frame SMPS

Description

The highly integrated SG6741A series of PWM

controllers provides several features to enhance the

performance of flyback converters.

To minimize standby power consumption, a proprietary

green-mode function provides off-time modulation to

linearly decrease the switching frequency at light-load

conditions. To avoid acoustic-noise problems, the

minimum PWM frequency is set above 18KHz. This

green-mode function enables the power supply to meet

international power conservation requirements. With the

internal high-voltage startup circuitry, the power loss

due to bleeding resistors is eliminated. To further

reduce power consumption, SG6741A is manufactured

using the BiCMOS process, which allows an operating

current of only 4mA.

SG6741A integrates a frequency-hopping function

internally to reduce EMI emission of a power supply

with minimum line filters. A built-in synchronized slope

compensation achieves stable peak-current-mode

control. The proprietary internal line compensation

ensures constant output power limit over a wide AC

input voltages, from 90VAC to 264 VAC.

SG6741A provides many protection functions. In

addition to cycle-by-cycle current limiting, the internal

open-loop protection circuit ensures safety when an

open-loop or output short-circuit failure occurs. PWM

output is disabled until VDD drops below the UVLO lower

limit, when the controller starts up again. As long as VDD

exceeds ~26V, the internal OVP circuit is triggered.

SG6741A is available in an 8-pin SOP package.

Ordering Information

Part Number Operating

Temperature Range Package Eco

Status Packing Method

SG6741ASZ -40 to +105°C 8-Lead Small Outline Package (SOP) Green Tape & Reel

SG6741ASY -40 to +105°C 8-Lead Small Outline Package (SOP) Green Tape & Reel

For Fairchild’s defini t i on of “green” Eco St atus, pleas e visit: http://www.fairchildsemi.com/company/green/rohs_green.html.

SG6741A • Rev. 1.0.1 2

SG6741A — Highly Integrated Green-Mode PWM Controller

Application Diagram

Figure 1. Typical Application

Block Diagram

Figure 2. Block Diagram

SG6741A • Rev. 1.0.1 3

SG6741A — Highly Integrated Green-Mode PWM Controller

Marking Informa ti on

Figure 3. Top Mark

Pin Configuration

Figure 4. Pin Configuration

Pin Definitions

Pin # Name Description

1 GND Ground.

2 FB

Feedback. The signal from the external compensation circuit is fed into this pin. The PWM duty

cycle is determined in response to the signal on this pin and the current-sense signal on SENSE

pin.

3 NC No Connection.

4 HV Startup Input. For startup, this pin is pulled HIGH to the line input or bulk capacitor via resistors.

5 RI

Reference Setting. A resistor connected from the RI pin to GND pin provides a constant current

source, which determines the center PWM frequency. Increasing the resistance reduces PWM

frequency. Using a 26KΩ resistor for RI results in a 65kHz center PWM frequency.

6 SENSE

Current Sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle

current limiting.

7 VDD

Power Supply. The internal protection circuit disables PWM output as long as VDD exceeds the

OVP trigger point.

8 GATE Driver Output. Totem-pole output driver. Soft driving waveform is implemented for improved EMI.

※marking for SG6741ASY

※marking for SG6741ASZ

HV

NC

GATE

VDD

SENSE

RI

GND

FB

ZXYTT

6741A

TPM

SG6741ATP

XXXXXXXXYWWV

F: Fairchild logo

Z: Plant code

X: 1 digit year code

Y: 1 digit week code

TT: 2 digits die run code

T: Package type (S = SOP)

P: Y=Green package

M: Manufacture flow code

T: S = SOP

P: Z =Lead Free

Null=regular package

XXXXXXXX: Wafer Lot

Y: Year; WW: Week

V: Assembly Location

SG6741A • Rev. 1.0.1 4

SG6741A — Highly Integrated Green-Mode PWM Controller

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device

reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are

given with respect to the ground pin.

Symbol Parameter Min. Max. Unit

VVDD DC Supply Voltage(1, 2) 30 V

VFB FB Pin Input Voltage -0.3 7.0 V

VSENSE SENSE Pin Input Voltage -0.3 7.0 V

VRI RI Pin Input Voltage -0.3 7.0 V

VHV HV Pin Input Voltage 500 V

PD Power Dissipation (TA＜50°C) 400 mW

ΘJA Thermal Resistance (Junction-to-Air) 141 °C/W

TJ Operating Junction Temperature -40 +125 °C

TSTG Storage Temperature Range -55 +150 °C

TL Lead Temperature (Wave Soldering or IR, 10 Seconds) +260 °C

Electrostatic Discharge Capability,

Human Body Model, JESD22-A114 All Pins Except HV Pin 4 kV

ESD Electrostatic Discharge Capability,

Machine Model, JESD22-A115 All Pins Except HV Pin 200 V

Notes:

1. All voltage values, except differential voltages, are given with respect to the network ground terminal.

2. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device.

SG6741A • Rev. 1.0.1 5

SG6741A — Highly Integrated Green-Mode PWM Controller

Electrical Characteristics

VDD=15V; TA=25C°, unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Units

VDD Section

VDD-OP Continuously Operating Voltage 22 V

VDD-ON Start Threshold Voltage 15.5 16.5 17.5 V

VDD-OFF Minimum Operating Voltage 9.5 10.5 11.5 V

IDD-ST Startup Current VDD-ON – 0.16V 30 µA

IDD-OP Operating Supply Current VDD=15V, GATE Open 4 5 mA

IDD-OLP Internal Sink Current VDD-OLP +0.1V 50 70 90 µA

VDD-OLP I

DD-OLP off Voltage 6.5 7.5 8.0 V

VDD-OVP V

DD Over-Voltage Protection Auto Restart 25 26 27 V

tD-VDDOVP VDD Over-Voltage Protection

Debounce Time Auto Restart 100 180 260 µs

HV Electrical Characteristics

IHV Supply Current Drawn from HV

VAC=90V, (VDC=120V)

VDD=10µF 2 mA

IHV-LC Leakage Current After Startup HV=500V, VDD=VDD-

OFF+1V 1 20 µA

Oscillator Section

Center Frequency 62 65 68

fOSC Frequency in Nominal Mode Hopping Range ±3.7 ±4.2 ±4.7 kHz

tHOP Hopping Period 4.4 ms

fOSC-G Green-Mode Frequency 16 18 21 kHz

fDV Frequency Variation vs. VDD

Deviation VDD=11V to 22V 5 %

fDT Frequency Variation vs.

Temperature Deviation TA=-20 to 85°C 5 %

Feedback Input Section

AV Input Voltage to Current-Sense

Attenuation 1/3.75 1/3.20 1/2.75 V/V

ZFB Input Impedance 4 7 kΩ

VFB-OPEN FB Output High Voltage FB Pin Open 5.5 V

VFB-OLP FB Open-loop Trigger Level 3.7 4.0 4.3 V

tD-OLP The Delay Time of FB Pin Open-

Loop Protection RI=26kΩ 50 56 62 ms

VFB-N Green-Mode Entry FB Voltage 1.9 2.1 2.3 V

VFB-G Green-Mode Ending FB Voltage VFB-N -

0.5 V

VFB-ZDC Zero Duty-Cycle Input Voltage 1 V

Continued on following page…

SG6741A • Rev. 1.0.1 6

SG6741A — Highly Integrated Green-Mode PWM Controller

Electrical Characteristics (Continued)

VDD=15V; TA=25C°, unless otherwise noted.

OSC

f

OSC

-

V

FB-G

V

FB-ZDC

V

FB

V

FB-N

PWM Frequency

Figure 5. PWM Frequency

Symbol Parameter Conditions Min. Typ. Max. Units

Current Sense Section

ZSENSE Input Impedance 12 KΩ

VSTHFL Current Limit Flatten Threshold Voltage 0.87 0.90 0.93 V

VSTHVA Current Limit Valley Threshold Voltage VSTHFL–VSTHVA 0.18 0.22 0.26 V

tPD Delay to Output 100 200 ns

tLEB Leading-Edge Blanking Time 275 350 425 ns

Gate Section

DCYMAX Maximum Duty Cycle 60 65 70 %

VGATE-L Gate Low Voltage VDD=15V, IO=50mA 1.5 V

VGATE-H Gate High Voltage VDD=12.5V, IO=-50mA 8 V

tr Gate Rising Time VDD=15V, CL=1nF 150 250 350 ns

tf Gate Falling Time VDD=15V, CL=1nF 30 50 90 ns

IGATE-SOURCE Gate Source Current VDD=15V, GATE=6V 250 mA

VGATE-CLAMP Gate Output Clamping Voltage VDD=22V 18 V

DCYMAX Maximum Duty Cycle 60 65 70 %

SG6741A • Rev. 1.0.1 7

SG6741A — Highly Integrated Green-Mode PWM Controller

Typical Performance Characteristics

0

5

10

15

20

25

-40-25-10 5 203550658095110125

Tem

p

erature

(

°C

)

IDD-ST (µA)

0.0

1.0

2.0

3.0

4.0

5.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (°C )

I

DD-OP

(

m

A

)

Figure 6. Startup Current (IDD-ST) vs. Temperature Figure 7. Operating Supply Current (IDD-OP)

vs. Temperature

15.0

16.0

17.0

18.0

19.0

20.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature ( )

V

DD -ON

(V)

°C

8.0

9.0

10.0

11.0

12.0

13.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Tem

p

erature

(

°

C

)

V

DD-OFF

(V)

Figure 8. Start Threshold Voltage (VDD-ON)

vs. Temperature Figure 9. Minimum Operating Voltage (VDD-OFF)

vs. Temperature

0.0

1.0

2.0

3.0

4.0

5.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Tempe ratur e (°C )

I

HV

(mA)

0

2

4

6

8

10

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (°C )

I

HV-LC

(µA)

Figure 10. Supply Current Drawn from HV Pin (IHV)

vs. Temperature Figure 11. Figure Caption

60

62

64

66

68

70

-4 0 -2 5 -1 0 5 2 0 3 5 5 0 6 5 8 0 9 5 1 1 0 1 2 5

Temperatur e (°C )

f

OSC

(kHz)

60.0

62.0

64.0

66.0

68.0

70.0

-40 -25 -10 5 20 35 50 65 80 95 110 125

Temperature (°C )

DC

Y

MAX

(

%

)

Figure 12. Frequency in Nominal Mode (fOSC)

vs. Temperature Figure 13. Maximum Duty Cycle (DCYMAX)

vs. Temperature

SG6741A • Rev. 1.0.1 8

SG6741A — Highly Integrated Green-Mode PWM Controller

Functional Description

Startup Current

For startup, the HV pin is connected to the line input or

bulk capacitor through an external resistor, RHV, which

is recommended as 100KΩ. Typical startup current

drawn from pin HV is 2mA and charges the hold-up

capacitor through the resistor RHV. When the VDD

capacitor level reaches VDD-ON, the startup current

switches off. At this moment, the VDD capacitor only

supplies the SG6741A to maintain VDD before the

auxiliary winding of the main transformer provides the

operating current.

Operating Current

Operating current is around 4mA. The low operating

current enables a better efficiency and reduces the

requirement of VDD hold-up capacitance.

Green-Mode Operation

The proprietary green-mode function provides an off-

time modulation to reduce the switching frequency in

the light-load and no-load conditions. The on-time is

limited for better abnormal or brownout protection. VFB,

which is derived from the voltage feedback loop, is

taken as the reference. Once VFB is lower than the

threshold voltage, switching frequency is continuously

decreased to the minimum green-mode frequency

around 18KHz (RI=26KΩ).

Oscillator Operation

A resistor connected from the RI pin to the GND pin

generates a constant current source for the controller.

This current is used to determine the center PWM

frequency. Increasing the resistance reduces PWM

frequency. Using a 26KΩ resistor RI results in a

corresponding 65KHz PWM frequency. The relationship

between RI and the switching frequency is:

(KHz)

)(K

I

R

1690

PWM

fΩ

= (1)

The range of the PWM oscillation frequency is designed

as 47kHz ~ 109kHz.

Current Sensing and PWM Current

Limiting

Peak-current-mode control is utilized in SG6741A to

regulate output voltage and provide pulse-by-pulse

current limiting. The switch current is detected by a

sense resistor into the SENSE pin. The PWM duty cycle

is determined by this current sense signal and VFB, the

feedback voltage. When the voltage on the SENSE pin

reaches around VCOMP = (VFB–1.2)/3.2, a switch cycle

terminates immediately. VCOMP is internally clamped to a

variable voltage around 0.85V for output power limit.

Leading-Edge Blanking (LEB)

Each time the power MOSFET is switched on, a turn-on

spike occurs on the sense-resistor. To avoid premature

termination of the switching pulse, a leading-edge

blanking time is built in. During this blanking period, the

current-limit comparator is disabled and cannot switch

off the gate driver.

Under-Voltage Lockout ( UVLO )

The turn-on and turn-off thresholds are fixed internally

at 16.5V and 10.5V. During startup, the hold-up

capacitor must be charged to 16.5V through the startup

resistor to enable the IC. The hold-up capacitor

continues to supply VDD before the energy can be

delivered from auxiliary winding of the main transformer.

VDD must not drop below 10.5V during startup. This

UVLO hysteresis window ensures that hold-up capacitor

is adequate to supply VDD during startup.

Gate Output / Soft Driving

The BiCMOS output stage is a fast totem-pole gate

driver. Cross conduction is avoided to minimize heat

dissipation, increase efficiency, and enhance reliability.

The output driver is clamped by an internal 18V Zener

diode to protect power MOSFET transistors against

undesirable gate over voltage. A soft driving waveform

is implemented to minimize EMI.

Built- in Slope Compensation

The sensed voltage across the current-sense resistor is

used for peak-current-mode control and pulse-by-pulse

current limiting. Built-in slope compensation improves

stability or prevents sub-harmonic oscillation. SG6741A

inserts a synchronized positive-going ramp at every

switching cycle.

Constant Output Power Li mi t

When the SENSE voltage, across the sense resistor Rs,

reaches the threshold voltage, around 0.9V, the output

GATE drive is turned off after a small delay, tPD. This

delay introduces an additional current proportional to tPD

• VIN / LP. Since the delay is nearly constant, regardless

of the input voltage VIN, higher input voltage results in a

larger additional current and the output power limit is

higher than that under low input line voltage. To

compensate this variation for wide AC input range, a

sawtooth power-limiter is designed to solve the unequal

power-limit problem. The power limiter is designed as a

positive ramp signal fed to the inverting input of the

OCP comparator. This results in a lower current limit at

high-line inputs than at low-line inputs.

SG6741A • Rev. 1.0.1 9

SG6741A — Highly Integrated Green-Mode PWM Controller

VDD Over-voltage Protection ( O VP)

VDD over-voltage protection has been built in to prevent

damage due to abnormal conditions. Once the VDD

voltage is over the VDD over-voltage protection voltage

(VDD-OVP) and lasts for tD-VDDOVP, the PWM pulses are

disabled until the VDD voltage drops below the UVLO,

then starts again. Over-voltage conditions are usually

caused by open feedback loops.

Limited Power Control

The FB voltage increases every time the output of the

power supply is shorted or overloaded. If the FB voltage

remains higher than a built-in threshold for longer than

tD-OLP, PWM output is turned off. As PWM output is

turned off, the supply voltage VDD begins decreasing.

When VDD goes below the turn-off threshold (~10.5V)

the controller is totally shut down. VDD is charged up to

the turn-on threshold voltage of 16V through the startup

resistor until PWM output is restarted. This protection

feature continues as long as the overloading condition

persists. This prevents the power supply from

overheating due to overloading conditions.

Noise Immunit y

Noise on the current sense or control signal may cause

significant pulse-width jitter, particularly in continuous-

conduction mode. Slope compensation helps alleviate

this problem. Good placement and layout practices

should be followed. Avoiding long PCB traces and

component leads, locating compensation and filter

components near the SG6741A, and increasing the

power MOS gate resistance improve performance.

SG6741A • Rev. 1.0.1 10

SG6741A — Highly Integrated Green-Mode PWM Controller

Reference Circuit

1

2

3

CN1

C2

21

+C4

2

1

3

4

BD1

2 1

D2

1

23

Q2

R7

GND

1

FB

2

NC

3

HV

4RI 5

SENSE 6

VDD 7

GATE 8

U1 SG6741A

R4

12

43

U2

C6R2

1

3

2

Q1

21

+C7

21 D3

R9

R11

R10

R8

C11

21

+C9

VZ1

C1

1 2

3 4

T1

4

2

3 7

8

6

5

T2

VO+

VO-

C3

1 2

3 4

L1

21

+C8

1 2

3 4

L2

2 1

D1

A K

R

U3

VO+

1 2

L4

R3

VO+

R1

C5

R6 C10

R5

C12

Figure 14. Circuit (12V/5A)

BOM

Reference Component Reference Component

BD1 BD 4A/600V Q2 MOS 7A/600V

C1 XC 0.68µF/300V R1 R 100KΩ 1/2W

C2 XC 0.1µF/300V R2 R 47Ω 1/4W

C3 YC 222pF/Y1 R3 R 100KΩ 1/2W

C4 EC 120µF/400V R4 R 20Ω 1/8W

C5 CC 0.01µF/500V R5 R 100Ω 1/8W

C6 CC 102pF/100V R6 R 33KΩ 1/8W

C7 EC 1000µF/25V R7 R 0.3Ω 2W

C8 EC 470µF/25V R8 R 680Ω m 1/8W

C9 EC 22µF/50V R9 R 4.7KΩ 1/8W

C10 CC 470pF/50V R10 R 150KΩ m 1/8W

C11 CC 222pF/50V R11 R 39KΩ 1/8W

C12 CC 103pF/50V T1 10mH

D1 Zener Diode 15V 1/2W (option) T2 600µH(PQ2620)

D2 BYV95C U1 IC SG6741A

D3 FR103 U2 IC PC817

F1 FUSE 4A/250V U3 IC TL431

L1 900µH VZ1 VZ 9G

Q1 STP20-100CT

SG6741A • Rev. 1.0.1 11

SG6741A — Highly Integrated Green-Mode PWM Controller

Physical Dimensions

8°

0°

SEE DETAIL A

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AA, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD: SOIC127P600X175-8M.

E) DRAWING FILENAME: M08AREV13

LAND PATTERN RECOMMENDATION

SEATING PLANE

0.10 C

C

GAGE PLANE

x 45°

DETAIL A

SCALE: 2:1

PIN ONE

INDICATOR

4

8

1

C

MBA0.25

B

5

A

5.60

0.65

1.75

1.27

6.20

5.80

3.81

4.00

3.80

5.00

4.80

(0.33)

1.27

0.51

0.33

0.25

0.10

1.75 MAX

0.25

0.19

0.36

0.50

0.25

R0.10

0.90

0.406 (1.04)

OPTION A - BEVEL EDGE

OPTION B - NO BEVEL EDGE

Figure 15. 8-Lead Small Outline Package (SOP)

Pack age drawings are provi ded as a servic e to customers considering Fairchild components. Drawings may change in any manner

without notice. P l ease note the revi sion and/or date on t he drawing and contac t a Fairchild S emic onductor representative to v er ify

or obtain the most recent revi sion. Pac kage specif i cations do not expand the terms of Fai rchild’s worldwi de terms and condition s,

specifically the warranty t herei n, which covers Fairc hi l d products.

Always vis i t Fairchild S emiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/.

SG6741A • Rev. 1.0.1 12

SG6741A — Highly Integrated Green-Mode PWM Controller