VESD05A8C-HNH Vishay Semiconductors 8-Line ESD-Protection Diode Array in LLP1713-9L FEATURES 1 * Ultra compact LLP1713-9L package 8 9 2 7 3 6 4 5 * Low package profile < 0.6 mm * 8-line ESD-protection * Low leakage current IR < 1 A * Low load capacitance CD = 10 pF 20522 20521 * ESD-immunity acc. IEC 61000-4-2 8 kV contact discharge 12 kV air discharge MARKING (example only) * Working voltage range VRWM = 5 V YXX * e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn) 20719 * Compliant to RoHS directive 2002/95/EC and in accordance to WEEE 2002/96/EC Dot = pin 1 marking Y = type code (see table below) XX = date code ORDERING INFORMATION DEVICE NAME VESD05A8C-HNH ORDERING CODE TAPED UNITS PER REEL (8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY VESD05A8C-HNH-GS08 3000 15 000 PACKAGE DATA DEVICE NAME PACKAGE NAME TYPE CODE WEIGHT MOLDING COMPOUND FLAMMABILITY RATING MOISTURE SENSITIVITY LEVEL SOLDERING CONDITIONS VESD05A8C-HNH LLP1713-9L F 3.7 mg UL 94 V-0 MSL level 1 (according J-STD-020) 260 C/10 s at terminals ABSOLUTE MAXIMUM RATINGS VESD05A8C-HNH PARAMETER TEST CONDITIONS SYMBOL VALUE UNIT Peak pulse current BiAs-mode: each input (pin 1 to pin 8) to ground (pin 9); acc. IEC 61000-4-5; tp = 8/20 s; single shot IPPM 2.5 A Peak pulse power BiAs-mode: each input (pin 1 to pin 8) to ground (pin 9); acc. IEC 61000-4-5; tp = 8/20 s; single shot PPP 33 W 8 kV 12 kV TJ - 40 to + 125 C TSTG - 55 to + 150 C ESD immunity Operating temperature Contact discharge acc. IEC 61000-4-2; 10 pulses; BiAs-mode: each input (pin 1 to pin 8) to ground (pin 9) Air discharge acc. IEC 61000-4-2; 10 pulses; BiAs-mode: each input (pin 1 to pin 8) to ground (pin 9) Junction temperature Storage temperature VESD ** Please see document "Vishay Material Category Policy": www.vishay.com/doc?99902 Document Number: 81705 Rev. 1.2, 15-Jul-10 For technical questions, contact: ESDprotection@vishay.com www.vishay.com 1 VESD05A8C-HNH Vishay Semiconductors 8-Line ESD-Protection Diode Array in LLP1713-9L BiAs-MODE (8-line bidirectional asymmetrical protection mode) With the VESD05A8C-HNH up to 8 signal- or data-lines (L1 to L8) can be protected against voltage transients. With pin 9 connected to ground and pin 1 up to pin 8 connected to a signal- or data-line which has to be protected. As long as the voltage level on the data- or signal-line is between 0 V (ground level) and the specified maximum reverse working voltage (VRWM) the protection diode between data line and ground offer a high isolation to the ground line. The protection device behaves like an open switch. As soon as any positive transient voltage signal exceeds the break through voltage level of the protection diode, the diode becomes conductive and shorts the transient current to ground. Now the protection device behaves like a closed switch. The clamping voltage (VC) is defined by the breakthrough voltage (VBR) level plus the voltage drop at the series impedance (resistance and inductance) of the protection device. Any negative transient signal will be clamped accordingly. The negative transient current is flowing in the forward direction of the protection diode. The low forward voltage (VF) clamps the negative transient close to the ground level. Due to the different clamping levels in forward and reverse direction the VESD05A8C-HNH clamping behaviour is bidirectional and asymmetrical (BiAs). L1 1 L8 8 9 L2 L3 L4 2 7 3 6 4 L7 L6 L5 5 20524 ELECTRICAL CHARACTERISTICS VESD05A8C-HNH PARAMETER Protection paths Reverse working voltage Reverse current Reverse breakdown voltage Reverse clamping voltage Forward clamping voltage Capacitance TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT Number of lines which can be protected at IR = 1 A at VR = VRWM = 5 V at IR = 1 mA at IPP = 2.5 A acc. IEC 61000-4-5 at IF = 2.5 A acc. IEC 61000-4-5 at VR = 0 V; f = 1 MHz at VR = 2.5 V; f = 1 MHz Nlines VRWM IR VBR VC VF CD CD 5 6 - 10 5 8 0.1 8 13 4.5 13 7 lines V A V V V pF pF Notes * Ratings at 25 C, ambient temperature unless otherwise specified. BiAs mode: each input (pin 1 to pin 8) to ground (pin 9) If a higher surge current or peak pulse current (IPP) is needed, some protection diodes in the VESD05A8C-HNH can also be used in parallel in order to "multiply" the performance. If two diodes are switched in parallel you get * double surge power = double peak pulse current (2 x IPPM) * half of the line inductance = reduced clamping voltage * half of the line resistance = reduced clamping voltage * double line capacitance (2 x CD) * double reverse leakage current (2 x IR) L1 1 8 L4 9 L2 2 7 3 6 4 5 L3 20525 www.vishay.com 2 For technical questions, contact: ESDprotection@vishay.com Document Number: 81705 Rev. 1.2, 15-Jul-10 VESD05A8C-HNH 8-Line ESD-Protection Diode Array in Vishay Semiconductors LLP1713-9L TYPICAL CHARACTERISTICS (Tamb = 25 C, unless otherwise specified) 100 Pin 9 to Pin 1, 2, 3, 4, 5, 6, 7 or 8 8 s to 100 % 100 % 10 IF (mA) 80 % IPPM 60 % 20 s to 50 % 1 0.1 40 % 0.01 20 % 0% 0 10 20 20548 30 0.001 0.5 40 Time (s) Fig. 1 - 8/20 s Peak Pulse Current Wave Form acc. IEC 61000-4-5 0.7 0.8 0.9 1 1.1 VF (V) Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF 8 120 % Pin 1, 2, 3, 4, 5, 6, 7 or 8 to Pin 9 Rise time = 0.7 ns to 1 ns 7 100 % 6 80 % 5 VR (V) Discharge Current IESD 0.6 20692 60 % 53 % 4 3 40 % 2 27 % 20 % 1 0% - 10 0 10 20 30 40 50 60 70 80 90 100 Fig. 2 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) 1 10 100 1000 10000 IR (A) Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR 14 12 f = 1 MHz 12 10 positive surge 10 BiAs-mode 8 8 Pin 1, 2, 3, 4, 5, 6, 7 or 8 to Pin 9 VC (V) CD (pF) 0.1 20693 Time (ns) 20557 0 0.01 6 6 Measured acc. IEC 61000-4-5 (8/20 s - wave form) 4 VC 2 4 Pin 1, 2, 3, 4, 5, 6, 7 or 8 to Pin 9 BiSy-mode between two Pins (1 - 8) Pin 9 not connetced 2 0 -2 0 negative surge -4 0 1 20691 2 3 4 5 Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR Document Number: 81705 Rev. 1.2, 15-Jul-10 0 6 VR (V) 1 20694 2 3 4 IPP (A) Fig. 6 - Typical Peak Clamping Voltage VC vs. Peak Pulse Current IPP For technical questions, contact: ESDprotection@vishay.com www.vishay.com 3 VESD05A8C-HNH Vishay Semiconductors 8-Line ESD-Protection Diode Array in LLP1713-9L PACKAGE DIMENSIONS in millimeters (inches): LLP1713-9L 1.05 (0.041) 0.3 (0.012) exp. DAP 0.35 (0.014) 0.45 (0.018) 0.2 (0.008) x 45 0.24 (0.009) 0.23 (0.009) 0.17 (0.007) 0.4 (0.016) bsc 1.2 (0.047) ref. 1.4 (0.055) 0.5 (0.020) 0.6 (0.024) 1.75 (0.069) 1.65 (0.065) 0.152 (0.006) ref. 0 (0.000) 0.05 (0.002) 1.3 (0.051) Pin 1 marking Foot print recommendation: 3 x 0.4 = 1.2 (0.047) 20386 www.vishay.com 4 For technical questions, contact: ESDprotection@vishay.com Solder resist mask 0.42 (0.017) 0.4 (0.016) Document no.:S8-V-3906.04-001 (4) Created - Date: 28. August 2006 Rev. 1 - Date: 27. May 2008 1 (0.039) 0.4 (0.016) 0.2 (0.008) 0.15 (0.006) 0.4 (0.016) Solder pad Document Number: 81705 Rev. 1.2, 15-Jul-10 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000