Document Number: 81705 For technical questions, contact: ESDprotection@vishay.com www.vishay.com
Rev. 1.2, 15-Jul-10 1
8-Line ESD-Protection Diode Array in LLP1713-9L
VESD05A8C-HNH
Vishay Semiconductors
MARKING (example only)
Dot = pin 1 marking
Y = type code (see table below)
XX = date code
FEATURES
Ultra compact LLP1713-9L package
Low package profile < 0.6 mm
8-line ESD-protection
Low leakage current IR < 1 μA
Low load capacitance CD = 10 pF
ESD-immunity acc. IEC 61000-4-2
± 8 kV contact discharge
± 12 kV air discharge
Working voltage range VRWM = 5 V
e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn)
Compliant to RoHS directive 2002/95/EC and in
accordance to WEEE 2002/96/EC
20522
1
2
3
4
8
7
6
5
20521
9
YXX
20719
ORDERING INFORMATION
DEVICE NAME ORDERING CODE TAPED UNITS PER REEL
(8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY
VESD05A8C-HNH VESD05A8C-HNH-GS08 3000 15 000
PACKAGE DATA
DEVICE NAME PACKAGE
NAME
TYPE
CODE WEIGHT MOLDING COMPOUND
FLAMMABILITY RATING
MOISTURE
SENSITIVITY LEVEL
SOLDERING
CONDITIONS
VESD05A8C-HNH LLP1713-9L F 3.7 mg UL 94 V-0 MSL level 1
(according J-STD-020) 260 °C/10 s at terminals
ABSOLUTE MAXIMUM RATINGS VESD05A8C-HNH
PARAMETER TEST CONDITIONS SYMBOL VALUE UNIT
Peak pulse current BiAs-mode: each input (pin 1 to pin 8) to ground (pin 9);
acc. IEC 61000-4-5; tp = 8/20 μs; single shot IPPM 2.5 A
Peak pulse power BiAs-mode: each input (pin 1 to pin 8) to ground (pin 9);
acc. IEC 61000-4-5; tp = 8/20 μs; single shot PPP 33 W
ESD immunity
Contact discharge acc. IEC 61000-4-2; 10 pulses;
BiAs-mode: each input (pin 1 to pin 8) to ground (pin 9) VESD
± 8 kV
Air discharge acc. IEC 61000-4-2; 10 pulses;
BiAs-mode: each input (pin 1 to pin 8) to ground (pin 9) ± 12 kV
Operating temperature Junction temperature TJ- 40 to + 125 °C
Storage temperature TSTG - 55 to + 150 °C
** Please see document “Vishay Material Category Policy”: www.vishay.com/doc?99902
www.vishay.com For technical questions, contact: ESDprotection@vishay.com Document Number: 81705
2Rev. 1.2, 15-Jul-10
VESD05A8C-HNH
Vishay Semiconductors 8-Line ESD-Protection Diode Array in
LLP1713-9L
BiAs-MODE (8-line bidirectional asymmetrical protection mode)
With the VESD05A8C-HNH up to 8 signal- or data-lines (L1 to L8) can be protected against voltage transients. With pin 9
connected to ground and pin 1 up to pin 8 connected to a signal- or data-line which has to be protected. As long as the voltage
level on the data- or signal-line is between 0 V (ground level) and the specified maximum reverse working voltage (VRWM) the
protection diode between data line and ground offer a high isolation to the ground line. The protection device behaves like an
open switch.
As soon as any positive transient voltage signal exceeds the break through voltage level of the protection diode, the diode
becomes conductive and shorts the transient current to ground. Now the protection device behaves like a closed switch. The
clamping voltage (VC) is defined by the breakthrough voltage (VBR) level plus the voltage drop at the series impedance
(resistance and inductance) of the protection device.
Any negative transient signal will be clamped accordingly. The negative transient current is flowing in the forward direction of
the protection diode. The low forward voltage (VF) clamps the negative transient close to the ground level.
Due to the different clamping levels in forward and reverse direction the VESD05A8C-HNH clamping behaviour is bidirectional
and asymmetrical (BiAs).
Notes
Ratings at 25 °C, ambient temperature unless otherwise specified. BiAs mode: each input (pin 1 to pin 8) to ground (pin 9)
If a higher surge current or peak pulse current (IPP) is needed, some protection diodes in the VESD05A8C-HNH can also be used
in parallel in order to “multiply” the performance.
If two diodes are switched in parallel you get
double surge power = double peak pulse current (2 x IPPM)
half of the line inductance = reduced clamping voltage
half of the line resistance = reduced clamping voltage
double line capacitance (2 x CD)
double reverse leakage current (2 x IR)
ELECTRICAL CHARACTERISTICS VESD05A8C-HNH
PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT
Protection paths Number of lines which can be protected Nlines --8lines
Reverse working voltage at IR = 1 μA VRWM 5--V
Reverse current at VR = VRWM = 5 V IR--0.1μA
Reverse breakdown voltage at IR = 1 mA VBR 6-8V
Reverse clamping voltage at IPP = 2.5 A acc. IEC 61000-4-5 VC--13V
Forward clamping voltage at IF = 2.5 A acc. IEC 61000-4-5 VF--4.5V
Capacitance at VR = 0 V; f = 1 MHz CD-1013pF
at VR = 2.5 V; f = 1 MHz CD-57pF
L1 L8
L3 L6
L2 L7
L4 L5
20524
1
2
3
4
8
7
6
5
9
L1 L4
L2 L3
20525
1
2
3
4
8
7
6
5
9
Document Number: 81705 For technical questions, contact: ESDprotection@vishay.com www.vishay.com
Rev. 1.2, 15-Jul-10 3
VESD05A8C-HNH
8-Line ESD-Protection Diode Array in
LLP1713-9L Vishay Semiconductors
TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
Fig. 1 - 8/20 μs Peak Pulse Current Wave Form
acc. IEC 61000-4-5
Fig. 2 - ESD Discharge Current Wave Form
acc. IEC 61000-4-2 (330 Ω/150 pF)
Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR
Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF
Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR
Fig. 6 - Typical Peak Clamping Voltage VC vs.
Peak Pulse Current IPP
0 %
20 %
40 %
60 %
80 %
100 %
010203040
Time (µs)
IPPM
20 µs to 50 %
8 µs to 100 %
20548
0 %
20 %
40 %
60 %
80 %
100 %
120 %
- 10 0 10 20 30 40 50 60 70 80 90 100
Time (ns)
Discharge Current IESD
Rise time = 0.7 ns to 1 ns
53 %
27 %
20557
0
2
4
6
8
10
12
012 456
VR (V)
CD (pF)
f = 1 MHz
BiAs-mode
BiSy-mode
Pin 1, 2, 3, 4, 5, 6, 7 or 8 to Pin 9
between two Pins (1 - 8)
Pin 9 not connetced
3
20691
0.001
0.01
0.1
1
10
100
0.5 0.6 0.7 0.8 0.9 1 1.1
Pin 9 to
Pin 1, 2, 3, 4, 5, 6, 7 or 8
VF (V)
I
F
(mA)
20692
0
1
2
3
4
5
6
7
8
0.01 0.1 1 10 100 1000 10000
Pin 1, 2, 3, 4, 5, 6, 7 or 8 to Pin 9
IR (µA)
VR (V)
20693
- 4
- 2
0
2
4
6
8
10
01234
VC
positive surge
negative surge
Measured
acc. IEC 61000-4-5
(8/20 µs - wave form)
IPP (A)
VC (V)
20694
14
12
Pin 1, 2, 3, 4, 5, 6, 7 or 8 to Pin 9
www.vishay.com For technical questions, contact: ESDprotection@vishay.com Document Number: 81705
4Rev. 1.2, 15-Jul-10
VESD05A8C-HNH
Vishay Semiconductors 8-Line ESD-Protection Diode Array in
LLP1713-9L
PACKAGE DIMENSIONS in millimeters (inches): LLP1713-9L
20386
Foot print recommendation:
Created - Date: 28. August 2006
Document no.:S8-V-3906.04-001 (4)
1.75 (0.069)
1.65 (0.065)
Pin 1 marking
0.05 (0.002)
0 (0.000)
0.152 (0.006) ref.
1.2 (0.047) ref.
0.3 (0.012)
0.24 (0.009)
0.4 (0.016) bsc 0.23 (0.009)
0.17 (0.007)
1.05 (0.041)
1.4 (0.055)
1.3 (0.051)
0.6 (0.024)
0.5 (0.020)
0.45 (0.018)
0.35 (0.014)
exp. DAP
0.2 (0.008) x 45°
Solder
resist mask
Solder pad
0.4 (0.016) 0.2 (0.008)
3 x 0.4 = 1.2 (0.047)
1 (0.039)
0.4 (0.016)
0.15 (0.006)
0.4 (0.016)
0.42 (0.017)
Rev. 1 - Date: 27. May 2008
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www.vishay.com Vishay
Revision: 02-Oct-12 1Document Number: 91000
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Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
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