LTC1066-1
1
10661fa
■
DC Gain Linearity: 14 Bits
■
Maximum DC Offset: ±1.5mV
■
DC Offset TempCo: 7µV/°C
■
Device Fully Tested at f
CUTOFF
= 80kHz
■
Maximum Cutoff Frequency: 120kHz (V
S
= ±8V)
■
Drives 1kΩ Load with 0.02% THD or Better
■
Signal-to-Noise Ratio: 90dB
■
Input Impedance: 500MΩ
■
Selectable Elliptic or Linear Phase Response
■
Operates from Single 5V up to ±8V Power Supplies
■
Available in an 18-Pin SO Wide Package
FREQUENCY (Hz)
100 10k 100k 1M
1066-1 TA02
1k
GAIN (dB)
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
f
C
= 800Hz
f
C
= 80kHz
7.5V
1066-1 TA01
–7.5V
–7.5V
7.5V
VOUT;
VOS(OUT) =
2.5mVMAX
VIN
40kHz ≤ fCLK ≤ 4MHz
1µF
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
15pF
OUT A
–IN A
+IN A
V–
V+
CONNECT 1
FILTEROUT
50/100
CLK
V+
OUT B
+IN B
GND
FILTERIN
COMP 2
CONNECT 2
COMP 1
V–
LTC1066-1
20k
30k
SHORT CONNECTION UNDER
IC AND SHIELDED BY A
GROUND PLANE
BYPASS THE POWER SUPPLIES
WITH 0.1µF DISC CERAMIC
■
Instrumentation
■
Data Acquisition Systems
■
Anti-Aliasing Filters
■
Smoothing Filters
■
Audio Signal Processing
APPLICATIO S
U
FEATURES
DESCRIPTIO
U
14-Bit DC Accurate
Clock-Tunable, 8th Order Elliptic
or Linear Phase Lowpass Filter
Amplitude Response
Clock-Tunable, DC Accurate, 800Hz to 80kHz Elliptic Lowpass Filter
The LTC
®
1066-1 is an 8th order elliptic lowpass filter
which simultaneously provides clock-tunability and DC
accuracy. The unique and proprietary architecture of the
filter allows 14 bits of DC gain linearity and a maximum of
1.5mV DC offset. An external RC is required for DC
accurate operation. With ±7.5V supplies, a 20k resistor
and a 1µF capacitor, the cutoff frequency can be tuned
from 800Hz to 100kHz. A clock-tunable 10Hz to 100kHz
operation can also be achieved (see Typical Application
section).
The filter does not require any external active components
such as input/output buffers. The input/output impedance
is 500MΩ/0.1Ω and the output of the filter can source or
sink 40mA. When pin 8 is connected to V
+
, the clock-to-
cutoff frequency ratio is 50:1 and the input signal is
sampled twice per clock cycle to lower the risk of aliasing.
For frequencies up to 0.75f
CUTOFF
, the passband ripple is
±0.15dB. The gain at f
CUTOFF
is –1dB and the filter’s
stopband attenuation is 80dB at 2.3f
CUTOFF
. Linear phase
operation is also available with a clock-to-cutoff frequency
ratio of 100:1 when pin 8 is connected to ground.
The LTC1066-1 is available in an 18-pin SO Wide package.
TYPICAL APPLICATIO
U
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
LTC1066-1
2
10661fa
PARAMETER CONDITIONS MIN TYP MAX UNITS
Passband Gain (0.01f
CUTOFF
to 0.25f
CUTOFF
)f
CLK
= 400kHz, f
TEST
= 2kHz ●– 0.18 0.16 0.36 dB
Passband Ripple (0.01f
CUTOFF
to 0.75f
CUTOFF
)f
CUTOFF
≤ 50kHz (See Note on Test Circuit) ±0.15 dB
for f
CLK
/f
CUTOFF
= 50:1
Gain at 0.50f
CUTOFF
for f
CLK
/f
CUTOFF
= 50:1 f
CLK
= 400kHz, f
TEST
= 4kHz – 0.09 0.02 0.09 dB
●– 0.14 0.05 0.14 dB
f
CLK
= 2MHz, f
TEST
= 20kHz – 0.16 – 0.05 0.02 dB
●– 0.22 – 0.10 0.02 dB
Gain at 0.75f
CUTOFF
for f
CLK
/f
CUTOFF
= 50:1 f
CLK
= 400kHz, f
TEST
= 6kHz – 0.18 – 0.05 0.05 dB
●– 0.22 – 0.10 0.05 dB
f
CLK
= 2MHz, f
TEST
= 30kHz – 0.36 – 0.20 0.05 dB
●– 0.45 – 0.30 0.05 dB
f
CLK
= 4MHz, f
TEST
= 60kHz – 0.65 – 0.30 0.25 dB
●– 0.85 – 0.40 0.75 dB
Gain at 1.00f
CUTOFF
for f
CLK
/f
CUTOFF
= 50:1 f
CLK
= 400kHz, f
TEST
= 8kHz – 1.50 – 1.10 – 0.05 dB
●– 1.80 – 1.20 – 0.05 dB
f
CLK
= 2MHz, f
TEST
= 40kHz – 2.10 – 1.60 – 1.20 dB
●– 2.30 – 1.60 – 1.20 dB
f
CLK
= 4MHz, f
TEST
= 80kHz – 2.20 – 1.60 – 0.05 dB
●– 2.50 – 1.60 0.25 dB
Gain at 2.00f
CUTOFF
for f
CLK
/f
CUTOFF
= 50:1 f
CLK
= 400kHz, f
TEST
= 16kHz – 56 –58 –64 dB
●–54 –57 –64 dB
f
CLK
= 2MHz, f
TEST
= 80kHz – 53 –56 –62 dB
●–51 –55 –62 dB
f
CLK
= 4MHz, f
TEST
= 160kHz – 50 –52 –60 dB
●–48 –51 –60 dB
TOP VIEW
SW PACKAGE
18-LEAD PLASTIC SO WIDE
T
JMAX
= 110°C, θ
JA
= 75°C/W
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
OUT A
–IN A
+IN A
V
–
V
+
CONNECT 1
FILTER
OUT
50/100
CLK
V
+
OUT B
+IN B
GND
FILTER
IN
COMP 2
CONNECT 2
COMP 1
V
–
ELECTRICAL CHARACTERISTICS
(See Test Circuit)
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at VS = ±7.5V,
RL = 1k, TA = 25°C, fCLK signal level is TTL or CMOS (maximum clock rise or fall time ≤ 1µs) unless otherwise specified. All AC gain
measurements are referenced to passband gain.
Total Supply Voltage (V
+
to V
–
) .......................... 16.5V
Power Dissipation............................................. 700mW
Burn-In Voltage ................................................... 16.5V
Voltage at Any Input ..... (V
–
– 0.3V) ≤ V
IN
≤ (V
+
+ 0.3V)
Maximum Clock Frequency
V
S
= ±8V ....................................................... 6.1MHz
V
S
= ±7.5V .................................................... 5.4MHz
V
S
= ±5V ....................................................... 4.1MHz
V
S
= Single 5V ............................................... 1.8MHz
Operating Temperature Range* .................. 0°C to 70°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ABSOLUTE AXI U RATI GS
W
WW
U
(Note 1)
ORDER PART
NUMBER
LTC1066-1CSW
WU
U
PACKAGE/ORDER I FOR ATIO
* For an extended operating temperature range contact LTC Marketing
for details.
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
LTC1066-1
3
10661fa
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
(See Test Circuit)
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at VS = ±7.5V,
RL = 1k, TA = 25°C, fCLK signal level is TTL or CMOS (maximum clock rise or fall time ≤ 1µs) unless otherwise specified. All AC gain
measurements are referenced to passband gain.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Gain at f
CUTOFF
for f
CLK
= 20kHz, V
S
= ±7.5V f
CLK
/f
CUTOFF
= 50:1, f
TEST
= 400Hz ●–1.75 –1.25 – 0.50 dB
Gain at f
CUTOFF
for V
S
= ±2.375V, f
CLK
/f
CUTOFF
= 50:1 f
CLK
= 1MHz, f
TEST
= 20kHz ●–1.75 –0.70 0.10 dB
Gain at 70kHz for V
S
= ±5V, f
CLK
/f
CUTOFF
= 50:1 f
CLK
= 4MHz, f
TEST
= 70kHz ●1.00 1.40 dB
Linear Phase Response Phase at 0.25f
CUTOFF
f
CLK
= 400kHz, f
TEST
= 1kHz –48.5 –50.0 –51.5 Deg
f
CLK
/f
CUTOFF
= 100:1, ●–48.0 –50.0 – 52.0 Deg
Pin 8 at GND Gain at 0.25f
CUTOFF
f
CLK
= 400kHz, f
TEST
= 1kHz ●–0.65 –0.25 0.25 dB
Phase at 0.50f
CUTOFF
f
CLK
= 400kHz, f
TEST
= 2kHz –97.5 –99.5 – 101.5 Deg
●– 97.0 – 99.5 – 102.0 Deg
Gain at 0.50f
CUTOFF
f
CLK
= 400kHz, f
TEST
= 2kHz ●–0.75 –0.50 – 0.10 dB
Phase at 0.75f
CUTOFF
f
CLK
= 400kHz, f
TEST
= 3kHz – 148.0 – 150.5 – 152.5 Deg
●– 147.5 – 150.5 – 153.0 Deg
Gain at 0.75f
CUTOFF
f
CLK
= 400kHz, f
TEST
= 3kHz ●–1.40 –1.00 – 0.60 dB
Phase at f
CUTOFF
f
CLK
= 400kHz, f
TEST
= 4kHz – 208.0 – 210.0 – 212.5 Deg
●– 207.5 – 210.0 – 213.0 Deg
Gain at f
CUTOFF
f
CLK
= 400kHz, f
TEST
= 4kHz ●–2.10 –1.80 – 1.60 dB
Input Bias Current V
S
= ±2.375V 60 nA
●70 135 nA
Input Offset Current V
S
= ±2.375V ●±10 ±40 nA
V
S
≥ ±5V (Note 3) ●±10 ±45 nA
Input Offset Current TempCo ±2.375V ≤ V
S
≤ ±7.5V 40 pA/°C
Output Voltage Offset TempCo ±2.375V ≤ V
S
≤ ±7.5V 7 µV/°C
Output Offset Voltage V
S
= ±2.375V, f
CLK
= 400kHz ±0.5 mV
●±1.0 ±1.5 mV
V
S
≥ ±5V ±0.5 mV
(Note 3) ●±1.0 ±1.5 mV
Common Mode Rejection V
S
= ±7.5V 90 96 dB
V
CM
= –5V to 5V ●84 90 dB
Power Supply Rejection V
S
= ±2.5V to ±7.5V 80 84 dB
●78 82 dB
Input Voltage Range and Output Voltage Swing V
S
= ±2.375V, R
L
= 1k ±1.2 ±1.4 V
●±1.1 V
V
S
= ±5V, R
L
= 1k ±3.4 ±3.6 V
●±3.2 V
V
S
= ±7.5V, R
L
= 1k ±5.4 ±5.8 V
●±5.0 V
Output Short-Circuit Current ±2.375V ≤ V
S
≤ ±7.5V ±20 mA
Power Supply Current (Note 2) V
S
= ±2.375V 14 16 mA
●16 19 mA
V
S
= ±5V 22 26 mA
●23 29 mA
V
S
= ±7.5V 25 30 mA
●26 33 mA
Power Supply Range ±2.375 ±8V
ELECTRICAL C CHARA TERISTICS
Note 2: The maximum current over temperature is at 0°C. At 70°C the
maximum current is less than its maximum value at 25°C.
Note 3: Guaranteed by design and test correlation.
LTC1066-1
4
10661fa
FREQUENCY (kHz)
1
–5
GAIN (dB)
–3
–1
1
3
10 100
1066-1 G08
–4
–2
0
2
4
AD
V
S
= ±5V, T
A
= 70°C
f
CLK
/f
C
= 50:1
R
F
= 20k, C
F
= 1µF
RC COMPENSATION
=15pF IN SERIES
WITH 30kΩ
5
B
A. f
CLK
= 1MHz
B. f
CLK
= 2MHz
C. f
CLK
= 3MHz
D. f
CLK
= 4MHz
C
FREQUENCY (kHz)
1
GAIN (dB)
10 50
1066-1 G07
3
2
1
0
–1
–2
–3
–4
–5
–6
V
S
= SINGLE 5V
T
A
= 70°C
f
CLK
/f
C
= 50:1
R
F
= 20k, C
F
= 1µF
RC COMPENSATION
= 15pF IN SERIES
WITH 30kΩ
A. f
CLK
= 1MHz (GND = 2.5V)
B. f
CLK
= 1.4MHz (GND = 2V)
C. f
CLK
= 1.8MHz (GND = 2V)
ABC
FREQUENCY (kHz)
4
GAIN (dB)
–1
0
20
10666-1 G06
–3
–5
612 16
PHASE (DEG)
2
3
2
1
–2
–4
–6
180
120
60
0
–60
–120
–180
–240
–300
–360
810141822
ELLIPTIC RESPONSE
fC = 20kHz, fCLK/fC = 100:1
PIN 8 AT V–, RF = 20k, CF = 1µF
(SEE BLOCK DIAGRAM)
PHASE
GAIN
VS = ±7.5V
TA = 25°C
FREQUENCY (kHz)
4
GAIN (dB)
–1
0
20
10666-1 G05
–3
–5
612 16
PHASE (DEG)
2
3
2
1
–2
–4
–6
180
120
60
0
–60
–120
–180
–240
–300
–360
810141822
LINEAR PHASE RESPONSE
f
C
= 20kHz, f
CLK
/f
C
= 100:1
PIN 8 AT GND, R
F
= 20k, C
F
= 1µF
(SEE BLOCK DIAGRAM)
PHASE
GAIN
V
S
= ±7.5V
T
A
= 25°C
FREQUENCY (kHz)
4
GAIN (dB)
–1
0
20
10666-1 G04
–3
–5
612 16
PHASE (DEG)
2
3
2
1
–2
–4
–6
180
120
60
0
–60
–120
–180
–240
–300
–360
810141822
ELLIPTIC RESPONSE
f
C
= 20kHz, f
CLK
= 1MHz
f
CLK
/f
C
= 50:1, PIN 8 AT V
+
R
F
= 20k, C
F
= 1µF
(SEE BLOCK DIAGRAM)
PHASE
GAIN
V
S
= ±7.5V
T
A
= 25°C
FREQUENCY (Hz)
1k
–50
GAIN (dB)
–40
–30
–20
–10
10k 100k 1M
1066-1 G03
–60
–70
–90
0
–80
10
–100
–110
f
CLK
= 1MHz f
CLK
= 5MHz
V
S
= ±7.5V
T
A
= 25°C
f
CLK
/f
C
= 100:1
PIN 8 TO V
–
FREQUENCY (Hz)
1k
–50
GAIN (dB)
–40
–30
–20
–10
10k 100k 1M
1066-1 G02
–60
–70
–90
0
–80
10
–100
–110
f
CLK
= 1MHz f
CLK
= 5MHz
V
S
= ±7.5V
T
A
= 25°C
f
CLK
/f
C
= 100:1
NO COMPENSATION
PIN 8 TO AGND
1066-1 G01
FREQUENCY (Hz)
1k
–50
GAIN (dB)
–40
–30
–20
–10
10k 100k 1M
–60
–70
–90
0
–80
10
–100
–110
fCLK= 500kHz
fCLK= 5MHz
VS = ±7.5V
TA = 25°C
fCLK/fC = 50:1
COMPENSATION
= 30k, 15pF fCLK= 2.5MHz
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
Gain vs Frequency
VS = ±7.5V, fCLK/fC = 50:1
Gain vs Frequency
VS = ±7.5V, fCLK/fC = 100:1
Gain vs Frequency
VS = ±7.5V, fCLK/fC = 100:1
Passband Gain and Phase
vs Frequency
Passband Gain and Phase
vs Frequency
Passband Gain and Phase
vs Frequency
Passband Gain vs Frequency
and fCLK
Passband Gain vs Frequency
and fCLK
LTC1066-1
5
10661fa
FREQUENCY (kHz)
1
–90
–80
–70
–60
–50
10
1066-1 G17
–85
–75
–65
–55
–45 V
S
= SINGLE 5V
V
IN
= 0.5V
RMS
T
A
= 25°C
f
CLK
= 1MHz
f
CLK
/f
C
= 50:1
(5 REPRESENTATIVE
UNITS)
–40
20
V
IN
THD + NOISE
()
(dB)20 log
FREQUENCY (kHz)
1
–90
–80
–70
–60
–50
10
1066-1 G16
–85
–75
–65
–55
–45 V
S
= ±5V
V
IN
= 1V
RMS
T
A
= 25°C
f
CLK
= 1MHz
f
CLK
/f
C
= 50:1
(5 REPRESENTATIVE
UNITS)
–40
20
V
IN
THD + NOISE
()
(dB)20 log
FREQUENCY (kHz)
11050
1066-1 G15
–90
–80
–50
–70
–65
–55
–40
–45
–60
–75
–85
V
S
= ±7.5V
V
IN
= 1V
RMS
T
A
= 25°C
f
CLK
= 2.5MHz
f
CLK
/f
C
= 50:1
A. R
L
= ∞, C
L
= 100pF
B. R
L
= 1k, C
L
= 100pF
C. R
L
= 200Ω, C
L
= 100pF
A
B
C
V
IN
THD + NOISE
()
(dB)20 log
FREQUENCY (kHz)
11050
1066-1 G14
–90
–80
–50
–70
–65
–55
–40
–45
–60
–75
–85
V
S
= ±7.5V
V
IN
= 1V
RMS
T
A
= 25°C
f
CLK
= 2.5MHz
f
CLK
/f
C
= 50:1
(5 REPRESENTATIVE
UNITS)
V
IN
THD + NOISE
()
(dB)20 log
INPUT VOLTAGE (V
RMS
)
0.1
–90
–80
–70
–60
–50
1
1066-1 G13
–85
–75
–65
–55
–45 f
IN
= 1kHz
V
S
= SINGLE 5V
f
CLK
= 1MHz
f
CLK
/f
C
= 50:1
T
A
= 25°C
–40
2
V
IN
THD + NOISE
()
(dB)20 log
GND PIN 15 AT 2V
GND PIN 15 AT 2.5V
INPUT VOLTAGE (V
RMS
)
0.1 1 5
1066-1 G12
–90
–80
–50
–70
–65
–55
–40
–45
–60
–75
–85
T
A
= 25°C
f
IN
= 1kHz
f
CLK
= 1MHz
f
CLK
/f
C
= 50:1
V
IN
THD + NOISE
()
(dB)20 log
V
S
= ±5V
V
S
= ±7.5V
FREQUENCY (f
CUTOFF
/FREQUENCY)
0.2
PHASE DIFFERENCE (±DEG)
1.25
1.00
0.75
0.50
0.25
00.8
A
B
1066-1 G11
0.4 0.6 1.0
PHASE DIFFERENCE BETWEEN
ANY TWO UNITS (SAMPLE OF
50 REPRESENTATIVE UNITS)
V
S
≥ ±5V, T
A
= 25°C
f
CLK
≤ 2.5MHz
A. ELLIPTIC RESPONSE
f
CLK
/f
C
= 50:1 (PIN 8 to V
+
)
B. LINEAR PHASE RESPONSE
f
CLK
/f
C
= 100:1 (PIN8 TO GND)
FREQUENCY (kHz)
2
20
GROUP DELAY (µs)
30
40
50
60
70
80
6101418
1066-1 G10
22
VS = ±5V
TA = 25°C
fC = 20kHz
41281620
A
B
C
A. fCLK/fC = 50:1 (PIN 8 TO V+)
B. fCLK/fC = 100:1 (PIN 8 TO V–)
C. LINEAR PHASE REPONSE
fCLK/fC = 100:1 (PIN 8 TO GND)
FREQUENCY (kHz)
1
–5
GAIN (dB)
–3
–1
1
3
10 100
1066-1 G08
–4
–2
0
2
4
AD
V
S
= ±5V, T
A
= 70°C
f
CLK
/f
C
= 50:1
R
F
= 20k, C
F
= 1µF
RC COMPENSATION
=15pF IN SERIES
WITH 30kΩ
5
B
A. f
CLK
= 1MHz
B. f
CLK
= 2MHz
C. f
CLK
= 3MHz
D. f
CLK
= 4MHz
C
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
Passband Gain vs Frequency Group Delay vs Frequency Phase Matching vs Frequency
THD + Noise vs Input Voltage THD + Noise vs Input Voltage THD + Noise vs Frequency
THD + Noise vs Frequency THD + Noise vs Frequency THD + Noise vs Frequency
LTC1066-1
6
10661fa
TOTAL POWER SUPPLY VOLTAGE (V)
02 6 10 14 18
POWER SUPPLY CURRENT (mA)
30
27
24
21
18
15
12
9
6
3
0
16
1066-1 G18
4812 20
0°C
25°C
70°C
CCHARA TERISTICS
UW
ATYPICALPER
FORCE
Power Supply Current vs
Power Supply Voltage
100µs/DIV
LINEAR PHASE (PIN 8 TO GND)
f
IN
= 1kHz, f
CUTOFF
= 10kHz
1066-1 G20
Transient Response
1V/DIV
1V/DIV
100µs/DIV
ELLIPTIC RESPONSE (PIN 8 TO V
+
)
f
IN
= 1kHz, f
CUTOFF
= 10kHz
1066-1 G19
Transient Response
Table 1. Elliptic Response, fC = 10kHz, fCLK/fCUTOFF = 50:1,
VS = ±7.5V, RF = 20k, CF = 1µF, No RC Compensation,
TA = 25°C
FREQUENCY GAIN PHASE GROUP DELAY
(kHz) (dB) (DEG) (µs)
2.000 0.117 –50.09 70.52
3.000 0.118 –75.75 72.04
4.000 0.116 –101.96 74.32
5.000 0.112 –129.25 77.59
6.000 0.104 –157.82 82.04
7.000 0.074 171.68 88.56
8.000 –0.014 138.41 97.80
9.000 –0.278 101.26 110.33
10.000 – 0.986 58.98 124.91
Table 2. Elliptic Response, fC = 50kHz, fCLK/fCUTOFF = 50:1,
VS = ±7.5V, RF = 20k, CF = 1µF, No RC Compensation,
TA = 25°C
FREQUENCY GAIN PHASE GROUP DELAY
(kHz) (dB) (DEG) (µs)
10.000 0.104 – 50.91 14.32
15.000 0.105 – 76.95 14.61
20.000 0.107 – 103.51 15.05
25.000 0.109 – 131.13 15.70
30.000 0.107 – 160.03 16.57
35.000 0.089 169.22 17.85
40.000 0.014 135.72 19.66
45.000 – 0.231 98.44 22.10
50.000 – 0.905 56.15 24.93
Table 3. Linear Phase Response, fC = 10kHz,
fCLK/fCUTOFF = 100:1, VS = ±7.5V, RF = 20k, CF = 1µF,
No RC Compensation, TA = 25°C
FREQUENCY GAIN PHASE GROUP DELAY
(kHz) (dB) (DEG) (µs)
2.000 –0.020 – 39.96 55.25
3.000 –0.181 – 59.76 55.03
4.000 –0.383 – 79.60 54.98
5.000 –0.601 – 99.34 55.28
6.000 –0.811 –119.40 56.34
7.000 –1.004 –139.91 58.56
8.000 –1.196 –161.56 62.34
9.000 –1.451 175.21 67.29
10.000 – 1.910 149.99 72.31
Table 4. Linear Phase Response, fC = 50kHz,
fCLK/fCUTOFF = 100:1, VS = ±7.5V, RF = 20k, CF = 1µF,
No RC Compensation, TA = 25°C
FREQUENCY GAIN PHASE GROUP DELAY
(kHz) (dB) (DEG) (µs)
10.000 0.039 – 40.72 11.30
15.000 – 0.068 – 61.01 11.31
20.000 – 0.202 – 81.42 11.36
25.000 – 0.345 –101.88 11.48
30.000 – 0.479 –122.74 11.73
35.000 – 0.594 –144.09 12.20
40.000 – 0.701 – 166.68 12.99
45.000 – 0.860 169.15 14.06
50.000 – 1.214 142.72 15.19
LTC1066-1
7
10661fa
level threshold values for a dual or single supply operation.
Sine waves are not recommended for clock input frequen-
cies less than 100kHz, since excessively slow clock rise or
fall times generate internal clock jitter (maximum clock
rise or fall time ≤ 1µs). The clock signal should be routed
from the left side of the IC package and perpendicular to it
to avoid coupling to any input or output analog signal path.
A 200Ω resistor between clock source and pin 9 will slow
down the rise and fall times of the clock to further reduce
charge coupling.
Table 5. Clock Source High and Low Threshold Levels
POWER SUPPLY HIGH LEVEL LOW LEVEL
Dual Supply = ±7.5V ≥ 2.18V ≤ 0.5V
Dual Supply = ±5V ≥ 1.45V ≤ 0.5V
Dual Supply = ±2.5V ≥ 0.73V ≤ –2.0V
Single Supply = 12V ≥ 7.80V ≤ 6.5V
Single Supply = 5V ≥ 1.45V ≤ 0.5V
50:1/100:1 Pin (8)
The DC level at pin 8 determines the ratio of the clock to
the filter cutoff frequency. When pin 8 is connected to
V
+
the clock-to-cutoff frequency ratio (f
CLK
/f
CUTOFF
) is
50:1 and the filter response is elliptic. The design of the
internal switched-capacitor filter was optimized for a 50:1
operation.
When pin 8 is connected to ground (or 1/2 supply for
single supply operation), the f
CLK
/f
CUTOFF
ratio is equal to
100:1 and the filter response is pseudolinear phase (see
Group Delay vs Frequency in Typical Performance Charac-
teristic section).
When pin 8 is connected to V
–
(or ground for single supply
operation), the f
CLK
/f
CUTOFF
ratio is 100:1 and the filter
response is transitional Butterworth elliptic. The Typical
Performance Characteristics provide all the necessary
information.
If the DC level at pin 8 is mechanically switched, a 10k
resistor should be connected between pin 8 and the DC
source.
Input Pins (2, 3, 14, 16)
Pin 3 (+IN A) and pin 2 (–IN A) are the positive and
negative inputs of an internal high performance op amp A
PIN FUNCTIONS
UUU
Power Supply Pins (5, 18, 4, 10)
The power supply pins should be bypassed with a 0.1µF
capacitor to an adequate analog ground. The bypass
capacitors should be connected as close as possible to the
power supply pins. The V
+
pins (5, 18) and the V
–
pins (4,
10) should always be tied to the same positive supply and
negative supply value respectively. Low noise linear sup-
plies are recommended. Switching power supplies are not
recommended as they will lower the filter dynamic range.
When the LTC1066-1 is powered up with dual supplies
and, if V
+
is applied prior to a floating V
–
, connect a signal
diode (1N4148) between pin 10 and ground to prevent
power supply reversal and latch-up. A signal diode
(1N4148) is also recommended between pin 5 and ground
if the negative supply is applied prior to the positive supply
and the positive supply is floating. Note, in most labora-
tory supplies, reversed biased diodes are always con-
nected between the supply output terminals and ground,
and the above precautions are not necessary. However,
when the filter is powered up with conventional 3-terminal
regulators, the diodes are recommended.
Analog Ground Pin (15)
The filter performance depends on the quality of the
analog signal ground. For either dual or single supply
operation, an analog ground plane surrounding the pack-
age is recommended. The analog ground plane should be
connected to any digital ground at a single point. For dual
supply operation, pin 15 should be connected to the
analog ground plane. For single supply operation pin 15
should be biased at 1/2 supply and should be bypassed to
the analog ground plane with at least a 1µF capacitor (see
Typical Applications). For single 5V operation and for
f
CLK
≥ 1.4MHz, pin 15 should be biased at 2V. This
minimizes passband gain and phase variations.
Clock Input Pin (9)
Any TTL or CMOS clock source with a square-wave output
and 50% duty cycle (±10%) is an adequate clock source
for the device. The power supply for the clock source
should not be the filter’s power supply. The analog ground
for the filter should be connected to clock’s ground at a
single point only. Table 5 shows the clock’s low and high
LTC1066-1
8
10661fa
15pF capacitor should be connected between pins 11 and
13. Compensation is recommended for the following
cases shown in Table 6.
Table 6. Cases Where an RC Compensation (15pF in Series with
30kΩ pins 11, 13) is Recommended, fCLK/fCUTOFF = 50:1
V
S
= Single 5V (AGND = 2V) T
A
= 25°Cf
CUTOFF
≥ 28kHz
T
A
= 70°Cf
CUTOFF
≥ 24kHz
V
S
= ±5V T
A
= 25°Cf
CUTOFF
≥ 60kHz
T
A
= 70°Cf
CUTOFF
≥ 50kHz
V
S
= ±7.5V T
A
= 25°Cf
CUTOFF
≥ 70kHz
T
A
= 70°Cf
CUTOFF
≥ 60kHz
Connect Pins (6, 12)
Pin 6 (CONNECT 1) and pin 12 (CONNECT 2) should be
shorted. In a printed circuit board the connection should
be done under the IC package through a short trace
surrounded by the analog ground plane. Pin 6 should be
0.2 inches away from any other circuit trace.
PIN FUNCTIONS
UUU
(see Block Diagram). Input bias current flows out of pins
2 and 3. Pin 16 (+IN B) is the positive input of a high
performance op amp B which is internally connected as
a unity-gain follower. Op amp B buffers the switched-
capacitor network output. The input capacitance of both
op amps is 10pF.
Pin 14 (FILTER
IN
) is the input of a switched-capacitor
network. The input impedance of pin 14 is typically 11k.
Output Pins (1, 7, 17)
Pins 1 and 17 are the outputs of the internal high perfor-
mance op amps A and B. Pin 1 is usually connected to the
internal switched-capacitor filter network input pin 14.
Pin 17 is the buffered output of the filter and it can drive
loads as heavy as 200Ω (see THD + Noise curves under
Typical Performance Characteristics). Pin 7 is the internal
switched-capacitor network output and it can typically
sink or source 1mA.
Compensation Pins (11, 13)
Pins 11 and 13 are the AC compensation pins. If compen-
sation is needed, an external 30k resistor in series with a
LTC1066-1
9
10661fa
FILTERIN
CONNECT 1
COMP1
COMP2
CONNECT 2
FILTEROUT
8TH ORDER
SWITCHED-
CAPACITOR
NETWORK
5,18 4,10 15 8 9 6 7 16
17
12
13
11
141
3
2
–IN A
+IN A
V+V–GND 50/100 CLK
+IN B
PATENT PENDING
LTC1066-1
OUT B
OUT A
CF
RF
11066-1 BD
–
+
HIGH SPEED
OP AMP
–
+
HIGH SPEED
OP AMP
BLOCK DIAGRA
W
TEST CIRCUIT
1066-1 TC01
NOTE: RC COMPENSATION BETWEEN PINS 11 AND 13 IS
REQUIRED ONLY FOR CLOCK-TUNABLE OPERATION FOR:
50kHz < f
CUTOFFs
≤ 100kHz.
THE TEST SPECIFICATIONS FOR:
f
CLK
= 2MHz, f
CUTOFF
= 40kHz, AND
f
CLK
= 4MHz, f
CUTOFF
= 80kHz
INCLUDE THE EFFECTS OF RC COMPENSATION.
COMPENSATION DOES NOT INFLUECE THE SPECIFICATIONS
FOR:
f
CLK
= 400kHz, f
CUTOFF
= 8kHz.
FOR CLOCK-TUNABLE f
CUTOFFs
FROM 2kHz TO 50kHz
COMPENSATION IS NOT REQUIRED AND THE FILTER’S
PASSBAND PERFORMANCE IS REPRESENTED BY THE
TYPICAL SPECIFICATIONS AT:
f
CLK
= 400kHz, f
CUTOFF
= 8kHz.
V
+
V
+
V
–
V
–
V
+
V
OUT
V
IN
f
CLK
(DUTY CYCLE
= 50% ±10%
)
ELLIPTIC
RESPONSE
50:1
LINEAR PHASE
RESPONSE
100:1
1µF
0.1µF
15pF
0.1µF
0.1µF
10k
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
20k
20Ω
30k
LTC1066-1
0.1µF
20Ω
OUT A
–IN A
+IN A
V
–
V
+
CONNECT 1
FILTER
OUT
50/100
CLK
V
+
OUT B
+IN B
GND
FILTER
IN
COMP 2
CONNECT 2
COMP 1
V
–
LTC1066-1
10
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APPLICATIONS INFORMATION
WUUU
DC PERFORMANCE
The DC performance of the LTC1066-1 is dictated by the
DC characteristics of the input precision op amp.
1. DC input voltages in the vicinity of the filter’s half of the
total power supply are processed with exactly 0dB (or
1V/V) of gain.
2. The typical DC input voltage ranges are equal to:
V
IN
= ±5.8V, V
S
= ±7.5V
V
IN
= ±3.6V, V
S
= ±5V
V
IN
= ±1.4V, V
S
= ±2.5V
With an input DC voltage range of V
IN
= ±5V, (V
S
=
±7.5V), the measured CMRR was 100dB. Figure 1
shows the DC gain linearity of the filter exceeding the
requirements of a 14-bit, 10V full scale system.
3. The filter output DC offset V
OS(OUT)
is measured with the
input grounded and with dual power supplies. The
V
OS(OUT)
is typically ±0.1mV and it is optimized for the
filter connection shown in the test circuit figure. The
filter output offset is equal to:
V
OS(OUT)
= V
OS
(op amp A) –I
BIAS
× R
F
= 0.1mV (Typ)
4. The V
OS(OUT)
temperature drift is typically 7µV/°C
(T
A
> 25°C), and –7µV/°C (T
A
< 25°C).
5. The V
OS(OUT)
temperature drift can be improved by
using an input resistor R
IN
equal to the feedback resis-
tor R
F
, however, the absolute value of V
OS(OUT)
will
increase. For instance, if a 20k resistor is added in series
with pin 3 (see Test Circuit), the output V
OS
drift will be
improved by 2µV/°C to 3µV/°C, however, the V
OS(OUT)
may increase by 1mV
(MAX)
.
6. The filter DC output offset voltage V
OS(OUT)
is indepen-
dent from the filter clock frequency (f
CLK
≤ 250kHz).
Figures 2 and 3 show the V
OS(OUT)
variation for three
different power supplies and for clock frequencies up to
5MHz. Both figures were traced with the LTC1066-1
soldered into the PC board. Power supply decoupling is
very important, especially with ±7.5V supplies. If nec-
essary connect a small resistor (20Ω) between pins 5
and 18, and between pins 10 and 4, to isolate the
precision op amp supply pin from the switched
capacitor network supply (see the Test Circuit).
INPUT VOLTAGE (VDC)
–6 –5 –3 –1 1 3 5
V
IN
– V
OUT
(µV)
75
50
25
0
–25
–50
–75
–100
–125 2
1066-1 F01
–4 –2 046
V
S
= ±7.5V
T
A
= 25°C
f
CLK
= 1MHz
f
C
= 20kHz
Figure 1. DC Gain Linearity
CLOCK FREQUENCY (MHz)
0 0.5 1.5 2.5 3.5 4.5
FILTER OUTPUT OFFSET VOLTAGE CHANGE (mV)
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
4.0
1066-1 F03
1.0 2.0 3.0 5.0
V
S
= ±2.5V
V
S
= ±5V
V
S
= ±7.5V
T
A
= 25°C
f
CLK
/f
C
= 50:1
CLOCK FREQUENCY (MHz)
0 0.5 1.5 2.5 3.5 4.5
FILTER OUTPUT OFFSET VOLTAGE CHANGE (mV)
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
4.0
1066-1 F02
1.0 2.0 3.0 5.0
V
S
= ±2.5V
V
S
= ±5V
V
S
= ±7.5V
LINEAR PHASE
T
A
= 25°C
f
CLK
/f
C
= 100:1
Figure 2. Output Offset Change vs Clock
(Relative to Offset for fCLK = 250kHz)
Figure 3. Output Offset Change vs Clock
(Relative to Offset for fCLK = 250kHz)
LTC1066-1
11
10661fa
APPLICATIONS INFORMATION
WUUU
AC PERFORMANCE
AC (Passband) Gain
The passband gain of the LTC1066-1 is equal to the
passband gain of the internal switched-capacitor lowpass
filter, and it is measured at f = 0.25f
CUTOFF
. Unlike conven-
tional monolithic filters, the LTC1066-1 starts with an
absolutely perfect 0dB DC gain and phases into an “imper-
fect” AC passband gain, typically ±0.1dB.
The filter’s low passband ripple, typically 0.05dB, is mea-
sured with respect to the AC passband gain.
The LTC1066-1 DC stabilizing loop slightly warps the
filter’s passband performance if the – 3dB frequency of the
feedback passive elements (1/2πR
F
C
F
) is more than the
Figure 4. Passband Behavior
FREQUENCY (Hz)
10
GAIN (dB)
100 1k 10k 20k
1066-1 F04
1.00
0.75
0.50
0.25
0
–0.25
–0.50
–0.75
–1.00
T
A
= 25°C
f
CLK
/f
C
= 50:1
R
F
= 20k,
C
F
= 1µF
CURVE D: f
CUTOFF
= 20kHz = 2500 ×2πR
F
C
F
1
CURVE C: f
CUTOFF
= 5kHz = 625 ×
2πR
F
C
F
1
CURVE B: f
CUTOFF
= 2kHz = 250 ×2πR
F
C
F
1
CURVE A: f
CUTOFF
= 1kHz = 125 ×
2πR
F
C
F
1
A B CD
cutoff frequency of the internal switched-capacitor filter
divided by 250. The LTC1066-1 clock tunability directly
relates to the above constraint. Figure 4 illustrates the
passband behavior of the LTC1066-1 and it demonstrates
the clock tunability of the device. A typical LTC1066-1
device was used to trace all four curves of Figure 4. Curve
D, for instance, has nearly zero ripple and 0.04dB passband
gain. Curve D’s 20kHz cutoff is much higher than the 8Hz
cutoff frequency of the R
F
C
F
feedback network, so its
passband is free from any additional error due to R
F
C
F
feedback elements. Curve B illustrates the passband error
when the 1MHz clock of curve D is lowered to 100kHz. A
0.1dB error is added to the filter’s original AC gain of
0.04dB.
LTC1066-1
12
10661fa
INPUT
90%
50%
10%
OUTPUT
tr
td
ts
1066-1 F05
RISE TIME (t
r
)
SETTLING TIME (t
s
)
DELAY TIME (t
d
)
50:1 ELLIPTIC
0.43
f
CUTOFF
3.4
f
CUTOFF
0.709
f
CUTOFF
±5%
±5%
±5%
0.43
f
CUTOFF
2.05
f
CUTOFF
0.556
f
CUTOFF
±5%
±5%
±5%
100:1 LINEAR PHASE
APPLICATIONS INFORMATION
WUUU
Transient Response and Settling Time
The LTC1066-1 exhibits two different transient behaviors.
First, during power-up the DC correcting loop will settle
after the voltage offset of the internal switched-capacitor
network is stored across the feedback capacitor C
F
(see
Block Diagram). It takes approximately five time constants
(5R
F
C
F
) for settling to 1%. Second, following DC loop
settling, the filter reaches steady state. The filter transient
response is then defined by the frequency characteristics
of the internal switched-capacitor lowpass filter. Figure 5
shows details.
DC loop settling is also observed if, at steady state, the DC
offset of the internal switched-capacitor network suddenly
changes. A sudden change may occur if the clock fre-
quency is instantaneously stepped to a value above 1MHz.
and on the value of the power supplies. With proper layout
techniques the values of the clock feedthrough are shown
on Table 7.
Table 7. Clock Feedthrough
POWER SUPPLY 50:1 100:1
Single 5V 70µV
RMS
90µV
RMS
±5V 100µV
RMS
200µV
RMS
±7.5V 160µV
RMS
650µV
RMS
Wideband Noise
The wideband noise of the filter is the total RMS value of
the device’s noise spectral density and is used to deter-
mine the operating signal-to-noise ratio. Most of its fre-
quency contents lie within the filter passband and cannot
be reduced with post filtering. For instance, the LTC1066-
1 wideband noise at ±5V supply is 100µV
RMS
, 95µV
RMS
of
which have frequency contents from DC up to the filter’s
cutoff frequency. The total wideband noise (µV
RMS
) is
nearly independent of the value of the clock. The clock
feedthrough specifications are not part of the wideband
noise. Table 8 lists the typical wideband noise for each
supply.
Table 8. Wideband Noise
POWER SUPPLY 50:1 100:1 (Pin 8 to GND)
Single 5V 90µV
RMS
80µV
RMS
±5V 100µV
RMS
85µV
RMS
±7.5V 106µV
RMS
90µV
RMS
Speed Limitations
To avoid op amp slew rate limiting at maximum clock
frequencies, the signal amplitude should be kept below a
specified level as shown in Table 9.
Table 9. Maximum VIN
INPUT FREQUENCY MAXIMUM V
IN
≥250kHz 0.50V
RMS
≥700kHz 0.25V
RMS
Clock Feedthrough
Clock feedthrough is defined as the RMS value of the clock
frequency and its harmonics that are present at the filter’s
output pin (9). The clock feedthrough is tested with the
input pin (2) grounded and depends on PC board layout
Figure 5. Transient Response
LTC1066-1
13
10661fa
ALIASED OUTPUT (dB)
0
–26
–85
INPUT FREQUENCY
1066-1 F07
f
CLK
– f
C
2f
CLK
– f
C
2f
CLK
– 4f
C
f
CLK
– 4f
C
f
CLK
+ 4f
C
2f
CLK
+ 4f
C
f
CLK
+ f
C
2f
CLK
+ f
C
f
CLK
2f
CLK
ALIASED OUTPUT (dB)
0
–60
–80
INPUT FREQUENCY 1066-1 F06
fCLK – fC
2fCLK – fC
2fCLK – 2.3fC2fCLK + 2.3fC
fCLK + fC
2fCLK + fC
fCLK
2fCLK
APPLICATIONS INFORMATION
WUUU
Aliasing
In a sampled-data system the sampling theorem says that
if an input signal has any frequency components greater
than one half the sampling frequency, aliasing errors will
appear at the output. In practice, aliasing is not always a
serious problem. High order switched-capacitor lowpass
filters are inherently band limited and significant aliasing
occurs only for input signals centered around the clock
frequency and its multiples.
Figure 6 shows the LTC1066-1 aliasing response when
operated with a clock-to-cutoff frequency ratio of 50:1.
With a 50:1 ratio LTC1066-1 samples its input twice
during one clock period and the sampling frequency is
equal to two times the clock frequency.
The figure also shows the maximum aliased output gener-
ated for inputs in the range of 2f
CLK
±f
C
. For instance, if the
LTC1066-1 is programmed to produce a cutoff frequency
of 20kHz with 1MHz clock, a 10mV, 1.02MHz input signal
will cause a 10µV aliased signal at 20kHz. This signal will
be buried in the noise. Maximum aliasing will occur only
for input signals in the narrow range of 2MHz ±20kHz or
multiples of 2MHz.
Figure 7 shows the LTC1066-1 aliased response when
operated with a clock-to-cutoff frequency ratio of 100:1
(linear phase response with pin 8 to ground).
Figure 6. Aliasing vs Frequency
fCLK/fC = 50:1 (Pin 8 to V +)
Clock is a 50% Duty Cycle Square Wave
Figure 7. Aliasing vs Frequency
fCLK/f
C = 100:1 (Pin 8 to Ground)
Clock is a 50% Duty Cycle Square Wave
LTC1066-1
14
10661fa
7.5V
1066-1 TA03
–7.5V
–7.5V
7.5V
7.5V
V
OUT
V
IN
f
CLK
33µF
0.1µF1N4148*
1N4148*
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
0.1µF
15pF
OUT A
–IN A
+IN A
V
–
V
+
CONNECT 1
FILTER
OUT
50/100
CLK
V
+
OUT B
+IN B
GND
FILTER
IN
COMP 2
CONNECT 2
COMP 1
V
–
0.1µF
0.1µF
0.1µF
LTC1066-1
100k
200Ω
30k
20Ω
20Ω
100k
MAXIMUM OUTPUT VOLTAGE OFFSET = ±5.5mV, DC LINEARITY = ±0.0063%, T
A
= 25°C.
THE PINS 6 TO 12 CONNECTION SHOULD BE UNDER THE IC AND SHIELDED BY AN
ANALOG SYSTEM GROUND PLANE.
RC COMPENSATION BETWEEN PINS 11 AND 13 REQUIRED ONLY FOR f
CUTOFF
≥ 60kHz.
THE 33µF CAPACITOR IS A NONPOLARIZED, ALUMINUM ELECTROLYTIC, ±20%, 16V
(NICHICON UUPIC 330MCRIGS OR NIC NACEN 33M16V 6.3 × 5.5 OR EQUIVALENT).
* PROTECTION DIODES, 1N4148 ARE OPTIONAL. SEE PIN DESCRIPTIONS.
Dual Supply Operation
DC Accurate,
10Hz to 100kHz
, Clock-Tunable, 8th Order Elliptic Lowpass Filter
fCLK/f
C = 50:1
TYPICAL APPLICATIO
U
LTC1066-1
15
10661fa
5V
1066-1 TA04
5V
5V
V
OUT
V
IN
f
CLK
33µF
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
0.1µF
15pF
OUT A
–IN A
+IN A
V
–
V
+
CONNECT 1
FILTER
OUT
50/100
CLK
V
+
OUT B
+IN B
GND
FILTER
IN
COMP 2
CONNECT 2
COMP 1
V
–
0.1µF
0.1µF
1µF
LTC1066-1
100k
200Ω
30k
100k 10k
10k
INPUT LINEAR RANGE = 1.4V to 3.6V. DC LINEARITY = ±0.0063%.
THE PINS 6 TO 12 CONNECTION SHOULD BE UNDER THE IC AND SHIELDED BY AN
ANALOG SYSTEM GROUND PLANE.
RC COMPENSATION BETWEEN PINS 11 AND 13 REQUIRED ONLY FOR f
CUTOFF
≥ 24kHz.
THE 33µF CAPACITOR IS A NONPOLARIZED, ALUMINUM ELECTROLYTIC, ±20%, 16V
(NICHICON UUPIC 330MCRIGS OR NIC NACEN 33M16V 6.3 × 5.5)
Single 5V Supply Operation
DC Accurate,
10Hz to 36kHz
, Clock-Tunable, 8th Order Elliptic Lowpass Filter
fCLK/f
C = 50:1
TYPICAL APPLICATIO
U
LTC1066-1
16
10661fa
1066-1 TA05
7.5V
–7.5V
7.5V
2ND ORDER BUTTERWORTH ANTI-
ALIASING FILTER PROVIDES –68dB
ATTENUATION TO INPUTS AT 2fCLK
–7.5V
VOUT
VIN
fCLK
CF
RF
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
C2
OUT A
–IN A
+IN A
V–
V+
CONNECT 1
FILTEROUT
50/100
CLK
V+
OUT B
+IN B
GND
FILTERIN
COMP 2
CONNECT 2
COMP 1
V–
0.1µF
0.1µF
0.1µF
LTC1066-1
20Ω
20Ω
R1 R2
0.1µF
C1
fCUTOFF = , =
fCLK
50
fCUTOFF
250
1
2πRFCF
= 2Hz, SET RF = 80.6k, CF = 1µF AND C1 = 0.0027µF
1
2πRFCF
f–3dB = 2•fCUTOFF (f–3dB IS THE –3dB FREQUENCY OF THE
2ND ORDER ANTI-ALIASING FILTER)
1
2π(R1 + R2)C1 = 0.707•f–3dB, R2 = 17.946•R1, C2 = 10•C1
FOR CUTOFF FREQUENCIES 2kHz TO 5kHz, SET RF = 20k,
CF = 1µF AND R1 + R2 ≤ 2k
FOR CUTOFF FREQUENCIES <2kHz, SET R1 + R2 = RF
FOR EXAMPLE:
IF THE CUTOFF FREQUENCY OF LTC1066-1 IS 500Hz, THEN
f–3dB = 1000Hz
R1 + R2 = 80.6k, R1 = 4.22k AND R2 = 76.8k ROUNDED TO NEAREST 1% VALUE.
C2 = 0.027µF ROUNDED TO NEAREST STANDARD VALUE.
NOTE: RF SHOULD BE ≤100k TO MINIMIZE DC OFFSET TO ±5.5mV
DC Accurate Lowpass Filter with Input Anti-Aliasing
(fCLK ≤250kHz)
TYPICAL APPLICATIO
U
LTC1066-1
17
10661fa
TYPICAL APPLICATIO
U
1066-1 TA06
7.5V
–7.5V
7.5V
2ND ORDER RC ANTI-ALIASING
FILTER PROVIDES –36dB ATTENUATION
TO INPUTS AT 2fCLK
–7.5V
VOUT
VIN
fCLK
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
OUT A
–IN A
+IN A
V–
V+
CONNECT 1
FILTEROUT
50/100
CLK
V+
OUT B
+IN B
GND
FILTERIN
COMP 2
CONNECT 2
COMP 1
V–
0.1µF
0.1µF
0.1µF
LTC1066-1
20Ω
20Ω
402Ω1k
20k
0.1µF
1µF
CC
f–3dB = 5•fCUTOFF
C = µF (f–3dB IN Hz)
fCUTOFF = fCLK
50
100
f–3dB
f–3dB IS THE –3dB FREQUENCY
OF THE 2ND ORDER RC FILTER
DC Accurate Lowpass Filter with Input Anti-Aliasing
(fCLK > 250kHz)
LTC1066-1
18
10661fa
–
+
–
+
–
+
–
+
13121110
R
F
–
+
–
+
+
V
IN
C
P
50pF
C
A
0.047µF
0.1µF
7
9
5
12
5
7
8
10
9
15
16
2
6
11
14
3
1
4
3
2
8
15
16
17
18
413
19
LTC1045
14 R
A
PULSE
OUTPUT
6
R
P
2k
12.1k
1k
500Ω
500Ω
0.1µF
0.1µF
CLOCK INPUT
(TTL OR CMOS)
PULSE
AVERAGE
CLOCK FREQUENCY DETECTOR
20
LTC1045
1
1µF
5V
0.1µF
0.1µF
0.1µF
LTC202
–5V 5V
5V
C3
C2
R1
1k
R
IN
*
200Ω
20Ω
20Ω
CLOCK-TUNABLE,
8TH ORDER LOWPASS FILTER
FIRST ORDER RC
LOWPASS ANTI-ALIASING FILTER
1
C
F
18
0.1µF
C1
C
IN
*
0.1µF
0.1µF
0.1µF
V
OUT
0.1µF0.1µF
–5V
C4
C5
217
316
415
514
613
712
811
910
V
+
OUT B
+IN B
GND
LTC1066-1
F
IN
COMP 2
CON 2
COMP 1
V
–
OUT A
–IN A
+IN A
V
–
V
+
CON 1
F OUT
50/100
CLK
COMPONENT CALCULATIONS FOR A CLOCK-TUNABLE RANGE OF FIVE OCTAVES:
DEFINITIONS: 1. THE CUTOFF FREQUENCY OF LTC1066-1 IS ABBREVIATED AS f
C
2. f
C(LOW)
IS THE LOWEST CUTOFF FREQUENCY OF INTEREST
3. A RANGE OF FIVE OCTAVES IS FROM f
C(LOW)
TO 32f
C(LOW)
COMPONENT CALCULATIONS:
EXAMPLE:
1
2πR
F
C
F
f
C(LOW)
125
1
f
C(LOW)
= ; R
IN
* = R
F
(IF R
F
CAN BE CHOSEN TO BE 20k, R
IN
AND C
IN
ARE OMITTED.
f
C(LOW)
/125 ALLOWS FOR 0.2dB GAIN PEAK IN THE PASSBAND)
C1 = µF (f
C(LOW)
IN Hz) ; R1 = 1k
10
5
50•f
C(LOW)
5 × 10
5
50•f
C(LOW)
C
P
= 50pF; R
P
= k
C
A
= 0.047µF; R
A
= k
C2 = C1, C3 = 2•C1, C4 = 4•C1, C5 = 8•C1
LET’S CHOOSE A FIVE OCTAVE RANGE FROM 1kHz TO 32kHz. f
C(LOW)
= 1kHz (1000Hz).
LET C
F
= 1µF, THEN R
F
CALCULATES TO BE 20k. R
IN
AND C
IN
OMITTED;
R1 = 1k, C1 = 0.001µF, C2 = 0.001µF, C3 = 0.0022µF, C4 = 0.0039µF,
C5 = 0.0082µF. C
P
= 50pF, R
P
= 2k, C
A
= 0.047µF, R
A
= 10k
1066-1 TA07
DC Accurate Clock-Tunable Lowpass Filter with Tunable Input Anti-Aliasing Filter
(Circuit provides at least – 20dB attenuation to input frequencies at 2fCLK.
The clock-tunable range is 5 octaves.)
TYPICAL APPLICATIO
U
LTC1066-1
19
10661fa
S18 (WIDE) 0502
NOTE 3
.447 – .463
(11.354 – 11.760)
NOTE 4
15 14 13 12 11 10
16
9
N/2
12345678
.394 – .419
(10.007 – 10.643)
1718
N
.037 – .045
(0.940 – 1.143)
.004 – .012
(0.102 – 0.305)
.093 – .104
(2.362 – 2.642)
.050
(1.270)
BSC .014 – .019
(0.356 – 0.482)
TYP
0° – 8° TYP
NOTE 3
.009 – .013
(0.229 – 0.330)
.016 – .050
(0.406 – 1.270)
.291 – .299
(7.391 – 7.595)
NOTE 4
× 45°
.010 – .029
(0.254 – 0.737)
.420
MIN
.325 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
N
1 2 3 N/2
.050 BSC
.030 ±.005
TYP
.005
(0.127)
RAD MIN
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
4. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTIO
U
SW Package
18-Lead Plastic Small Outline (Wide .300 Inch)
(Reference LTC DWG # 05-08-1620)
LTC1066-1
20
10661fa
FREQUENCY (Hz)
10k
GAIN (dB)
100k 1M 10M
1066-1 TA08b
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1066-1 TA08a
8V
–8V
OUTPUT CLOCK
FEEDTHROUGH
FILTER
8V
2ND ORDER BUTTERWORTH INPUT
ANTI-ALIASING FILTER PROVIDES
–68dB ATTENUATION TO INPUTS AT 2fCLK.
f–3dB = 200kHz
–8V
VOUT
VIN
fCLK
C1
51pF
C2
510pF
20pF
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
OUT A
–IN A
+IN A
V–
V+
CONNECT 1
FILTEROUT
50/100
CLK
V+
OUT B
+IN B
GND
FILTERIN
COMP 2
CONNECT 2
COMP 1
V–
0.1µF
0.1µF
0.1µF
LTC1066-1
100Ω
30k
2.49k
2.49k
10k
0.1µF1000pF
f–3dB = 2•fCUTOFF
fCUTOFF =
C1 =
C2 = µF (f–3dB IN Hz)
fCLK
50
C2
10
100
f–3dB
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 1994
LT/LT 0905 REV A • PRINTED IN USA
TYPICAL APPLICATIONS
U
100kHz Elliptic Lowpass Filter with Input Anti-Aliasing and Output Clock Feedthrough Filters
(Not DC Accurate)
Gain vs Frequency
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PART NUMBER DESCRIPTION COMMENTS
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Noise 100kHz to 10MHz, 3V Supply
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RMS
Noise 100kHz to 20MHz, 3V Supply
