Publication# 11507 Rev. FAmendment/0
Issue Date: May 1995 2-79
Advanced
Micro
Devices
Am27C020
2 Megabit (262,144 x 8-Bit) CMOS EPROM
FINAL
DISTINCTIVE CHARACTERISTICS
■Fast access time
— 70 ns
■Low power consumption
— 100 µA maximum CMOS standby current
■JEDEC-approved pinout
— Plug in upgrade of 1 Mbit EPROM
— Easy upgrade from 28-pin JEDEC EPROMs
■Single +5 V power supply
■±10% power supply tolerance standard on
most speeds
■100% Flashrite programming
— Typical programming time of 32 seconds
■Latch-up protected to 100 mA from –1 V to
VCC + 1 V
■High noise immunity
■Compact 32-pin DIP, PDIP, TSOP, and PLCC
packages
GENERAL DESCRIPTION
The Am27C020 is a 2 Mbit, ultraviolet erasable pro-
grammable read-only memory. It is organized as 256K
words by 8 bits per word, operates from a single +5 V
supply, has a static standby mode, and features fast sin-
gle address location programming. Products are avail-
able in windowed ceramic DIP packages, as well as
plastic one-time programmable (OTP) including TSOP,
PLCC, and PDIP.
Typically, any byte can be accessed in less than 70 ns,
allowing operation with high-performance microproces-
sors without any WAIT states. The Am27C020 offers
separate Output Enable (OE) and Chip Enable (CE)
controls, thus eliminating bus contention in a multiple
bus microprocessor system.
AMD’s CMOS process technology provides high speed,
low power, and high noise immunity. Typical power con-
sumption is only 100 mW in active mode, and 100 µW in
standby mode.
All signals are TTL levels, including programming sig-
nals. Bit locations may be programmed singly, in blocks,
or at random. The Am27C020 supports AMD’s Flashrite
programming algorithm (100 µs pulses) resulting in typi-
cal programming times of 32 seconds.
BLOCK DIAGRAM VCC
Output Enable
Chip Enable
and
Prog Logic
Y
Decoder
X
Decoder
CE
OE Output
Buffers
Y
Gating
2,097,152-Bit
Cell Matrix
A0–A17
Address
Inputs
Data Outputs
DQ0–DQ7
11507F-1
VPP
VSS
PGM
AMD
2-80 Am27C020
PRODUCT SELECTOR GUIDE
Family Part No.
Ordering Part No:
VCC ±5% -75 -255
VCC ±10% -70 -90 -120 -150 -200
Max Access Time (ns) 70 90 120 150 200 250
CE (E) Access (ns) 70 90 120 150 200 250
OE (G) Access (ns) 40 40 50 65 75 100
Am27C020
CONNECTION DIAGRAMS
Top View DIP
Notes:
1. JEDEC nomenclature is in parentheses.
2. The 32-pin DIP to 32-pin PLCC configuration varies from the JEDEC 28-pin DIP to 32-pin PLCC configuration.
11507F-2
PLCC
VPP VCC
DQ0
A14
1
3
5
7
9
11
12
10
2
4
8
6
32
30
28
26
24
14
21
23
31
29
25
27
13
22
20
19
15
16 18
17
DQ1
DQ2
VSS
PGM (P)
A17
A13
A8
A9
A11
OE (G)
A10
CE (E)
DQ7
DQ6
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ5
DQ4
DQ3 11507F-3
11507F-4
TSOP
1
16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
17
31
30
29
28
27
26
25
24
23
22
21
20
19
18
A11
A4
A9
A8
A13
A14
A17
PGM
VCC
VPP
A16
A15
A12
A7
A6
A5
OE
A3
A10
CE
DQ7
DQ6
DQ5
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
DQ4
Standard Pinout
VPP
131 30
2
3
4
5
6
7
8
9
10
11
12
13 17 18 19 2016
15
14
29
28
27
26
25
24
23
22
21
32
A6
A5
A4
A3
A2
A1
A0
A7 A14
A13
A8
A9
A11
OE (G)
CE (E)
A10
DQ7
A12
VCC
PGM (P)
NC
DQ1
DQ2
VSS
DQ3
DQ4
DQ5
DQ0
A15
A16
DQ6
AMD
2-81Am27C020
11507F-5
A0–A17
DQ0–DQ7
CE (E)
PGM (P)
OE (G)
8
18
PIN DESIGNATIONS
A0–A17 = Address Inputs
CE (E) = Chip Enable Input
DQ0–DQ7 = Data Input/Outputs
OE (G) = Output Enable Input
PGM (P) = Program Enable Input
VCC =VCC Supply Voltage
VPP = Program Voltage Input
VSS = Ground
LOGIC SYMBOL
AMD
2-82 Am27C020
ORDERING INFORMATION
UV EPROM Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended Commercial (–55°C to +125°C)
PACKAGE TYPE
D = 32-Pin Ceramic DIP (CDV032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27C020
2 Megabit (262,144 x 8-Bit) CMOS UV EPROM
AM27C020-70
AM27C020-90
AM27C020-120
AM27C020-150
AM27C020-200
AM27C020-255
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the lo-
cal AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
DC, DCB, DI, DIB
Valid Combinations
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-In
DC, DCB, DI, DIB,
DE, DEB
AM27C020 -70 D C B
DC, DCB, DI, DIB
AMD
2-83Am27C020
ORDERING INFORMATION
OTP Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of:
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to 85°C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded
Chip Carrier (PL 032)
E = 32-Pin TSOP Standard Pinout (TS 032)
SPEED OPTION
See Product Selector Guide and
Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am27C020
2 Megabit (262,144 x 8-Bit) CMOS OTP EPROM
AM27C020-75
AM27C020-90
AM27C020-120
AM27C020-150
AM27C020-200
AM27C020-255
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific
valid combinations and to check on newly released
combinations.
Valid Combinations
OPTIONAL PROCESSING
Blank = Standard Processing
PC, JC, PI,
JI, EC, EI
AM27C020 -75 P C
AMD
2-84 Am27C020
FUNCTIONAL DESCRIPTION
Erasing the Am27C020
In order to clear all locations of their programmed con-
tents, it is necessary to expose the Am27C020 to an ul-
traviolet light source. A dosage of 15 W seconds/cm2 is
required to completely erase an Am27C020. This dos-
age can be obtained by exposure to an ultraviolet lamp
— wavelength of 2537 A
° — with intensity of 12,000 µW/
cm2 for 15 to 20 minutes. The Am27C020 should be di-
rectly under and about one inch from the source and all
filters should be removed from the UV light source prior
to erasure.
It is important to note that the Am27C020, and similar
devices, will erase with light sources having wave-
lengths shorter than 4000 A
°. Although erasure times will
be much longer than with UV sources at 2537A
°,
nevertheless the exposure to fluorescent light and sun-
light will eventually erase the Am27C020 and exposure
to them should be prevented to realize maximum sys-
tem reliability. If used in such an environment, the
package window should be covered by an opaque label
or substance.
Programming the Am27C020
Upon delivery, or after each erasure, the Am27C020
has all 2,097,152 bits in the “ONE”, or HIGH state.
“ZEROs” are loaded into the Am27C020 through the
procedure of programming.
The programming mode is entered when 12.75 V ±
0.25V is applied to the VPP pin, CE and PGM are at VIL
and OE is at VIH.
For programming, the data to be programmed is applied
8 bits in parallel to the data output pins.
The Flashrite algorithm reduces programming time by
using 100 µs programming pulse and by giving each
address only as many pulses as are necessary in order
to reliably program the data. After each pulse is applied
to a given address, the data in that address is verified. If
the data does not verify, additional pulses are given until
it verifies or the maximum is reached. This process is
repeated while sequencing through each address of the
Am27C020. This part of the algorithm is done at VCC =
6.25 V to assure that each EPROM bit is programmed to
a sufficiently high threshold voltage. After the final
address is completed, the entire EPROM memory is
verified at VCC = VPP = 5.25 V.
Program Inhibit
Programming of multiple Am27C020s in parallel with
different data is also easily accomplished. Except for
CE, all like inputs of the parallel Am27C020 may be
common. A TTL low-level program pulse applied to an
Am27C020 CE input with VPP = 12.75 V ± 0.25 V, PGM
LOW, and OE HIGH will program that Am27C020.
A high-level CE input inhibits the other Am27C020s
from being programmed.
Program Verify
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The
verify should be performed with OE and CE at VIL, PGM
at VIH, and VPP between 12.5 V and 13.0 V.
Auto Select Mode
The auto select mode allows the reading out of a binary
code from an EPROM that will identify its manufacturer
and type. This mode is intended for use by programming
equipment for the purpose of automatically matching
the device to be programmed with its corresponding
programming algorithm. This mode is functional in the
25°C ± 5°C ambient temperature range that is required
when programming the Am27C020.
To activate this mode, the programming equipment
must force 12.0 V ± 0.5 V on address line A9 of the
Am27C020. Two identifier bytes may then be se-
quenced from the device outputs by toggling address
line A0 from VIL to VIH. All other address lines must be
held at VIL during auto select mode.
Byte 0 (A0 = VIL) represents the manufacturer code, and
Byte 1 (A0 = VIH), the device identifier code. For the
Am27C020, these two identifier bytes are given in the
Mode Select table. All identifiers for manufacturer and
device codes will possess odd parity, with the MSB
(DQ7) defined as the parity bit.
Read Mode
The Am27C020 has two control functions, both of which
must be logically satisfied in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable (OE)
is the output control and should be used to gate data to
the output pins, independent of device selection. As-
suming that addresses are stable, address access time
(tACC) is equal to the delay from CE to output (tCE). Data
is available at the outputs tOE after the falling edge of
OE, assuming that CE has been LOW and addresses
have been stable for at least tACC – tOE.
Standby Mode
The Am27C020 has a CMOS standby mode which re-
duces the maximum VCC current to 100 µA. It is placed
in CMOS-standby when CE is at VCC ± 0.3 V. The
Am27C020 also has a TTL-standby mode which re-
duces the maximum VCC current to 1.0 mA. It is placed in
TTL-standby when CE is at VIH. When in standby mode,
the outputs are in a high-impedance state, independent
of the OE input.
AMD
2-85Am27C020
Output OR-Tieing
To accommodate multiple memory connections, a two-
line control function is provided to allow for:
Low memory power dissipation, and
Assurance that output bus contention will not occur
It is recommended that CE be decoded and used as the
primary device-selecting function, while OE be made a
common connection to all devices in the array and con-
nected to the READ line from the system control bus.
This assures that all deselected memory devices are in
their low-power standby mode and that the outut pins
are only active when data is desired from a particular
memory device.
System Applications
During the switch between active and standby condi-
tions, transient current peaks are produced on the rising
and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1 µF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VSS to minimize transient effects. In addition, to
overcome the voltage drop caused by the inductive ef-
fects of the printed circuit board traces on EPROM ar-
rays, a 4.7 µF bulk electrolytic capacitor should be used
between VCC and VSS for each eight devices. The loca-
tion of the capacitor should be close to where the power
supply is connected to the array.
MODE SELECT TABLE
CE OE PGM A0 A9 VPP Outputs
Read VIL VIL XXXXD
OUT
Output Disable X VIH X X X X High Z
Standby (TTL) VIH X X X X X High Z
Standby (CMOS) VCC ± 0.3 V X X X X X High Z
Program VIL VIH VIL XXV
PP DIN
Program Verify VIL VIL VIH XXV
PP DOUT
Program Inhibit VIH XX XXV
PP High Z
VIL VIL XV
IL VHX 01H
VIL VIL XV
IH VHX 97H
Pins
Manufacturer Code
Device Code
Auto Select
(Note 3)
Notes:
1. V
H
= 12.0 V
±
0.5 V.
2. X = Either V
IH
or V
IL
.
3. A1–A8 = A10–A17 = V
IL
.
4. See DC Programming Characteristics for V
PP
voltage during programming.
Mode
AMD
2-86 Am27C020
ABSOLUTE MAXIMUM RATINGS
Storage Temperature:
OTP Products –65°C to +125°C. . . . . . . . . . . . . . . . .
All Other Products –65°C to +150°C. . . . . . . . . . . . . .
Ambient Temperature
with Power Applied –55°C to +125°C. . . . . . . . . . . . .
Voltage with Respect to VSS:
All pins except A9, VPP, and
VCC (Note 1) –0.6 V to VCC + 0.6 V. . . . . . . . . . . . . .
A9 and VPP (Note 2) –0.6 V to 13.5 V. . . . . . . . . . . . .
VCC –0.6 V to 7.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
1. During transitions, the input may overshoot V
SS
to –2.0 V
for periods of up to 20 ns. Maximum DC voltage on input
and I/O may overshoot to V
CC
+ 2.0 V for periods of up to
20 ns.
2. During transitions, A9 and V
PP
may overshoot V
SS
to
–2.0V for periods of up to 20 ns. A9 and V
PP
must not
exceed 13.5 V for any period of time.
Stresses above those listed under Absolute Maximum Rat-
ings may cause permanent device failure. Functionality at or
above these limits is not implied. Exposure to absolute maxi-
mum ratings for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA)0°C to +70°C. . . . . . . . . .
Industrial (I) Devices
Ambient Temperature (TA) –40°C to +85°C. . . . . . . .
Extended Commercial (E) Devices
Ambient Temperature (TA) –55°C to +125°C. . . . . . .
Supply Read Voltages:
VCC for Am27C020-XX5 +4.75 V to +5.25 V. . . . . . . .
VCC for Am27C020-XX0 +4.50 V to +5.50 V. . . . . . . .
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
AMD
2-87Am27C020
DC CHARACTERISTICS over operating ranges unless otherwise specified
(Notes 1, 2, and 4)
Parameter
Symbol Parameter Description Test Conditions Min Max Unit
VOH Output HIGH Voltage IOH = –400 µA 2.4 V
VOL Output LOW Voltage IOL = 2.1 mA 0.45 V
VIH Input HIGH Voltage 2.0 VCC + 0.5 V
VIL Input LOW Voltage –0.5 +0.8 V
ILI Input Load Current VIN = 0 V to VCC 1.0 µA
ILO Output Leakage Current VOUT = 0 V to VCC 5.0 µA
ICC1 VCC Active Current CE = VIL, C/I Devices 30
(Note 3) f = 10 MHz,
IOUT = 0 mA E Devices 60
ICC2 VCC TTL Standby Current CE = VIH 1.0 mA
ICC3 VCC CMOS Standby Current CE = VCC + 0.3 V 100 µA
IPP1 VPP Supply Current (Read) CE = OE = VIL, VPP = VCC 100 µA
mA
PRELIMINARY
Notes:
1. V
CC
must be applied simultaneously or before V
PP
, and removed simultaneously or after V
PP
.
2. Caution: The Am27C020 must not be removed from (or inserted into) a socket when V
CC
or V
PP
is applied.
3. I
CC1
is tested with
OE
= V
IH
to simulate open outputs.
4. Minimum DC Input Voltage is –0.5 V. During transitions, the inputs may overshoot to –2.0 V for periods less than 20 ns.
Maximum DC Voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods less than 20 ns.
Frequency in MHz 11507F-6
12345678910
30
25
20
15
10
Supply Current
in mA
11507F-7
–75 –50 –25 0 25 50 75 100 125 150
30
25
20
15
10
Supply Current
in mA
Temperature in °C
Figure 1. Typical Supply Current
vs. Frequency
VCC = 5.5 V, T = 25°C
Figure 2. Typical Supply Current
vs. Temperature
VCC = 5.5 V, f = 10 MHz
AMD
2-88 Am27C020
CAPACITANCE
Parameter Parameter
Symbol Description Test Conditions Typ Max Typ Max Typ Max Typ Max Unit
CIN Input Capacitance VIN = 0 V 10 12 10 12 8 10 10 12 pF
COUT Output Capacitance VOUT = 0 V 12 15 12 15 9 12 12 14 pF
CDV032 PD 032 PL 032
Notes:
1. This parameter is only sampled and not 100% tested.
2. T
A
= +25
°
C, f = 1 MHz.
TS 032
SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified
(Notes 1, 3, and 4)
Parameter -75
JEDEC Standard Description Test Conditions -70 -90 -120 -150 -200 -255 Unit
tAVQV tACC Address to Min — — — — — —
Output Delay Max 70 90 120 150 200 250
tELQV tCE Chip Enable Min — — — — — —
to Output Delay Max 70 90 120 150 200 250
tGLQV tOE Output Enable to Min — — — — — —
Output Delay Max 40 40 50 65 75 100
tEHQZ,t
DF Chip Enable HIGH Min — — — — — —
tGHQZ (Note 2) or Output Enable
HIGH, whichever Max 25 25 30 30 40 60
comes first, to
Output Float
tAXQX tOH Output Hold from Min 0 0 0 0 0 0
Addresses, CE, or
OE, whichever Max — — — — — —
occurred first
CE = OE = VIL
OE = VIL
CE = VIL
ns
Am27C020
Notes:
1. V
CC
must be applied simultaneously or before V
PP
, and removed simultaneously or after V
PP
.
2. This parameter is only sampled and not 100% tested.
3. Caution: The Am27C020 must not be removed from, or inserted into a socket or board when V
PP
or V
CC
is applied.
4. Output Load: 1 TTL gate and C
L
= 100 pF,
Input Rise and Fall Times: 20 ns,
Input Pulse Levels: 0.45 V to 2.4 V,
Timing Measurement Reference Level: 0.8 V and 2 V inputs and outputs.
ns
ns
ns
ns
Parameter
Symbols
AMD
2-89Am27C020
SWITCHING TEST CIRCUIT
11507F-8
Device
Under
Test 5.0 V
Diodes = IN3064
or Equivalent
CL6.2 kΩ
2.7 kΩ
CL = 100 pF including jig capacitance
SWITCHING TEST WAVEFORM
2.0 V
0.8 V 0.8 V
2.0 V
2.4 V
0.45 V Input Output 11507F-9
AC Testing: Inputs are driven at 2.4 V for a Logic “1” and 0.45 V for a Logic “0.” Input pulse rise and fall times are ≤ 20 ns.
Test Points
AMD
2-90 Am27C020
KEY TO SWITCHING WAVEFORMS
Must Be
Steady
May
Change
from H to L
May
Change
from L to H
Does Not
Apply
Don’t Care,
Any Change
Permitted
Will Be
Steady
Will Be
Changing
from H to L
Will Be
Changing
from L to H
Changing,
State
Unknown
Center
Line is High
Impedance
“Off” State
WAVEFORM INPUTS OUTPUTS
KS000010
SWITCHING WAVEFORM
Addresses
CE
OE
Output
11507F-10
Addresses Valid
High Z High Z
tCE
Valid Output
2.4
0.45
2.0
0.8 2.0
0.8
tACC
(Note 1)
tOE tDF
(Note 2)
tOH
Notes:
1.
OE
may be delayed up to tACC – tOE after the falling edge of the addresses without impact on tACC.
2. tDF is specified from
OE
or
CE
, whichever occurs first.
