Single-Phase Energy Measurement IC with
8052 MCU, RTC, and LCD Driver
Data Sheet
ADE5166/ADE5169/ADE5566/ADE5569
Rev. D
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GENERAL FEATURES
Wide supply voltage operation: 2.4 V to 3.7 V
Internal bipolar switch between regulated and battery inputs
Ultralow power operation with power saving modes (PSM)
Full operation: 4.4 mA to 1.6 mA (PLL clock dependent)
Battery mode: 3.3 mA to 400 µA (PLL clock dependent)
Sleep mode
Real-time clock (RTC) mode: 1.7 µA
RTC and LCD mode: 38 µA (LCD charge pump enabled)
Reference: 1.2 V ± 0.1% (10 ppm/°C drift)
64-lead, low profile quad flat, RoHS-compliant package (LQFP)
Operating temperature range: −40°C to +85°C
ENERGY MEASUREMENT FEATURES
Proprietary analog-to-digital converters (ADCs) and digital
signal processing (DSP) provide high accuracy active
(watt), reactive (var), and apparent energy (volt-ampere
(VA)) measurement
<0.1% error on active energy over a dynamic range of
1000 to 1 @ 25°C
<0.5% error on reactive energy over a dynamic range of
1000 to 1 @ 25°C (ADE5169 and ADE5569 only)
<0.5% error on root mean square (rms) measurements
over a dynamic range of 500 to 1 for current (Irms) and
100 to 1 for voltage (Vrms) @ 25°C
Supports IEC 62053-21; IEC 62053-22; IEC 62053-23;
EN 50470-3 Class A, Class B, and Class C; and ANSI C12-16
Differential input with programmable gain amplifiers (PGAs)
supports shunts, current transformers, and di/dt current
sensors (ADE5169 and ADE5569 only)
2 current inputs for antitamper detection in the ADE5166/
ADE5169
High frequency outputs proportional to Irms, active, reactive,
or apparent power (AP)
Table 1. Features Available on Each Part
Part No. Antitamper
Watt,
VA,
Irms, Vrms Var
di/dt
Sensor
Memory
Size
ADE5166 Yes Yes No No 62kB
ADE5169 Yes Yes Yes Yes 32kB or
62kB
ADE5566 No Yes No No 62kB
ADE5569 No Yes Yes Yes 62kB
MICROPROCESSOR FEATURES
8052-based core
Single-cycle 4 MIPS 8052 core
8052-compatible instruction set
32.768 kHz external crystal with on-chip PLL
2 external interrupt sources
External reset pin
Low power battery mode
Wake-up from I/O, temperature change, alarm, and
universal asynchronous receiver/transmitter (UART)
LCD driver operation with automatic scrolling
Temperature measurement
Real-time clock (RTC)
Counter for seconds, minutes, hours, days, months,
and years
Date counter, including leap year compensation
Automatic battery switchover for RTC backup
Operation down to 2.4 V
Ultralow battery supply current: 1.7 µA
Selectable output frequency: 1 Hz to 16 kHz
Embedded digital crystal frequency compensation for
calibration and temperature variation of 2 ppm resolution
Integrated LCD driver
108-segment driver for the ADE5566 and ADE5569
104-segment driver for the ADE5166 and ADE5169
2×, 3×, or 4× multiplexing
4 LCD memory banks for screen scrolling
LCD voltages generated internally or with external resistors
Internal adjustable drive voltages up to 5 V independent
of power supply level
On-chip peripherals
2 independent UART interfaces
SPI or I2C
Watchdog timer
Power supply management with user-selectable levels
Memory: 62 kB flash memory, 2.256 kB RAM
Development tools
Single-pin emulation
IDE-based assembly and C source debugging
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 2 of 156
TABLE OF CONTENTS
General Features ............................................................................... 1
Energy Measurement Features ........................................................ 1
Microprocessor Features .................................................................. 1
Revision History ............................................................................... 4
General Description ......................................................................... 5
32 Kb Flash Option ...................................................................... 5
Functional Block Diagrams ............................................................. 5
Specifications ..................................................................................... 7
Energy Metering ........................................................................... 7
Analog Peripherals ....................................................................... 8
Digital Interface ............................................................................ 9
Timing Specifications ................................................................ 11
Absolute Maximum Ratings .......................................................... 16
Thermal Resistance .................................................................... 16
ESD Caution ................................................................................ 16
Pin Configurations and Function Descriptions ......................... 17
Typical Performance Characteristics ........................................... 21
Terminology .................................................................................... 25
Special Function Register (SFR) Mapping .................................. 26
Power Management ........................................................................ 28
Power Management Register Details ....................................... 28
Power Supply Architecture ........................................................ 31
Battery Switchover ...................................................................... 31
Power Supply Management (PSM) Interrupt ......................... 31
Using the Power Supply Features ............................................. 33
Operating Modes ............................................................................ 36
PSM0 (Normal Mode) ............................................................... 36
PSM1 (Battery Mode) ................................................................ 36
PSM2 (Sleep Mode) .................................................................... 36
3.3 V Peripherals and Wake-Up Events ................................... 37
Transitioning Between Operating Modes ............................... 38
Using the Power Management Features .................................. 38
Energy Measurement ..................................................................... 39
Access to Energy Measurement SFRs ...................................... 39
Access to Internal Energy Measurement Registers ................ 39
Energy Measurement Registers ................................................ 42
Energy Measurement Internal Registers Details .................... 43
Interrupt Status/Enable SFRs .................................................... 46
Analog Inputs .............................................................................. 47
Analog-to-Digital Conversion .................................................. 48
Fault Detection (ADE5166/ADE5169 Only) .......................... 52
di/dt Current Sensor and Digital Integrator
(ADE5169/ADE5569 Only) ...................................................... 53
Power Quality Measurements ................................................... 54
Phase Compensation ................................................................. 56
RMS Calculation ........................................................................ 57
Active Power Calculation .......................................................... 59
Active Energy Calculation ........................................................ 62
Reactive Power Calculation (ADE5169/ADE5569 Only) ..... 65
Reactive Energy Calculation (ADE5169/ADE5569 Only) ... 67
Apparent Power Calculation ..................................................... 70
Apparent Energy Calculation ................................................... 70
Ampere-Hour Accumulation ................................................... 72
Energy-to-Frequency Conversion............................................ 73
Energy Register Scaling ............................................................. 73
Energy Measurement Interrupts .............................................. 74
Temperature, Battery, and Supply Voltage Measurements........ 75
Temperature Measurement ....................................................... 77
Battery Measurement ................................................................. 77
External Voltage Measurement ................................................ 78
8052 MCU Core Architecture....................................................... 80
MCU Registers ............................................................................ 80
Basic 8052 Registers ................................................................... 82
Standard 8052 SFRs .................................................................... 84
Memory Overview ..................................................................... 85
Addressing Modes ...................................................................... 86
Instruction Set ............................................................................ 87
Read-Modify-Write Instructions ............................................. 89
Instructions That Affect Flags .................................................. 90
Dual Data Pointers ......................................................................... 92
Interrupt System ............................................................................. 93
Standard 8052 Interrupt Architecture ..................................... 93
Interrupt Architecture ............................................................... 93
Interrupt Registers...................................................................... 93
Interrupt Priority ........................................................................ 94
Interrupt Flags ............................................................................ 95
Interrupt Vectors ........................................................................ 97
Interrupt Latency ........................................................................ 97
Context Saving ............................................................................ 97
Watchdog Timer ............................................................................. 98
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 3 of 156
Writing to the Watchdog Timer SFR (WDCON, Address
0xC0) ............................................................................................. 99
Watchdog Timer Interrupt......................................................... 99
LCD Driver.................................................................................... 100
LCD Registers ........................................................................... 100
LCD Setup ................................................................................. 103
LCD Timing and Waveforms ................................................. 103
Blink Mode ................................................................................ 104
Scrolling Mode ......................................................................... 104
Display Element Control ......................................................... 104
Voltage Generation .................................................................. 105
LCD External Circuitry ........................................................... 105
LCD Function in PSM2 Mode ............................................... 106
Flash Memory ............................................................................... 107
Flash Memory Overview ......................................................... 107
Flash Memory Organization ................................................... 107
Using the Flash Memory ......................................................... 108
Protecting the Flash Memory ................................................. 111
In-Circuit Programming ......................................................... 113
Flash Memory Organization for the 32 kB Model ............... 114
Timers ............................................................................................ 115
Timer Registers ......................................................................... 115
Timer 0 and Timer 1 ................................................................ 117
Timer 2 ...................................................................................... 118
PLL ................................................................................................. 120
PLL Registers ............................................................................ 120
Real-Time Clock (RTC) .............................................................. 121
Access to RTC SFRs ................................................................. 121
Access to Internal RTC Registers ........................................... 121
RTC SFRs .................................................................................. 122
RTC Registers ........................................................................... 125
RTC Calendar ........................................................................... 126
RTC Interrupts ......................................................................... 127
RTC Crystal Compensation .................................................... 128
UART Serial Interface ................................................................... 129
UART SFRs ................................................................................ 129
UART Operation Modes .......................................................... 132
UART Baud Rate Generation .................................................. 133
UART Additional Features ...................................................... 135
UART2 Serial Interface................................................................. 136
UART2 SFRs .............................................................................. 136
UART2 Operation Modes ........................................................ 138
UART2 Baud Rate Generation ................................................ 138
UART2 Additional Features .................................................... 139
Serial Peripheral Interface (SPI) .................................................. 140
SPI Registers .............................................................................. 140
SPI Pins ....................................................................................... 143
SPI Master Operating Modes .................................................. 144
SPI Interrupt and Status Flags ................................................. 145
I2C-Compatible Interface ............................................................. 146
Serial Clock Generation ........................................................... 146
Slave Addresses .......................................................................... 146
I2C Registers ............................................................................... 146
Read and Write Operations ..................................................... 147
I2C Receive and Transmit FIFOs ............................................. 148
I/O Ports ......................................................................................... 149
Parallel I/O ................................................................................. 149
I/O Registers .............................................................................. 150
Port 0........................................................................................... 153
Port 1........................................................................................... 153
Port 2........................................................................................... 153
Determining the Version of the
ADE5166/ADE5169/ADE5566/ADE5569 ................................ 154
Outline Dimensions ...................................................................... 155
Ordering Guide ......................................................................... 155
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 4 of 156
REVISION HISTORY
4/12—Rev. C to Rev. D
Changes to Table 1 ............................................................................. 1
Moved Revision History ................................................................... 4
Added 32 kB Flash Option Section ................................................. 5
Changes to Vrms Measurement Bandwidth Parameter, Table 2 ... 7
Changes to Table 17 ......................................................................... 28
Changes to Figure 39 ....................................................................... 40
Changes to Figure 40 ....................................................................... 41
Changes to RMS Calculation Section, Current Channel RMS
Calculation Section, and Figure 60 ............................................... 57
Changes to Current Channel RMS Offset Compensation
Section, Figure 61, and Figure 62 .................................................. 58
Changes to Figure 63 and Voltage Channel RMS Calculation
Section ............................................................................................... 59
Changes to Figure 74 ....................................................................... 68
Added Flash Memory Organization for the 32 kB Model
Section and Figure 97, Renumbered Sequentially ....................114
Change to Table 127 ......................................................................122
Changes to UART Timer Generated Baud Rates Section ........135
Changes to Table 149.....................................................................137
Removed UART2 TxD2 Signal Modulation Section ................137
Changes to Table 155.....................................................................143
Changes to Table 161.....................................................................150
Changes to Table 167 .................................................................... 151
Changes to Ordering Guide ......................................................... 155
6/10—Rev. B to Rev. C
Changes to Bit 5, Table 161 .......................................................... 148
Changes to Ordering Guide ......................................................... 153
11/09—Rev. A to Rev. B
Deleted RTCCAL Function.......................................... Throughout
Changes to Fault Detection (ADE5166/ADE5169
Only) Section .................................................................................. 51
2/09—Rev. 0 to Rev. A
Added ADE5566/ADE5569 .............................................. Universal
Changes to General Features and Microprocessor Features ........ 1
Change to Figure 29, Figure 30, and Figure 31 .......................... 23
Changes to Figure 46...................................................................... 49
Changes to Figure 59...................................................................... 56
Changes to Figure 61...................................................................... 57
Change to Figure 73 ....................................................................... 67
Changes to Figure 89...................................................................... 95
Changes to Figure 103 ................................................................. 120
Changes to Determining the Version of the
ADE5166/ADE5169/ADE5566/ADE5569 Section .................. 152
Changes to Ordering Guide ........................................................ 153
10/08—Revision 0: Initial Version
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 5 of 156
GENERAL DESCRIPTION
The ADE5166/ADE5169/ADE5566/ADE55691 integrate the
Analog Devices, Inc., energy (ADE) metering IC analog front
end and fixed function DSP solution with an enhanced 8052 MCU
core, a full RTC, an LCD driver, and all the peripherals to make
an electronic energy meter with an LCD display in a single part.
The ADE measurement core includes active, reactive, and apparent
energy calculations, as well as voltage and current rms measure-
ments. This information is accessible for energy billing by using the
built-in energy scalars. Many power line supervisory features such
as SAG, peak, and zero crossing are included in the energy
measurement DSP to simplify energy meter design.
The microprocessor functionality includes a single-cycle 8052 core,
a full RTC with a power supply backup pin, an SPI or I2C interface,
and two independent UART interfaces. The ready-to-use infor-
mation from the ADE core reduces the requirement for program
memory size, making it easy to integrate complicated design into
62 kB of flash memory.
The ADE5166/ADE5169 include a 104-segment LCD driver and
the ADE5566/ADE5569 include a 108-segment LCD driver, each
with the capability to store up to four LCD screens in memory. This
driver generates voltages capable of driving LCDs up to 5 V.
32 KB FLASH OPTION
A reduced memory version of the ADE5169 is available with
32 kB of flash memory. A description of the flash memory
organization of this model is provided in the Flash Memory
Organization for the 32 kB Model section. All other features
and functionality are identical between the models and no
reference is made in the remainder of this data sheet to the
32 kB model. If using the 32 kB model, 32 kB should therefore
be substituted in any references to 62 kB of flash memory.
1 Patents pending.
FUNCTIONAL BLOCK DIAGRAMS
I
PA
I
N
V
P
V
N
REF
IN/OUT
ENERGY
MEASUREMENT
DSP
OSC
COM0
...
...
COM3
...
CF1
CF2
3V/ 5V LCD
CHARGE P UM P
SINGLE
CYCLE
8052
MCU
ADE5166/ADE5169
V
DCIN
V
BAT
V
DD
V
SWOUT
DGND
AGND
LCDVA
LCDVB
LCDVC
...
FP0
FP15
RTC
SS
SCLK
MISO
MOSI/SDATA
T2
T2EX
T0
T1
LCDVP1
LCDVP2
XTAL2
XTAL1
INT0
INT1
FP16
FP17
FP23
FP22
FP21
FP20
FP19
FP18
FP25
FP24
1.20V
REF
52
53
49
50
I
PB 55
63
54
58
64 61
60 4647 48 45
5
6
FP28
FP27
2
1
7
8
9
10
11
12
13
14
20
35
1
4
15
17
18
16
19
44
14
13
12
57 43 42 39 38 7 6 45 11 43 42 41 40 39 38 37 36 5678 9 1038 39 40 41
PGA2
–
+
PGA1
–
+
PGA1
–
+
ADC
ADC
ADC
TEMP
ADC
VSW
ADC
PROGRAM MEMORY
62kB FLASH
POWER SUPPLY
CONTROL AND
MONITORING
USER RAM
256 BYT E S
USER X RAM
2kB
TEMP
SENSOR
BATTERY
ADC
SPI/I
2
C
SERIAL
INTERFACE
3 × 16-BI T
COUNTER
TIMERS
104-SEGMENT
LCD DRIVER
WATCHDOG
TIMER
PLL
07411-201
LDO
V
INTD
V
INTA
RESET
TxD
UART
SERIAL
PORT
UART2
SERIAL
PORT
UART2
TIMER
RxD
62 56 51
TxD2
44
36
RxD2
38
37
59
DOWNLOADER
DEBUGGER
1-PIN
EMULATOR
LDO
EA
UART
TIMER
POR
P0.7/SS/T1/RxD2
P0.6/SCLK/T0
P0.5/MISO/ZX
P0.4/MOSI/SDATA
P0. 0 ( BCTRL/I NT1/ P 0.0)
P1.0/RxD
P1.1/TxD
P1.2/FP25/ZX
P1.3/T2EX/FP24
P1.6/FP21
P1.7/FP20
P1.4/T2/FP23
P1.5/FP22
P0.1/FP19
P0.2/CF1
P0.3/CF2
P2.0/FP18
P2.1/FP17
P2.2/FP16
P2. 3 ( S DE N/P2. 3/T xD2)
Figure 1. ADE5166/ADE5169 Functional Block Diagram
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 6 of 156
IP
IN
VP
VN
REF
IN/OUT
ENERGY
MEASUREMENT
DSP
OSC
COM0
...
...
COM3
...
CF1
CF2
LDO
3V/ 5V LCD
CHARGE P UM P
SINGLE
CYCLE
8052
MCU
ADE5566/ADE5569
FP26
V
DCIN
VBAT
V
DD
V
SWOUT
V
INTD
V
INTA
RESET
DGND
AGND
TxD
UART
SERIAL
PORT
UART2
SERIAL
PORT
UART2
TIMER
LCDVA
LCDVB
LCDVC
...
FP0
FP15
RTC
SS
SCLK
MISO
MOSI/SDATA
RxD
T2
T2EX
T0
T1
LCDVP1
LCDVP2
XTAL2
XTAL1
INT0
INT1
FP16
FP17
FP23
FP22
FP21
FP20
FP19
FP18
FP25
FP24
P0.7/SS/T1/RxD2
P0.6/SCLK/T0
P0.5/MISO/ZX
P0.4/MOSI/SDATA
P0. 0 ( BCTRL/I NT1/ P 0.0)
P1.0/RxD
P1.1/TxD
P1.2/FP25/ZX
P1.3/T2EX/FP24
P1.6/FP21
P1.7/FP20
P1.4/T2/FP23
P1.5/FP22
P2.0/FP18
P2.1/FP17
P2.2/FP16
P2. 3 ( S DE N/P2. 3/T xD2)
P0.1/FP19
P0.2/CF1
P0.3/CF2
1.20V
REF
53
52
55
49
50
63
54
58
64 61
60 62 56 51
TxD2
44
36
RxD2
38
37 46
47 48 45
5
FP28
FP27
2
1
6
7
8
9
10
11
12
13
14
20
35
1
4
15
17
18
16
19
44
14
13
12
57 43 42 39 38 7645 11 43 42 41 40 39 38 37 36 5678910
38 39 40 41
59
PGA2
–
+
PGA1
–
+ADC
ADC
TEMP
ADC
VSW
ADC
PROGRAM MEMORY
62kB FLASH
POWER SUPPLY
CONTROL AND
MONITORING
USER RAM
256 BYT E S
USER X RAM
2kB
TEMP
SENSOR
BATTERY
ADC
SPI/I2C
SERIAL
INTERFACE
3 × 16-BI T
COUNTER
TIMERS
108-SEGMENT
LCD DRIVER
WATCHDOG
TIMER
DOWNLOADER
DEBUGGER
PLL
1-PIN
EMULATOR
LDO
EA
UART
TIMER
POR
07411-001
Figure 2. ADE5566/ADE5569 Functional Block Diagram
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 7 of 156
SPECIFICATIONS
VDD = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTALx = 32.768 kHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
ENERGY METERING
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
MEASUREMENT ACCURACY1
Phase Error Between Channels
PF = 0.8 Capacitive ±0.05 Degrees Phase lead: 37°
PF = 0.5 Inductive ±0.05 Degrees Phase lag: 60°
Active Energy Measurement Error2 0.1 % of reading Over a dynamic range of 1000 to 1 at 25°C
AC Power Supply Rejection2 VDD = 3.3 V + 100 mV rms/120 Hz
Output Frequency Variation 0.01 % IPx = VP = ±100 mV rms
DC Power Supply Rejection2 VDD = 3.3 V ± 117 mV dc
Output Frequency Variation
0.01
%
Active Energy Measurement Bandwidth1 8 kHz
Reactive Energy Measurement Error2 0.5 % of reading Over a dynamic range of 1000 to 1 at 25°C
Vrms Measurement Error2 0.5 % of reading Over a dynamic range of 100 to 1 at 25°C
Vrms Measurement Bandwidth1 63.7 Hz Fundamental only, mean absolute
measurement
Irms Measurement Error2 0.5 % of reading Over a dynamic range of 500 to 1 at 25°C
Irms Measurement Bandwidth1 3.9 kHz
ANALOG INPUTS
Maximum Signal Levels
±500
mV peak
V
P
− V
N
differential input
ADE5166/ADE5169 ±500 mV peak IPA − IN and IPB − IN differential inputs
ADE5566/ADE5569 ±500 mV peak IP − IN
Input Impedance (DC) 770 kΩ
ADC Offset Error2 ±10 mV PGA1 = PGA2 = 1
±1
mV
PGA1 = 16
Gain Error2
Current Channel ±3 % IPA = IPB = 0.5 V dc or IP = 0.5 V dc
Voltage Channel ±3 % VP − VN = 0.5 V dc
Gain Error Match ±0.2 %
CF1 AND CF2 PULSE OUTPUT
Maximum Output Frequency 21.6 kHz VP − VN = 500 mV peak; IPA − IN = 500 mV for
the ADE5166/ADE5169; IP − IN = 500 mV for
the ADE5566/ADE5569
Duty Cycle 50 % If the CF1 or CF2 frequency > 5.55 Hz
Active High Pulse Width 90 ms If the CF1 or CF2 frequency < 5.55 Hz
FAULT DETECTION3
Fault Detection Threshold
Inactive Input ≠ Active Input 6.25 % of active IPA or IPB active
Input Swap Threshold
Inactive Input > Active Input 6.25 % of active IPA or IPB active
Accuracy Fault Mode Operation
I
PA
Active, I
PB
= AGND
0.1
% of reading
Over a dynamic range of 500 to 1
IPB Active, IPA = AGND 0.1 % of reading Over a dynamic range of 500 to 1
Fault Detection Delay 3 Seconds
Swap Delay 3 Seconds
1 These specifications are not production tested but are guaranteed by design and/or characterization data on production release.
2 See the Terminology section for definition.
3 Available only in the ADE5166/ADE5169.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 8 of 156
ANALOG PERIPHERALS
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
INTERNAL ADCs (BATTERY, TEMPERATURE, V
DCIN
)
Power Supply Operating Range 2.4 3.7 V Measured on VSWOUT
No Missing Codes1 8 Bits
Conversion Delay2 38 µs
ADC Gain
VDCIN Measurement 15.3 mV/LSB
VBAT Measurement 14.6 mV/LSB
Temperature Measurement 0.83 °C/LSB
ADC Offset
VDCIN Measurement at 3 V 200 LSB
VBAT Measurement at 3.7 V 246 LSB
Temperature Measurement at 25°C 123 LSB
VDCIN Analog Input
Maximum Signal Levels 0 3.3 V
Input Impedance (DC) 1 MΩ
Low VDCIN Detection Threshold 1.09 1.2 1.27 V
POWER-ON RESET (POR)
VDD POR
Detection Threshold 2.5 2.95 V
POR Active Timeout Period 33 ms
VSWOUT POR
Detection Threshold 1.8 2.2 V
POR Active Timeout Period 20 ms
VINTD POR
Detection Threshold 2.0 2.25 V
POR Active Timeout Period 16 ms
VINTA POR
Detection Threshold 2.0 2.25 V
POR Active Timeout Period 120 ms
BATTERY SWITCHOVER
Voltage Operating Range (VSWOUT) 2.4 3.7 V
VDD to VBAT Switching
Switching Threshold (VDD) 2.5 2.95 V
Switching Delay 10 ns When VDD to VBAT switch is activated by VDD
30 ms When VDD to VBAT switch is activated by VDCIN
VBAT to VDD Switching
Switching Threshold (VDD) 2.5 2.95 V
Switching Delay 30 ms Based on VDD > 2.75 V
VSWOUT to VB AT Leakage Current 10 nA VBAT = 0 V, VSWOUT = 3.43 V, TA = 25°C
LCD, CHARGE PUMP ACTIVE
Charge Pump Capacitance Between
LCDVP1 and LCDVP2
100 nF
LCDVA, LCDVB, LCDVC Decoupling Capacitance
470
nF
LCDVA 0 1.9 V
LCDVB 0 3.8 V 1/3 bias mode
LCDVC 0 5.8 V 1/3 bias mode
V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 µA
V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 µA
V3 Segment Line Voltage LCDVC − 0.1 LCDVC V Current on segment line = −2 µA
DC Voltage Across Segment and COMx Pin 50 mV LCDVC − LCDVB, LCDVC − LCDVA, or
LCDVB − LCDVA
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 9 of 156
Parameter Min Typ Max Unit Test Conditions/Comments
LCD, RESISTOR LADDER ACTIVE
Leakage Current ±20 nA 1/2 and 1/3 bias modes, no load
V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 µA
V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 µA
V3 Segment Line Voltage
LCDVC − 0.1
LCDVC
V
Current on segment line = −2 µA
ON-CHIP REFERENCE Nominal 1.2035 V
Reference Error −2.2 +2.2 mV TA = 25°C, fCORE = 1.024 MHz
Power Supply Rejection 80 dB
Temperature Coefficient1 10 50 ppm/°C fCORE = 1.024 MHz
1 These specifications are not production tested but are guaranteed by design and/or characterization data on production release.
2 Delay between ADC conversion request and interrupt set.
DIGITAL INTERFACE
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS1
All Inputs Except XTAL1, XTAL2, BCTRL,
INT0, INT1, RESET
Input High Voltage, VINH 2.0 V
Input Low Voltage, VINL 0.8 V
BCTRL, INT0, INT1, RESET
Input High Voltage, VINH 1.3 V
Input Low Voltage, VINL 0.8 V
Input Currents
RESET
100
nA
RESET
= V
SWOUT
= 3.3 V
Port 0, Port 1, Port 2 ±100 nA Internal pull-up disabled, input = 0 V or
VSWOUT
−3.75 −8.5 µA Internal pull-up enabled, input = 0 V,
VSWOUT = 3.3 V
Input Capacitance 10 pF All digital inputs
FLASH MEMORY
Endurance2 20,000 Cycles At 25°C
Data Retention3 20 Years TJ = 85°C
CRYSTAL OSCILLATOR4
Crystal Equivalent Series Resistance 30 50 kΩ
Crystal Frequency 32 32.768 33.5 kHz
XTAL1 Input Capacitance 12 pF
XTAL2 Output Capacitance 12 pF
MCU CLOCK RATE (fCORE) 4.096 MHz Crystal = 32.768 kHz and CD bits = 0b000
32 kHz Crystal = 32.768 kHz and CD bits = 0b111
LOGIC OUTPUTS
Output High Voltage, VOH 2.4 V VDD = 3.3 V ± 5%
ISOURCE 80 µA
Output Low Voltage, VOL5 0.4 V VDD = 3.3 V ± 5%
ISINK 2 mA
START-UP TIME6
PSM0 Power-On Time 880 ms VDD at 2.75 V to PSM0 code execution
From Power Saving Mode 1 (PSM1)
PSM1 to PSM0 130 ms VDD at 2.75 V to PSM0 code execution
From Power Saving Mode 2 (PSM2)
PSM2 to PSM1 48 ms Wake-up event to PSM1 code execution
PSM2 to PSM0 186 ms VDD at 2.75 V to PSM0 code execution
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 10 of 156
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY INPUTS
VDD 3.13 3.3 3.46 V
VBAT 2.4 3.3 3.7 V
INTERNAL POWER SUPPLY SWITCH (VSWOUT)
VBAT to VSWOUT On Resistance 12 Ω VBAT = 2.4 V
VDD to VSWOUT On Resistance 9 Ω VDD = 3.13 V
VBAT to/from VDD Switching Open Time 40 ns
BCTRL State Change and Switch Delay 18 µs
VSWOUT Output Current Drive 6 mA
POWER SUPPLY OUTPUTS
V
INTA
2.3
2.70
V
VINTD 2.3 2.70 V
VINTA Power Supply Rejection 60 dB
VINTD Power Supply Rejection 50 dB
POWER SUPPLY CURRENTS
Current in Normal Mode (PSM0) 4.4 5.3 mA fCORE = 4.096 MHz, LCD and meter active
2.2 mA fCORE = 1.024 MHz, LCD and meter active
1.6 mA fCORE = 32.768 kHz, LCD and meter active
3 3.9 mA fCORE = 4.096 MHz; metering ADC and DSP,
powered down
Current in Battery Mode (PSM1) 3.3 5.05 mA fCORE = 4.096 MHz, LCD active, VB AT = 3.7 V
1 mA fCORE = 1.024 MHz, LCD active
Current in Sleep Mode (PSM2) 38 µA LCD active with charge pump at 3.3 V + RTC,
VBAT = 3.3 V
1.7 µA RTC only, TA = 25°C, VB AT = 3.3 V
1 Specifications guaranteed by design.
2 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
3 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
4 Recommended crystal specifications.
5 Test carried out with all the I/Os set to a low output level.
6 Delay between power supply valid and execution of first instruction by 8052 core.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 11 of 156
TIMING SPECIFICATIONS
AC inputs during testing were driven at VSWOUT − 0.5 V for Logic 1
and at 0.45 V for Logic 0. Timing measurements were made at VIH
minimum for Logic 1 and at VIL maximum for Logic 0, as shown in
Figure 3.
For timing purposes, a port pin is no longer floating when
a 100 mV change from load voltage occurs. A port pin begins
to float when a 100 mV change from the loaded VOH/VOL level
occurs, as shown in Figure 3.
CLOAD = 80 pF for all outputs, unless otherwise noted. VDD = 2.7 V
to 3.6 V; all specifications TMIN to TMAX, unless otherwise noted.
VSWOUT – 0. 5V
0.45V
0.2VSWOUT + 0. 9V
TEST POINTS
0.2VSWOUT – 0.1V
VLOAD – 0.1V
VLOADVLOAD + 0. 1V
TIMING
REFERENCE
POINTS
VLOAD – 0.1VVLOAD
VLOAD – 0.1V
07411-002
Figure 3. Timing Waveform Characteristics
Table 5. Clock Input (External Clock Driven XTAL1) Parameters
32.768 kHz External Crystal
Parameter Description Min Typ Max Unit
tCK XTAL1 period 30.52 µs
tCKL XTAL1 width low 6.26 µs
tCKH XTAL1 width high 6.26 µs
t
CKR
XTAL1 rise time
9
ns
tCKF XTAL1 fall time 9 ns
1/tCORE Core clock frequency1 1.024 MHz
1 The ADE5166/ADE5169/ADE5566/ADE5569 internal PLL locks onto a multiple (512×) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal
clock for the system. The core can operate at this frequency or at a binary submultiple defined by the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26).
Table 6. I2C-Compatible Interface Timing Parameters (400 kHz)
Parameter Description Typ Unit
tBUF Bus-free time between stop condition and start condition 1.3 µs
tL SCLK low pulse width 1.36 µs
tH SCLK high pulse width 1.14 µs
tSHD Start condition hold time 251.35 µs
tDSU Data setup time 740 ns
tDHD Data hold time 400 ns
tRSU Setup time for repeated start 12.5 ns
tPSU Stop condition setup time 400 ns
tR Rise time of both SCLK and SDATA 200 ns
tF Fall time of both SCLK and SDATA 300 ns
tSUP1 Pulse width of spike suppressed 50 ns
1 Input filtering on both the SCLK and SDATA suppresses noise spikes of <50 ns.
MSB
tBUF
SDATA (I/O)
SCL K ( I)
STOP
CONDITION START
CONDITION REPEATED
START
LSB ACK MSB
12 TO 7 8 9 1
S(R)
PS
tPSU
tDSU
tSHD
tDHD tDSU tDHD
tSUP
tH
tSUP
tL
tRSU tR
tR
tF
tF
07411-003
Figure 4. I2C-Compatible Interface Timing
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 12 of 156
Table 7. SPI Master Mode Timing Parameters (SPICPHA = 1)
Parameter Description Min Typ Max Unit
tSL SCLK low pulse width 2SPIR × tCORE1 ns
tSH SCLK high pulse width 2SPIR × tCORE1 ns
tDAV Data output valid after SCLK edge 3 × tCORE1 ns
tDSU Data input setup time before SCLK edge 0 ns
tDHD Data input hold time after SCLK edge tCORE1 ns
tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
tSF SCLK fall time 19 ns
1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz.
SCLK
(SPICPOL = 0)
t
DSU
SCLK
(SPICPOL = 1)
MOSI
MISO
MSB LSB
LSB IN
BITS[6:1]
BITS[6:1]
t
DHD
t
DR
t
DAV
t
DF
t
SH
t
SL
t
SR
t
SF
MSB IN
07411-004
Figure 5. SPI Master Mode Timing (SPICPHA = 1)
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 13 of 156
Table 8. SPI Master Mode Timing Parameters (SPICPHA = 0)
Parameter Description Min Typ Max Unit
tSL SCLK low pulse width 2SPIR × tCORE1 (SPIR + 1) × tCORE1 ns
tSH SCLK high pulse width 2SPIR × tCORE1 (SPIR + 1) × tCORE1 ns
tDAV Data output valid after SCLK edge 3 × tCORE1 ns
tDOSU Data output setup before SCLK edge 75 ns
tDSU Data input setup time before SCLK edge 0 ns
tDHD Data input hold time after SCLK edge tCORE1 ns
tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
t
SF
SCLK fall time
19
ns
1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz.
SCLK
(SPICPOL = 0)
t
DSU
SCLK
(SPICPOL = 1)
MOSI
MISO
MSB LSB
LSB IN
BITS[6:1]
BITS[6:1]
tDHD
tDR
tDAV
tDF
tDOSU
tSH tSL tSR tSF
MSB IN
07411-005
Figure 6. SPI Master Mode Timing (SPICPHA = 0)
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 14 of 156
Table 9. SPI Slave Mode Timing Parameters (SPICPHA = 1)
Parameter Description Min Typ Max Unit
tSS SS to SCLK edge 145 ns
tSL SCLK low pulse width 6 × tCORE1 ns
tSH SCLK high pulse width 6 × tCORE1 ns
tDAV Data output valid after SCLK edge 25 ns
tDSU Data input setup time before SCLK edge 0 ns
tDHD Data input hold time after SCLK edge 2 × tCORE1 + 0.5 µs
tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
tSF SCLK fall time 19 ns
tSFS SS high after SCLK edge 0 ns
1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz.
MSB
MOSI BITS[6:1]
tDHD
tDSU
MSB IN LSB IN
BITS[6:1] LSB
tDR
tDF
t
DAV
MISO
t
SL
t
SH
t
SR
t
SF
t
SFS
t
SS
SCLK
(SPICPOL = 1)
SCLK
(SPICPOL = 0)
SS
07411-006
Figure 7. SPI Slave Mode Timing (SPICPHA = 1)
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 15 of 156
Table 10. SPI Slave Mode Timing Parameters (SPICPHA = 0)
Parameter Description Min Typ Max Unit
tSS SS to SCLK edge 145 ns
tSL SCLK low pulse width 6 × tCORE1 ns
tSH SCLK high pulse width 6 × tCORE1 ns
tDAV Data output valid after SCLK edge 25 ns
tDSU Data input setup time before SCLK edge 0 ns
tDHD Data input hold time after SCLK edge 2 × tCORE1+ 0.5 µs
tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
tSF SCLK fall time 19 ns
tDOSS Data output valid after SS edge 0 ns
tSFS SS high after SCLK edge 0 ns
1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz.
MSB
MOSI BITS[6:1]
t
DHD
t
DSU
LSB IN
BITS[6:1] LSB
t
DR
t
DF
t
DAV
MISO
t
SR
t
SF
t
SFS
t
SS
SCLK
(SPICPOL = 1)
SCLK
(SPICPOL = 0)
SS
t
SH
t
SL
t
DOSS
MSB IN
07411-007
Figure 8. SPI Slave Mode Timing (SPICPHA = 0)
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 16 of 156
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 11.
Parameter Rating
VDD to DGND −0.3 V to +3.7 V
VBAT to DGND −0.3 V to +3.7 V
VDCIN to DGND −0.3 V to VSWOUT + 0.3 V
Input LCD Voltage to AGND, LCDVA,
LCDVB, LCDVC1
−0.3 V to VSWOUT + 0.3 V
Analog Input Voltage to AGND, VP, VN,
IP/IPA, IPB, and IN
−2 V to +2 V
Digital Input Voltage to DGND −0.3 V to VSWOUT + 0.3 V
Digital Output Voltage to DGND −0.3 V to VSWOUT + 0.3 V
Operating Temperature Range (Industrial) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
64-Lead LQFP, Power Dissipation
Lead Temperature (Soldering, 30 sec) 300°C
1 When used with external resistor divider.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case condition, that is, a device
soldered in a circuit board for surface-mount packages.
Table 12. Thermal Resistance
Package Type θJA θJC Unit
64-Lead LQFP 60 20.5 °C/W
ESD CAUTION
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 17 of 156
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
64
VDCIN
63
DGND
62
VINTD
61
VSWOUT
60
VDD
59
VINTA
58
VBAT
57
REFIN/OUT
56
IPB
55
RESET
54
AGND
53
IN
52
IPA
51
EA
50
VN
49
VP
47 XTAL1
46 XTAL2
45 BCTRL/INT1/P0.0
42 P0.3/CF2
43 P0.2/CF1
44 SDEN/P2.3/TxD2
48 INT0
41 P0.4/MOSI/SDATA
40 P0.5/MISO/ZX
39 P0.6/SCLK/T0
37 P1.0/RxD
36 P1.1/TxD
35 FP0
34 FP1
33 FP2
38 P0.7/SS/T1/RxD2
2
COM2/FP28
3
COM1
4
COM0
7
P1.4/T2/FP23
6
P1.3/T2EX/FP24
5
P1.2/FP25/ZX
1
COM3/FP27
8
P1.5/FP22
9
P1.6/FP21
10
P1.7/FP20
12
P2.0/FP18
13
P2.1/FP17
14
P2.2/FP16
15
LCDVC
16
LCDVP2
11
P0.1/FP19
17
LCDVB
18
LCDVA
19
LCDVP1
20
FP15
21
FP14
22
FP13
23
FP12
24
FP11
25
FP10
26
FP9
27
FP8
28
FP7
29
FP6
30
FP5
31
FP4
32
FP3
PIN 1
ADE5166/ADE5169
TOP VIEW
(No t t o Scal e)
07411-010
Figure 9. ADE5166/ADE5169 Pin Configuration
Table 13. Pin Function Descriptions
Pin No. Mnemonic Description
1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane.
2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane.
3 COM1 Common Output 1. COM1 is used for the LCD backplane.
4
COM0
Common Output 0. COM0 is used for the LCD backplane.
5 P1.2/FP25/ZX General-Purpose Digital I/O Port 1.2/LCD Segment Output 25/ZX Output.
6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24.
7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23.
8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22.
9
P1.6/FP21
General-Purpose Digital I/O Port 1.6/LCD Segment Output 21.
10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20.
11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19.
12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18.
13 P2.1/FP17 General-Purpose Digital I/O Port 2.1/LCD Segment Output 17.
14 P2.2/FP16 General-Purpose Digital I/O Port 2.2/LCD Segment Output 16.
15 LCDVC Output Port for LCD Levels. This pin should be decoupled with a 470 nF capacitor.
16 LCDVP2 Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP1 for the internal LCD
charge pump device.
17, 18 LCDVB, LCDVA Output Ports for LCD Levels. These pins should be decoupled with a 470 nF capacitor.
19 LCDVP1 Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP2 for the internal LCD
charge pump device.
20 to 35 FP15 to FP0 LCD Segment Output 15 to LCD Segment Output 0.
36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous).
37 P1.0/RxD General-Purpose Digital I/O Port 1.0/Receive Data Input (Asynchronous).
38 P0.7/SS/T1/RxD2 General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input/Receive Data
Input 2 (Asynchronous).
39
P0.6/SCLK/T0
General-Purpose Digital I/O Port 0.6/Clock Output for I
2
C or SPI Port/Timer 0 Input.
40 P0.5/MISO/ZX General-Purpose Digital I/O Port 0.5/Data Input for SPI Port/ZX Output.
41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 18 of 156
Pin No. Mnemonic Description
42 P0.3/CF2 General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, or apparent power or Irms information.
43 P0.2/CF1 General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1. The CF1 logic output gives
instantaneous active, reactive, or apparent power or Irms information.
44
SDEN
/P2.3/TxD2
Serial Download Mode Enable/General-Purpose Digital Output Port 2.3/Transmitter Data Output 2
(Asynchronous). This pin is used to enable serial download mode through a resistor when pulled low on
power-up or reset. On reset, this pin momentarily becomes an input, and the status of the pin is sampled.
If there is no pull-down resistor in place, the pin momentarily goes high, and then user code is executed.
If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains
low during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3)
or as Transmitter Data Output 2 (asynchronous).
45 BCTRL/INT1/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic
input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left
open, the connection between VDD or VBAT and VSWOUT is selected internally.
46 XTAL2 A crystal can be connected across this pin and XTAL1 (see the XTAL1 pin description) to provide a clock
source. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate
oscillator circuit. An internal 6 pF capacitor is connected to this pin.
47 XTAL1 An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected
across XTAL1 and XTAL2 to provide a clock source. The clock frequency for specified operation is 32.768 kHz.
An internal 6 pF capacitor is connected to this pin.
48 INT0 External Interrupt Input 0.
49, 50
V
P
, V
N
Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500 mV for specified operation. This channel also has an internal PGA.
51 EA Input for Emulation. When held high, this input enables the device to fetch code from internal program
memory locations. The ADE5166/ADE5169 do not support external code memory. This pin should not be left
floating.
52, 53 IPA, IN Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500 mV for specified operation. This channel also has an internal PGA.
54 AGND Ground Reference for Analog Circuitry.
55 IPB Analog Input for Second Current Channel. This input is fully differential with a maximum differential level of
±500 mV, referred to IN for specified operation. This channel also has an internal PGA.
56 RESET Reset Input, Active Low.
57
REF
IN/OUT
Access to On-Chip Voltage Reference. The on-chip reference has a nominal value of 1.2 V ± 0.1% and a typical
temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled with a 1 µF capacitor in
parallel with a ceramic 100 nF capacitor.
58 VBAT Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to VDD when
the battery is selected as the power supply.
59 VINTA Access to On-Chip 2.5 V Analog LDO. No external active circuitry should be connected to this pin. This pin
should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
60 VDD 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is
selected as the power supply. This pin should be decoupled with a 10 µF capacitor in parallel with a ceramic
100 nF capacitor.
61 VSWOUT 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and the internal circuitry. This
pin should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
62 VINTD Access to On-Chip 2.5 V Digital LDO. No external active circuitry should be connected to this pin. This pin
should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
63 DGND Ground Reference for Digital Circuitry.
64 VDCIN Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to
AGND. This pin is used to monitor the preregulated dc voltage.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 19 of 156
64
VDCIN
63
DGND
62
VINTD
61
VSWOUT
60
VDD
59
VINTA
58
VBAT
57
REFIN/OUT
56 55
RESET
54
AGND
53
IN
52 51
EA
50
VN
49
VP
47 XTAL1
46 XTAL2
45 BCTRL/INT1/P0.0
42 P0.3/CF2
43 P0.2/CF1
44 SDEN/P2.3/TxD2
48 INT0
41 P0.4/MOSI/SDATA
40 P0.5/MISO/ZX
39 P0.6/SCLK/T0
37 P1.0/RxD
36 P1.1/TxD
35 FP0
34 FP1
33 FP2
38 P0.7/SS/T1/RxD2
2
COM2/FP28
3
COM1
4
COM0
7
P1.4/T2/FP23
6
P1.3/T2EX/FP24
5
P1.2/FP25/ZX
1
COM3/FP27
8
P1.5/FP22
9
P1.6/FP21
10
P1.7/FP20
12
P2.0/FP18
13
P2.1/FP17
14
P2.2/FP16
15
LCDVC
16
LCDVP2
11
P0.1/FP19
17
LCDVB
18
LCDVA
19
LCDVP1
20
FP15
21
FP14
22
FP13
23
FP12
24
FP11
25
FP10
26
FP9
27
FP8
28
FP7
29
FP6
30
FP5
31
FP4
32
FP3
PIN 1
ADE5566/ADE5569
TOP VIEW
(No t t o Scal e)
07411-028
IP
FP26
Figure 10. ADE5566/ADE5569 Pin Configuration
Table 14. Pin Function Descriptions
Pin No. Mnemonic Description
1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane.
2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane.
3 COM1 Common Output 1. COM1 is used for the LCD backplane.
4 COM0 Common Output 0. COM0 is used for the LCD backplane.
5
P1.2/FP25/ZX
General-Purpose Digital I/O Port 1.2/LCD Segment Output 25/ZX Output.
6
P1.3/T2EX/FP24
General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24.
7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23.
8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22.
9 P1.6/FP21 General-Purpose Digital I/O Port 1.6/LCD Segment Output 21.
10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20.
11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19.
12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18.
13 P2.1/FP17 General-Purpose Digital I/O Port 2.1/LCD Segment Output 17.
14 P2.2/FP16 General-Purpose Digital I/O Port 2.2/LCD Segment Output 16.
15 LCDVC Output Port for LCD Levels. This pin should be decoupled with a 470 nF capacitor.
16 LCDVP2 Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP1 for the internal LCD
charge pump device.
17, 18 LCDVB, LCDVA Output Ports for LCD Levels. These pins should be decoupled with a 470 nF capacitor.
19 LCDVP1 Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP2 for the internal LCD
charge pump device.
20 to 35 FP15 to FP0 LCD Segment Output 15 to LCD Segment Output 0.
36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous).
37
P1.0/RxD
General-Purpose Digital I/O Port 1.0/Receive Data Input (Asynchronous).
38 P0.7/SS/T1/RxD2 General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input/Receive Data
Input 2 (Asynchronous).
39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input.
40 P0.5/MISO/ZX General-Purpose Digital I/O Port 0.5/Data Input for SPI Port/ZX Output.
41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line.
42 P0.3/CF2 General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, or apparent power or Irms information.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 20 of 156
Pin No. Mnemonic Description
43 P0.2/CF1 General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1. The CF1 logic output gives
instantaneous active, reactive, or apparent power or Irms information.
44 SDEN/P2.3/TxD2 Serial Download Mode Enable/General-Purpose Digital Output Port 2.3/Transmitter Data Output 2
(Asynchronous). This pin is used to enable serial download mode through a resistor when pulled low on
power-up or reset. On reset, this pin momentarily becomes an input, and the status of the pin is sampled.
If there is no pull-down resistor in place, the pin momentarily goes high, and then user code is executed.
If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin
remains low during the internal program execution. After reset, this pin can be used as a digital output port
pin (P2.3) or as Transmitter Data Output 2 (asynchronous).
45 BCTRL/INT1/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic
input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left
open, the connection between VDD or VBAT and VSWOUT is selected internally.
46 XTAL2 A crystal can be connected across this pin and XTAL1 (see the XTAL1 pin description) to provide a clock
source. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate
oscillator circuit. An internal 6 pF capacitor is connected to this pin.
47 XTAL1 An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected
across XTAL1 and XTAL2 to provide a clock source. The clock frequency for specified operation is 32.768 kHz.
An internal 6 pF capacitor is connected to this pin.
48 INT0 External Interrupt Input 0.
49, 50 VP, VN Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500 mV for specified operation. This channel also has an internal PGA.
51
EA
Input for Emulation. When held high, this input enables the device to fetch code from internal program
memory locations. The ADE5566/ADE5569 do not support external code memory. This pin should not be left
floating.
52, 53 IP, IN Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500 mV for specified operation. This channel also has an internal PGA.
54 AGND Ground Reference for Analog Circuitry.
55 FP26 LCD Segment Output 26.
56 RESET Reset Input, Active Low.
57 REFIN/OUT Access to On-Chip Voltage Reference. The on-chip reference has a nominal value of 1.2 V ± 0.1% and a typical
temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled with a 1 µF capacitor in
parallel with a ceramic 100 nF capacitor.
58
V
BAT
Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to V
DD
when
the battery is selected as the power supply.
59 VINTA Access to On-Chip 2.5 V Analog LDO. No external active circuitry should be connected to this pin. This pin
should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
60 VDD 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is
selected as the power supply. This pin should be decoupled with a 10 µF capacitor in parallel with a ceramic
100 nF capacitor.
61 VSWOUT 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and the internal circuitry. This
pin should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
62 VINTD Access to On-Chip 2.5 V Digital LDO. No external active circuitry should be connected to this pin. This pin
should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
63 DGND Ground Reference for Digital Circuitry.
64 VDCIN Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to
AGND. This pin is used to monitor the preregulated dc voltage.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 21 of 156
TYPICAL PERFORMANCE CHARACTERISTICS
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 110 100
MI D CLASS C
MI D CLASS C
–40°C; P F = 1
07411-126
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
+85° C; P F = 1
+25° C; P F = 1
GAIN = 1
INTEGRATOR OFF
INTERNAL RE FERE NCE
Figure 11. Active Energy Error as a Percentage of Reading (Gain = 1)
over Temperature with Internal Reference, Integrator Off
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0.1 110 100
MI D CLASS C
MI D CLASS C
–40°C; P F = 1
07411-127
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
+85° C; P F = 0. 5
+25° C; P F = 1
–40°C; P F = 0. 5
+85° C; P F = 1
+25° C; P F = 0. 5
GAIN = 1
INTEGRATOR OFF
INTERNAL RE FERE NCE
Figure 12. Active Energy Error as a Percentage of Reading (Gain = 1)
over Power Factor with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 110 100
–40°C; P F = 0
07411-128
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
+85° C; P F = 0
+25° C; P F = 0
GAIN = 1
INTEGRATOR OFF
INTERNAL RE FERE NCE
Figure 13. Reactive Energy Error as a Percentage of Reading (Gain = 1)
over Temperature with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 110 100
07411-129
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
GAIN = 1
INTEGRATOR OFF
INTERNAL RE FERE NCE
–40°C; P F = 0. 866 +85° C; P F = 0
+25° C; P F = 0. 866
–40°C; P F = 0
+25° C; P F = 0
Figure 14. Reactive Energy Error as a Percentage of Reading (Gain = 1)
over Power Factor with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 110 100
MI D CLASS C
MI D CLASS C
–40°C; P F = 1
07411-130
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
+85° C; P F = 1
+25° C; P F = 1
GAIN = 1
INTEGRATOR OFF
INTERNAL RE FERE NCE
Figure 15. Current RMS Error as a Percentage of Reading (Gain = 1)
over Temperature with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
0.1 110 100
MI D CLASS C
MI D CLASS C
07411-131
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
GAIN = 1
INTEGRATOR OFF
INTERNAL RE FERE NCE
–40°C; P F = 1
+85° C; P F = 0. 5
+25° C; P F = 1
–40°C; P F = 0. 5
+85° C; P F = 1
+25° C; P F = 0. 5
Figure 16. Current RMS Error as a Percentage of Reading (Gain = 1)
over Power Factor with Internal Reference, Integrator Off
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 22 of 156
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.1 110 100
07411-132
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
GAIN = 1
INTEGRATOR OFF
INTERNAL RE FERE NCE
VRMS; 3. 43V
VRMS; 3. 13V
IRMS; 3. 13V
IRMS; 3. 43V
VRMS; 3. 3V
IRMS; 3. 3V
Figure 17. Voltage and Current RMS Error as a Percentage of Reading
(Gain = 1) over Power Supply with Internal Reference
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
40 45 50 55 60 65 70
PF = 1
PF = 0.5
GAIN = 1
INTEGRATOR OFF
INTERNAL RE FERE NCE
07411-133
LINE F RE QUENCY ( Hz )
ERRO R ( % of Read in g)
MI D CLASS B
MI D CLASS B
Figure 18. Active Energy Error as a Percentage of Reading (Gain = 1)
over Frequency with Internal Reference, Integrator Off
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.1 110 100
07411-134
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
GAIN = 1
INTEGRATOR OFF
INTERNAL RE FERE NCE
VAR; 3.43V
W; 3.43V VAR; 3.3V
VAR; 3.13V
W; 3.13V
W; 3.3V
Figure 19. Active and Reactive Energy Error as a Percentage of Reading (Gain = 1)
over Power Supply with Internal Reference, Integrator Off
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0.1 110 100
MI D CLASS C
MI D CLASS C
07411-135
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
PF = +0.5
PF = +1
PF = –0.5
GAIN = 8
INTEGRATOR OFF
INTERNAL RE FERE NCE
Figure 20. Active Energy Error as a Percentage of Reading (Gain = 8)
over Power Factor with Internal Reference, Integrator Off
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0.1 110 100
07411-136
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
GAIN = 8
INTEGRATOR OFF
INTERNAL RE FERE NCE
PF = + 0.866
PF = 0
PF = –0.866
Figure 21. Reactive Energy Error as a Percentage of Reading (Gain = 8)
over Power Factor with Internal Reference, Integrator Off
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
0.1 110 100
MI D CLASS C
MI D CLASS C
07411-137
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
PF = +0.5
PF = +1
PF = –0.5
GAIN = 8
INTEGRATOR OFF
INTERNAL RE FERE NCE
Figure 22. Current RMS Error as a Percentage of Reading (Gain = 8)
over Power Factor with Internal Reference, Integrator Off
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 23 of 156
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
1.5
0.1 110 100
MI D CLASS C
MI D CLASS C
07411-138
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
GAIN = 16
INTEGRATOR OFF
INTERNAL RE FERE NCE
+25°C
;
PF = 1
–40°C
;
PF = 1
+85°C
;
PF = 1
Figure 23. Active Energy Error as a Percentage of Reading (Gain = 16)
over Temperature with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
1.5
0.1 110 100
MI D CLASS C
MI D CLASS C
07411-139
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
+25°C
;
PF = 1
+25°C
;
PF = 0.5
–40°C
;
PF = 0.5
–40°C
;
PF = 1
+85°C
;
PF = 0.5
GAIN = 16
INTEGRATOR OFF
INTERNAL RE FERE NCE
+85°C
;
PF = 1
Figure 24. Active Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator Off
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0.1 110 100
07411-140
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
GAIN = 16
INTEGRATOR OFF
INTERNAL RE FERE NCE
+85° C; P F = 0 –40°C; PF = 0
+25° C; P F = 0
Figure 25. Reactive Energy Error as a Percentage of Reading (Gain = 16)
over Temperature with Internal Reference, Integrator Off
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0.1 110 100
07411-141
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
GAIN = 16
INTEGRATOR OFF
INTERNAL RE FERE NCE
+85° C; P F = 0 –40°C; P F = 0
–40°C; P F = 0. 866
+25° C; P F = 0 +25° C; P F = 0. 866
+85° C; P F = 0. 866
Figure 26. Reactive Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
1.5
0.1 110 100
MI D CLASS C
MI D CLASS C
07411-142
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
GAIN = 16
INTEGRATOR OFF
INTERNAL RE FERE NCE
+25°C
;
PF = 1
+85°C
;
PF = 1
–40°C
;
PF = 1
Figure 27. Current RMS Error as a Percentage of Reading (Gain = 16)
over Temperature with Internal Reference, Integrator Off
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
1.5
0.1 110 100
MI D CLASS C
MI D CLASS C
07411-143
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
GAIN = 16
INTEGRATOR OFF
INTERNAL RE FERE NCE
+25°C
;
PF = 1
+85°C
;
PF = 1
+85°C
;
PF = 0.5
+25°C
;
PF = 0.5
–40°C
;
PF = 1
–40°C
;
PF = 0.5
Figure 28. Current RMS Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator Off
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 24 of 156
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
1.5
0.1 110 100
MI D CLASS C
MI D CLASS C
07411-144
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
GAIN = 16
INTEGRATOR ON
INTERNAL RE FERE NCE
+25° C; P F = 1
+25° C; P F = 0. 5
+85°C
;
PF = 1 +85°C
;
PF = 0.5
–40°C
;
PF = 1
–40°C
;
PF = 0.5
Figure 29. Active Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator On
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
0.1 110 100
07411-145
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
GAIN = 16
INTEGRATOR ON
INTERNAL RE FERE NCE
+85° C; P F = 0 –40°C; P F = 0
–40°C; P F = 0. 866
+25° C; P F = 0 +25°C; P F = 0. 866
+85° C; P F = 0. 866
Figure 30. Reactive Energy Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator On
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
2.0
1.5
0.1 110 100
MI D CLASS C
MI D CLASS C
07411-146
CURRENT CHANNE L (% o f Fu ll S cale)
ERRO R ( % of Read in g)
GAIN = 16
INTEGRATOR ON
INTERNAL RE FERE NCE
+25° C; P F = 0. 5
+25° C; P F = 1
+85°C
;
PF = 1
+85°C
;
PF = 0.5
–40°C; P F = 0. 5
–40°C; P F = 1
Figure 31. Current RMS Error as a Percentage of Reading (Gain = 16)
over Power Factor with Internal Reference, Integrator On
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 25 of 156
TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the
ADE5166/ADE5169/ADE5566/ADE5569 is defined by the fol-
lowing formula:
Measurement Error =
%100×
−
Energy
True
EnergyTrueRegisterEnergy
Phase Error Between Channels
The digital integrator and the high-pass filter (HPF) in the current
channel have a nonideal phase response. To offset this phase
response and equalize the phase response between channels,
two phase correction networks are placed in the current channel:
one for the digital integrator and the other for the HPF. The phase
correction networks correct the phase response of the corre-
sponding component and ensure a phase match between the
current channel and the voltage channel to within ±0.1° over a
range of 45 Hz to 65 Hz with the digital integrator off. With the
digital integrator on, the phase is corrected to within ±0.4° over
a range of 45 Hz to 65 Hz.
Power Supply Rejection (PSR)
PSR quantifies the ADE5166/ADE5169/ADE5566/ADE5569
measurement error as a percentage of reading when the power
supplies are varied. For the ac PSR measurement, a reading at
nominal supplies (3.3 V) is taken. A second reading is obtained
with the same input signal levels when an ac signal (100 mV rms/
120 Hz) is introduced onto the supplies. Any error introduced
by this ac signal is expressed as a percentage of the reading (see
the Measurement Error definition).
For the dc PSR measurement, a reading at nominal supplies
(3.3 V) is taken. A second reading is obtained with the same
input signal levels when the supplies are varied ±5%. Any error
introduced is expressed as a percentage of the reading.
ADC Offset Error
ADC offset error is the dc offset associated with the analog
inputs to the ADCs. It means that, with the analog inputs
connected to AGND, the ADCs still see a dc analog input
signal. The magnitude of the offset depends on the gain and
input range selection. However, when HPF1 is switched on,
the offset is removed from the current channel, and the power
calculation is not affected by this offset. The offsets can be
removed by performing an offset calibration (see the Analog
Inputs section).
Gain Error
Gain error is the difference between the measured ADC output
code (minus the offset) and the ideal output code (see the Current
Channel ADC section and the Voltage Channel ADC section).
It is measured for each of the gain settings on the current channel
(1, 2, 4, 8, and 16). The difference is expressed as a percentage
of the ideal code.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 26 of 156
SPECIAL FUNCTION REGISTER (SFR) MAPPING
Table 15. SFR Mapping
Mnemonic Address Description
INTPR 0xFF Interrupt pins configuration SFR
(see Table 17).
SCRATCH4 0xFE Scratch Pad 4 (see Table 25).
SCRATCH3 0xFD Scratch Pad 3 (see Table 24).
SCRATCH2 0xFC Scratch Pad 2 (see Table 23).
SCRATCH1 0xFB Scratch Pad 1 (see Table 22).
BATVTH 0xFA Battery detection threshold
(see Table 53).
STRBPER 0xF9 Peripheral ADC strobe period
(see Table 50).
IPSMF 0xF8 Power management interrupt flag
(see Table 18).
TEMPCAL
0xF7
RTC temperature compensation
(see Table 133).
RTCCOMP 0xF6 RTC nominal compensation
(see Table 132).
BATPR 0xF5 Battery switchover configuration
(see Table 19).
PERIPH 0xF4 Peripheral configuration
(see Table 20).
DIFFPROG 0xF3 Temperature and supply delta
(see Table 51).
B 0xF0 Auxiliary math (see Table 57).
VDCINADC 0xEF VDCINADC value (see Table 54).
SBAUD2 0xEE Enhanced Serial Baud Rate Control 2
(see Table 148).
LCDSEGE2 0xED LCD Segment Enable 2 (see Table 101).
IPSME 0xEC Power management interrupt enable
(see Table 21).
SBUF2 0xEB Serial Port 2 buffer (see Table 147).
SPISTAT 0xEA SPI interrupt status (see Table 155).
SPI2CSTAT 0xEA I2C interrupt status (see Table 159).
SPIMOD2 0xE9 SPI Configuration SFR 2 (see Table 154).
I2CADR 0xE9 I2C slave address (see Table 158).
SPIMOD1 0xE8 SPI Configuration SFR 1 (see Table 153).
I2CMOD
0xE8
I
2
C mode (see Table 157).
WAV2H 0xE7 Selection 2 sample MSB (see Table 31).
WAV2M 0xE6 Selection 2 sample middle byte
(see Table 31).
WAV2L 0xE5 Selection 2 sample LSB (see Table 31).
WAV1H 0xE4 Selection 1 sample MSB (see Table 31).
WAV1M 0xE3 Selection 1 sample middle byte
(see Table 31).
WAV1L 0xE2 Selection 1 sample LSB (see Table 31).
SCON2 0xE1 Serial Communications Control 2
(see Table 146).
ACC 0xE0 Accumulator (see Table 57).
BATADC 0xDF Battery ADC value (see Table 55).
MIRQSTH 0xDE Interrupt Status 3 (see Table 43).
MIRQSTM 0xDD Interrupt Status 2 (see Table 42).
MIRQSTL 0xDC Interrupt Status 1 (see Table 41).
MIRQENH 0xDB Interrupt Enable 3 (see Table 46).
MIRQENM 0xDA Interrupt Enable 2 (see Table 45).
Mnemonic Address Description
MIRQENL 0xD9 Interrupt Enable 1 (see Table 44).
ADCGO
0xD8
Start ADC measurement (see Table 52).
TEMPADC 0xD7 Temperature ADC value (see Table 56).
IRMSH 0xD6 Irms measurement MSB (see Table 31).
IRMSM 0xD5 Irms measurement middle byte
(see Table 31).
IRMSL 0xD4 Irms measurement LSB (see Table 31).
VRMSH
0xD3
V
rms
measurement MSB (see Table 31).
VRMSM 0xD2 Vrms measurement middle byte
(see Table 31).
VRMSL 0xD1 Vrms measurement LSB (see Table 31).
PSW 0xD0 Program status word (see Table 58).
TH2 0xCD Timer 2 high byte (see Table 120).
TL2 0xCC Timer 2 low byte (see Table 121).
RCAP2H 0xCB Timer 2 reload/capture high byte
(see Table 122).
RCAP2L 0xCA Timer 2 reload/capture low byte
(see Table 123).
T2CON 0xC8 Timer/Counter 2 control (see Table 115).
EADRH 0xC7 Flash high byte address (see Table 110).
EADRL 0xC6 Flash low byte address (see Table 109).
POWCON 0xC5 Power control (see Table 26).
KYREG 0xC1 Key (see Table 126).
WDCON 0xC0 Watchdog timer (see Table 88).
STCON
0xBF
Stack boundary (see Table 65).
EDATA 0xBC Flash data (see Table 108).
PROTKY 0xBB Flash protection key (see Table 107).
FLSHKY 0xBA Flash key (see Table 106).
ECON 0xB9 Flash control (see Table 105).
IP
0xB8
Interrupt priority (see Table 82).
SPH 0xB7 Stack pointer high (see Table 64).
PINMAP2 0xB4 Port 2 weak pull-up enable
(see Table 164).
PINMAP1 0xB3 Port 1 weak pull-up enable
(see Table 163).
PINMAP0 0xB2 Port 0 weak pull-up enable
(see Table 162).
LCDCONY 0xB1 LCD Configuration Y (see Table 94).
CFG 0xAF Configuration (see Table 66).
LCDDAT 0xAE LCD data (see Table 100).
LCDPTR 0xAC LCD pointer (see Table 99).
IEIP2 0xA9 Interrupt Enable and Priority 2
(see Table 83).
IE 0xA8 Interrupt enable (see Table 81).
DPCON 0xA7 Data pointer control (see Table 79).
RTCDAT 0xA4 RTC pointer data (see Table 131).
RTCPTR 0xA3 RTC pointer address (see Table 130).
TIMECON2 0xA2 RTC Configuration 2 (see Table 129).
TIMECON 0xA1 RTC configuration (see Table 128).
P2 0xA0 Port 2 (see Table 167).
EPCFG 0x9F Extended port configuration
(see Table 161).
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 27 of 156
Mnemonic Address Description
SBAUDT 0x9E Enhanced serial baud rate control
(see Table 142).
SBAUDF 0x9D UART timer fractional divider
(see Table 143).
LCDCONX
0x9C
LCD Configuration X (see Table 92).
SPI2CRx 0x9B SPI/I2C receive buffer (see Table 152).
SPI2CTx 0x9A SPI/I2C transmit buffer (see Table 151).
SBUF 0x99 Serial port buffer (see Table 141).
SCON 0x98 Serial communications control
(see Table 140).
LCDSEGE 0x97 LCD segment enable (see Table 98).
LCDCLK 0x96 LCD clock (see Table 95).
LCDCON 0x95 LCD configuration (see Table 91).
MDATH 0x94 Energy measurement pointer data MSB
(see Table 31).
MDATM
0x93
Energy measurement pointer data
middle byte (see Table 31).
MDATL 0x92 Energy measurement pointer data LSB
(see Table 31).
Mnemonic Address Description
MADDPT 0x91 Energy measurement pointer address
(see Table 30).
P1 0x90 Port 1 (see Table 166).
TH1 0x8D Timer 1 high byte (see Table 118).
TH0 0x8C Timer 0 high byte (see Table 116).
TL1 0x8B Timer 1 low byte (see Table 119).
TL0 0x8A Timer 0 low byte (see Table 117).
TMOD 0x89 Timer/Counter 0 and Timer/Counter 1
mode (see Table 113).
TCON 0x88 Timer/Counter 0 and Timer/Counter 1
control (see Table 114).
PCON 0x87 Program control (see Table 59).
DPH 0x83 Data pointer high (see Table 61).
DPL 0x82 Data pointer low (see Table 60).
SP 0x81 Stack pointer (see Table 63).
P0 0x80 Port 0 (see Table 165).
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 28 of 156
POWER MANAGEMENT
The ADE5166/ADE5169/ADE5566/ADE5569 have elaborate
power management circuitry that manages the regular power
supply to battery switchover and power supply failures.
The power management functionalities can be accessed directly
through the 8052 power management SFRs (see Table 16).
Table 16. Power Management SFRs
SFR Address R/W Mnemonic Description
0xEC R/W IPSME Power management interrupt enable (see Table 21).
0xF5 R/W BATPR Battery switchover configuration (see Table 19).
0xF8 R/W IPSMF Power management interrupt flag (see Table 18).
0xFF R/W INTPR Interrupt pins configuration (see Table 17).
0xF4 R/W PERIPH Peripheral configuration (see Table 20).
0xC5
R/W
POWCON
Power control (see Table 26).
0xFB R/W SCRATCH1 Scratch Pad 1 (see Table 22).
0xFC R/W SCRATCH2 Scratch Pad 2 (see Table 23).
0xFD R/W SCRATCH3 Scratch Pad 3 (see Table 24).
0xFE R/W SCRATCH4 Scratch Pad 4 (see Table 25).
POWER MANAGEMENT REGISTER DETAILS
Table 17. Interrupt Pins Configuration SFR (INTPR, Address 0xFF)
Bit Mnemonic Default Description
[7:4] Reserved N/A Reserved.
[3:1] INT1PRG 000 Controls the function of INT1.
INT1PRG Result
X001 GPIO enabled
X011 BCTRL enabled
01X
1
INT1
input disabled
11X1 INT1 input enabled
0 INT0PRG 0 Controls the function of INT0.
INT0PRG Result
0 INT0 input disabled
1 INT0 input enabled
1 X = don’t care
Writing to the Interrupt Pins Configuration SFR (INTPR, Address 0xFF)
To protect the RTC from runaway code, a key must be written to the key SFR (KYREG, Address 0xC1) to obtain write access to the
INTPR SFR. The KYREG SFR (see Table 126) should be set to 0xEA to unlock the INTPR SFR and reset to 0 after a timekeeping register is
written to. The RTC registers can be written using the following 8052 assembly code:
MOV KYREG, #0EAh
MOV INTPR, #080h
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 29 of 156
Table 18. Power Management Interrupt Flag SFR (IPSMF, Address 0xF8)
Bit Bit Address Mnemonic Default Description
7 0xFF FPSR 0 Power supply restored interrupt flag. Set when the VDD power supply has been restored.
This occurs when the source of VSWOUT changes from VBAT to VDD.
6 0xFE FPSM 0 PSM interrupt flag. Set when an enabled PSM interrupt condition occurs.
5 0xFD FSAG 0 Voltage SAG interrupt flag. Set when an ADE energy measurement SAG condition occurs.
4 0xFC Reserved 0 This bit must be kept at 0 for proper operation.
3 0xFB FVADC 0 VDCINADC monitor interrupt flag. Set when VDCIN changes by VDCIN_DIFF or when the VDCIN
measurement is ready.
2 0xFA FBAT 0 VBAT monitor interrupt flag. Set when VBAT falls below BATVTH or when VBAT measurement is
ready.
1
0xF9
FBSO
0
Battery switchover interrupt flag. Set when V
SWOUT
switches from V
DD
to V
BAT
.
0 0xF8 FVDCIN 0 VDCIN monitor interrupt flag. Set when VDCIN falls below 1.2 V.
Table 19. Battery Switchover Configuration SFR (BATPR, Address 0xF5)
Bit Mnemonic Default Description
[7:2] Reserved 0 These bits must be kept at 0 for proper operation.
[1:0] BATPRG 0 Control bits for battery switchover.
BATPRG Result
00 Battery switchover enabled on low VDD
01 Battery switchover enabled on low VDD and low VDCIN
1X1 Battery switchover disabled
1 X = don’t care.
Table 20. Peripheral Configuration SFR (PERIPH, Address 0xF4)
Bit Mnemonic Default Description
7 RX2FLAG 0 If set, indicates that an RxD2 edge event has triggered wake-up from PSM2.
6 VSWSOURCE 1 Indicates the power supply that is internally connected to VSWOUT.
0 = VSWOUT is connected to VBAT.
1 = V
SWOUT
is connected V
DD
.
5 VDD_OK 1 If set, indicates that the VDD power supply is ready for operation.
4 PLL_FLT 0 If set, indicates that a PLL fault occurred where the PLL lost lock. Set the PLLACK bit (Bit 7) in the start
ADC measurement SFR (ADCGO, Address 0xD8) to acknowledge the fault and clear the PLL_FLT bit
(see Table 52).
3 REF_BAT_EN 0 Set this bit to enable the internal voltage reference in PSM2 mode. This bit should be set if LCD is on
in the PSM1 and PSM2 modes.
2 Reserved 0 This bit must be kept at 0 for proper operation.
[1:0] RXPROG 0 Controls the function of the P0.7/SS/T1/RxD2 pin.
RXPROG Result
00 GPIO
01 RxD2 with wake-up disabled
11 RxD2 with wake-up enabled
Table 21. Power Management Interrupt Enable SFR (IPSME, Address 0xEC)
Bit Mnemonic Default Description
7 EPSR 0 Enables a PSM interrupt when the power supply restored interrupt flag (FPSR) is set.
6 Reserved 0 Reserved.
5 ESAG 0 Enables a PSM interrupt when the voltage SAG interrupt flag (FSAG) is set.
4 Reserved 0 This bit must be kept at 0 for proper operation.
3 EVADC 0 Enables a PSM interrupt when the VDCINADC monitor interrupt flag (FVADC) is set.
2 EBAT 0 Enables a PSM interrupt when the VBAT monitor interrupt flag (FBAT) is set.
1
EBSO
0
Enables a PSM interrupt when the battery switchover interrupt flag (FBSO) is set.
0 EVDCIN 0 Enables a PSM interrupt when the VDCIN monitor interrupt flag (FVDCIN) is set.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 30 of 156
Table 22. Scratch Pad 1 SFR (SCRATCH1, Address 0xFB)
Bit Mnemonic Default Description
[7:0] SCRATCH1 0 Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 23. Scratch Pad 2 SFR (SCRATCH2, Address 0xFC)
Bit Mnemonic Default Description
[7:0] SCRATCH2 0 Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 24. Scratch Pad 3 SFR (SCRATCH3, Address 0xFD)
Bit Mnemonic Default Description
[7:0] SCRATCH3 0 Value can be written/read in this register. This value is maintained in all the power saving modes.
Table 25. Scratch Pad 4 SFR (SCRATCH4, Address 0xFE)
Bit Mnemonic Default Description
[7:0] SCRATCH4 0 Value can be written/read in this register. This value is maintained in all the power saving modes.
Clearing the Scratch Pad Registers (SCRATCH1, Address 0xFB to SCRATCH4, Address 0xFE)
Note that these scratch pad registers are cleared only when the part loses VDD and VBAT.
Table 26. Power Control SFR (POWCON, Address 0xC5)
Bit Mnemonic Default Description
7 Reserved 1 Reserved.
6 METER_OFF 0 Set this bit to turn off the modulators and energy metering DSP circuitry to reduce power if metering
functions are not needed in PSM0 mode.
5 Reserved 0 This bit should be kept at 0 for proper operation.
4 COREOFF 0 Set this bit to shut down the core and enter PSM2 mode if in the PSM1 operating mode.
3 Reserved 0 Reserved.
[2:0]
CD
010
Controls the core clock frequency, f
CORE
. f
CORE
= 4.096 MHz/2
CD
.
CD Result (fCORE in MHz)
000 4.096
001 2.048
010 1.024
011 0.512
100 0.256
101 0.128
110 0.064
111 0.032
Writing to the Power Control SFR (POWCON, Address 0xC5)
Writing data to the power control SFR (POWCON, Address 0xC5) involves writing 0xA7 into the key SFR (KYREG, Address 0xC1),
which is described in Table 126, followed by a write to the POWCON SFR. For example,
MOV KYREG,#0A7h ;Write KYREG to 0xA7 to get write access to the POWCON SFR
MOV POWCON,#10h ;Shut down the core
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 31 of 156
POWER SUPPLY ARCHITECTURE
The ADE5166/ADE5169/ADE5566/ADE5569 have two power
supply inputs, VDD and VBAT. They require only a single 3.3 V power
supply at VDD for full operation. A battery backup, or secondary
power supply, with a maximum of 3.7 V can be connected to the
VBAT input. Internally, the ADE5166/ADE5169/ADE5566/
ADE5569 connect VDD or VBAT to VSWOUT, which is used to derive
power for the ADE5166/ADE5169/ADE5566/ADE5569 circuitr y.
The VSWOUT output pin reflects the voltage at the internal power
supply (VSWOUT) and has a maximum output current of 6 mA. This
pin can also be used to power a limited number of peripheral com-
ponents. The 2.5 V analog supply (VINTA) and the 2.5 V supply for
the core logic (VINTD) are derived by on-chip linear regulators from
VSWOUT. Figure 32 shows the ADE5166/ADE5169/ADE5566/
ADE5569 power supply architecture.
POWER SUPPLY
MANAGEMENT
LDO VINTD
LDO VINTA
ADC
VSW
ADC
SCRATCH PAD LCD RTC
TEMPERATURE ADC 3.3V
MCU
ADE
SPI/I2C
UART
2.5V
VDCIN VDD VBAT VSWOUT
BCTRL
07411-011
Figure 32. Power Supply Architecture
The ADE5166/ADE5169/ADE5566/ADE5569 provide automatic
battery switchover between VDD and VBAT based on the voltage
level detected at VDD or VDCIN. In addition, the BCTRL input can be
used to trigger a battery switchover. The conditions for switching
VSWOUT from VDD to VBAT and back to VDD are described in the
Battery Switchover section. VDCIN is an input pin that can be con-
nected to a dc signal of 0 V to 3.3 V. This input is intended for
power supply supervisory purposes and does not provide power
to the ADE5166/ADE5169/ADE5566/ADE5569 circuitry (see
the Battery Switchover section).
BATTERY SWITCHOVER
The ADE5166/ADE5169/ADE5566/ADE5569 monitor VDD,
VBAT, and VDCIN. Automatic battery switchover from VDD to VBAT
can be configured based on the status of the VDD, VDCIN, or BCTRL
pin. Battery switchover is enabled by default. Setting Bit 1 in the
battery switchover configuration SFR (BATPR, Address 0xF5)
disables battery switchover so that VDD is always connected to
VSWOUT (see Table 19). The source of VSWOUT is indicated by Bit 6
in the peripheral configuration SFR (PERIPH, Address 0xF4),
which is described in Table 20. Bit 6 is set when VSWOUT is con-
nected to VDD and cleared when VSWOUT is connected to VBAT.
The battery switchover functionality provided by the ADE5166/
ADE5169/ADE5566/ADE5569 allows a seamless transition from
VDD to VBAT. An automatic battery switchover option ensures a
stable power supply to the ADE5166/ADE5169/ADE5566/
ADE5569, as long as the external battery voltage is above 2.75 V.
It allows continuous code execution even while the internal power
supply is switching from VDD to VBAT and back. Note that the energy
metering ADCs are not available when VBAT is used for VSWOUT.
Power supply management (PSM) interrupts can be enabled to
indicate when battery switchover occurs and when the VDD power
supply is restored (see the Power Supply Management (PSM)
Interrupt section).
Switching from VDD to VBAT
The following three events switch the internal power supply
(VSWOUT) from VDD to VBAT:
• VDCIN < 1.2 V. When VDCIN falls below 1.2 V, V SWOUT switches
from VDD to VBAT. This event is enabled when the BATPRG
bits (Bits[1:0]) in the battery switchover configuration SFR
(BATPR, Address 0xF5) are set to 0b01.
• VDD < 2.75 V. When VDD falls below 2.75 V, VSWOUT switches
from VDD to VBAT. This event is enabled when the BATPRG
bits in the BATPR SFR are cleared.
• Falling edge on BCTRL. When the battery control pin,
BCTRL, goes low, VSWOUT switches from VDD to VBAT. This
external switchover signal can trigger a switchover to VBAT
at any time. Setting the INT1PRG bits (Bits[3:1]) to 0bX01 in
the interrupt pins configuration SFR (INTPR, Address 0xFF)
enables the BCTRL pin (see Table 17).
Switching from VBAT to VDD
To switch VSWOUT from VBAT to VDD, all of the following events
must be true:
• VDD > 2.75 V. VSWOUT switches back to VDD after VDD remains
above 2.75 V.
• VDCIN > 1.2 V and VDD > 2.75 V. If the low VDCIN condition
is enabled, VSWOUT switches to VDD after VDCIN remains
above 1.2 V and VDD remains above 2.75 V.
• Rising edge on BCTRL. If the battery control pin is enabled,
VSWOUT switches back to VDD after BCTRL is high, and the
first or second bullet point is satisfied.
POWER SUPPLY MANAGEMENT (PSM) INTERRUPT
The power supply management (PSM) interrupt alerts the 8052
core of power supply events. The PSM interrupt is disabled by
default. Setting Bit 1 (EPSM) in the Interrupt Enable and Priority 2
SFR (IEIP2, Address 0xA9) enables the PSM interrupt (see
Table 83).
The power management interrupt enable SFR (IPSME,
Address 0xEC) controls the events that result in a PSM interrupt
(see Table 21).
Figure 33 illustrates how the PSM interrupt vector is shared among
the PSM interrupt sources. The PSM interrupt flags are latched
and must be cleared by writing to the power management interrupt
flag SFR (IPSMF, Address 0xF8), as described in Table 18.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 32 of 156
EPSR
FPSR
ESAG
FSAG
EVADC
FVADC
EBAT
FBAT
EBSO
FBSO
EVDCIN
FVDCIN
FPSM
EPSM TRUE? PENDING PSM
INTERRUPT
EPSR RESERVED ESAG RESERVED EVADC EBAT EBSO EVDCIN
FPSR FPSM FSAG RESERVED FVADC FBAT FBSO FVDCIN
PS2 PTI ES2 PSI EADE ETI EPSM ESI
IPSME ADDR. 0xE C
IPSMF ADDR. 0xF8
IEIP2 ADDR. 0xA9
NOT INVOLVED IN PSM INTERRUPT SIGNAL CHAIN
07411-012
Figure 33. Power Supply Management Interrupt Sources
Battery Switchover and Power Supply Restored
PSM Interrupt
The ADE5166/ADE5169/ADE5566/ADE5569 can be configured
to generate a PSM interrupt when the source of VSWOUT changes
from VDD to VBAT, indicating battery switchover. Setting the EBSO
bit (Bit 1) in the power management interrupt enable SFR (IPSME,
Address 0xEC) enables this event to generate a PSM interrupt
(see Table 21).
The ADE5166/ADE5169/ADE5566/ADE5569 can also be con-
figured to generate an interrupt when the source of VSWOUT changes
from VBAT to VDD, indicating that the VDD power supply has been
restored. Setting the EPSR bit (Bit 7) in the power management
interrupt enable SFR (IPSME, Address 0xEC) enables this event to
generate a PSM interrupt.
The flags in the IPSMF SFR for these interrupts, FBSO (Bit 1)
and FPSR (Bit 7), are set regardless of whether the respective
enable bits are set. The battery switchover and power supply
restore event flags (FBSO and FPSR) are latched. These events
must be cleared by writing 0 to these bits. The VSWSOURCE bit
(Bit 6) in the peripheral configuration SFR (PERIPH, Address
0xF4) tracks the source of VSWOUT. The bit is set when VSWOUT is
connected to VDD and cleared when VSWOUT is connected to VBAT.
VDCINADC PSM Interrupt
The ADE5166/ADE5169/ADE5566/ADE5569 can be configured
to generate a PSM interrupt when VDCIN changes magnitude by
more than a configurable threshold. This threshold is set in the
temperature and supply delta SFR (DIFFPROG, Address 0xF3),
as described in Table 51. See the External Voltage Measurement
section for more information. Setting the EVADC bit (Bit 3) in
the power management interrupt enable SFR (IPSME, Address
0xEC) enables this event to generate a PSM interrupt.
The VDCIN voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to check
the change in VDCIN. Conversions can also be initiated by writing to
the start ADC measurement SFR (ADCGO, Address 0xD8), as
described in Table 52. The FVADC flag indicates when a VDCIN
measurement is ready. See the External Voltage Measurement
section for details on how VDCIN is measured.
VBAT Monitor PSM Interrupt
The VBAT voltage is measured using a dedicated ADC. These
measurements take place in the background at intervals to check
the change in VBAT. The FBAT bit (Bit 2 in the IPSMF SFR) is
set when the battery level is lower than the threshold set in the
battery detection threshold SFR (BATVTH, Address 0xFA),
described in Table 53; or when a new measurement is ready in
the battery ADC value SFR (BATADC, Address 0xDF), described
in Table 55. See the Battery Measurement section for more infor-
mation. Setting the EBAT bit (Bit 2) in the power management
interrupt enable SFR (IPSME, Address 0xEC) enables this event
to generate a PSM interrupt.
VDCIN Monitor PSM Interrupt
The VDCIN voltage is monitored by a comparator. The FVDCIN
bit (Bit 0) in the power management interrupt flag SFR (IPSMF,
Address 0xF8) is set when the VDCIN input level is lower than 1.2 V.
Setting the EVDCIN bit (Bit 0) in the IPSME SFR enables this
event to generate a PSM interrupt. This event, which is associated
with the SAG monitoring, can be used to detect that a power
supply (VDD) is compromised and to trigger further actions prior to
initiating a switch from VDD to VBAT.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 33 of 156
SAG Monitor PSM Interrupt
The ADE5166/ADE5169/ADE5566/ADE5569 energy measure-
ment DSP monitors the ac voltage input at the VP and VN input
pins. The SAGLVL register (Address 0x14) is used to set the thresh-
old for a line voltage SAG event. The FSAG bit (Bit 5) in the
power management interrupt flag SFR (IPSMF, Address 0xF8)
is set if the line voltage stays below the level set in the SAGLVL
register for the number of line cycles set in the SAGCYC register
(Address 0x13). See the Line Voltage SAG Detection section
for more information. Setting the ESAG bit (Bit 5) in the power
management interrupt enable SFR (IPSME, Address 0xEC)
enables this event to generate a PSM interrupt.
USING THE POWER SUPPLY FEATURES
In an energy meter application, the 3.3 V power supply (VDD)
is typically generated from the ac line voltage and regulated to
3.3 V by a voltage regulator IC. The preregulated dc voltage,
typically 5 V to 12 V, can be connected to VDCIN through a
resistor divider. A 3.6 V battery can be connected to VBAT.
Figure 34 shows how the ADE5166/ADE5169/ADE5566/
ADE5569 power supply inputs are set up in this application.
Figure 35 shows the sequence of events that occurs if the main
power supply generated by the PSU starts to fail in the power
meter application shown in Figure 34. The SAG detection can
provide the earliest warning of a potential problem on VDD.
When a SAG event occurs, user code can be configured to back
up data and prepare for battery switchover, if desired. The rela-
tive spacing of these interrupts depends on the design of the
power supply.
Figure 36 shows the sequence of events that occurs if the main
power supply starts to fail in the power meter application shown
in Figure 34, with battery switchover on low VDCIN or low VDD
enabled.
Finally, the transition between VDD and VBAT and the different
power supply modes (see the Operating Modes section) are
represented in Figure 37 and Figure 38.
VOLTAGE
SUPERVISORY POWER SUPPLY
MANAGEMENT
IPSMF SF R
(ADDR. 0xF8)
VSW
VBAT
VSWOUT
VDD
58
61
60
VOLTAGE
SUPERVISORY
64
VDCIN
3.3V
REGULATOR
5V T O 12V DC
PSU
50
SAG
DETECTION
49
45
BCTRL
VP
VN
(240V, 220 V, 110V TYP ICAL )
AC INP UT
07411-013
Figure 34. Power Supply Management for Energy Meter Application
Table 27. Power Supply Event Timing Operating Modes
Parameter Time Description
t1 10 ns min Time between when VDCIN goes below 1.2 V and when FVDCIN is raised.
t2 10 ns min Time between when VDD falls below 2.75 V and when battery switchover occurs.
t3 30 ms typ Time between when VDCIN falls below 1.2 V and when battery switchover occurs if VDCIN is enabled to cause
battery switchover.
t4 130 ms typ Time between when power supply restore conditions are met (VDCIN > 1.2 V and VDD > 2.75 V if the BATPRG
bits = 0b01, or VDD > 2.75 V if the BATPRG bits = 0b00) and when VSWOUT switches to VDD.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 34 of 156
t1
t2
V
DD
V
DCIN
V
P
– V
N
2.75V
1.2V
SAG LEVEL TRIP POINT
SAG CY C = 1
SAG EVENT
(F S AG = 1) V
DCIN
EVENT
(F V DCIN = 1)
IF SWITCHOVER ON LOW V
DD
IS E NABLED,
AUTOMAT IC BAT TERY S WI TCHOV E R OCCURS.
V
SWOUT
IS CONNECT E D TO V
BAT
.
BSO EVENT
(F BS O = 1)
07411-014
Figure 35. Power Supply Management Interrupts and Battery Switchover with Only VDD Enabled for Battery Switchover
t
1
t
3
V
DD
V
DCIN
V
P
– V
N
2.75V
1.2V
SAG LEVEL TRIP POINT
SAG CY C = 1
SAG EVENT
(F S AG = 1) V
DCIN
EVENT
(F V DCIN = 1) IF SWITCHOVER ON LOW V
DCIN
IS
ENABL E D, AUTOMATI C BATT E RY
SW ITCHOVE R OCCURS. V
SWOUT
IS CONNECT E D TO V
BAT
.
BSO EVENT
(F BS O = 1)
07411-015
Figure 36. Power Supply Management Interrupts and Battery Switchover with VDD or VDCIN Enabled for Battery Switchover
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 35 of 156
V
P
− V
N
SAG LEVEL
TRIP POINT
SAG EVENT
V
DCIN
1.2V
30ms 130ms
V
DCIN
EVENT
V
DCIN
EVENT
V
BAT
V
DD
2.75V
V
SWOUT
BATTERY SWITCH
ENABLED ON
LOW V
DCIN
V
SWOUT
BATTERY SWITCH
ENABLED ON
LOW V
DD
PSM0 PSM0
PSM0 PSM0
PSM1 OR PSM2
PSM1 OR PSM2
07411-016
Figure 37. Power Supply Management Transitions Between Modes
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 36 of 156
OPERATING MODES
PSM0 (NORMAL MODE)
In PSM0 mode, or normal operating mode, VSWOUT is connected to
VDD. All of the analog circuitry and digital circuitry powered by
VINTD and VINTA are enabled by default. In normal mode, the
default clock frequency, fCORE, which is established during a
power-on reset or software reset, is 1.024 MHz.
PSM1 (BATTERY MODE)
In PSM1 mode, or battery mode, VSWOUT is connected to VBAT.
In this operating mode, the 8052 core and all of the digital circuitry
are enabled by default. The analog circuitry for the ADE energy
metering DSP powered by VINTA is disabled. This analog circuitry
automatically restarts, and the switch to the VDD power supply
occurs when the VDD supply is greater than 2.75 V and the
PWRDN bit in the MODE1 register (Address 0x0B) is cleared
(see Table 33). The default fCORE for PSM1, established during
a power-on reset or software reset, is 1.024 MHz.
PSM2 (SLEEP MODE)
PSM2 mode is a low power consumption sleep mode for use
in battery operation. In this mode, VSWOUT is connected to VBAT.
All of the 2.5 V digital and analog circuitry powered through VI NTA
and VINTD is disabled, including the MCU core, resulting in the
following:
• The RAM in the MCU is no longer valid.
• The program counter for the 8052, also held in volatile
memory, becomes invalid when the 2.5 V supply is shut
down. Therefore, the program does not resume from where
it left off but always starts from the power-on reset vector
when the ADE5166/ADE5169/ADE5566/ADE5569 exit
PSM2 mode.
The 3.3 V peripherals (temperature ADC, VDCINADC, RTC, and
LCD) are active in PSM2 mode. They can be enabled or disabled
to reduce power consumption and are configured for PSM2
operation when the MCU core is active (see Table 29 for more
information about the individual peripherals and their PSM2
configuration). The ADE5166/ADE5169/ADE5566/ADE5569
remain in PSM2 mode until an event occurs to wake them up.
In PSM2 mode, the ADE5166/ADE5169/ADE5566/ADE5569
provide four scratch pad RAM SFRs that are maintained during
this mode. These SFRs can be used to save data from the PSM0
or PSM1 mode when entering PSM2 mode (see Table 22 to
Table 25).
In PSM2 mode, the ADE5166/ADE5169/ADE5566/ADE5569
maintain some SFRs (see Table 28). The SFRs that are not listed
in this table should be restored when the part enters PSM0 or
PSM1 mode from PSM2 mode.
Table 28. SFRs Maintained in PSM2 Mode
I/O Configuration Power Supply Management RTC Peripherals LCD Peripherals
Interrupt pins configuration SFR
(INTPR, Address 0xFF);
see Table 17.
Battery detection threshold SFR
(BATVTH, Address 0xFA);
see Table 53.
RTC nominal compensation SFR
(RTCCOMP, Address 0xF6); see Table 132.
LCD Segment Enable 2 SFR
(LCDSEGE2, Address 0xED);
see Table 101.
Peripheral configuration SFR
(PERIPH, Address 0xF4);
see Table 20.
Battery switchover configuration
SFR (BATPR, Address 0xF5);
see Table 19.
RTC temperature compensation SFR
(TEMPCAL, Address 0xF7); see Table 133.
LCD Configuration Y SFR
(LCDCONY, Address 0xB1);
see Table 94.
Port 0 weak pull-up enable SFR
(PINMAP0, Address 0xB2);
see Table 162.
Battery ADC value SFR (BATADC,
Address 0xDF); see Table 55.
RTC configuration SFR (TIMECON,
Address 0xA1); see Table 128.
LCD Configuration X SFR
(LCDCONX, Address 0x9C);
see Table 92.
Port 1 weak pull-up enable SFR
(PINMAP1, Address 0xB3);
see Table 163.
Peripheral ADC strobe period SFR
(STRBPER, Address 0xF9);
see Table 50.
RTC Configuration 2 SFR (TIMECON2,
Address 0xA2); see Table 129.
LCD configuration SFR
(LCDCON, Address 0x95);
see Table 91.
Port 2 weak pull-up enable SFR
(PINMAP2, Address 0xB4);
see Table 164.
Temperature and supply delta
SFR (DIFFPROG, Address 0xF3);
see Table 51.
All indirectly accessible registers defined
in the RTC register list; see Table 134.
LCD clock SFR (LCDCLK,
Address 0x96); see Table 95.
Scratch Pad 1 SFR (SCRATCH1,
Address 0xFB); see Table 22.
VDCINADC value SFR (VDCINADC,
Address 0xEF); see Table 54.
LCD segment enable SFR
(LCDSEGE, Address 0x97);
see Table 98.
Scratch Pad 2 SFR (SCRATCH2,
Address 0xFC); see Table 23.
Temperature ADC value SFR
(TEMPADC, Address 0xD7);
see Table 56.
LCD pointer SFR (LCDPTR,
Address 0xAC); see Table 99.
Scratch Pad 3 SFR (SCRATCH3,
Address 0xFD); see Table 24.
LCD data SFR (LCDDAT,
Address 0xAE); see Table 100.
Scratch Pad 4 SFR (SCRATCH4,
Address 0xFE); see Table 25)
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 37 of 156
3.3 V PERIPHERALS AND WAKE-UP EVENTS
Some of the 3.3 V peripherals are capable of waking the ADE5166/
ADE5169/ADE5566/ADE5569 from PSM2 mode. The events that
can cause the ADE5166/ADE5169/ADE5566/ADE5569 to wake
up from PSM2 mode are listed in the wake-up event column in
Table 29. The interrupt flag associated with these events must
be cleared prior to executing instructions that put the ADE5166/
ADE5169/ADE5566/ADE5569 in PSM2 mode after wake-up.
Table 29. 3.3 V Peripherals and Wake-Up Events
3.3 V
Peripheral
Wake-Up
Event
Wake-Up
Enable Bits Flag
Interrupt
Vector Comments
Temperature
ADC
∆T Maskable The temperature ADC can wake up the ADE5166/ADE5169/
ADE5566/ADE5569. A pending interrupt is generated according
to the description in the Temperature Measurement section.
This wake-up event can be disabled by disabling temperature
measurements in the temperature and supply delta SFR
(DIFFPROG, Address 0xF3) in PSM2 mode. The temperature
interrupt needs to be serviced and acknowledged prior to
entering PSM2 mode.
VDCINADC ΔV Maskable FVADC
(IPSMF[3])
IPSM The VDCIN measurement can wake up the ADE5166/ADE5169/
ADE5566/ADE5569. The FVADC flag, Bit 3 of the power manage-
ment interrupt flag SFR (IPSMF, Address 0xF8), is set according to
the description in the External Voltage Measurement section.
This wake-up event can be disabled by clearing the EVADC bit,
Bit 3 in the power management interrupt enable SFR (IPSME,
Address 0xEC); see Table 21. The FVADC flag needs to be cleared
prior to entering PSM2 mode.
Power Supply
Management
PSR Nonmaskable FPSR
(IPSMF[7])
IPSM The ADE5166/ADE5169/ADE5566/ADE5569 wake up if the power
supply is restored (if VSWOUT switches to be connected to VDD). The
VSWSOURCE flag, Bit 6 of the peripheral configuration SFR (PERIPH,
Address 0xF4), is set to indicate that VSWOUT is connected to VDD.
RTC Interval Maskable ITFLAG
(TIMECON[2])
IRTC The ADE5166/ADE5169/ADE5566/ADE5569 wake up after the
programmable time interval has elapsed. The RTC interrupt needs
to be serviced and acknowledged prior to entering PSM2 mode.
Alarm
Maskable
ALFLAG
(TIMECON[6])
IRTC
An alarm can be set to wake the ADE5166/ADE5169/ADE5566/
ADE5569 after the desired amount of time. The RTC alarm is
enabled by setting the ALxxx_EN bits in the RTC Configuration 2
SFR (TIMECON2, Address 0xA2). The RTC interrupt needs to be
serviced and acknowledged prior to entering PSM2 mode.
I/O Ports1 INT0 INT0PRG = 1
(INTPR[0])
N/A IE0 The edge of the interrupt is selected by the IT0 bit, Bit 0 in the
TCON SFR (TCON, Address 0x88). The IE0 flag, Bit 1 in the TCON
SFR, is not affected. The Interrupt 0 interrupt needs to be serviced
and acknowledged prior to entering PSM2 mode.
INT1 INT1PRG = 11x
(INTPR[3:1])
N/A IE1 The edge of the interrupt is selected by the IT1 bit, Bit 2 in the
TCON SFR (TCON, Address 0x88). The IE1 flag, Bit 3 in the TCON
SFR, is not affected. The Interrupt 1 interrupt needs to be
serviced and acknowledged prior to entering PSM2 mode.
Rx2 edge RXPROG = 11
(PERIPH[1:0])
RX2FLAG
(PERIPH[7])
N/A An Rx edge event occurs if a rising or falling edge is detected
on the RxD2 line. The UART2 RxD flag needs to be cleared prior
to entering PSM2 mode.
External
Reset
Reset Nonmaskable N/A N/A If the RESET pin is brought low while the ADE5166/ADE5169/
ADE5566/ADE5569 are in PSM2 mode, they wake up to PSM1
mode.
LCD N/A N/A N/A N/A The LCD can be enabled/disabled in PSM2 mode. The LCD data
memory remains intact.
Scratch Pad N/A N/A N/A N/A The four SCRATCHx registers remain intact in PSM2 mode.
1 All I/O pins are treated as inputs. The weak pull-up on each I/O pin can be disabled individually in the Port 0 weak pull-up enable SFR (PINMAP0, Address 0xB2), Port 1
weak pull-up enable SFR (PINMAP1, Address 0xB3), and Port 2 weak pull-up enable SFR (PINMAP2, Address 0xB4) to decrease current consumption. The interrupts can
be enabled or disabled.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 38 of 156
TRANSITIONING BETWEEN OPERATING MODES
The operating mode of the ADE5166/ADE5169/ADE5566/
ADE5569 is determined by the power supply connected to
VSWOUT. Therefore, changes in the power supply, such as when
VSWOUT switches from VDD to VBAT or when VSWOUT switches to
VDD, alter the operating mode. This section describes events
that change the operating mode.
Automatic Battery Switchover (PSM0 to PSM1)
If any of the enabled battery switchover events occurs (see the
Battery Switchover section), VSWOUT switches to VBAT. This switch-
over results in a transition from PSM0 to PSM1 operating mode.
When battery switchover occurs, the analog circuitry used in
the ADE energy measurement DSP is disabled. To reduce power
consumption, user code can initiate a transition to PSM2 mode.
Entering Sleep Mode (PSM1 to PSM2)
To reduce power consumption when VSWOUT is connected to VBAT,
user code can initiate sleep mode, PSM2, by setting Bit 4 in the
power control SFR (POWCON, Address 0xC5) to shut down the
MCU core. Events capable of waking the MCU can be enabled
(see the 3.3 V Peripherals and Wake-Up Events section).
Servicing Wake-Up Events (PSM2 to PSM1)
The ADE5166/ADE5169/ADE5566/ADE5569 may need to
wake up from PSM2 mode to service wake-up events (see the
3.3 V Peripherals and Wake-Up Events section). PSM1 code
execution begins at the power-on reset vector. After servicing
the wake-up event, the ADE5166/ADE5169/ADE5566/ADE5569
can return to PSM2 mode by setting Bit 4 in the power control SFR
(POWCON, Address 0xC5) to shut down the MCU core.
Automatic Switch to VDD (PSM2 to PSM0)
If the conditions to switch VSWOUT from VBAT to VDD occur (see the
Battery Switchover section), the operating mode switches to PSM0
mode. When this switch occurs, the MCU core and the analog
circuitry used in the ADE energy measurement DSP automatically
restart. PSM0 code execution begins at the power-on reset vector.
Automatic Switch to VDD (PSM1 to PSM0)
If the conditions to switch VSWOUT from VBAT to VDD occur (see
the Battery Switchover section), the operating mode switches
to PSM0 mode. When this switch occurs, the analog circuitry
used in the ADE energy measurement DSP automatically restarts.
Note that code execution continues normally. A software reset
can be performed to start PSM0 code execution at the power-on
reset vector.
USING THE POWER MANAGEMENT FEATURES
Because program flow is different for each operating mode, the
status of VSWOUT must be known at all times. The VSWSOURCE bit
in the peripheral configuration SFR (PERIPH, Address 0xF4)
indicates the power supply to which VSWOUT is connected (see
Table 20). This bit can be used to control program flow on wake-
up. Because code execution always starts at the power-on reset
vector, Bit 6 of the PERIPH SRF can be tested to determine which
power supply is being used and to branch to normal code execution
or to wake up event code execution. Power supply events can
also occur when the MCU core is active. To be aware of the
events that change what VSWOUT is connected to, use the
following guidelines:
• Enable the battery switchover interrupt (EBSO)
if VSWOUT = VDD at power-up.
• Enable the power supply restored interrupt (EPSR)
if VSWOUT = VBAT at power-up.
An early warning that battery switchover is about to occur is
provided by SAG detection and, possibly, by low VDCIN
detection (see the Battery Switchover section).
For a user-controlled battery switchover, enable automatic battery
switchover on low VDD only. Next, enable the low VDCIN event to
generate the PSM interrupt. When a low VDCIN event occurs, start
data backup. Upon completion of the data backup, enable battery
switchover on low VDCIN. Battery switchover occurs 30 ms later.
PSM1
BATTERY MODE
VSWOUT IS CONNECT E D TO VBAT
PSM0
NORMAL MO DE
VSWOUT IS CONNECT E D TO VDD
PSM2
SLEEP MODE
VSWOUT IS CONNECT E D TO VBAT
POWER SUPPLY
RESTORED
AUTOMATIC BATTERY
SWITCHOVER
WAKE-UP
EVENT
USER CODE DI RE CTS M CU
TO SHUT DOW N CORE AFTER
SERVICING A WAKE-UP EVENT
POWER SUPPLY
RESTORED
07411-017
Figure 38. Transitioning Between Operating Modes
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 39 of 156
ENERGY MEASUREMENT
The ADE5166/ADE5169/ADE5566/ADE5569 offer a fixed func-
tion, energy measurement, digital processing core that provides
all the information needed to measure energy in single-phase
energy meters. The part provides two ways to access the energy
measurements: direct access through SFRs for time sensitive
information and indirect access through address and data SFRs
for the majority of energy measurements. The Irms, Vrms, interrupt,
and waveform registers are readily available through the SFRs, as
shown in Table 31. Other energy measurement information is
mapped to a page of memory that is accessed indirectly through
the MADDPT, MDATL, MDATM, and MDATH SFRs. The
address and data SFRs act as pointers to the energy measurement
internal registers.
ACCESS TO ENERGY MEASUREMENT SFRs
Access to the energy measurement SFRs is achieved by reading
or writing to the SFR addresses detailed in Table 31. The internal
data for the MIRQx SFRs is latched byte by byte into the SFR
when the SFR is read.
The WAV1x, WAV2x, VRMSx, and IRMSx registers are all 3-byte
SFRs. The 24-bit data is latched into these SFRs when the high
byte is read. Reading the low or medium byte before the high
byte results in reading the data from the previous latched sample.
Sample code to read the VRMSx register is as follows:
MOV R1, VRMSH //latches data in VRMSH,
VRMSM, and VRMSL SFRs
MOV R2, VRMSM
MOV R3, VRMSL
ACCESS TO INTERNAL ENERGY MEASUREMENT
REGISTERS
Access to the internal energy measurement registers is achieved
by writing to the energy measurement pointer address SFR
(MADDPT, Address 0x91). This SFR selects the energy measure-
ment register to be accessed and determines if a read or a write
is performed (see Table 30).
Table 30. Energy Measurement Pointer Address SFR
(MADDPT, Address 0x91)
Bit Description
7 1 = write
0 = read
[6:0]
Energy measurement internal register address
Writing to the Internal Energy Measurement Registers
When Bit 7 of the energy measurement pointer address SFR
(MADDPT, Address 0x91) is set, the contents of the MDATx SFRs
(MDATL, MDATM, and MDATH) are transferred to the internal
energy measurement register designated by the address in the
MADDPT SFR. If the internal register is one byte long, only the
MDATL SFR contents are copied to the internal register. The
MDATM SFR and MDATH SFR contents are ignored.
The energy measurement core functions with an internal clock of
4.096 MHz∕5 or 819.2 kHz. Because the 8052 core functions with
another clock, 4.096 MHz∕2CD, synchronization between the two
clock environments when CD = 0 or 1 is an issue. When data is
written to the internal energy measurement registers, a small
wait period needs to be implemented before another read or
write to these registers can take place.
Sample code to write 0x0155 to the 2-byte SAGLVL register,
located at Address 0x14 in the energy measurement memory
space, is as follows:
MOV MDATM,#01h
MOV MDATL,#55h
MOV MADDPT,#SAGLVL_W (Address 0x94)
MOV A,#05h
DJNZ ACC,$
;Next write or read to energy
measurement SFR can be done after this.
Reading the Internal Energy Measurement Registers
When Bit 7 of energy measurement pointer address SFR
(MADDPT, Address 0x91) is cleared, the contents of the inter-
nal energy measurement register designated by the address in
MADDPT are transferred to the MDATx SFRs. If the internal
register is one byte long, only the MDATL SFR contents are
updated with a new value. The MDATM SFR and MDATH SFR
contents are reset to 0x00.
The energy measurement core functions with an internal clock
of 4.096 MHz∕5 or 819.2 kHz. Because the 8052 core functions
with another clock, 4.096 MHz∕2CD, synchronization between
the two clock environments is an issue when CD = 0 or CD = 1.
When data is read from the internal energy measurement registers,
a small wait period needs to be implemented before the MDATx
SFRs are transferred to another SFR.
Sample code to read the peak voltage in the 2-byte VPKLVL
register, located at Address 0x16, into the data pointer is as
follows:
MOV MADDPT,#VPKLVL_R (Address 0x16)
MOV A,#05h
DJNZ ACC,$
MOV DPH,MDATM
MOV DPL,MDATL
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 40 of 156
Table 31. Energy Measurement SFRs
Address R/W Mnemonic Description
0x91 R/W MADDPT Energy measurement pointer address.
0x92 R/W MDATL Energy measurement pointer data LSB.
0x93 R/W MDATM Energy measurement pointer data middle byte.
0x94 R/W MDATH Energy measurement pointer data MSB.
0xD1 R VRMSL Vrms measurement LSB.
0xD2 R VRMSM Vrms measurement middle byte.
0xD3 R VRMSH Vrms measurement MSB.
0xD4 R IRMSL Irms measurement LSB.
0xD5 R IRMSM Irms measurement middle byte.
0xD6
R
IRMSH
I
rms
measurement MSB.
0xD9 R/W MIRQENL Energy measurement interrupt enable LSB.
0xDA R/W MIRQENM Energy measurement interrupt enable middle byte.
0xDB R/W MIRQENH Energy measurement interrupt enable MSB.
0xDC R/W MIRQSTL Energy measurement interrupt status LSB.
0xDD R/W MIRQSTM Energy measurement interrupt status middle byte.
0xDE R/W MIRQSTH Energy measurement interrupt status MSB.
0xE2 R WAV1L Selection 1 sample LSB.
0xE3 R WAV1M Selection 1 sample middle byte.
0xE4 R WAV1H Selection 1 sample MSB.
0xE5 R WAV2L Selection 2 sample LSB.
0xE6 R WAV2M Selection 2 sample middle byte.
0xE7 R WAV2H Selection 2 sample MSB.
07411-117
×1, ×2, ×4,
×8, ×16
ADC
IPA
IN
PGA1
I
{GAIN[2:0]}
HPF
ADC
IPB
PGA1 HPF
IBGAIN[11:0]
ADC
DFC
MULTIPLIER
INTEGRATOR
WATTOS[15:0]
VAGAIN[11:0]
VADIV[7:0]
IRMSOS[11:0]
VRMSOS[11:0]
WGAIN[11:0]
dt
MET ERING S FRs
VN
VPPGA2
CF1
WDIV[7:0]
%%
Ф
π
2
VARDIV[7:0]
%
VAROS[15:0]
VARGAIN[11:0]
DFC
CF2NUM[15:0]
CF2DEN[15:0]
CF1DEN[15:0]
CF1NUM[15:0]
CF2
HPF
HPF
LPF1
LPF3
LPF3
LPF2
LPF2
LPF2
x2
|X|
PHCAL[7:0]
Figure 39. ADE5166/ADE5169 Energy Metering Block Diagram
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 41 of 156
07411-100
×1, ×2, ×4,
×8, ×16
ADC
IPA
IN
PGA1
I
{GAIN[2:0]}
HPF
ADC
DFC
MULTIPLIER
INTEGRA
TOR
WATTOS[15:0]
VAGAIN[11:0]
VADIV[7:0]
IRMSOS[11:0]
VRMSOS[11:0]
dt
MET ERING S FRs
VN
VPPGA2
CF1
WDIV[7:0]
%%
Ф
π
2
VARDIV[7:0]
%
VAROS[15:0]
VARGAIN[11:0]
DFC
CF2NUM[15:0]
CF2DEN[15:0]
CF1DEN[15:0]
CF1NUM[15:0]
CF2
HPF
HPF
LPF1
LPF3
LPF3
LPF2
LPF2
LPF2
x
2
PHCAL[7:0]
|X|
WGAIN[11:0]
Figure 40. ADE5566/ADE5569 Energy Metering Block Diagram
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 42 of 156
ENERGY MEASUREMENT REGISTERS
Table 32. Energy Measurement Register List
Address
MADDPT[6:0] Mnemonic R/W
Length
(Bits)
Signed/
Unsigned Default Description
0x01 WATTHR R 24 S 0 Reads the Wh accumulator without reset.
0x02 RWAT THR R 24 S 0 Reads the Wh accumulator with reset.
0x03 LWATTHR R 24 S 0 Reads the Wh accumulator synchronous to line cycle.
0x04 VARHR1 R 24 S 0 Reads the varh accumulator without reset.
0x05 RVARHR1 R 24 S 0 Reads the varh accumulator with reset.
0x06 LVARHR1 R 24 S 0 Reads the varh accumulator synchronous to line cycle.
0x07 VAHR R 24 S 0 Reads VAh accumulator without reset. If the VARMSCFCON bit in the
MODE2 register (Address 0x0C) is set, this register accumulates Irms.
0x08 RVAHR R 24 S 0 Reads VAh accumulator with reset. If the VARMSCFCON bit in the
MODE2 register (Address 0x0C) is set, this register accumulates Irms.
0x09 LVAHR R 24 S 0 Reads VAh accumulator synchronous to line cycle. If the VARMSCFCON
bit in the MODE2 register (Address 0x0C) is set, this register accumulates
Irms.
0x0A PER_FREQ R 16 U 0 Reads line period or frequency register, depending on MODE2 register.
0x0B MODE1 R/W 8 U 0x06 Sets basic configuration of energy measurement (see Table 33).
0x0C MODE2 R/W 8 U 0x40 Sets basic configuration of energy measurement (see Table 34).
0x0D WAVMODE R/W 8 U 0 Sets configuration of Waveform Sample 1 and Waveform Sample 2
(see Table 35).
0x0E NLMODE R/W 8 U 0 Sets level of energy no load thresholds (see Table 36).
0x0F ACCMODE R/W 8 U 0 Sets configuration of watt and var accumulation and various tamper
alarms (see Table 37).
0x10 PHCAL R/W 8 S 0x40 Sets phase calibration register (see the Phase Compensation section).
0x11 ZXTOUT R/W 12 U 0xFFF Sets timeout for zero-crossing timeout detection (see the Zero-
Crossing Timeout section).
0x12 LINCYC R/W 16 U 0xFFFF Sets number of half-line cycles for LWATTHR, LVARHR, and LVAHR
accumulators.
0x13 SAGCYC R/W 8 U 0xFF Sets number of half-line cycles for SAG detection (see the Line
Voltage SAG Detection section).
0x14 SAGLVL R/W 16 U 0 Sets detection level for SAG detection (see the Line Voltage SAG
Detection section).
0x15 IPKLVL R/W 16 U 0xFFFF Sets peak detection level for current peak detection (see the Peak
Detection section).
0x16
VPKLVL
R/W
16
U
0xFFFF
Sets peak detection level for voltage peak detection (see the Peak
Detection section).
0x17 IPEAK R 24 U 0 Reads current peak level without reset (see the Peak Detection section).
0x18 RSTIPEAK R 24 U 0 Reads current peak level with reset (see the Peak Detection section).
0x19 VPEAK R 24 U 0 Reads voltage peak level without reset (see the Peak Detection section).
0x1A RSTVPEAK R 24 U 0 Reads voltage peak level with reset (see the Peak Detection section).
0x1B GAIN R/W 8 U 0 Sets PGA gain of analog inputs (see Table 38).
0x1C IBGAIN2 R/W 12 S 0 Sets matching gain for IPB current input.
0x1D WGAIN R/W 12 S 0 Sets watt gain register.
0x1E VARGAIN1 R/W 12 S 0 Sets var gain register.
0x1F VAGAIN R/W 12 S 0 Sets VA gain register.
0x20
WAT TOS
R/W
16
S
0
Sets watt offset register.
0x21 VAROS1 R/W 16 S 0 Sets var offset register.
0x22 IRMSOS R/W 12 S 0 Sets current rms offset register.
0x23 VRMSOS R/W 12 S 0 Sets voltage rms offset register.
0x24 WDIV R/W 8 U 0 Sets watt energy scaling register.
0x25 VARDIV1 R/W 8 U 0 Sets var energy scaling register.
0x26 VADIV R/W 8 U 0 Sets VA energy scaling register.
0x27 CF1NUM R/W 16 U 0 Sets CF1 numerator register.
0x28 CF1DEN R/W 16 U 0x003F Sets CF1 denominator register.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 43 of 156
Address
MADDPT[6:0] Mnemonic R/W
Length
(Bits)
Signed/
Unsigned Default Description
0x29 CF2NUM R/W 16 U 0 Sets CF2 numerator register.
0x2A CF2DEN R/W 16 U 0x003F Sets CF2 denominator register.
0x2B MODE3 R/W 8 U 0 Enables zero-crossing outputs (see Table 39).
0x3B Reserved 0 This register must be set to its default value for proper operation.
0x3C Reserved 0x0300 This register must be set to its default value for proper operation.
0x3D CALMODE2 R/W 8 U 0 Sets calibration mode (see Table 40).
0x3E Reserved 0 This register must be set to its default value for proper operation.
0x3F Reserved 0 This register must be set to its default value for proper operation.
1 This function is not available in the ADE5166 and ADE5566.
2 This function is not available in the ADE5566 and ADE5569.
ENERGY MEASUREMENT INTERNAL REGISTERS DETAILS
Table 33. Mode 1 Register (MODE1, Address 0x0B)
Bit Mnemonic Default Description
7
SWRST
0
Setting this bit resets all of the energy measurement registers to their default values.
6 DISZXLPF 0 Setting this bit disables the zero-crossing low-pass filter.
5 INTE 0 Setting this bit enables the digital integrator for use with a di/dt sensor.
4 SWAPBITS 0 Setting this bit swaps CH1 ADC and CH2 ADC.
3 PWRDN 0 Setting this bit powers down voltage and current ADCs.
2 DISCF2 1 Setting this bit disables Frequency Output CF2.
1 DISCF1 1 Setting this bit disables Frequency Output CF1.
0 DISHPF 0 Setting this bit disables the HPFs in voltage and current channels.
Table 34. Mode 2 Register (MODE2, Address 0x0C)
Bit Mnemonic Default Description
[7:6] CF2SEL 01 Configuration bits for CF2 output.
CF2SEL Result
00 CF2 frequency is proportional to active power
01 CF2 frequency is proportional to reactive power1
1X2 CF2 frequency is proportional to apparent power or Irms
[5:4]
CF1SEL
00
Configuration bits for CF1 output.
CF1SEL Result
00 CF1 frequency is proportional to active power
01 CF1 frequency is proportional to reactive power1
1X2 CF1 frequency is proportional to apparent power or Irms
3 VARMSCFCON 0 Configuration bit for apparent power or Irms for CF1 and CF2 outputs and VA accumulation registers (VAHR,
RVAHR, and LVAHR). Note that CF1 cannot be proportional to VA if CF2 is proportional to Irms, and vice versa.
VARMSCFCON Result
0 If CF1SEL = 1X, CF1 is proportional to VA
If CF2SEL = 1X, CF2 is proportional to VA
1 If CF1SEL = 1X, CF1 is proportional to Irms
If CF2SEL = 1X, CF2 is proportional to Irms
2 ZXRMS 0 Logic 1 enables update of rms values synchronously to Voltage ZX.
1 FREQSEL 0 Configuration bit to select period or frequency measurement for the PER_FREQ register (Address 0x0A).
FREQSEL Result
0 The PER_FREQ register holds a period measurement
1 The PER_FREQ register holds a frequency measurement
0 WAVEN 0 When this bit is set, waveform sampling mode is enabled.
1 This function is not available in the ADE5166 and ADE5566.
2 X = don’t care.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 44 of 156
Table 35. Waveform Mode Register (WAVMODE, Address 0x0D)
Bit Mnemonic Default Description
[7:5] WAV2SEL 000 Waveform Sample 2 selection for samples mode.
WAV2SEL Source
000 Current
001 Voltage
010 Active power multiplier output
011 Reactive power multiplier output1
100 VA multiplier output
101 Irms LPF output (low 24-bit)
110, 111 Reserved
[4:2] WAV1SEL 000 Waveform Sample 1 selection for samples mode.
WAV1SEL Source
000 Current
001 Voltage
010 Active power multiplier output
011 Reactive power multiplier output1
100 VA multiplier output
101
I
rms
LPF output (low 24-bit)
110, 111 Reserved
[1:0] DTRT 00 Waveform samples output data rate.
DTRT Update Rate (Clock = fCORE/5 = 819.2 kHz)
00 25.6 kSPS (clock/32)
01 12.8 kSPS (clock/64)
10 6.4 kSPS (clock/128)
11 3.2 kSPS (clock/256)
1 This function is not available in the ADE5166 and ADE5566.
Table 36. No Load Configuration Register (NLMODE, Address 0x0E)
Bit Mnemonic Default Description
7
DISVARCMP
1
0
Setting this bit disables fundamental var gain compensation over line frequency.
6 IRMSNOLOAD 0 Logic 1 enables Irms no load threshold detection. The level is defined by the setting of the
VANOLOAD bits.
[5:4] VANOLOAD 00 Apparent power no load threshold.
VANOLOAD Result
00 No load detection disabled
01 No load detection enabled with threshold = 0.030% of full scale
10 No load detection enabled with threshold = 0.015% of full scale
11 No load detection enabled with threshold = 0.0075% of full scale
[3:2] VARNOLOAD1 00 Reactive power no load threshold.
VARNOLOAD
Result
00 No load detection disabled
01
No load detection enabled with threshold = 0.015% of full scale
10 No load detection enabled with threshold = 0.0075% of full scale
11 No load detection enabled with threshold = 0.0037% of full scale
[1:0] APNOLOAD 00 Active power no load threshold.
APNOLOAD Result
00 No load detection disabled
01 No load detection enabled with threshold = 0.015% of full scale
10 No load detection enabled with threshold = 0.0075% of full scale
11
No load detection enabled with threshold = 0.0037% of full scale
1 This function is not available in the ADE5166 and ADE5566.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 45 of 156
Table 37. Accumulation Mode Register (ACCMODE, Address 0x0F)
Bit Mnemonic Default Description
7 ICHANNEL1 0 This bit indicates the current channel used to measure energy in antitampering mode.
0 = Channel A (IPA).
1 = Channel B (IPB).
6 FAULTSIGN1 0 Configuration bit to select the event that triggers a fault interrupt.
0 = FAULTSIGN interrupt occurs when the part enters fault mode.
1 = FAULTSIGN interrupt occurs when the part enters normal mode.
5 VARSIGN2 0 Configuration bit to select the event that triggers a reactive power sign interrupt.
If cleared to 0, a VARSIGN interrupt occurs when reactive power changes from positive to negative.
If set to 1, a VARSIGN interrupt occurs when reactive power changes from negative to positive.
4 APSIGN 0 Configuration bit to select the event that triggers an active power sign interrupt.
If cleared to 0, an APSIGN interrupt occurs when active power changes from positive to negative.
If set to 1, an APSIGN interrupt occurs when active power changes from negative to positive.
3 ABSVARM2 0 Logic 1 enables absolute value accumulation of reactive power in energy register and pulse output.
2 SAVARM2 0 Logic 1 enables reactive power accumulation depending on the sign of the active power.
If active power is positive, var is accumulated as it is.
If active power is negative, the sign of the var is reversed for the accumulation.
This accumulation mode affects both the var registers (VARHR, RVARHR, LVARHR) and the pulse
output when connected to the reactive measurement.2
1 POAM 0 Logic 1 enables positive-only accumulation of active power in energy register and pulse output.
0 ABSAM 0 Logic 1 enables absolute value accumulation of active power in energy register and pulse output.
1 This function is not available in the ADE5566 and ADE5569.
2 This function is not available in the ADE5166 and ADE5566.
Table 38. Gain Register (GAIN, Address 0x1B)
Bit
Mnemonic
Default
Description
[7:5] PGA2 000 These bits define the voltage channel input gain.
PGA2 Result
000 Gain = 1
001 Gain = 2
010 Gain = 4
011 Gain = 8
100 Gain = 16
4 Reserved 0 Reserved.
3 CFSIGN_OPT 0 This bit defines where the CF change of sign detection (APSIGN or VARSIGN) is implemented.
CFSIGN_OPT Result
0 Filtered power signal
1 On a per CF pulse basis
[2:0] PGA1 000 These bits define the current channel input gain.
PGA1 Result
000 Gain = 1
001 Gain = 2
010 Gain = 4
011 Gain = 8
100
Gain = 16
Table 39. Mode 3 Register (MODE3, Address 0x2B)
Bit Mnemonic Default Description
[7:2] Reserved 0 Reserved.
1 ZX1 0 Setting this bit enables the zero-crossing output signal on P1.2.
0 ZX2 0 Setting this bit enables the zero-crossing output signal on P0.5.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 46 of 156
Table 40. Calibration Mode Register (CALMODE, Address 0x3D)1
Bit Mnemonic Default Description
[7:6] Reserved 00 These bits must be kept at 0 for proper operation.
[5:4] SEL_I_CH 00 These bits define the current channel used for energy measurements.
SEL_I_CH Result
00
Current channel automatically selected by the tampering condition
01 Current channel connected to IPA
10 Current channel connected to IPB
11 Current channel automatically selected by the tampering condition
3 V_CH_SHORT 0 Logic 1 shorts the voltage channel to ground.
2 I_CH_SHORT 0 Logic 1 shorts the current channel to ground.
[1:0] Reserved 00 These bits must be kept at 0 for proper operation.
1 This register is not available in the ADE5566 and ADE5569.
INTERRUPT STATUS/ENABLE SFRS
Table 41. Interrupt Status 1 SFR (MIRQSTL, Address 0xDC)
Bit
Interrupt Flag
Description
7 ADEIRQFLAG This bit is set if any of the ADE status flags that are enabled to generate an ADE interrupt is set. This bit is
automatically cleared when all of the enabled ADE status flags are cleared.
6 Reserved Reserved.
5 FAULTSIGN 1 Logic 1 indicates that the fault mode has changed according to the configuration of the ACCMODE register.
4 VARSIGN2 Logic 1 indicates that the reactive power sign has changed according to the configuration of the ACCMODE register.
3 APSIGN Logic 1 indicates that the active power sign has changed according to the configuration of the ACCMODE register.
2 VANOLOAD
Logic 1 indicates that an interrupt has been caused by apparent power no load detection. This interrupt is also
used to reflect that the part is entering the Irms no load mode.
1 RNOLOAD2 Logic 1 indicates that an interrupt has been caused by reactive power no load detection.
0 APNOLOAD Logic 1 indicates that an interrupt has been caused by active power no load detection.
1 This function is not available in the ADE5566 and ADE5569.
2 This function is not available in the ADE5166 and ADE5566.
Table 42. Interrupt Status 2 SFR (MIRQSTM, Address 0xDD)
Bit Interrupt Flag Description
7 CF2 Logic 1 indicates that a pulse on CF2 has been issued. The flag is set even if the CF2 pulse output is not
enabled by clearing Bit 2 of the MODE1 register.
6 CF1 Logic 1 indicates that a pulse on CF1 has been issued. The flag is set even if the CF1 pulse output is not
enabled by clearing Bit 1 of the MODE1 register.
5
VAEOF
Logic 1 indicates that the VAHR register has overflowed.
4 REOF1 Logic 1 indicates that the VARHR register has overflowed.
3 AEOF Logic 1 indicates that the WATTHR register has overflowed.
2 VAEHF Logic 1 indicates that the VAHR register is half full.
1 REHF1 Logic 1 indicates that the VARHR register is half full.
0
AEHF
Logic 1 indicates that the WATTHR register is half full.
1 This function is not available in the ADE5166 or ADE5566.
Table 43. Interrupt Status 3 SFR (MIRQSTH, Address 0xDE)
Bit Interrupt Flag Description
7
RESET
Indicates the end of a reset (for both software and hardware reset).
6 Reserved Reserved.
5 WFSM Logic 1 indicates that new data is present in the waveform registers (Address 0xE2 to Address 0xE7).
4 PKI Logic 1 indicates that the current channel has exceeded the IPKLVL value.
3 PKV Logic 1 indicates that the voltage channel has exceeded the VPKLVL value.
2 CYCEND Logic 1 indicates the end of the energy accumulation over an integer number of half-line cycles.
1 ZXTO Logic 1 indicates that no zero crossing on the line voltage occurred for the last ZXTOUT half-line cycles.
0 ZX Logic 1 indicates detection of a zero crossing in the voltage channel.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 47 of 156
Table 44. Interrupt Enable 1 SFR (MIRQENL, Address 0xD9)
Bit Interrupt Enable Bit Description
[7:6] Reserved Reserved.
5 FAULTSIGN 1 When this bit is set to Logic 1, the FAULTSIGN flag set creates a pending ADE interrupt to the 8052 core.
4 VARSIGN2 When this bit is set to Logic 1, the VARSIGN flag set creates a pending ADE interrupt to the 8052 core.
3 APSIGN When this bit is set to Logic 1, the APSIGN flag set creates a pending ADE interrupt to the 8052 core.
2 VANOLOAD When this bit is set to Logic 1, the VANOLOAD flag set creates a pending ADE interrupt to the 8052 core.
1 RNOLOAD2 When this bit is set to Logic 1, the RNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
0 APNOLOAD When this bit is set to Logic 1, the APNOLOAD flag set creates a pending ADE interrupt to the 8052 core.
1 This function is not available in the ADE5566 and ADE5569.
2 This function is not available in the ADE5166 and ADE5566.
Table 45. Interrupt Enable 2 SFR (MIRQENM, Address 0xDA)
Bit Interrupt Enable Bit Description
7
CF2
When this bit is set to Logic 1, a CF2 pulse creates a pending ADE interrupt to the 8052 core.
6 CF1 When this bit is set to Logic 1, a CF1 pulse creates a pending ADE interrupt to the 8052 core.
5 VAEOF When this bit is set to Logic 1, the VAEOF flag set creates a pending ADE interrupt to the 8052 core.
4 REOF1 When this bit is set to Logic 1, the REOF flag set creates a pending ADE interrupt to the 8052 core.
3 AEOF When this bit is set to Logic 1, the AEOF flag set creates a pending ADE interrupt to the 8052 core.
2 VAEHF When this bit is set to Logic 1, the VAEHF flag set creates a pending ADE interrupt to the 8052 core.
1 REHF1 When this bit is set to Logic 1, the REHF flag set creates a pending ADE interrupt to the 8052 core.
0 AEHF When this bit is set to Logic 1, the AEHF flag set creates a pending ADE interrupt to the 8052 core.
1 This function is not available in the ADE5166 and ADE5566.
Table 46. Interrupt Enable 3 SFR (MIRQENH, Address 0xDB)
Bit Interrupt Enable Bit Description
[7:6] Reserved Reserved.
5 WFSM When this bit is set to Logic 1, the WFSM flag set creates a pending ADE interrupt to the 8052 core.
4 PKI When this bit is set to Logic 1, the PKI flag set creates a pending ADE interrupt to the 8052 core.
3 PKV When this bit is set to Logic 1, the PKV flag set creates a pending ADE interrupt to the 8052 core.
2 CYCEND When this bit is set to Logic 1, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.
1 ZXTO When this bit is set to Logic 1, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.
0 ZX When this bit is set to Logic 1, the ZX flag set creates a pending ADE interrupt to the 8052 core.
ANALOG INPUTS
Each ADE5166/ADE5169/ADE5566/ADE5569 has two fully dif-
ferential voltage input channels. The maximum differential input
voltage for the VP/VN, IPA/IN, IPB/IN, and IP/IN input pairs is ±0.5 V.
Each analog input channel has a programmable gain amplifier
(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The gain
selections are made by writing to the gain register (see Table 38
and Figure 41).
00000000
76543210
GAIN REGISTER*
CURRENT AND VOLTAGE CHANNE LS P GA CONT RO L
PG A2 GAIN S E LECT
000 = ×1
001 = ×2
010 = ×4
011 = ×8
100 = ×16
PG A1 GAIN S E LECT
000 = ×1
001 = ×2
010 = ×4
011 = ×8
100 = ×16
RESERVED
*REG IST E R CONT E NTS S HOW P OWE R- ON DEFAULTS.
ADDR:
0x1B
CFSIGN_OPT
07411-019
Figure 41. Analog Gain Register
Bit 2 to Bit 0 select the gain for the PGA in the current channel,
and Bit 7 to Bit 5 select the gain for the PGA in the voltage
channel. Figure 42 shows how a gain selection for the current
channel is made using the gain register.
K × V
IN
I
P
, I
Px
I
IN
00000000
76543210
GAIN[7:0]
GAIN (K)
SELECTION
V
IN
07411-018
Figure 42. PGA in Current Channel
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 48 of 156
ANALOG-TO-DIGITAL CONVERSION
Each ADE5166/ADE5169/ADE5566/ADE5569 has two Σ-Δ
analog-to-digital converters (ADCs). The outputs of these ADCs
are mapped directly to waveform sampling SFRs (Address 0xE2
to Address 0xE7) and are used for energy measurement internal
digital signal processing. In PSM1 (battery) mode and PSM2
(sleep) mode, the ADCs are powered down to minimize power
consumption.
For simplicity, the block diagram in Figure 44 shows a first-order
Σ-∆ ADC. The converter is made up of the Σ-∆ modulator and
the digital low-pass filter (LPF).
A Σ-∆ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE5166/ADE5169/ADE5566/ADE5569, the sam-
pling clock is equal to 4.096 MHz/5. The 1-bit DAC in the feedback
loop is driven by the serial data stream. The DAC output is
subtracted from the input signal. If the loop gain is high enough,
the average value of the DAC output (and, therefore, the bit stream)
can approach that of the input signal level.
For any given input value in a single sampling interval, the data
from the 1-bit ADC is virtually meaningless. Only when a large
number of samples is averaged is a meaningful result obtained.
This averaging is carried into the second part of the ADC, the
digital LPF. By averaging a large number of bits from the modu-
lator, the low-pass filter can produce 24-bit data-words that are
proportional to the input signal level.
The Σ-∆ converter uses two techniques to achieve high resolution
from what is essentially a 1-bit conversion technique. The first
is oversampling. Oversampling means that the signal is sampled
at a rate (frequency) that is many times higher than the bandwidth
of interest. For example, the sampling rate in the ADE5166/
ADE5169/ADE5566/ADE5569 is 4.096 MHz/5 (819.2 kHz);
and the band of interest is 40 Hz to 2 kHz. Oversampling has
the effect of spreading the quantization noise (noise due to
sampling) over a wider bandwidth. With the noise spread more
thinly over a wider bandwidth, the quantization noise in the band
of interest is lowered (see Figure 43).
409.60819.22
NOISE
SIGNAL
DIGITAL
FILTER
ANTIALIASING
FILTER ( RC) SAMPLING
FREQUENCY
HIGH RESOLUTION
OUTPUT FROM DIGITAL
LPF
SHAPED
NOISE
409.60819.22
NOISE
SIGNAL
FREQUENCY (kHz)
FREQUENCY (kHz)
07411-021
Figure 43. Noise Reduction Due to Oversampling and
Noise Shaping in the Analog Modulator
However, oversampling alone is not efficient enough to improve
the signal-to-noise ratio (SNR) in the band of interest. For example,
an oversampling ratio of 4 is required to increase the SNR by only
6 dB (one bit). To keep the oversampling ratio at a reasonable level,
it is possible to shape the quantization noise so that the majority
of the noise lies at the higher frequencies. In the Σ-∆ modulator,
the noise is shaped by the integrator, which has a high-pass type of
response for the quantization noise. The result is that most of
the noise is at the higher frequencies where it can be removed
by the digital LPF. This noise shaping is shown in Figure 43.
+
–
INTEGRATOR
V
REF
1-BI T DAC
DIGITAL
LOW-PASS
FILTER
24
MCLK/5
C
R
ANALOG
LOW-PASS FILTER
... 10100101 .. .
LATCHED
COMPARATOR
07411-020
Figure 44. First-Order
Σ
-∆ ADC
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 49 of 156
Antialiasing Filter
Figure 44 also shows an analog LPF (RC) on the input to the
modulator. This filter is present to prevent aliasing, an artifact
of all sampled systems. Aliasing means that frequency components
in the input signal to the ADC that are higher than half the
sampling rate of the ADC appear in the sampled signal at a fre-
quency below half the sampling rate. Figure 45 illustrates the effect.
Frequency components (the black arrows) above half the sampling
frequency (also known as the Nyquist frequency, that is, 409.6 kHz)
are imaged or folded back down below 409.6 kHz. This happens
with all ADCs, regardless of the architecture. In Figure 45, only
frequencies near the sampling frequency (819.2 kHz) move into
the band of interest for metering (40 Hz to 2 kHz). This allows
the use of a very simple LPF to attenuate high frequency (at
approximately 819.2 kHz) noise and prevents distortion in the
band of interest.
409.60819.22FREQUENCY (kHz)
SAMPLING
FREQUENCY
ALIASING EFFECTS
IMAGE
FREQUENCIES
07411-022
Figure 45. ADC and Signal Processing in Current Channel Outline Dimensions
For conventional current sensors, a simple RC filter (single-pole
LPF) with a corner frequency of 10 kHz produces an attenuation
of approximately 40 dB at 819.2 kHz (see Figure 45). The 20 dB
per decade attenuation is usually sufficient to eliminate the effects
of aliasing for conventional current sensors. However, for a di/dt
sensor such as a Rogowski coil, the sensor has a 20 dB per decade
gain. This neutralizes the −20 dB per decade attenuation produced
by one simple LPF. Therefore, when using a di/dt sensor, care
should be taken to offset the 20 dB per decade gain. One simple
approach is to cascade two RC filters to produce the −40 dB per
decade attenuation needed.
ADC Transfer Function
Both ADCs in the ADE5166/ADE5169/ADE5566/ADE5569 are
designed to produce the same output code for the same input
signal level. With a full-scale signal on the input of 0.5 V and an
internal reference of 1.2 V, the ADC output code is nominally
2,147,483 or 0x20C49B. The maximum code from the ADC is
±4,194,304; this is equivalent to an input signal level of ±0.794 V.
However, for specified performance, it is recommended that the
full-scale input signal level of 0.5 V not be exceeded.
Current Channel ADC
Figure 46 and Figure 47 show the ADC and signal processing
chain for the current channel. In waveform sampling mode, the
ADC outputs a signed, twos complement, 24-bit data-word at a
maximum of 25.6 kSPS (4.096 MHz/160).
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 50 of 156
PGA1 ADC
I
PA
I
PB
I
N
I
REFERENCE
IBGAIN
×1, ×2, ×4
×8, × 16
{GAIN[2:0]}
HPF
DIGITAL
INTEGRATOR*
dt
MODE1[5] CURRENT RMS ( I
rms
)
CALCULATION
WAVEFORM SAMPLE
REGISTER
ACTIVE AND RE ACTI V E
PO WER CAL CULAT IO N
0V
V1
ANALOG
INPUT
RANGE
0.25V , 0.125V ,
62.5mV , 31.3mV
CURRENT CHANNE L
WAVEFORM
DATA RANGE
0x28F5C2
0x000000
0xD70A3E
CURRENT CHANNE L
WAVEFORM
DATA RANGE AF TER
INTEG RATO R ( 50Hz )
0x342CD0
0x000000
0xCBD330
CURRENT CHANNE L
WAVEFORM
DATA RANGE AF TER
INTEG RATO R ( 60Hz )
0x2B7850
0x000000
0xD487B0
60Hz
50Hz
PGA1 ADC HPF
*WHE N THE DI GI TAL INT E GRATOR I S E NABLED, F ULL- S CALE OUT P UT DAT A IS ATTE NUATED
DEPE NDING ON T HE S IG NAL F RE QUENCY BE CAUS E THE INT E GRAT OR HAS A –20d B/DECADE
FRE QUENCY RE S P ONSE . W HE N DISABLED, THE OUT P UT I S NOT FURT HE R ATT E NUATED.
NOTE T HAT T HE DIG IT AL INTEGRAT OR I S NOT AV AIL ABLE IN T HE ADE 5166.
07411-009
Figure 46. ADC and Signal Processing in Current Channel for the ADE5166/ADE5169
PGA1 ADC
IP
IN
I
REFERENCE
×1, ×2, ×4
×8, × 16
{GAIN[2:0]}
HPF
DIGITAL
INTEGRATOR*
dt
MODE1[5] CURRENT RMS ( Irms)
CALCULATION
WAVEFORM SAMPLE
REGISTER
ACTIVE AND RE ACTI V E
PO WER CAL CULAT IO N
0V
V1
ANALOG
INPUT
RANGE
0.25V , 0.125V ,
62.5mV , 31.3mV CURRENT CHANNE L
WAVEFORM
DATA RANGE
0x28F5C2
0x000000
0xD70A3E
CURRENT CHANNE L
WAVEFORM
DATA RANGE AF TER
INTEG RATO R ( 50Hz )
0x342CD0
0x000000
0xCBD330
CURRENT CHANNE L
WAVEFORM
DATA RANGE AF TER
INTEG RATO R ( 60Hz )
0x2B7850
0x000000
0xD487B0
60Hz
50Hz
*WHE N THE DI GI TAL INT E GRATOR I S E NABLED, F ULL- S CALE OUT P UT DAT A IS ATTE NUATED
DEPE NDING ON T HE S IG NAL F RE QUENCY BE CAUS E THE INT E GRAT OR HAS A –20d B/DECADE
FRE QUENCY RE S P ONSE . W HE N DISABLED, THE OUT P UT I S NOT FURT HE R ATT E NUATED.
NOTE T HAT T HE DIG IT AL INTEGRAT OR I S NOT AV AIL ABLE IN T HE ADE 5566.
07411-008
Figure 47. ADC and Signal Processing in Current Channel for the ADE5566/ADE5569
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 51 of 156
Voltage Channel ADC
Figure 48 shows the ADC and signal processing chain for the
voltage channel. In waveform sampling mode, the ADC outputs
a signed, twos complement, 24-bit data-word at a maximum
of 25.6 kSPS (MCLK/160). The ADC produces an output code
that is approximately between 0x28F5 (+10,485d) and 0xD70B
(−10,485d).
Channel Sampling
The waveform samples of the current ADC and voltage ADC
can also be routed to the waveform registers to be read by the
MCU core. The active, reactive, and apparent power and energy
calculation remain uninterrupted during waveform sampling.
When in waveform sampling mode, one of four output sample
rates can be chosen by using the two DTRT bits of the WAVMODE
register (Address 0x0D[1:0]), as shown in Table 35. The output
sample rate can be 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS.
If the WFSM enable bit is set in the Interrupt Enable 3 SFR
(MIRQENH, Address 0xDB), the 8052 core has a pending ADE
interrupt. The sampled signals selected in the WAVMODE
register are latched into the waveform SFRs when the waveform
high byte (WAV1H or WAV2H) is read.
The ADE interrupt stays active until the WFSM status bit is
cleared (see the Energy Measurement Interrupts section).
ANALOG
INPUT
RANGE
HPF
ADC
REFERENCE
V2
0V
0.5V , 0.25V ,
0.125V , 62.5mV ,
31.3mV
VOLT AGE RMS (Vrms)
CALCULATION
VP
VN
PGA2
V2
VO LTAGE CHANNE L
WAVEFORM
DATA RANGE
0xD70B
0x0000
0x28F5
ACTI
VE AND REACTIVE
PO WER CAL CULAT IO N
LPF1
f
–3dB
= 63.7Hz
MODE1[6]
ZX SIGNAL
DATA RANGE F OR 60Hz S IG NAL
0xE230
0x0000
0x1DD0
ZX DETECTION
ZX SIGNAL
DATA RANGE F OR 50Hz S IG NAL
0xDFC9
0x0000
0x2037
VOLT AGE PEAK DETECT
×1, × 2, ×4,
×8, × 16
{GAIN[7:5]}
WAVEFORM SAMPLE
REGISTER
07411-024
Figure 48. ADC and Signal Processing in Voltage Channel
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 52 of 156
FAULT DETECTION (ADE5166/ADE5169 ONLY)
The ADE5166/ADE5169 incorporate a fault detection scheme
that warns of fault conditions and allows accurate measurement to
continue during a fault event. (This feature is not available in the
ADE5566/ADE5569.) The ADE5166/ADE5169 do this by con-
tinuously monitoring both current inputs (IPA and IPB). For ease of
understanding, these currents are referred to as phase and neutral
(return) currents. In the ADE5166/ADE5169, a fault condition is
defined when the difference between IPA and IPB is greater than
6.25% of the active channel caused by amplitude or phase. If a
fault condition is detected and the inactive channel is larger than
the active channel, the ADE5166/ ADE5169 automatically switch
current measurement to the inactive channel. During a fault, the
active, reactive, and apparent power and the Irms are generated
using the larger of the two cur-rents. On power-up, IPA is the
current input selected for active, reactive, and apparent power
and Irms calculations.
To pre vent a false alarm, averaging is done for the fault detection,
and a fault condition is detected approximately one second after
the event. The fault detection is automatically disabled when the
voltage signal is less than 0.3% of the full-scale input range. This
eliminates false detection of a fault due to noise at light loads.
Because the ADE5166/ADE5169 look for a difference between
the voltage signals on IPA and IPB, it is important that both current
transducers be closely matched.
Channel Selection Indication
The current channel selected for measurement is indicated
by the ICHANNEL bit (Bit 7) in the ACCMODE register
(Address 0x0F). When Bit 7 is cleared, IPA is selected; when Bit 7
is set, IPB is selected. The ADE5166/ADE5169 automatically switch
from one channel to the other and report the channel configuration
in the ACCMODE register.
The current channel selected for measurement can also be forced.
Setting the SEL_I_CH bits (Bits[5:4]) in the CALMODE register
(Address 0x3D) to 01 or 10 selects IPA and IPB, respectively. When
both bits are cleared or set, the current channel used for measure-
ment is selected automatically, based on the fault detection.
Fault Indication
The ADE5166/ADE5169 provide an indication of the part going
into or out of a fault condition. The new fault condition is indicated
by the FAULTSIGN flag (Bit 5) in the Interrupt Status 1 SFR
(MIRQSTL, Address 0xDC).
When the FAULTSIGN bit (Bit 6) in the ACCMODE register
(Address 0x0F) is cleared, the FAULTSIGN flag in the Interrupt
Status 1 SFR (MIRQSTL, Address 0xDC) is set when the part is
entering a fault condition or a normal condition.
When the FAULTSIGN bit (Bit 5) is set in the Interrupt Enable 1
SFR (MIRQENL, Address 0xD9) and the FAULTSIGN flag (Bit 5)
in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set,
the 8052 core has a pending ADE interrupt.
Fault with Active Input Greater Than Inactive Input
If IPA is the active current input (that is, IPA is being used for
billing), and the voltage signal on IPB (inactive input) falls below
93.75% of IPA , and the FAULTSIGN bit (Bit 6) of the ACCMODE
register (Address 0x0F) is cleared, the FAULTSIGN flag (Bit 5)
in the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set.
Both analog inputs are filtered and averaged to prevent false
triggering of this logic output. As a consequence of the filtering,
there is a time delay of approximately 3 sec on the logic output
after the fault event. The FAULTSIGN flag is independent of
any activity. Because IPA is the active input and it is still greater
than IPB, billing is maintained on IPA; that is, no swap to the IPB
input occurs. IPA remains the active input.
Fault with Inactive Input Greater Than Active Input
If the difference between IPB (the inactive input) and IPA (the active
input that is being used for billing) becomes greater than 6.25%
of IPB, and the FAULTSIGN bit (Bit 6) in the ACCMODE register
(Address 0x0F) is cleared, the FAULTSIGN flag (Bit 5) in the Inter-
rupt Status 1 SFR (MIRQSTL, Address 0xDC) is set. The IPB analog
input becomes the active input. Again, a time constant of about
3 sec is associated with this swap. IPA does not swap back to the
active channel until IPA is greater than IPB and the difference
between IPA and IPB, in this order, becomes greater than 6.25% of IPB.
However, if the FAULTSIGN bit (Bit 6) in the ACCMODE register
(Address 0x0F) is set, the FAULTSIGN flag (Bit 5) in the Interrupt
Status 1 SFR (MIRQSTL, Address 0xDC) is set as soon as IPA is
within 6.25% of IPB. This threshold eliminates concerns about
potential chatter between IPA and IPB calibration.
Calibration Concerns
Typically, when a meter is calibrated, the voltage and current cir-
cuits are separated (see Figure 49). Current passes through only
the phase circuit or the neutral circuit. Figure 49 shows current
being passed through the phase circuit. This is the preferred option
because the ADE5166/ADE5169 start billing on the IPA input on
power-up. The phase circuit, CT, is connected to IPA in the diagram.
Because the current sensors are not perfectly matched, it is impor-
tant to match current inputs. The ADE5166/ADE5169 provide a
gain calibration register for IPB, IBGAIN (Address 0x1C). IBGAIN
is a 12-bit, signed, twos complement register that provides a gain
resolution of 0.0244%/LSB.
AGND
I
B
I
N
I
PA
R
F
R
F
C
F
C
F
CT
CT
R
B
R
B
0V
V
A
0
I
PB
PHASE
NEUTRAL
R
F
R
A
V
P
R
F
V
N
C
T
C
F
V
TEST
CURRENT
240V rms
07411-025
+
–
+
–
+
–
Figure 49. Fault Conditions for Inactive Input Greater Than Active Input
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 53 of 156
For calibration, a first measurement should be done on IPA by
setting the SEL_I_CH bits (Bits[5:4]) to 0b01 in the CALMODE
register (Address 0x3D). This measurement should be compared
to the measurement on IPB. Measuring IPB can be forced by setting
the SEL_I_CH bits (Bits[5:4]) to 0b10 in the CALMODE register
(Address 0x3D). The gain error between these two measurements
can be evaluated using the following equation:
Error (%) =
)(
)()(
PA
PA
PB
ItMeasuremen
ItMeasuremenItMeasuremen −
The two channels, IPA and IPB, can then be matched by writing
–Error(%)/(1 + Error(%)) × 212 to the IBGAIN register
(Address 0x1C). This matching adjustment is valid for all energy
measurements made by the ADE5166/ADE5169, including
active power, reactive power (the ADE5169 only), apparent
power, and Irms.
di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR
(ADE5169/ADE5569 ONLY)
The di/dt sensor, a feature available for the ADE5169/ADE5569,
detects changes in the magnetic field caused by ac currents.
Figure 50 shows the principle of a di/dt current sensor.
MAGNE TI C FI E LD CREAT E D BY CURRENT
(DIRECTLY PROPORTIONAL TO CURRENT)
+ EMF (ELECTROMOT I VE F O RCE)
– INDUCED BY CHANG E S IN
MAGNE TI C FL UX DE NS ITY (di/dt)
07411-026
Figure 50. Principle of a di/dt Current Sensor
The flux density of a magnetic field induced by a current is directly
proportional to the magnitude of the current. The changes in the
magnetic flux density passing through a conductor loop generate
an electromotive force (EMF) between the two ends of the loop.
The EMF is a voltage signal that is proportional to the di/dt of the
current. The voltage output from the di/dt current sensor is deter-
mined by the mutual inductance between the current-carrying
conductor and the di/dt sensor. The current signal needs to be
recovered from the di/dt signal before it can be used. An integrator
is, therefore, necessary to restore the signal to its original form.
The ADE5169/ADE5569 has a built-in digital integrator to recover
the current signal from the di/dt sensor. The digital integrator
on the current channel is switched off by default when the
ADE5169/ADE5569 is powered up. Setting the INTE bit (Bit 5)
in the MODE1 register (Address 0x0B) turns on the integrator.
Figure 51 to Figure 54 show the gain and phase response of the
digital integrator.
FREQUENCY (Hz)
10
GAIN (d B)
0
–10
–20
–30
–40
–50 100 1000
07411-027
Figure 51. Combined Gain Response of the Digital Integrator and
Phase Compensator
FREQUENCY (Hz)
102103
FREQ
–88.0
PHASE ( Degrees)
–88.5
–89.0
–89.5
–90.0
–90.5
07411-106
Figure 52. Combined Phase Response of the Digital Integrator and
Phase Compensator
FREQUENCY (Hz)
–1.0
–6.040 7045
GAIN (d B)
50 55 60 65
–1.5
–2.0
–2.5
–3.5
–4.5
–5.5
–3.0
–4.0
–5.0
07411-029
Figure 53. Combined Gain Response of the Digital Integrator and
Phase Compensator (40 Hz to 70 Hz)
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 54 of 156
–89.75
–89.80
–89.85
–89.90
–89.95
–90.00
FREQUENCY (Hz)
PHASE ( Degrees)
40 45 7050 55 60 65
–90.05
–89.70
07411-030
Figure 54. Combined Phase Response of the Digital Integrator and
Phase Compensator (40 Hz to 70 Hz)
Note that the integrator has a −20 dB/dec attenuation and an
approximately −90° phase shift. When combined with a di/dt
sensor, the resulting magnitude and phase response should be
a flat gain over the frequency band of interest. The di/dt sensor
has a 20 dB/dec gain associated with it. It also generates significant
high frequency noise. Therefore, a more effective antialiasing
filter is needed to avoid noise due to aliasing (see the Antialiasing
Filter section).
When the digital integrator is switched off, the ADE5169/ADE5569
can be used directly with a conventional current sensor, such as a
current transformer (CT), or with a low resistance current shunt.
POWER QUALITY MEASUREMENTS
Zero-Crossing Detection
Each ADE5166/ADE5169/ADE5566/ADE5569 has a zero-
crossing detection circuit on the voltage channel. This external
zero-crossing signal can be output on P0.5 and P1.2 (see Table 39).
It is also used in calibration mode.
The zero crossing is generated by default from the output of LPF1.
This filter has a low cutoff frequency and is intended for 50 Hz
and 60 Hz systems. If needed, this filter can be disabled to allow
a higher frequency signal to be detected or to limit the group delay
of the detection. If the voltage input fundamental frequency is
below 60 Hz, and a time delay in ZX detection is acceptable, it
is recommended that LPF1 be enabled. Enabling LPF1 limits the
variability in the ZX detection by eliminating the high frequency
components. Figure 55 shows how the zero-crossing signal is
generated.
The zero-crossing signal, ZX, is generated from the output of
LPF1 (bypassed or not). LPF1 has a single pole at 63.7 Hz (at
MCLK = 4.096 MHz). As a result, there is a phase lag between
the analog input signal, V2, and the output of LPF1. The phase
lag response of LPF1 results in a time delay of approximately
2 ms (at 60 Hz) between the zero crossing on the analog inputs
of the voltage channel and ZX detection.
×1, × 2, ×4,
×8, × 16
ADC 2
REFERENCE
LPF1
f
–3dB
= 63.7Hz
PGA2
{GAIN[7:5]}
V
P
V
N
V2
ZERO
CROSSING
ZX
HPF
MODE1[6]
43.24° @ 60Hz
1.0
0.73 ZX
V2 LPF1
07411-031
Figure 55. Zero-Crossing Detection on the Voltage Channel
The zero-crossing detection also drives the ZX flag in the Inter-
rupt Status 3 SFR (MIRQSTH, Address 0xDE). If the ZX bit (Bit 0)
in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) is set,
the 8052 core has a pending ADE interrupt. The ADE interrupt
stays active until the ZX status bit is cleared (see the Energy
Measurement Interrupts section).
Zero-Crossing Timeout
The zero-crossing detection also has an associated timeout
register, ZXTOUT. This unsigned, 12-bit register is decremented
(1 LSB) every 160/MCLK sec. The register is reset to its user-
programmed, full-scale value every time a zero crossing is detected
on the voltage channel. The default power-on value in this register
is 0xFFF. If the internal register decrements to 0 before a zero
crossing is detected in the Interrupt Status 3 SFR (MIRQSTH,
Address 0xDE) and the ZXTO bit (Bit 1) in the Interrupt Enable 3
SFR (MIRQENH, Address 0xDB) is set, the 8052 core has a
pending ADE interrupt.
The ADE interrupt stays active until the ZXTO status bit is
cleared (see the Energy Measurement Interrupts section). The
ZXTOUT register (Address 0x11) can be written to or read by
the user (see the Energy Measurement Registers section). The
resolution of the register is 160/MCLK sec per LSB. Thus, the
maximum delay for an interrupt is 0.16 sec (1/MCLK × 212) when
MCLK = 4.096 MHz.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 55 of 156
Figure 56 shows the mechanism of the zero-crossing timeout
detection when the line voltage stays at a fixed dc level for more
than MCLK/160 × ZXTOUT seconds.
12-BI T INTERNAL
REG IST E R V ALUE
ZXTOUT
ZXTO
FLAG
BIT
VOLTAGE
CHANNEL
07411-032
Figure 56. Zero-Crossing Timeout Detection
Period or Frequency Measurements
The ADE5166/ADE5169/ADE5566/ADE5569 provide the period
or frequency measurement of the line. The period or frequency
measurement is selected by clearing or setting the FREQSEL bit
(Bit 1) in the MODE2 register (Address 0x0C). The period/
frequency register, PER_FREQ (Address 0x0A), is an unsigned
16-bit register that is updated every period. If LPF1 is enabled,
a settling time of 1.8 sec is associated with this filter before the
measurement is stable.
When the period measurement is selected, the measurement has a
2.44 µs/LSB (4.096 MHz/10) resolution, which represents 0.014%
when the line frequency is 60 Hz. When the line frequency is
60 Hz, the value of the period register is approximately 0d6827.
The length of the register enables the measurement of line fre-
quencies as low as 12.5 Hz. The period register is stable at ±1 LSB
when the line is established and the measurement does not change.
When the frequency measurement is selected, the measurement
has a 0.0625 Hz/LSB resolution when MCLK = 4.096 MHz, which
represents 0.104% when the line frequency is 60 Hz. When the
line frequency is 60 Hz, the value of the frequency register is 0d960.
The frequency register is stable at ±4 LSB when the line is estab-
lished and the measurement does not change.
Line Voltage SAG Detection
In addition to detection of the loss of the line voltage signal
(zero crossing), the ADE5166/ADE5169/ADE5566/ADE5569 can
also be programmed to detect when the absolute value of the line
voltage drops below a certain peak value for a number of line
cycles. This condition is illustrated in Figure 57.
SAG IS RESET LO W
WHEN VOLTAGE
CHANNEL E X CE E DS
SAG LVL [ 15: 0] AND
SAG FLAG I S RESET
FULL SCALE
SAGLVL[15:0]
SAG FLAG SAGCY C[ 7: 0] = 0x04
3 LINE CYCLES
VO LTAGE CHANNE L
07411-033
Figure 57. SAG Detection
Figure 57 shows the line voltage falling below a threshold that
is set in the SAG level register (SAGLVL, Address 0x14[15:0])
for three line cycles. The quantities 0 and 1 are not valid for the
SAGCYC register, and the contents represent one more than the
desired number of full line cycles. For example, when the SAG
cycle register (SAGCYC, Address 0x13[7:0]) contains 0x04, FSAG
(Bit 5) in the power management interrupt flag SFR (IPSMF,
Address 0xF8) is set at the end of the third line cycle after the line
voltage falls below the threshold. If the SAG enable bit (ESAG,
Bit 5) in the power management interrupt enable SFR (IPSME,
Address 0xEC) is set, the 8052 core has a pending power supply
management interrupt. The PSM interrupt stays active until the
FSAG bit is cleared (see the Power Supply Management (PSM)
Interrupt section).
In Figure 57, the SAG flag (FSAG) is set on the fifth line cycle
after the signal on the voltage channel first drops below the
threshold level.
SAG Level Set
The 2-byte contents of the SAG level register (SAGLVL,
Address 0x14) are compared to the absolute value of the output
from LPF1. Therefore, when LPF1 is enabled, writing 0x2038 to the
SAG level register puts the SAG detection level at full scale (see
Figure 57). Writing 0x00 or 0x01 puts the SAG detection level
at 0. The SAG level register is compared to the input of the ZX
detection, and detection is made when the ZX input falls below the
contents of the SAG level register.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 56 of 156
Peak Detection
The ADE5166/ADE5169/ADE5566/ADE5569 can be program-
med to detect when the absolute value of the voltage or current
channel exceeds a specified peak value. Figure 58 illustrates the
behavior of the peak detection for the voltage channel. Both
voltage and current channels are monitored at the same time.
PKV RESET
LOW WHEN
MIRQSTH SFR
IS RE AD
VPKLVL[15:0]
V
2
RESET BIT PKV
IN MIRQSTH SFR
PKV INTE RRUP T
FLAG
07411-034
Figure 58. Peak Level Detection
Figure 58 shows a line voltage exceeding a threshold that is set in
the voltage peak register (VPKLVL, Address 0x16[15:0]). The
voltage peak event is recorded by setting the PKV flag (Bit 3)
in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE). If
the PKV enable bit (Bit 3) is set in the Interrupt Enable 3 SFR
(MIRQENH, Address 0xDB), the 8052 core has a pending ADE
interrupt. Similarly, the current peak event is recorded by setting
the PKI flag (Bit 4) in the Interrupt Status 3 SFR (MIRQSTH,
Address 0xDE). The ADE interrupt stays active until the PKV or
PKI status bit is cleared (see the Energy Measurement Interrupts
section).
Peak Level Set
The contents of the VPKLVL register (Address 0x16) and the
IPKLVL register (Address 0x15) are compared to the absolute value
of the voltage and two MSBs of the current channel, respectively.
Thus, for example, the nominal maximum code from the current
channel ADC with a full-scale signal is 0x28F5C2 (see the Current
Channel ADC section). Therefore, writing 0x28F5 to the IPKLVL
register puts the current channel peak detection level at full scale
and sets the current peak detection to its least sensitive value.
Writing 0x00 puts the current channel detection level at 0. The
detection is done by comparing the contents of the IPKLVL reg-
ister to the incoming current channel sample. The PKI flag (Bit 4)
in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) indicates
that the peak level is exceeded. If the PKI bit (Bit 4) or the PKV
bit (Bit 3) is set in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB), the 8052 core has a pending ADE interrupt.
Peak Level Record
Each ADE5166/ADE5169/ADE5566/ADE5569 records the maxi-
mum absolute value reached by the current and voltage channels
in two different registers, IPEAK (Address 0x17) and VPEAK
(Address 0x19), respectively. Each register is a 24-bit, unsigned
register that is updated each time that the absolute value of the
waveform sample from the corresponding channel is above the
value stored in the IPEAK or VPEAK register. The contents of the
IPEAK and VPEAK registers represent the maximum absolute
value observed on the current and voltage channel input,
respectively. Reading the RSTIPEAK (Address 0x18) and
RSTVPEAK (Address 0x1A) registers clears their respective
contents after the read operation.
PHASE COMPENSATION
The ADE5166/ADE5169/ADE5566/ADE5569 must work with
transducers that can have inherent phase errors. For example,
a phase error of 0.1° to 0.3° is not uncommon for a current trans-
former (CT). These phase errors can vary from part to part, and
they must be corrected to perform accurate power calculations.
The errors associated with phase mismatch are particularly notice-
able at low power factors. The ADE5166/ADE5169/ADE5566/
ADE5569 provide a means of digitally calibrating these small phase
errors. The part allows a small time delay or time advance to be
introduced into the signal processing chain to compensate for
small phase errors. Because the compensation is in time, this
technique should be used only for small phase errors in the range
of 0.1° to 0.5°. Correcting large phase errors using a time shift
technique may introduce significant phase errors at higher
harmonics.
The phase calibration register (PHCAL[7:0], Address 0x10) is
a twos complement, signed, single-byte register that has values
ranging from 0x82 (−126d) to 0x68 (+104d).
The PHCAL register is centered at 0x40, meaning that writing
0x40 to the register gives 0 delay. By changing this register, the
time delay in the voltage channel signal path can change from
−231.93 µs to +48.83 µs (MCLK = 4.096 MHz). One LSB is equiv-
alent to a 1.22 µs (4.096 MHz/5) time delay or advance. A line
frequency of 60 Hz gives a phase resolution of 0.026° at the
fundamental (that is, 360° × 1.22 µs × 60 Hz).
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 57 of 156
Figure 59 illustrates how the phase compensation is used to
remove a 0.1° phase lead in the current channel due to the
external transducer. To cancel the lead (0.1°) in the current
channel, a phase lead must also be introduced into the voltage
channel. The resolution of the phase adjustment allows the intro-
duction of a phase lead in increments of 0.026°. The phase lead is
achieved by introducing a time advance into the voltage channel.
A time advance of 4.88 µs is made by writing −4 (0x3C) to the
time delay block, thus reducing the amount of time delay by
4.88 µs, or equivalently, a phase lead of approximately 0.1° at a
line frequency of 60 Hz (0x3C represents −4 because the register
is centered with 0 at 0x40).
110100
1
7 0
PGA1
IP/IPA
IN
IADC 1
HPF 24
PGA2
VP
VN
VADC 2
24 LPF2
VI
60Hz
0.1°
I
V
CHANNEL 2 DE LAY
REDUCED BY 4.88µs
(0. 1°LE AD AT 60Hz)
0x3C IN P HCAL[7:0]
PHCAL[7:0]
–231.93µ s TO + 48.83µs
60Hz
11
DEL AY BLOCK
1.22µs/LSB
07411-035
Figure 59. Phase Calibration
RMS CALCULATION
Current Channel RMS Calculation
The root mean square (rms) value of a continuous signal, I(t), is
defined as
( )
∫
×=
T
rms dttI
T
I
0
2
1
(1)
For time sampling signals, rms calculation involves squaring the
signal, taking the average, and obtaining the square root. The
ADE5166/ADE5169/ADE5566/ADE5569 implement this method
on the current channel by serially squaring the input, averaging
the results, and then taking the square root of the average. The
averaging part of this signal processing is done by
implementing a low-pass filter (LPF3 in Figure 60, Figure 61
and Figure 62).
This LPF has a −3 dB cutoff frequency of 2 Hz when MCLK =
4.096 MHz.
( )
)sin(2tItI
ω
×=
(2)
where V is the rms voltage.
( )
tIItI
ω
2cos)( 222 −=
(3)
When this signal goes through LPF3, the cos(2ωt) term is atte-
nuated and only the dc term, Irms2 (shown as I2 in Figure 60),
goes through.
IRMS
LPF3
INPUT
I
2
(t) = I
2
– I
2
cos(2ωt)
I
2
(t) = I
2
I(t) = √2 × I sin(ωt)
07411-036
Figure 60. IRMS Signal Processing
The Irms signal can be read from the waveform register by set-
ting the WAVMODE register (Address 0x0D) and setting the
WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB). Like the current and voltage channels waveform
sampling modes, the waveform data is available at sample rates of
25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and 3.2 kSPS.
It is important to note that when the current input is larger than
40% of full scale, the Irms waveform sample register does not
represent the true processed rms value. The rms value processed
with this level of input is larger than the 24-bit read by the wave-
form register, making the value read truncated on the high end.
Figure 61 and Figure 62 show the detail of the signal processsing
chain for the rms calculation on the current channel. The current
channel rms value is processed from the samples used in the
current channel waveform sampling mode and is stored in the
unsigned, 24-bit IRMS SFRs (IRMSL, Address 0xD4; IRMSM,
Address 0xD5; and IRMSH, Address 0xD6). One LSB of the
current channel rms register (IRMSL, IRMSM, and IRMSH) is
equivalent to 1 LSB of a current channel waveform sample.
The update rate of the current channel rms measurement is
4.096 MHz/5. To minimize noise in the reading of the register, the
Irms register can also be configured to update only with the zero
crossing of the voltage input. This configuration is done by setting
the ZXRMS bit (Bit 2) in the MODE2 register (Address 0x0C).
With the different specified full-scale analog input values, the ADC
produces an output code that is approximately ±0d2,684,354
(see the Current Channel ADC section). Similarly, the equiva-
lent rms value of a full-scale ac signal is 0d1,898,124 (0x1CF68C).
The current rms measurement provided in the ADE5166/
ADE5169/ADE5566/ADE5569 is accurate to within ±0.5%
for signal inputs between full scale and full scale/500. The
conversion from the register value to amps must be done
externally in the microprocessor using an amps/LSB constant.
Current Channel RMS Offset Compensation
The ADE5166/ADE5169/ADE5566/ADE5569 incorporate a cur-
rent channel rms offset compensation register (IRMSOS). This is
a 12-bit, signed register that can be used to remove offset in the
current channel rms calculation. An offset can exist in the rms
calculation due to input noises that are integrated into the dc
component of V2(t).
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 58 of 156
One LSB of the current channel rms offset is equivalent to
32,768 LSBs of the square of the current channel rms register.
Assuming that the maximum value from the current channel
rms calculation is 0d1,898,124 with full-scale ac inputs, then
1 LSB of the current channel rms offset represents 0.23% of
measurement error at −60 dB down from full scale.
768,32
2×+= IRMSOSII 0
rmsrms
(4)
where Irms0 is the rms measurement without offset correction.
I
rms
(t)
0x00
+
IRMSOS[11:0]
I
rms
[23:0]
2
26
2
25
sgn 2
27
2
17
2
16
2
18
24
24
dt
HPF
MODE1[5]
HPF
CURRENT CHANNE L
WAVEFORM
DATA RANGE W IT H
INTEGRATOR OFF
0xD70A3E
0x000000
0x28F5C2
60Hz
0xD487B0
I
PA
I
PB
0x2B7850
0x000000
CURRENT CHANNE L
WAVEFORM
DATA RANGE W IT H
INTEG RATO R ON (60Hz )
HPF1
DIGITAL
INTEGRATOR* LPF3
07411-057
LPF2
IBGAIN
*NOTE T HAT T HE DIG IT AL INTEGRAT OR I S NOT AV AILABLE IN T HE ADE 5166.
Figure 61. ADE5166/ADE5169 Current Channel RMS Signal Processing with PGA1 = 2, 4, 8, or 16
I
rms
(t)
0x00
+
IRMSOS[11:0]
Irms[23:0]
226
225
sgn 227 217 216
218
24
24
dt
MODE1[5]
CURRENT CHANNE L
WAVEFORM
DATA RANGE W IT H
INTEGRATOR OFF
0xD70A3E
0x000000
0x28F5C2
60Hz
0xD487B0
0x2B7850
0x000000
CURRENT CHANNE L
WAVEFORM
DATA RANGE W IT H
INTEG RATO R ON (60Hz )
DIGITAL
INTEGRATOR* LPF3
07411-059
HPF
IPA
*NOTE T HAT T HE DIG IT AL INTEGRAT OR I S NOT AV AILABLE IN T HE ADE 5566.
HPF1 LPF2
Figure 62. ADE5566/ADE5569 Current Channel RMS Signal Processing with PGA1 = 2, 4, 8, or 16
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 59 of 156
LPF3
VO LTAGE CHANNE L
0x28F5C2
++
VRMSOS[11:0]
VOLT AGE SI G NAL (V(t))
0x28F5
0x0
0xD70B 2
16
sgn 2
15
2
7
2
6
2
8
07411-038
V
rms
(t)
0x00
V
rms
[23:0]
|X|
HPF LPF1
Figure 63. Voltage Channel RMS Signal Processing
Voltage Channel RMS Calculation
The voltage channel rms estimation is performed in the
ADE5166/ADE5169/ADE5566/ADE5569 using a mean absolute
value calculation. This calculation accurately estimates the rms of
the voltage channel fundamental signal. Figure 63 shows details
of the signal processing chain for the rms calculation on the
voltage channel. The voltage channel rms value is processed from
the samples used in the voltage channel waveform sampling
mode and is stored in the unsigned 24-bit VRMS SFRs
(VRMSL, Address 0xD1; VRMSM, Address 0xD2; and
VRMSH, Address 0xD3).
The update rate of the voltage channel rms measurement is
MCLK/5. To minimize noise in the reading of the register, the
VRMS SFRs can also be configured to update only with the zero
crossing of the voltage input. This configuration is done by setting
the ZXRMS bit (Bit 2) in the MODE2 register (Address 0x0C).
With the specified full-scale ac analog input signal of 0.5 V, t h e
output from the LPF1 in Figure 63 swings between 0x28F5 and
0xD70B at 60 Hz (see the Voltage Channel ADC section). The
equivalent rms value of this full-scale ac signal is approximately
0d1,898,124 (0x1CF68C) in the VRMS SFRs. The voltage rms
measurement provided in the ADE5166/ADE5169/ADE5566/
ADE5569 is accurate to within ±0.5% for signal input between
full scale and full scale/20. The conversion from the register
value to volts must be done externally in the microprocessor
using a V/LSB constant.
Voltage Channel RMS Offset Compensation
The ADE5166/ADE5169/ADE5566/ADE5569 incorporate the
voltage channel rms offset compensation register (VRMSOS,
Address 0x23). This 12-bit, signed register can be used to remove
offset in the voltage channel rms calculation. An offset can exist
in the rms calculation due to input noises and dc offset in the input
samples. One LSB of the voltage channel rms offset is equivalent to
64 LSBs of the voltage channel rms register. Assuming that the
maximum value from the voltage channel rms calculation is
0d1,898,124 with full-scale ac inputs, then 1 LSB of the voltage
channel rms offset represents 3.37% of measurement error at
−60 dB down from full scale.
Vrms = Vrms0 + 64 × VRMSOS (5)
where Vrms0 is the rms measurement without offset correction.
ACTIVE POWER CALCULATION
Active power is defined as the rate of energy flow from source
to load. It is the product of the voltage and current waveforms.
The resulting waveform is called the instantaneous power signal
and is equal to the rate of energy flow at every instant of time.
The unit of power is the watt or joules/second. Equation 8 gives an
expression for the instantaneous power signal in an ac system.
( )
)sin(2tVtV ω×=
(6)
( )
)sin(2tItI ω×=
(7)
where:
V is the rms voltage.
I is the rms current.
P(t) = V(t) × I(t)
)2cos()( tVIVItP ω−=
(8)
The average power over an integral number of line cycles (n) is
given by the expression in Equation 9.
∫== nT VIdttP
nT
P0)(
1
(9)
where:
T is the line cycle period.
P is referred to as the active or real power.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 60 of 156
Note that the active power is equal to the dc component of the
instantaneous power signal, P(t), in Equation 9, that is, VI. This
is the relationship used to calculate active power in the ADE5166/
ADE5169/ADE5566/ADE5569. The instantaneous power signal,
P(t), is generated by multiplying the current and voltage signals.
The dc component of the instantaneous power signal is then
extracted by LPF2 (low-pass filter) to obtain the active power
information (see Figure 64).
INSTANTANEOUS
PO WER SIG NAL P(t) = V × I – V × I × cos(2ωt)
ACTIVE REAL POWER
SIGNAL = V × I
0x19999A
VI
0xCCCCD
0x00000
CURRENT
I(t) = 2 × I × sin(ωt)
VOLTAGE
V(t) = 2 × V × sin(ωt)
07411-039
Figure 64. Active Power Calculation
Because LPF2 does not have an ideal brick wall frequency response
(see Figure 65), the active power signal has some ripple due to
the instantaneous power signal. This ripple is sinusoidal and has
a frequency equal to 2× the line frequency. Because of its sinu-
soidal nature, the ripple is removed when the active power signal is
integrated to calculate energy (see the Active Energy Calculation
section).
FREQUENCY (Hz)
–24 1
ATTENUATION (dB)
–20
310 30 100
–12
–16
–8
–4
0
07411-040
Figure 65. Frequency Response of LPF2
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 61 of 156
Active Power Gain Calibration
Figure 66 shows the signal processing chain for the active power
calculation in the ADE5166/ADE5169/ADE5566/ADE5569. As
explained previously, the active power is calculated by filtering the
output of the multiplier with a low-pass filter. Note that, when
reading the waveform samples from the output of LPF2, the gain
of the active energy can be adjusted by using the multiplier and
writing a twos complement, 12-bit word to the the watt gain reg-
ister (WGAIN, Address 0x1D[11:0]). Equation 10 shows how
the gain adjustment is related to the contents of the watt gain
register.
+×= 12
2
1WGAIN
PowerActiveWGAINOutput
(10)
For example, when 0x7FF is written to the watt gain register, the
power output is scaled up by 50% (0x7FF = 2047d, 2047/212 = 0.5).
Similarly, 0x800 = −2048d (signed, twos complement), and power
output is scaled by −50%. Each LSB scales the power output by
0.0244%. The minimum output range is given when the watt gain
register contents are equal to 0x800, and the maximum output
range is given by writing 0x7FF to the watt gain register. This
register can be used to calibrate the active power (or energy)
calculation in the ADE5166/ADE5169/ADE5566/ADE5569.
Active Power Offset Calibration
The ADE5166/ADE5169/ADE5566/ADE5569 also incorporate
an active power offset register (WATTOS, Address 0x20[15:0]).
It is a signed, twos complement, 16-bit register that can be used
to remove offsets in the active power calculation (see Figure 66).
An offset can exist in the power calculation due to crosstalk
between channels on the PCB or in the IC itself. The offset
calibration allows the contents of the active power register to be
maintained at 0 when no power is being consumed.
The 256 LSBs (WATTOS = 0x0100) written to the active power
offset register are equivalent to 1 LSB in the waveform sample
register. Assuming the average value, output from LPF2 is
0xCCCCD (838,861d) when inputs on the voltage and current
channels are both at full scale. At −60 dB down on the current
channel (1/1000 of the current channel full-scale input), the
average word value output from LPF2 is 838.861 (838,861/1000).
One LSB in the LPF2 output has a measurement error of
1/838.861 × 100% = 0.119% of the average value. The active
power offset register has a resolution equal to 1/256 LSB of
the waveform register. Therefore, the power offset correction
resolution is 0.000464%/LSB (0.119%/256) at −60 dB.
Active Power Sign Detection
The ADE5166/ADE5169/ADE5566/ADE5569 can detect a
change of sign in the active power. The APSIGN flag (Bit 3) in
the Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) records
that a change of sign has occurred according to the APSIGN bit
(Bit 4) in the ACCMODE register (Address 0x0F). If the APSIGN
flag (Bit 3) is set in the Interrupt Enable 1 SFR (MIRQENL,
Address 0xD9), the 8052 core has a pending ADE interrupt. The
ADE interrupt stays active until the APSIGN status bit is cleared
(see the Energy Measurement Interrupts section).
When the APSIGN bit (Bit 4) in the ACCMODE register
(Address 0x0F) is cleared (default), a transition from positive
to negative active power sets the APSIGN flag (Bit 3) in the
Interrupt Status 1 SFR (MIRQSTL, Address 0xDC).
When the APSIGN bit (Bit 4) in the ACCMODE register
(Address 0x0F) is set, the APSIGN flag (Bit 3) in the MIRQSTL
SFR (Address 0xDC) is set when a transition from negative to
positive active power occurs.
Active Power No Load Detection
The ADE5166/ADE5169/ADE5566/ADE5569 include a no load
threshold feature on the active power that eliminates any creep
effects in the meter. The part accomplishes this by not accumu-
lating energy if the multiplier output is below the no load
threshold. When the active power is below the no load threshold,
the APNOLOAD flag (Bit 0) in the Interrupt Status 1 SFR
(MIRQSTL, Address 0xDC) is set. If the APNOLOAD bit (Bit 0)
is set in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9),
the 8052 core has a pending ADE interrupt. The ADE interrupt
stays active until the APNOLOAD status bit is cleared (see the
Energy Measurement Interrupts section).
The no load threshold level can be selected by setting the
APNOLOAD bits (Bits[1:0]) in the NLMODE register
(Address 0x0E). Setting these bits to 0b00 disables the no load
detection; setting them to 0b01, 0b10, or 0b11 sets the no load
detection threshold to 0.015%, 0.0075%, or 0.0037% of the multi-
plier full-scale output frequency, respectively. The IEC 62053-21
specification states that the meter must start up with a load of
≤0.4% IPB, which translates to 0.0167% of the full-scale output
frequency of the multiplier.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 62 of 156
ACTIVE ENERGY CALCULATION
As stated in the Active Power Calculation section, active power
is defined as the rate of energy flow. This relationship can be
expressed mathematically, as shown in Equation 11.
dt
dE
P=
(11)
where:
P is power.
E is energy.
Conversely, energy is given as the integral of power.
∫
=dttPE )(
(12)
The ADE5166/ADE5169/ADE5566/ADE5569 achieve the inte-
gration of the active power signal by continuously accumulating
the active power signal in an internal, nonreadable, 49-bit energy
register. The WAT T H R register (Address 0x01) represents the
upper 24 bits of this internal register. This discrete time
accumulation or summation is equivalent to integration in
continuous time. Equation 13 expresses the relationship.
×==
∑
∫
∞
=
→1
0)(lim)
(
n
tTnTPdttPE
(13)
where:
n is the discrete time sample number.
T is the discrete time sample period.
The discrete time sample period (T) for the accumulation
register in the ADE5166/ADE5169/ADE5566/ADE5569 is 1.22 µs
(5/MCLK). In addition to calculating the energy, this integration
removes any sinusoidal components that may be in the active
power signal. Figure 66 shows this discrete time integration or
accumulation. The active power signal in the waveform register
is continuously added to the internal active energy register.
The active energy accumulation depends on the setting of
POAM (Bit 1) and ABSAM (Bit 0) in the ACCMODE register
(Address 0x0F). When both bits are cleared, the addition is signed
and, therefore, negative energy is subtracted from the active
energy contents. When both bits are set, the ADE5166/ADE5169/
ADE5566/ADE5569 are set to the more restrictive mode, the
positive-only accumulation mode.
When POAM (Bit 1) in the ACCMODE register (Address 0x0F)
is set, only positive power contributes to the active energy accumu-
lation. When ABSAM (Bit 0) in the ACCMODE register
(Address 0x0F) is set, the absolute active power is used for the
active energy accumulation (see the Watt Absolute Accumulation
Mode section).
The output of the multiplier is divided by the value in the WDIV
register (Address 0x24). If the value in the WDIV register is equal
to 0, the internal active energy register is divided by 1. WDIV is an
8-bit, unsigned register. After dividing by WDIV, the active energy
is accumulated in a 49-bit internal energy accumulation register.
The upper 24 bits of this register are accessible through a read
to the active energy register (WATTHR, Address 0x01[23:0]).
A read to the RWATTHR register (Address 0x02) returns the
contents of the WATTHR register, and the upper 24 bits of the
internal register are cleared. As shown in Figure 66, the active
power signal is accumulated in an internal 49-bit, signed register.
The active power signal can be read from the waveform register
by setting the WAVMODE register (Address 0x0D) and setting
the WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB). Like the current and voltage channel waveform
sampling modes, the waveform data is available at sample rates of
25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and 3.2 kSPS.
WGAIN[11:0]
WDIV[7:0]
LPF2
CURRENT
CHANNEL
VOLTAGE
CHANNEL
OUTPUT LPF2
TIME (nT)
5
MCLK
T
ACTIVE POWER
SIGNAL
++
WATTHR[23:0]
OUTPUTS FROM THE LPF2 ARE
ACCUMUL ATED (INT E GRAT E D) IN
THE INTE RNAL ACT IVE E NE RGY RE GIS TER
UPPE R 24 BITS ARE
ACCESS IBLE THRO UGH
WATTHR[ 23: 0] RE GI S TER
23 0
48 0
%
WATTOS[15:0]
2
6
sgn
2
5
2
–6
2
–7
2
–8
+
+
FOR WAVEFORM
SAMPLING
TO
DIGITAL-TO-FREQUENCY
CONVERTER
WAVEFORM
REGISTER
VALUES
07411-041
Figure 66. Active Energy Calculation
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 63 of 156
Figure 67 shows this energy accumulation for full-scale signals
(sinusoidal) on the analog inputs. The three displayed curves
illustrate the minimum period of time it takes the energy register
to roll over when the active power gain register contents are
0x7FF, 0x000, and 0x800. The watt gain register is used to carry
out power calibration in the ADE5166/ADE5169/ADE5566/
ADE5569. As shown, the fastest integration time occurs when
the watt gain register is set to maximum full scale, that is, 0x7F F.
0x00 0000
0x7F FFFF
0x3F FFFF
0x40 0000
0x80 0000
WATTHR[23:0]
6.823.41 10.2 13.7 T I ME (Mi n u tes)
WG AIN = 0x7FF
WG AIN = 0x000
WG AIN = 0x800
07411-042
Figure 67. Energy Register Rollover Time for Full-Scale Power
(Minimum and Maximum Power Gain)
Note that the energy register contents roll over to full-scale negative
(0x800000) and continue to increase in value when the power or
energy flow is positive (see Figure 67). Conversely, if the power is
negative, the energy register underflows to full-scale positive
(0x7FFFFF) and continues to decrease in value.
Using the Interrupt Enable 2 SFR (MIRQENM, Address 0xDA),
the ADE5166/ADE5169/ADE5566/ADE5569 can be configured
to issue an ADE interrupt to the 8052 core when the active
energy register is half full (positive or negative) or when an
overflow or underflow occurs.
Integration Time Under Steady Load—Active Energy
As mentioned in the Active Energy Calculation section, the
discrete time sample period (T) for the accumulation register
is 1.22 µs (5/MCLK). With full-scale sinusoidal signals on the
analog inputs and the WGAIN register (Address 0x1D) set to
0x000, the average word value from each LPF2 is 0xCCCCD
(see Figure 64). The maximum positive value that can be stored in
the internal 49-bit register is 248 (or 0xFFFF FFFF FFFF) before it
overflows. The integration time under these conditions when
WDIV = 0 is calculated in the following equation:
Time =
min82.6sec6.409μs22.1
xCCCCD0
FFFFFFFFxFFFF0==×
(14)
When WDIV is set to a value other than 0, the integration time
varies, as shown in Equation 15.
Time = TimeWDIV = 0 × WDIV (15)
Active Energy Accumulation Modes
Watt Signed Accumulation Mode
The ADE5166/ADE5169/ADE5566/ADE5569 active energy
default accumulation mode is a watt-signed accumulation that
is based on the active power information.
Watt Positive-Only Accumulation Mode
The ADE5166/ADE5169/ADE5566/ADE5569 are placed in watt
positive-only accumulation mode by setting the POAM bit (Bit 1)
in the ACCMODE register (Address 0x0F). In this mode, the
energy accumulation is done only for positive power, ignoring
any occurrence of negative power above or below the no load
threshold (see Figure 68). The CF pulse also reflects this accumu-
lation method when in this mode. The default setting for this
mode is off. Detection of transitions in the direction of power
flow and detection of no load threshold are active in this mode.
POSPOS
INTERRUPT STAT US RE GI S TERS
NEG
APSIGN FLAG
NO LOAD
THRESHOLD
ACTIVE POWER
NO LOAD
THRESHOLD
ACTIVE E NE RGY
07411-043
Figure 68. Energy Accumulation in Positive-Only Accumulation Mode
Watt Absolute Accumulation Mode
The ADE5166/ADE5169/ADE5566/ADE5569 are placed in watt
absolute accumulation mode by setting the ABSAM bit (Bit 0) in
the ACCMODE register (Address 0x0F). In this mode, the
energy accumulation is done using the absolute active power,
ignoring any occurrence of power below the no load threshold
(see Figure 69). The CF pulse also reflects this accumulation
method when in this mode. The default setting for this mode is
off. Detection of transitions in the direction of power flow and
detection of no load threshold are active in this mode.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 64 of 156
POSPOS
INTERRUPT STAT US RE GI S TERS
NEG
APSIGN FLAG
NO LOAD
THRESHOLD
ACTIVE POWER
NO LOAD
THRESHOLD
ACTIVE E NE RGY
APNOLOAD APNOLOAD
07411-044
Figure 69. Energy Accumulation in Absolute Accumulation Mode
Active Energy Pulse Output
All of the ADE5166/ADE5169/ADE5566/ADE5569 circuitry
has a pulse output whose frequency is proportional to active
power (see the Active Power Calculation section). This pulse
frequency output uses the calibrated signal from the WGAIN
register (Address 0x1D) output, and its behavior is consistent
with the setting of the active energy accumulation mode in the
ACCMODE register (Address 0x0F). The pulse output is active
low and should preferably be connected to an LED, as shown in
Figure 80.
Line Cycle Active Energy Accumulation Mode
In line cycle active energy accumulation mode, the energy accumu-
lation of the ADE5166/ADE5169/ADE5566/ADE5569 can be
synchronized to the voltage channel zero crossing so that active
energy can be accumulated over an integral number of half-line
cycles. The advantage of summing the active energy over an integer
number of line cycles is that the sinusoidal component in the active
energy is reduced to 0. This eliminates any ripple in the energy
calculation. Energy is calculated more accurately and more quickly
because the integration period can be shortened. By using this
mode, the energy calibration can be greatly simplified, and the
time required to calibrate the meter can be significantly reduced.
In the line cycle active energy accumulation mode, the ADE5166/
ADE5169/ADE5566/ADE5569 accumulate the active power signal
in the LWATTHR register (Address 0x03) for an integral number
of line cycles, as shown in Figure 70. The number of half-line cycles
is specified in the LINCYC register (Address 0x12).
The ADE5166/ADE5169/ADE5566/ADE5569 can accumulate
active power for up to 65,535 half-line cycles. Because the active
power is integrated on an integral number of line cycles, the
CYCEND flag (Bit 2) in the Interrupt Status 3 SFR (MIRQSTH,
Address 0xDE) is set at the end of an active energy accumulation
line cycle. If the CYCEND enable bit (Bit 2) in the Interrupt
Enable 3 SFR (MIRQENH, Address 0xDB) is set, the 8052 core
has a pending ADE interrupt. The ADE interrupt stays active until
the CYCEND status bit is cleared (see the Energy Measurement
Interrupts section). Another calibration cycle starts as soon as the
CYCEND flag is set. If the LWATTHR register (Address 0x03) is
not read before a new CYCEND flag is set, the LWATTHR
register is overwritten by a new value.
WDIV[7:0]WATTOS[15:0]
WGAIN[11:0]
LPF1
++
LWATTHR[23:0]
ACCUMULATE
ACTIVE ENERGY IN
INTERNAL REGISTER
AND UPDAT E THE
LWATTHR REGISTER
AT THE END OF LI NCY C
HALF-L INE CY CLES
OUTPUT
FROM
LPF2
FROM VOLTAGE
CHANNEL
ADC
23 0
LINCYC[15:0]
48 0
%
ZERO-CROSSING
DETECTION CALIBRATION
CONTROL
TO
DIGITAL-TO-FREQUENCY
CONVERTER
07411-046
Figure 70. Line Cycle Active Energy Accumulation Mode
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 65 of 156
When a new half-line cycle is written in the LINCYC register
(Address 0x12), the LWATTHR register (Address 0x03) is reset,
and a new accumulation starts at the next zero crossing. The
number of half-line cycles is then counted until LINCYC is
reached. This implementation provides a valid measurement at
the first CYCEND interrupt after writing to the LINCYC register
(see Figure 71). The line active energy accumulation uses the
same signal path as the active energy accumulation. The LSB
size of these two registers is equivalent.
LINCYC
VALUE
CYCEND IRQ
LWATTHR REGISTER
07411-045
Figure 71. Energy Accumulation When LINCYC Changes
Using the information from Equation 8 and Equation 9
( )
( )
dtft
f
VI
dtVItE
nTnT π
+
−= ∫∫ 2cos
9.8
10
2
0
(16)
where:
n is an integer.
T is the line cycle period.
Because the sinusoidal component is integrated over an integer
number of line cycles, its value is always 0. Therefore,
0
0
+= ∫
nT
VIdtE
(17)
E(t) = VInT (18)
Note that in this mode, the 16-bit LINCYC register can hold
a maximum value of 65,535. In other words, the line energy
accumulation mode can be used to accumulate active energy
for a maximum duration of 65,535 half-line cycles. At a 60 Hz
line frequency, the total duration of 65,535/120 Hz = 546 sec.
REACTIVE POWER CALCULATION
(ADE5169/ADE5569 ONLY)
Reactive power, a function available for the ADE5169/ADE5569,
is defined as the product of the voltage and current waveforms
when one of these signals is phase-shifted by 90°. The resulting
waveform is called the instantaneous reactive power signal.
Equation 21 gives an expression for the instantaneous reactive
power signal in an ac system when the phase of the current
channel is shifted by 90°.
)sin(2)( θtVtV +ω×=
(19)
)sin(2)( tItI ω×=
π
+ω×= 2
sin2)(' tItI (20)
where:
θ is the phase difference between the voltage and current channel.
V is the rms voltage.
I is the rms current.
q(t) = V(t) × I’(t) (21)
q(t) = VI sin (θ) + VI sin(2ωt + θ)
The average reactive power over an integral number of lines (n)
is given in Equation 22.
∫
θ==
nT
VIdttq
nT
Q
0
)sin()(
1
(22)
where:
T is the line cycle period.
q is referred to as the reactive power.
Note that the reactive power is equal to the dc component of
the instantaneous reactive power signal, q(t), in Equation 21.
The instantaneous reactive power signal, q(t), is generated by
multiplying the voltage and current channels. In this case, the
phase of the current channel is shifted by 90°. The dc component of
the instantaneous reactive power signal is then extracted by a
low-pass filter to obtain the reactive power information (see
Figure 72).
In addition, the phase-shifting filter has a nonunity magnitude
response. Because the phase-shifted filter has a large attenuation
at high frequency, the reactive power is primarily for calculation
at line frequency. The effect of harmonics is largely ignored in
the reactive power calculation. Note that, because of the magnitude
characteristic of the phase shifting filter, the weight of the reactive
power is slightly different from the active power calculation
(see the Energy Register Scaling section).
The frequency response of the LPF in the reactive signal path is
identical to the one used for LPF2 in the average active power
calculation. Because LPF2 does not have an ideal brick wall
frequency response (see Figure 65), the reactive power signal
has some ripple due to the instantaneous reactive power signal.
This ripple is sinusoidal and has a frequency equal to 2× the
line frequency. Because the ripple is sinusoidal in nature, it is
removed when the reactive power signal is integrated to
calculate energy.
The reactive power signal can be read from the waveform register
by setting the WAVMODE register (Address 0x0D) and the
WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB). Like the current and voltage channels waveform
sampling modes, the waveform data is available at sample rates
of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and 3.2 kSPS.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 66 of 156
Reactive Power Gain Calibration
Figure 72 shows the signal processing chain for the ADE5169/
ADE5569 reactive power calculation. As explained in the Reactive
Power Calculation (ADE5169/ADE5569) section, the reactive
power is calculated by applying a low-pass filter to the instanta-
neous reactive power signal. Note that, when reading the waveform
samples from the output of LPF2, the gain of the reactive energy
can be adjusted by using the multiplier and by writing a twos
complement, 12-bit word to the var gain register (VARGAIN,
Address 0x1E[11:0]). Equation 23 shows how the gain adjust-
ment is related to the contents of the var gain register.
Output VARGAIN =
+× 12
2
1VARGAIN
PowerReactive
(23)
The resolution of the VARGAIN register is the same as the
WGAIN register (Address 0x1D) (see the Active Power Gain
Calibration section). VARGAIN can be used to calibrate the
reactive power (or energy) calculation in the ADE5169/ADE5569.
Reactive Power Offset Calibration
The ADE5169/ADE5569 also incorporate a reactive power offset
register (VAROS, Address 0x21). This is a signed, twos comple-
ment, 16-bit register that can be used to remove offsets in the
reactive power calculation (see Figure 72). An offset can exist in
the reactive power calculation due to crosstalk between channels
on the PCB or in the IC itself. The offset calibration allows the
contents of the reactive power register to be maintained at 0 when
no power is being consumed.
The 256 LSBs (VAROS = 0x0100) written to the reactive power
offset register are equivalent to 1 LSB in the WAVMODE register
(Address 0x0D).
Sign of Reactive Power Calculation
Note that the average reactive power is a signed calculation.
The phase shift filter has −90° phase shift when the integrator
is enabled and +90° phase shift when the integrator is disabled.
Table 47 summarizes the relationship of the phase difference
between the voltage and the current and the sign of the resulting
var calculation.
Table 47. Sign of Reactive Power Calculation
Angle Integrator Sign
0° to +90° Off Positive
−90° to 0° Off Negative
0° to +90° On Positive
−90° to 0° On Negative
Reactive Power Sign Detection
The ADE5169/ADE5569 detect a change of sign in the reactive
power. The VARSIGN flag (Bit 4) in the Interrupt Status 1 SFR
(MIRQSTL, Address 0xDC) records when a change of sign has
occurred according to the VARSIGN bit (Bit 5) in the ACCMODE
register (Address 0x0F). If the VARSIGN bit (Bit 4) is set in the
Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), the 8052 core
has a pending ADE interrupt. The ADE interrupt stays active until
the VARSIGN status bit is cleared (see the Energy Measurement
Interrupts section).
When the VA R S IG N bit (Bit 5) in the ACCMODE register
(Address 0x0F) is cleared (default), a transition from positive to
negative reactive power sets the VARSIGN flag (Bit 4) in the
Interrupt Status 1 SFR (MIRQSTL, Address 0xDC).
When VARSIGN in the ACCMODE register (Address 0x0F)
is set, a transition from negative to positive reactive power sets
the VARSIGN flag in the Interrupt Status 1 SFR (MIRQSTL,
Address 0xDC).
Reactive Power No Load Detection
The ADE5169/ADE5569 include a no load threshold feature on the
reactive power that eliminates any creep effects in the meter. The
ADE5169/ADE5569 accomplish this by not accumulating reactive
energy when the multiplier output is below the no load threshold.
When the reactive power is below the no load threshold, the
RNOLOAD flag (Bit 1) in the Interrupt Status 1 SFR (MIRQSTL,
Address 0xDC) is set. If the RNOLOAD bit (Bit 1) is set in the
Interrupt Enable 1 SFR (MIRQENL, Address 0xD9), the 8052
core has a pending ADE interrupt. The ADE interrupt stays
active until the RNOLOAD status bit is cleared (see the Energy
Measurement Interrupts section).
The no load threshold level can be selected by setting the
VARNOLOAD bits (Bits[3:2])in the NLMODE register
(Address 0x0E). Setting these bits to 0b00 disables the no load
detection, and setting them to 0b01, 0b10, or 0b11 sets the no
load detection threshold to 0.015%, 0.0075%, and 0.0037% of
the full-scale output frequency of the multiplier, respectively.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 67 of 156
REACTIVE ENERGY CALCULATION
(ADE5169/ADE5569 ONLY)
As for active energy, the ADE5169/ADE5569 achieve the integra-
tion of the reactive power signal by continuously accumulating
the reactive power signal in an internal, nonreadable, 49-bit energy
register. The reactive energy register (VARHR, Address 0x04)
represents the upper 24 bits of this internal register. The VARHR
register and its function are available in the ADE5169/ADE5569.
The discrete time sample period (T) for the accumulation register
in the ADE5169/ADE5569 is 1.22 µs (5/MCLK). As well as
calculating the energy, this integration removes any sinusoidal
components that may be in the active power signal. Figure 72
shows this discrete time integration or accumulation. The
reactive power signal in the waveform register is continuously
added to the internal reactive energy register.
The reactive energy accumulation depends on the setting of
S AVA R M (Bit 2) and ABSVARM (Bit 3) in the ACCMODE
register (Address 0x0F). When both bits are cleared, the addition
is signed and, therefore, negative energy is subtracted from the
reactive energy contents. When both bits are set, the ADE5169/
ADE5569 are set to the more restrictive mode, which is the
absolute accumulation mode.
When the S AVA R M bit (Bit 2) in the ACCMODE register
(Address 0x0F) is set, the reactive power is accumulated
depending on the sign of the active power. When active power
is positive, the reactive power is added as it is to the reactive energy
register. When active power is negative, the reactive power is
subtracted from the reactive energy accumulator (see the Var
Antitamper Accumulation Mode section).
When the ABSVARM bit (Bit 3) in the ACCMODE register
(Address 0x0F) is set, the absolute reactive power is used for the
reactive energy accumulation (see the Var Absolute Accumulation
Mode section).
The output of the multiplier is divided by VARDIV. If the value
in the VARDIV register (Address 0x25) is equal to 0, the internal
reactive energy register is divided by 1. VARDIV is an 8-bit,
unsigned register. After dividing by VARDIV, the reactive energy is
accumulated in a 49-bit internal energy accumulation register.
The upper 24 bits of this register are accessible through a read to
the reactive energy register (VARHR, Address 0x04[23:0]). A read
to the RVARHR register (Address 0x05) returns the contents of
the VARHR register, and the upper 24 bits of the internal register
are cleared.
As shown in Figure 72, the reactive power signal is accumulated in
an internal 49-bit, signed register. The reactive power signal can be
read from the waveform register by setting the WAVMODE reg-
ister (Address 0x0D) and setting the WFSM bit (Bit 5) in the Inter-
rupt Enable 3 SFR (MIRQENH, Address 0xDB). Like the current
and voltage channel waveform sampling modes, the waveform data
is available at sample rates of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, and
3.2 kSPS.
Figure 67 shows this energy accumulation for full-scale signals
(sinusoidal) on the analog inputs. These curves also apply to the
reactive energy accumulation.
Note that the energy register contents roll over to full-scale
negative (0x800000) and continue to increase in value when
the power or energy flow is positive. Conversely, if the power is
negative, the energy register underflows to full-scale positive
(0x7FFFFF) and continues to decrease in value.
Using the Interrupt Enable 2 SFR (MIRQENM, Address 0xDA),
the ADE5169/ADE5569 can be configured to issue an ADE
interrupt to the 8052 core when the reactive energy register is
half full (positive or negative) or when an overflow or under-
flow occurs.
VARGAIN[11:0]
VARDIV[7:0]
LPF2
CURRENT
CHANNEL
VOLTAGE
CHANNEL
OUTPUT LPF2
TIME (nT)
5
MCLK
T
REACTIVE PO W ER
SIGNAL
++
V
ARHR[23:0
]
UPPE R 24 BITS ARE
ACCESS IBLE THRO UGH
VARHR[23: 0] RE GIS TER
23 0
48 0
WAVEFORM
REGISTER
VALUES
%
VAROS[15:0]
2
6
sgn 2
5
2
–6
2
–7
2
–8
+
+
FOR WAVEFORM
SAMPLING
HPF
PHCAL[7:0]
90° P HAS E
SHIFTING FILTER
OUTPUTS FROM THE LPF2 ARE
ACCUMUL ATED (INT E GRAT E D) IN
THE INTE RNAL REACTI V E E NE RGY
REGISTER
TO
DIGITAL-TO-FREQUENCY
CONVERTER
07411-047
2
Figure 72. Reactive Energy Calculation
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 68 of 156
Integration Time Under Steady Load—Reactive Energy
As mentioned in the Active Energy Calculation section, the
discrete time sample period (T) for the accumulation register is
1.22 µs (5/MCLK). With full-scale sinusoidal signals on the analog
inputs, and with the VARGAIN register (Address 0x1E) and the
VARDIV register (Address 0x25) set to 0x000, the integration time
before the reactive energy register overflows is calculated in
Equation 24.
Time =
min82.6sec6.409s22.1
0xCCCCD
FFFFFFFF0xFFFF ==µ×
(24)
When VARDIV is set to a value other than 0, the integration
time varies, as shown in Equation 25.
Time = TimeVARDIV = 0 × VARDIV (25)
Reactive Energy Accumulation Modes
Var Signed Accumulation Mode
The ADE5169/ADE5569 reactive energy default accumulation
mode is a signed accumulation based on the reactive power
information.
Var Antitamper Accumulation Mode
The ADE5169/ADE5569 are placed in var antitamper accumu-
lation mode by setting SAVARM (Bit 2) in the ACCMODE
register (Address 0x0F). In this mode, the reactive power is
accumulated depending on the sign of the active power. When the
active power is positive, the reactive power is added as it is to the
reactive energy register. When the active power is negative, the
reactive power is subtracted from the reactive energy accumu-
lator (see Figure 73). The CF pulse also reflects this accumulation
method when in this mode. The default setting for this mode is off.
Transitions in the direction of power flow and no load threshold
are active in this mode.
Var Absolute Accumulation Mode
The ADE5169/ADE5569 are placed in absolute accumulation
mode by setting ABSVARM (Bit 3) in the ACCMODE register
(Address 0x0F). In absolute accumulation mode, the reactive
energy accumulation is done by using the absolute reactive
power and ignoring any occurrence of power below the no load
threshold for the reactive energy (see Figure 74). The CF pulse
also reflects this accumulation method when in the absolute
accumulation mode. The default setting for this mode is off.
Transitions in the direction of power flow and no load threshold
are active in this mode.
POSPOS
INT E RRUP T STAT US RE GI S TERS
NEG
VARSI GN F LAG
ACTIVE POWER
NO LOAD
THRESHOLD
NO LOAD
THRESHOLD
REACTIVE E NE RGY
NO LOAD
THRESHOLD
REACTIVE POWER
NO LOAD
THRESHOLD
07411-048
Figure 73. Reactive Energy Accumulation in
Var Antitamper Accumulation Mode
REACT IVE E NE RGY
NO LOAD
THRESHOLD
NO LOAD
THRESHOLD
REACTIVE PO W ER
07411-049
Figure 74. Reactive Energy Accumulation in Absolute Accumulation Mode
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 69 of 156
Reactive Energy Pulse Output
The ADE5169/ADE5569 provide all the circuitry with a pulse
output whose frequency is proportional to reactive power (see
the Energy-to-Frequency Conversion section). This pulse fre-
quency output uses the calibrated signal from the VA R G A I N
register output, and its behavior is consistent with the setting of the
reactive energy accu-mulation mode in the ACCMODE register
(Address 0x0F). The pulse output is active low and should
preferably be connected to an LED, as shown in Figure 80.
Line Cycle Reactive Energy Accumulation Mode
In line cycle reactive energy accumulation mode, the energy
accumulation of the ADE5169/ADE5569 can be synchronized
to the voltage channel zero crossing so that reactive energy can
be accumulated over an integral number of half-line cycles. The
advantages of this mode are similar to those described in the
Line Cycle Active Energy Accumulation Mode section.
In line cycle active energy accumulation mode, the ADE5169/
ADE5569 accumulate the reactive power signal in the LVARHR
register (Address 0x06) for an integral number of line cycles, as
shown in Figure 75. The number of half-line cycles is specified
in the LINCYC register (Address 0x12). The ADE5169 /ADE5569
can accumulate active power for up to 65,535 half-line cycles.
Because the reactive power is integrated on an integral number
of line cycles, the CYCEND flag (Bit 2) in the Interrupt Status 3
SFR (MIRQSTH, Address 0xDE) is set at the end of a reactive
energy accumulation line cycle. If the CYCEND enable bit (Bit 2)
in the Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) is set,
the 8052 core has a pending ADE interrupt. The ADE interrupt
stays active until the CYCEND status bit is cleared (see the Energy
Measurement Interrupts section). Another calibration cycle starts
as soon as the CYCEND flag is set. If the LVARHR register
(Address 0x06) is not read before a new CYCEND flag is set, the
LVARHR register is overwritten by a new value.
When a new half-line cycle is written in the LINCYC register
(Address 0x12), the LVARHR register is reset, and a new
accumulation starts at the next zero crossing. The number of
half-line cycles is then counted internally until the value program-
med in LINCYC is reached. This implementation provides a valid
measurement at the first CYCEND interrupt after writing to the
LINCYC register. The line reactive energy accumulation uses
the same signal path as the reactive energy accumulation. The
LSB size of these two registers is equivalent.
LPF1
++
ACCUMUL ATE REACTI V E
ENERGY I N INT E RNAL
REG IST E R AND UP DATE
THE LVARHR REGI S TER
AT THE END OF LI NCY C
HALF-L INE CY CLES
OUTPUT
FROM
LPF2
FROM VOLTAGE
CHANNEL ADC
23 0
LINCYC[15:0]
48 0
%
ZERO-CROSSING
DETECTION
LVARHR[23:0]
CALIBRATION
CONTROL
VARDIV[7:0]VAROS[15:0]
VARGAIN[11:0]
TO
DIGITAL-TO-FREQUENCY
CONVERTER
07411-050
Figure 75. Line Cycle Reactive Energy Accumulation Mode
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 70 of 156
APPARENT POWER CALCULATION
Apparent power is defined as the maximum power that can be
delivered to a load. Vrms and Irms are the effective voltage and current
delivered to the load, respectively. Therefore, the apparent power
(AP) = Vrms × Irms. This equation is independent of the phase
angle between the current and the voltage.
Equation 29 gives an expression of the instantaneous power signal
in an ac system with a phase shift.
)sin(2)( θtVtV rms +ω×=
(26)
( )
)sin(2θ+ω×= tItI
rms
(27)
P(t) = V(t) × I(t) (28)
( )
)2cos()cos( θ+ω−θ= tIVIVtP rmsrmsrmsrms
(29)
Figure 76 illustrates the signal processing for the calculation of the
apparent power in the ADE5166/ADE5169/ADE5566/ADE5569.
The apparent power signal can be read from the waveform register
by setting the WAVMODE register (Address 0x0D) and setting the
WFSM bit (Bit 5) in the Interrupt Enable 3 SFR (MIRQENH,
Address 0xDB). Like the current and voltage channel waveform
sampling modes, the waveform data is available at sample rates
of 25.6 kSPS, 12.8 kSPS, 6.4 kSPS, or 3.2 kSPS.
The gain of the apparent energy can be adjusted by using the
multiplier and by writing a twos complement, 12-bit word to the
VAGAIN register (VAGAIN, Address 0x1F[11:0]). Equation 30
shows how the gain adjustment is related to the contents of the
VAGAIN register.
Output VAGAIN =
+×
12
2
1VAGAIN
PowerApparent
(30)
For example, when 0x7FF is written to the VAGAIN register, the
power output is scaled up by 50% (0x7FF = 2048d, 2047/212 = 0.5).
Similarly, 0x800 = −2048d (signed, twos complement), and power
output is scaled by −50%. Each LSB represents 0.0244% of the
power output. The apparent power is calculated with the current
and voltage rms values obtained in the rms blocks of the
ADE5166/ADE5169/ADE5566/ADE5569.
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation register
to calibrate and eliminate the dc component in the rms value
(see the Current Channel RMS Calculation section and the
Voltage Channel RMS Calculation section). The rms values of the
voltage and current channels are then multiplied together in the
apparent power signal processing. Because no additional offsets are
created in the multiplication of the rms values, there is no specific
offset compensation in the apparent power signal processing. The
offset compensation of the apparent power measurement is deter-
mined by calibrating each individual rms measurement.
APPARENT ENERGY CALCULATION
The apparent energy is given as the integral of the apparent power.
Apparent Energy =
∫ower(t)dtApparent P
(31)
The ADE5166/ADE5169/ADE5566/ADE5569 achieve the
integration of the apparent power signal by continuously accumu-
lating the apparent power signal in an internal 48-bit register.
The apparent energy register ( VA H R , Address 0x07) represents
the upper 24 bits of this internal register. This discrete time
accumulation or summation is equivalent to integration in
continuous time. Equation 32 expresses the relationship.
×= ∑
∞
=
→0
0
)(lim
n
T
TnTPowerApparentEnergyApparent
(32)
where:
n is the discrete time sample number.
T is the discrete time sample period.
The discrete time sample period (T) for the accumulation register
in the ADE5166/ADE5169/ADE5566/ADE5569 is 1.22 µs
(5/MCLK).
V
rms
I
rms 0x1A36E2
APPARENT POWER
SIGNAL (P)
CURRENT RM S S IGNAL – I ( t )
VOLT AGE RMS SIG NAL – V(t)
0x00
0x1CF68C
0x00
0x1CF68C
VAGAIN
TO
DIGITAL-TO-FREQUENCY
CONVERTER
VARMSCFCON
07411-051
Figure 76. Apparent Power Signal Processing
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 71 of 156
Figure 77 shows this discrete time integration or accumulation.
The apparent power signal is continuously added to the internal
register. This addition is a signed addition even if the apparent
energy theoretically remains positive.
The 49 bits of the internal register are divided by VADIV. If the
value in the VADIV register (Address 0x26) is 0, the internal
apparent energy register is divided by 1. VADI V i s a n 8 -bit,
unsigned register. The upper 24 bits are then written to the 24-bit
apparent energy register (VAHR, Address 0x07[23:0]). The
RVAHR register (Address 0x08), which is 24 bits long, is provided
to read the apparent energy. This register is reset to 0 after a read
operation.
Note that the apparent energy register is unsigned. By setting
VA E H F (Bit 2) and VA E O F (Bit 5) in the Interrupt Enable 2 SFR
(MIRQENM, Address 0xDA), the ADE5166/ADE5169/ADE5566/
ADE5569 can be configured to issue an ADE interrupt to the 8052
core when the apparent energy register is half full or when an over-
flow occurs. The half-full interrupt for the unsigned apparent
energy register is based on 24 bits, as opposed to 23 bits for the
signed active energy register.
Integration Times Under Steady Load—Apparent Energy
As mentioned in the Apparent Energy Calculation section, the
discrete time sample period (T) for the accumulation register is
1.22 µs (5/MCLK). With full-scale sinusoidal signals on the analog
inputs and the VAGAIN register (Address 0x1F) set to 0x000,
the average word value from the apparent power stage is 0x1A36E2
(see the Apparent Energy Calculation section). The maximum
value that can be stored in the apparent energy register before it
over-flows is 224 or 0xFF FFFF. The average word value is added
to the internal register, which can store 248 or 0xFFFF FFFF FFFF
before it overflows. Therefore, the integration time under these
conditions, wit h VA DI V = 0, is calculated as follows:
Time =
min33.3sec199s22.1
0xD055
FFFFFFFF,0xFFFF, ==µ×
(33)
When VADIV is set to a value other than 0, the integration time
varies, as shown in Equation 34.
Time = TimeVADIV = 0 × VADIV (34)
Apparent Energy Pulse Output
All the ADE5166/ADE5169/ADE5566/ADE5569 circuitry has
a pulse output whose frequency is proportional to the apparent
power (see the Energy-to-Frequency Conversion section). This
pulse frequency output uses the calibrated signal from the
VA GA I N register. This output can also be used to output a pulse
whose frequency is proportional to Irms.
The pulse output is active low and should preferably be connected
to an LED, as shown in Figure 80.
VADIV
APPARENT POWER
or
Irms
+
+
VAHR[23:0]
APPARE NT PO WER OR Irms IS
ACCUMUL ATED (INT E GRAT E D)
IN THE APP ARE NT ENE RGY
REGISTER
23 0
48
0
48 0
%
TIME (nT)
T
APPARENT
POWER SIGNAL = P
07411-052
Figure 77. Apparent Energy Calculation
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 72 of 156
Line Cycle Apparent Energy Accumulation Mode
The ADE5166/ADE5169/ADE5566/ADE5569 are designed with
a special apparent energy accumulation mode that simplifies the
calibration process. By using the on-chip, zero-crossing detection,
the ADE5166/ADE5169/ADE5566/ADE5569 accumulate the
apparent power signal in the LVAHR register (Address 0x09) for
an integral number of half cycles, as shown in Figure 78. The line
cycle apparent energy accumulation mode is always active.
The number of half-line cycles is specified in the LINCYC
register (Address 0x12), which is an unsigned 16-bit register.
The ADE5166/ADE5169/ADE5566/ADE5569 can accumulate
apparent power for up to 65,535 combined half cycles. Because
the apparent power is integrated on the same integral number
of line cycles as the line active register and reactive energy register,
these values can easily be compared. The energies are calculated
more accurately because of this precise timing control and provide
all the information needed for reactive power and power factor
calculation.
At the end of an energy calibration cycle, the CYCEND flag (Bit 2)
in the Interrupt Status 3 SFR (MIRQSTH, Address 0xDE) is set.
If the CYCEND enable bit (Bit 2) in the Interrupt Enable 3 SFR
(MIRQENH, Address 0xDB) is set, the 8052 core has a pending
ADE interrupt.
When a new half-line cycle is written in the LINCYC register
(Address 0x12), the LVAHR register (Address 0x09) is reset and a
new accumulation starts at the next zero crossing. The number of
half-line cycles is then counted until LINCYC is reached.
This implementation provides a valid measurement at the first
CYCEND interrupt after writing to the LINCYC register. The
line apparent energy accumulation uses the same signal path as
the apparent energy accumulation. The LSB size of these two
registers is equivalent.
Apparent Power No Load Detection
The ADE5166/ADE5169/ADE5566/ADE5569 include a no load
threshold feature on the apparent power that eliminates any creep
effects in the meter. The ADE5166/ADE5169/ADE5566/ADE5569
accomplish this by not accumulating energy if the multiplier output
is below the no load threshold. When the apparent power is
below the no load threshold, the VANOLOAD flag (Bit 2) in the
Interrupt Status 1 SFR (MIRQSTL, Address 0xDC) is set.
If the VANOLOAD bit (Bit 2) is set in the Interrupt Enable 1
SFR (MIRQENL, Address 0xD9), the 8052 core has a pending
ADE interrupt. The ADE interrupt stays active until the
VA NOLOAD status bit is cleared (see the Energy Measurement
Interrupts section).
The no load threshold level can be selected by setting the
VANOLOAD bits (Bits[5:4]) in the NLMODE register
(Address 0x0E). Setting these bits to 0b00 disables the no load
detection, and setting them to 0b01, 0b10, or 0b11 sets the no
load detection threshold to 0.030%, 0.015%, and 0.0075% of the
full-scale output frequency of the multiplier, respectively.
This no load threshold can also be applied to the Irms pulse
output when selected. In this case, the level of the no load
threshold is the same as for the apparent energy.
AMPERE-HOUR ACCUMULATION
In a tampering situation where no voltage is available to the energy
meter, the ADE5166/ADE5169/ADE5566/ADE5569 are capable
of accumulating the ampere-hours instead of apparent power into
th e VA H R (Address 0x07), RVA H R (Address 0x08), a n d LVA H R
(Address 0x09) registers. When VA R M SC F C O N (Bit 3) of the
MODE2 register (Address 0x0C) is set, the VAHR, RVA H R ,
and LVA H R registers and the input for the digital-to-frequency
converter accumulate Irms instead of apparent power. All the signal
processing and calibration registers available for apparent power
and energy accumulation remain the same when ampere-hour
accumulation is selected. However, the scaling difference between
Irms and apparent power requires independent values for gain cali-
bration in the VAGAIN (Address 0x1F), VA D I V (Address 0x26),
CFxNUM (Address 0x27 and Address 0x29), and CFxDEN
(Address 0x28 and Address 0x2A) registers.
LPF1
++
LVAHR[23:0]
LV AHR RE GIS TER IS
UPDAT E D E V E RY LINCY C
ZERO CROSSING WITH THE
TOTAL APP ARE NT ENE RGY
DURING THAT DURAT IO N
FROM
VO LTAGE CHANNE L
ADC
23 0
LINCYC[15:0]
48 0
%
ZERO-CROSSING
DETECTION CALIBR
ATION
CONTROL
VADIV[7:0]
APPARENT POWER
OR I
rms
07411-053
Figure 78. Line Cycle Apparent Energy Accumulation Mode
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 73 of 156
ENERGY-TO-FREQUENCY CONVERSION
The ADE5166/ADE5169/ADE5566/ADE5569 also provide two
energy-to-frequency conversions for calibration purposes. After
initial calibration at manufacturing, the manufacturer or end
customer often verifies the energy meter calibration. One conve-
nient way to do this is for the manufacturer to provide an output
frequency that is proportional to the active power, reactive power,
apparent power, or Irms under steady load conditions. This output
frequency can provide a simple single-wire, optically isolated
interface to external calibration equipment. Figure 79 illustrates
the energy-to-frequency conversion in the ADE5166/ADE5169/
ADE5566/ADE5569.
VAR*
*AVAI LABLE ONL Y IN T HE ADE 5169 AND ADE 5569.
VA
CFxSEL[1:0]
WATT
VARMSCFCON
MO DE 2 RE GIS TER 0x0C
I
rms
CFx P ULSE
OUTPUT
CFxNUM
CFxDEN
÷
DFC
07411-054
Figure 79. Energy-to-Frequency Conversion
Two digital-to-frequency converters (DFC) are used to generate
the pulsed outputs. When WDIV = 0 or 1, the DFC generates a
pulse each time 1 LSB in the energy register is accumulated. An
output pulse is generated when a CFxNUM/CFxDEN number of
pulses are generated at the DFC output. Under steady load con-
ditions, the output frequency is proportional to the active power,
reactive power, apparent power, or Irms, depending on the
CFxSEL bits in the MODE2 register (Address 0x0C).
Both pulse outputs can be enabled or disabled by clearing or
setting the DISCF1 bit (Bit 1) and the DISCF2 bit (Bit 2) in the
MODE1 register (Address 0x0B), respectively.
Both pulse outputs set separate flags in the Interrupt Status 2 SFR
(MIRQSTM, Address 0xDD): CF1 (Bit 6) and CF2 (Bit 7). If the
CF1 enable bit (Bit 6) and CF2 enable bit (Bit 7) in the Interrupt
Enable 2 SFR (MIRQENM, Address 0xDA) are set, the 8052 core
has a pending ADE interrupt. The ADE interrupt stays active
until the CF1 or CF2 status bit is cleared (see the Energy
Measurement Interrupts section).
Pulse Output Configuration
The two pulse output circuits have separate configuration bits
in the MODE2 register (Address 0x0C). Setting the CFxSEL bits
to 0b00, 0b01, or 0b1X configures the DFC to create a pulse output
proportional to active power, reactive power, or apparent power
or Irms, respectively.
The selection between Irms and apparent power is done by the
VA R M S C F C O N b i t ( B it 3) in the MODE2 register (Address 0x0C).
With this selection, CF2 cannot be proportional to apparent power
if CF1 is proportional to Irms, and CF1 cannot be proportional to
apparent power if CF2 is proportional to Irms.
Pulse Output Characteristic
The pulse output for both DFCs stays low for 90 ms if the pulse
period is longer than 180 ms (5.56 Hz). If the pulse period is
shorter than 180 ms, the duty cycle of the pulse output is 50%.
The pulse output is active low and should preferably be connected
to an LED, as shown in Figure 80.
VDD
CF
07411-055
Figure 80. CF Pulse Output
The maximum output frequency with ac input signals at
full scale and CFxNUM = 0x00 and CFxDEN = 0x00 is
approximately 21.1 kHz.
The ADE5166/ADE5169/ADE5566/ADE5569 incorporate two
registers per DFC, CFxNUM[15:0] and CFxDEN[15:0], to set
the CFx frequency. These unsigned, 16-bit registers can be used
to adjust the CFx frequency to a wide range of values, scaling
the output frequency by 1/216 to 1 with a step of 1/216.
If 0 is written to any of these registers, 1 is applied to the register.
The ratio of CFxNUM/CFxDEN should be <1 to ensure proper
operation. If the ratio of the CFxNUM/CFxDEN registers is >1,
the register values are adjusted to a ratio of 1. For example, if the
output frequency is 1.562 kHz, and the content of CFxDEN is 0
(0x000), the output frequency can be set to 6.1 Hz by writing 0xFF
to the CFxDEN register.
ENERGY REGISTER SCALING
The ADE5166/ADE5169/ADE5566/ADE5569 provide measure-
ments of active, reactive, and apparent energy that use separate
paths and filtering for calculation. The difference in data paths can
result in small differences in LSB weight between active, reactive,
and apparent energy registers. These measurements are internally
compensated so that the scaling is nearly one to one. The relation-
ship between these registers is shown in Table 48.
Table 48. Energy Registers Scaling
Line Frequency = 50 Hz
Line Frequency = 60 Hz
Integrator
Var = 0.9952 × watt Var = 0.9949 × watt Off
VA = 0.9978 × watt
VA = 1.0015 × watt
Off
Var = 0.9997 × watt Var = 0.9999 × watt On
VA = 0.9977 × watt VA = 1.0015 × watt On
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 74 of 156
ENERGY MEASUREMENT INTERRUPTS
The energy measurement part of the ADE5166/ADE5169/
ADE5566/ADE5569 has its own interrupt vector for the 8052 core,
Vector Address 0x004B (see the Interrupt Vectors section). The bits
set in the Interrupt Enable 1 SFR (MIRQENL, Address 0xD9),
Interrupt Enable 2 SFR (MIRQENM, Address 0xDA), and
Interrupt Enable 3 SFR (MIRQENH, Address 0xDB) enable the
energy measurement interrupts that are allowed to interrupt the
8052 core. If an event is not enabled, it cannot create a system
interrupt.
The ADE interrupt stays active until the status bit that created the
interrupt is cleared. The status bit is cleared when a 0 is written to
this register bit.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 75 of 156
TEMPERATURE, BATTERY, AND SUPPLY VOLTAGE MEASUREMENTS
The ADE5166/ADE5169/ADE5566/ADE5569 include tem-
perature measurements as well as battery and supply voltage
measurements. These measurements enable many forms of
compensation. The temperature and supply voltage measurements
can be used to compensate external circuitry. The RTC can be
calibrated over temperature to ensure that it does not drift. Supply
voltage measurements allow the LCD contrast to be maintained
despite variations in voltage. Battery measurements allow for low
battery detection.
All ADC measurements are configured through the SFRs, as
shown in Table 49.
The temperature, battery, and supply voltage measurements can
be configured to continue functioning in PSM1 and PSM2 modes.
Keeping the temperature measurement active ensures that it is
not necessary to wait for the temperature measurement to settle
before using it for compensation.
Table 49. Temperature, Battery, and Supply Voltage Measurement SFRs
SFR
Address R/W Mnemonic Description
0xF9 R/W STRBPER Peripheral ADC strobe period (see Table 50).
0xF3 R/W DIFFPROG Temperature and supply delta (see Table 51).
0xD8 R/W ADCGO Start ADC measurement (see Table 52).
0xFA R/W BAT V TH Battery detection threshold (see Table 53).
0xEF R/W VDCINADC VDCINADC value (see Table 54).
0xDF
R/W
BATADC
Battery ADC value (see Table 55).
0xD7
R/W
TEMPADC
Temperature ADC value (see Table 56).
Table 50. Peripheral ADC Strobe Period SFR (STRBPER, Address 0xF9)
Bit Mnemonic Default Description
[7:6] Reserved 00 These bits must be kept at 0 for proper operation.
[5:4] VDCIN_PERIOD 00
Period for background external voltage measurements.
VDCIN_PERIOD Result
00 No VDCIN measurement
01 8 min
10 2 min
11 1 min
[3:2] BATT_PERIOD 00 Period for background battery level measurements.
BATT_PERIOD Result
00 No battery measurement
01 16 min
10 4 min
11
1 min
[1:0] TEMP_PERIOD 00 Period for background temperature measurements.
TEMP_PERIOD Result
00 No temperature measurement
01 8 min
10 2 min
11 1 min
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 76 of 156
Table 51. Temperature and Supply Delta SFR (DIFFPROG, Address 0xF3)
Bit Mnemonic Default Description
[7:6] Reserved 00 Reserved.
[5:3] TEMP_DIFF 00 Difference threshold between last temperature measurement interrupting 8052 and new
temperature measurement that should interrupt 8052.
TEMP_DIFF Result
000 No interrupt
001 1 LSB (~ 0.8°C)
010 2 LSB (~ 1.6°C)
011 3 LSB (~ 2.4°C)
100 4 LSB (~ 3.2°C)
101 5 LSB (~ 4°C)
110 6 LSB (~ 4.8°C)
111
Every temperature measurement
[2:0] VDCIN_DIFF 00 Difference threshold between the last external voltage measurement interrupting 8052 and the new
external voltage measurement that should interrupt 8052.
VDCIN_DIFF Result
000 No interrupt
001 1 LSB (~ 120 mV)
010 2 LSB (~ 240 mV)
011 3 LSB (~ 360 mV)
100 4 LSB (~ 480 mV)
101 5 LSB (~ 600 mV)
110 6 LSB (~ 720 mV)
111 Every VDCIN measurement
Table 52. Start ADC Measurement SFR (ADCGO, Address 0xD8)
Bit Bit Address Mnemonic Default Description
7 0xDF PLLACK 0 Set this bit to clear the PLL fault bit, PLL_FLT (Bit 4), in the PERIPH SFR (Address 0xF4).
A PLL fault is generated if a reset is caused because the PLL lost lock.
[6:3] 0xDE to 0xDB Reserved 0000 Reserved.
2 0xDA VDCIN_ADC_GO 0 Set this bit to initiate an external voltage measurement. This bit is cleared when
the measurement request is received by the ADC.
1 0xD9 TEMP_ADC_GO 0 Set this bit to initiate a temperature measurement. This bit is cleared when the
measurement request is received by the ADC.
0
0xD8
BATT_ADC_GO
0
Set this bit to initiate a battery measurement. This bit is cleared when the
measurement request is received by the ADC.
Table 53. Battery Detection Threshold SFR (BATVTH, Address 0xFA)
Bit Mnemonic Default Description
[7:0] BATVTH 0 The battery ADC value is compared to this register, the battery detection threshold register.
If BATADC is lower than the threshold, an interrupt is generated.
Table 54. VDCINADC Value SFR (VDCINADC, Address 0xEF)
Bit Mnemonic Default Description
[7:0] VDCINADC 0 The VDCINADC value in this register is updated when an ADC interrupt occurs.
Table 55. Battery ADC Value SFR (BATADC, Address 0xDF)
Bit Mnemonic Default Description
[7:0] BATADC 0 The battery ADC value in this register is updated when an ADC interrupt occurs.
Table 56. Temperature ADC Value SFR (TEMPADC, Address 0xD7)
Bit Mnemonic Default Description
[7:0] TEMPADC 0 The temperature ADC value in this register is updated when an ADC interrupt occurs.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 77 of 156
TEMPERATURE MEASUREMENT
To provide a digital temperature measurement, each ADE5166/
ADE5169/ADE5566/ADE5569 includes a dedicated ADC. The
8-bit temperature ADC value SFR (TEMPADC, Address 0xD7)
holds the results of the temperature conversion. The resolution of
the temperature measurement is 0.83°C/LSB. There are two ways
to initiate a temperature conversion: a single temperature measure-
ment or background temperature measurements.
Single Temperature Measurement
Set the TEMP_ADC_GO bit (Bit 1) in the start ADC measure-
ment SFR (ADCGO, Address 0xD8) to obtain a temperature
measurement (see Table 52). An interrupt is generated when the
conversion is complete and when the temperature measurement
is available in the temperature ADC value SFR (TEMPADC,
Address 0xD7).
Background Temperature Measurements
Background temperature measurements are disabled by default.
To configure the background temperature measurement mode,
set a temperature measurement interval in the peripheral ADC
strobe period SFR (STRBPER, Address 0xF9). Temperature mea-
surements are then performed periodically in the background (see
Table 50).
When a temperature conversion completes, the new temperature
ADC value is compared to the last temperature ADC value that
created an interrupt. If the absolute difference between the two
values is greater than the setting of the TEMP_DIFF bits in the
temperature and supply delta SFR (DIFFPROG, Address 0xF3[5:3]),
a TEMPADC interrupt is generated (see Table 51). This allows
temperature measurements to take place completely in the back-
ground, requiring MCU activity only if the temperature changes
more than a configurable delta.
To set up background temperature measurement
1. Initiate a single temperature measurement by setting the
TEMP_ADC_GO bit in the start ADC measurement SFR
(ADCGO, Address 0xD8[1]).
2. Upon completion of this measurement, configure the
TEMP_DIFF bits in the temperature and supppy delta SFR
(DIFFPROG, Address 0xF3[5:3]) to establish the change in
temperature that triggers an interrupt.
3. Set up the interval for background temperature measurements
by configuring the TEMP_PERIOD bits in the peripheral
ADC strobe period SFR (STRBPER, Address 0xF9[1:0]).
Temperature ADC in PSM0, PSM1, and PSM2 Modes
Depending on the operating mode of the ADE5166/ADE5169/
ADE5566/ADE5569, a temperature conversion is initiated only
by certain actions.
• In PSM0 operating mode, the 8052 is active. Temperature
measurements are available in the background measurement
mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active, and the part
is battery powered. Single temperature measurements
can be initiated by setting the TEMP_ADC_GO bit in the
start ADC measurement SFR (ADCGO, Address 0xD8[1]).
Background temperature measurements are not available.
• In PSM2 operating mode, the 8052 is not active. Temperature
conversions are available through the background measure-
ment mode only.
The temperature ADC value SFR (TEMPADC, Address 0xD7)
is updated with a new value only when a temperature ADC
interrupt occurs.
Temperature ADC Interrupt
The temperature ADC can generate an ADC interrupt when at
least one of the following conditions occurs:
• The difference between the new temperature ADC value and
the last temperature ADC value generating an ADC interrupt
is larger than the value set in the TEMP_DIFF bits.
• The temperature ADC conversion, initiated by setting start
ADC measurement SFR (ADCGO, Address 0xD8), finishes.
When the ADC interrupt occurs, a new value is available in the
temperature ADC value SFR (T EMPA DC, Address 0xD7). Note
that there is no flag associated with this interrupt.
BATTERY MEASUREMENT
To provide a digital battery measurement, each ADE5166/
ADE5169/ADE5566/ADE5569 includes a dedicated ADC. The
battery measurement is available in the 8-bit battery ADC value
SFR (BATADC, Address 0xDF). The battery measurement has a
resolution of 14.6 mV/LSB. A battery conversion can be initiated
by two methods: a single battery measurement or background
battery measurements.
Single Battery Measurement
To obtain a battery measurement, set the BATT_ADC_GO bit in
the start ADC measurement SFR (ADCGO, Address 0xD8[0]).
An interrupt is generated when the conversion is done and when
the battery measurement is available in the battery ADC value SFR
(BATADC, Address 0xDF).
Background Battery Measurements
To c onfigure background measurements for the battery, establish a
measurement interval in the peripheral ADC strobe period SFR
(STRBPER, Address 0xF9). Battery measurements are then
performed periodically in the background (see Table 50).
When a battery conversion completes, the battery ADC value is
compared to the low battery threshold, established in the battery
detection threshold SFR (BATVTH, Address 0xFA). If the battery
ADC value is below this threshold, a low battery flag is set. This
low battery flag is the FBAT bit (Bit 2) in the power management
interrupt flag SFR (IPSMF, Address 0xF8), used for power supply
management. This low battery flag can be enabled to generate
the PSM interrupt by setting the EBAT bit (Bit 2) in the power
management interrupt enable SFR (IPSME, Address 0xEC).
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 78 of 156
This method allows battery measurement to take place completely
in the background, requiring MCU activity only if the battery
drops below a user-specified threshold. To set up background
battery measurements, follow these steps:
1. Configure the battery detection threshold SFR (BATVTH,
Address 0xFA) to establish a low battery threshold. If the
BATADC measurement is below this threshold, the FBAT bit
(Bit 2) in the power management interrupt flag SFR ( I P SM F,
Address 0xF8) is set.
2. Set up the interval for background battery measurements
by configuring the BATT_PERIOD bits in the peripheral
ADC strobe period SFR (STRBPER, Adress 0xF9[3:2]).
Battery ADC in PSM0, PSM1, and PSM2 Modes
Depending on the operating mode, a battery conversion is
initiated only by certain actions.
• In PSM0 operating mode, the 8052 is active. Battery mea-
surements are available in the background measurement
mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active, and the part
is battery powered. Single battery measurements can be
initiated by setting the BATT_ADC_GO bit in the start
ADC measurement SFR (ADCGO, Address 0xD8[0]).
Background battery measurements are not available.
• In PSM2 operating mode, the 8052 is not active. Unlike
temperature and VDCIN measurements, the battery
conversions are not available in this mode.
Battery ADC Interrupt
The battery ADC can generate an ADC interrupt when at least
one of the following conditions occurs:
• The new battery ADC value is smaller than the value
set in the battery detection threshold SFR (BATVTH,
Address 0xFA), indicating a battery voltage loss.
• A single battery measurement, initiated by setting the
BATT_ADC_GO bit in the start ADC measurement SFR
(ADCGO, Address 0xD8[0]), finishes.
When the battery flag (FBAT, Bit 2) is set in the power manage-
ment interrupt flag SFR (IPSMF, Address 0xF8), a new ADC
value is available in the battery ADC value SFR (BATADC,
Address 0xDF). This battery flag can be enabled as a source of the
PSM interrupt to generate a PSM interrupt every time the battery
drops below a set voltage threshold or after a single conversion
initiated by setting the BATT_ADC_GO bit in the start ADC
measurement SFR (ADCGO, Address 0xD8[0]) is ready.
The battery ADC value SFR (BATADC, Address 0xDF) is updated
with a new value only when the battery flag (FBAT) is set in the
power management interrupt flag SFR (IPSMF, Address 0xF8).
EXTERNAL VOLTAGE MEASUREMENT
The ADE5166/ADE5169/ADE5566/ADE5569 include a dedicated
ADC to provide a digital measurement of an external voltage on
the VDCIN pin. The 8-bit VDCINADC value SFR (VDCINADC,
Address 0xEF) holds the results of the conversion. The resolution
of the external voltage measurement is 15.3 mV/LSB. There are
two ways to initiate an external voltage conversion: by using a single
external voltage measurement or through background external
voltage measurements.
Single External Voltage Measurement
To obtain an external voltage measurement, set the VDCIN_
ADC_GO bit in the start ADC measurement SFR (ADCGO,
Address 0xD8[2]). An interrupt is generated when the conversion
is done and when the external voltage measurement is available
in the VDCINADC value SFR (VDCINADC, Address 0xEF).
Background External Voltage Measurements
Background external voltage measurements are disabled by
default. To configure the background external voltage measure-
ment mode, set an external voltage measurement interval in the
peripheral ADC strobe period SFR (STRBPER, Address 0xF9).
External voltage measurements are performed periodically in
the background (see Table 50).
When an external voltage conversion is complete, the new
external voltage ADC value is compared to the last external
voltage ADC value that created an interrupt. If the absolute
difference between the two values is greater than the setting of
the VDCIN_DIFF bits in the temperature and supply delta SFR
(DIFFPROG, Address 0xF3[2:0]), a VDCINADC flag is set. This
VDCINADC flag is FVADC (Bit 3) in the power management
interrupt flag SFR (IPSMF, Address 0xF8), which is used for power
supply management. This VDCINADC flag can be enabled to
generate a PSM interrupt by setting the EVA D C bit (Bit 3) in the
power management interrupt enable SFR (IPSME, Address 0xEC).
This method allows external voltage measurements to take
place completely in the background, requiring MCU activity
only if the external voltage has changed more than a confi-
gurable delta.
To set up background external voltage measurements
1. Initiate a single external voltage measurement by setting
the VDCIN_ADC_GO bit in the start ADC measurement
SFR (ADCGO, Address 0xD8[2]).
2. Upon completion of this measurement, configure the
VDCIN_DIFF bits in the temperature and supply delta SFR
(DIFFPROG, Address 0xF3[2:0]) to establish the change
in voltage that sets the FVADC bit in the power manage-ment
interrupt flag SFR (IPSMF, Address 0xF8[3]).
3. Set up the interval for the background external voltage
measurements by configuring the VDCIN_PERIOD bits in
the peripheral ADC strobe period SFR (STRBPER,
Address 0xF9[5:4]).
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 79 of 156
External Voltage ADC in PSM1 and PSM2 Modes
An external voltage conversion is initiated only by certain actions
that depend on the operating mode of the ADE5166/ADE5169/
ADE5566/ADE5569.
• In PSM0 operating mode, the 8052 is active. External
voltage measurements are available in the background
measurement mode and by initiating a single measurement.
• In PSM1 operating mode, the 8052 is active and the part is
powered from battery. Single external voltage measurements
can be initiated by setting VDCIN_ADC_GO in the start
ADC measurement SFR (ADCGO, Address 0xD8[2]).
Background external voltage measurements are not available.
• In PSM2 operating mode, the 8052 is not active. External
voltage conversions are available through the background
measurement mode only.
The external voltage ADC in the VDCINADC value SFR
(VDCINADC, Address 0xEF) is updated with a new value
only when an external voltage ADC interrupt occurs.
External Voltage ADC Interrupt
The external voltage ADC can generate an ADC interrupt when
at least one of the following conditions occurs:
• The difference between the new external voltage ADC
value and the last external voltage ADC value generating
an ADC interrupt is larger than the value set in the
VDCIN_DIFF bits in the temperature and supply delta
SFR (DIFFPROG, Address 0xF3[2:0]).
• The external voltage ADC conversion, initiated by setting
the VDCIN_ADC_GO bit in the start ADC measurement
SFR (ADCGO, Address 0xD8[2]), finishes.
When the ADC interrupt occurs, a new value is available in the
VDCINADC value SFR (VDCINADC, Address 0xEF). Note that
there is no flag associated with this interrupt.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 80 of 156
8052 MCU CORE ARCHITECTURE
The ADE5166/ADE5169/ADE5566/ADE5569 have an 8052 MCU
core and use the 8051 instruction set. Some of the standard 8052
peripherals, such as the UART, have been enhanced. This section
describes the standard 8052 core and enhancements that have
been made to it in the ADE5166/ADE5169/ADE5566/ADE5569.
The special function register (SFR) space is mapped into the upper
128 bytes of internal data memory space and is accessed by direct
addressing only. It provides an interface between the CPU and all
on-chip peripherals. See Figure 81 for a block diagram showing
the programming model of the ADE5166/ADE5169/ADE5566/
ADE5569 via the SFR area.
All registers except the program counter (PC), instruction register
(IR), and the four general-purpose register banks reside in the
SFR area. The SFRs include control, configuration, and data
registers that provide an interface between the CPU and all on-
chip peripherals.
ENERGY
MEASUREMENT
PC
62kB EL E CTRICALL Y
REPROGRAMMABLE
NONVOLATILE
FLASH/EE
PROGRAM/DATA
MEMORY
8051-COMPATIBLE
CORE
2kB XRAM OT HE R ON-CHIP
PERIPHERALS:
SERIAL I/O
WDT
TIMERS
BATTERY
ADC
LCD DRIVER
TEMPERATURE
ADC
RTC
POWER
MANAGEMENT
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
IR
256 BYT E S
GENERAL-
PURPOSE
RAM
REGISTER
BANKS
07411-056
Figure 81. Block Diagram Showing Programming Model via the SFRs
MCU REGISTERS
The registers used by the MCU are summarized in Table 57.
Table 57. 8051 SFRs
Table 58. Program Status Word SFR (PSW, Address 0xD0)
Bit Bit
Address
Mnemonic Description
7 0xD7 CY Carry flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
6 0xD6 AC Auxiliary carry flag. Modified by ADD and ADDC instructions.
5 0xD5 F0 General-purpose flag available to the user.
[4:3] 0xD4,
0xD3
RS1, RS0 Register bank select bits.
RS1 RS0 Selected Bank
0
0
0
0 1 1
1 0 2
1 1 3
2 0xD2 OV Overflow flag. Modified by ADD, ADDC, SUBB, MUL, and DIV instructions.
1 0xD1 F1 General-purpose flag available to the user.
0 0xD0 P Parity bit. The number of bits set in the accumulator added to the value of the parity bit is always an
even number.
SFR Address Bit Addressable Description
ACC
0xE0
Yes
Accumulator.
B 0xF0 Yes Auxiliary math.
PSW 0xD0 Yes Program status word (see Table 58).
PCON 0x87 No Program control (see Table 59).
DPL 0x82 No Data pointer low (see Table 60).
DPH 0x83 No Data pointer high (see Table 61).
DPTR 0x82 and 0x83 No Data pointer (see Table 62).
SP 0x81 No Stack pointer (see Table 63).
SPH 0xB7 No Stack pointer high (see Table 64).
STCON 0xBF No Stack boundary (see Table 65).
CFG 0xAF No Configuration (see Table 66).
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 81 of 156
Table 59. Program Control SFR (PCON, Address 0x87)
Bit Mnemonic Default Description
7 SMOD 0 Double baud rate control.
[6:0] Reserved 0 Reserved. These bits must be kept at 0 for proper operation.
Table 60. Data Pointer Low SFR (DPL, Address 0x82)
Bit Mnemonic Default Description
[7:0] DPL 0 These bits contain the low byte of the data pointer.
Table 61. Data Pointer High SFR (DPH, Address 0x83)
Bit Mnemonic Default Description
[7:0] DPH 0 These bits contain the high byte of the data pointer.
Table 62. Data Pointer SFR (DPTR, Address 0x82 and Address 0x83)
Bit Mnemonic Default Description
[15:0] DP 0 These bits contain the 2-byte address of the data pointer. DPTR is a combination of the DPH and DPL SFRs.
Table 63. Stack Pointer SFR (SP, Address 0x81)
Bit Mnemonic Default Description
[7:0] SP 0 These bits contain the eight LSBs of the pointer for the stack.
Table 64. Stack Pointer High SFR (SPH, Address 0xB7)
Bit Mnemonic Default Description
7 Reserved 1 Reserved. This bit must be set to 1 for proper operation.
6 SBFLG 0 Stack bottom flag.
5 SSA[10] 0 Stack Starting Address Bit 10.
4 SSA[9] 0 Stack Starting Address Bit 9.
3
SSA[8]
1
Stack Starting Address Bit 8.
2 SP[10] 0 Stack Address Bit 10.
1 SP[9] 0 Stack Address Bit 9.
0 SP[8] 1 Stack Address Bit 8.
Table 65. Stack Boundary SFR (STCON, Address 0xBF)
Bit Mnemonic Default Description
[7:3] WTRLINE 0 Contains the stack waterline setting bits.
2 INT_RST 0 Interrupt/reset selection bit.
INT_RST
Result
0 An interrupt is issued when a stack violation occurs
1 A reset is issued when a stack violation occurs
1 SBE 0 Stack boundary enable bit.
0 WTRLFG 0 Waterline flag.
Table 66. Configuration SFR (CFG, Address 0xAF)
Bit Mnemonic Default Description
7 Reserved 1 Reserved. This bit should be left set for proper operation.
6 EXTEN 0 Enhanced UART enable bit.
EXTEN Result
0 Standard 8052 UART without enhanced error checking features
1 Enhanced UART with enhanced error checking (see the UART Additional Features section)
5 SCPS 0 Synchronous communication selection bit.
SCPS Result
0 I2C port is selected for control of the shared I2C/SPI (MOSI, MISO, SCLK, and SS) pins and SFRs
1 SPI port is selected for control of the shared I2C/SPI (MOSI, MISO, SCLK, and SS) pins and SFRs
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 82 of 156
Bit Mnemonic Default Description
4 MOD38EN 0 38 kHz modulation enable bit.
MOD38EN
Result
0 38 kHz modulation is disabled
1 38 kHz modulation is enabled on the pins selected by the MOD38 bits in the
EPCFG SFR (Address 0x9F[7:0])
[3:2] Reserved 00 Reserved. These bits should be kept at 0 for proper operation.
[1:0] XREN1,
XREN0
01 XREN1, XREN0 Result
XREN1 or XREN0 = 1 Enable MOVX instruction to use 256 bytes of extended RAM
XREN1 and XREN0 = 0 Disable MOVX instruction
BASIC 8052 REGISTERS
Program Counter (PC)
The program counter holds the 2-byte address of the next instruc-
tion to be fetched. The PC is initialized with 0x00 at reset and is
incremented after each instruction is performed. Note that the
amount that is added to the PC depends on the number of bytes
in the instruction; therefore, the increment can range from one
to three bytes. The program counter is not directly accessible to
the user but can be directly modified by CALL and JMP instruc-
tions that change which part of the program is active.
Instruction Register (IR)
The instruction register holds the opcode of the instruction being
executed. The opcode is the binary code that results from assem-
bling an instruction. This register is not directly accessible to
the user.
Register Banks
There are four banks, each containing an 8-byte-wide register, for
a total of 32 bytes of registers. These registers are convenient for
temporary storage of mathematical operands. An instruction in-
volving the accumulator and a register can be executed in one clock
cycle, as opposed to two clock cycles, to perform an instruction
involving the accumulator and a literal or a byte of general-purpose
RAM. The register banks are located in the first 32 bytes of RAM.
The active register bank is selected by RS0 and RS1 in the
program status wo r d S F R ( P S W, Address 0xD0[4:3]).
Accumulator
The accumulator is a working register, storing the results of many
arithmetic or logical operations. The accumulator is used in
more than half of the 8052 instructions, where it is usually
referred to as A. The program status word SFR (PSW) constantly
monitors the number of bits that are set in the accumulator to
determine if it has even or odd parity. The accumulator is stored
in the SFR space (see Table 57).
B Register
The B register is used by the multiply and divide instructions,
MUL AB and DIV AB, to hold one of the operands. Because it
is not used for many instructions, it can be used as a scratch pad
register like those in the register banks. The B register is stored
in the SFR space (see Table 57).
Program Status Word (PSW)
The PSW SFR (PSW, Address 0xD0) reflects the status of
arithmetic and logical operations through carry, auxiliary carry,
and overflow flags. The parity flag reflects the parity of the contents
of the accumulator, which can be helpful for communication
protocols. The program status word SFR is bit addressable (see
Table 58).
Data Pointer (DPTR)
The data pointer SFR (DPTR, Address 0x82 and Address 0x83)
is made up of two 8-bit registers: DPL (low byte, Address 0x82),
and DPH (high byte, Address 0x83). These SFRs provide memory
addresses for internal code and data access. The DPTR can be
manipulated as a 16-bit register (DPTR = DPH, DPL) or as two
independent 8-bit registers (DPH and DPL) (see Table 60 and
Table 61).
The 8052 MCU core architecture supports dual data pointers
(see the 8052 MCU Core Architecture section).
Stack Pointer (SP)
The stack pointer SFR (SP, Address 0x81) keeps track of the
current address of the top of the stack. To push a byte of data
onto the stack, the stack pointer is incremented, and the data is
moved to the new top of the stack. To pop a byte of data off the
stack, the top byte of data is moved into the awaiting address,
and the stack pointer is decremented. The stack uses a last in,
first out (LIFO) method of data storage because the most recent
addition to the stack is the first to come off it.
The stack is used during CALL and RET instructions to keep
track of the address to move into the PC when returning from
the function call. The stack is also manipulated when vectoring
for interrupts, to keep track of the prior state of the PC.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 83 of 156
The stack resides in the upper part of the extended internal RAM.
The SP bits in the stack pointer SFR (SP, Address 0x81[7:0]) and the
SP bits in the stack pointer high SFR (SPH, Address 0xB7[2:0])
hold the address of the stack in the extended RAM. The advantage
of this solution is that the use of the general-purpose RAM can
be limited to data storage. The use of the extended internal RAM
can be limited to the stack or, alternatively, split between the stack
and data storage if more space is required. This separation limits
the chance of data corruption because the stack can be contained
in the upper section of the XRAM and does not overflow into
the lower section containing data. Data can still be stored in
extended RAM by using the MOVX command.
The default starting address for the stack is 0x100, electing the
upper 1792 bytes of XRAM for the stack operation. The starting
address can be reconfigured to reduce the stack by writing to the
SSA bits in the stack pointer high SFR (SPH, Address 0xB7[5:3]).
These three bits set the value of the three most significant bits of
the stack pointer. For example, setting the SSA bits to a value of
110b moves the default starting address of the stack to 0x600,
allowing the highest 512 bytes of the XRAM to be used for stack
operation. If the stack reaches the top of the XRAM and overflows,
the stack pointer rolls over to the default starting address that is
written in the SSA bits (Address 0xB7[5:3]). Care should be taken
if altering the default starting address of the stack because, should
the stack overflow or underflow, unwanted overwrite operations
may occur.
Stack Boundary Protection
As a warning signal that the stack pointer is extending outside
the specified range, a stack boundary protection feature is included.
This feature is controlled through the stack boundary SFR
(STCON, Address 0xBF) and is disabled by default. To enable
this feature, set the boundary protection enable bit (SBE, Bit 1)
in the STCON SFR.
The stack boundary protection works in two ways to protect the
remainder of the XRAM from being corrupted. The waterline
detection feature monitors the top of the stack and warns the user
when the stack pointer is reaching the overflow point. By setting
the WTRLINE bits in the STCON SFR (Address 0xBF[7:3]), the
level of the waterline below the top of the XRAM can be set. For
example, by setting STCON[7:3] to the maximum value of 0x1F,
the waterline is set to its minimum value of 0x7FF − 0x1F = 0x7F0.
Similarly, by setting STCON[7:3] to 0x1, the waterline is set at the
top of the RAM space, Address 0x7FE. Note that if STCON[7:3]
are set to 000b, the feature is effectively disabled and no interrupt
or reset is generated.
The bottom of the stack is also preserved by the stack boundary
feature. Should the stack pointer be written to a value lower than
the default stack starting address defined in Bits[5:3] of the SPH
SFR, a warning is issued and the perpetrating command is ignored.
The protection for both the waterline and the stack starting
addresses are enabled simultaneously by setting the SBE bit in
the STCON SFR (Address 0xBF[1]).
When enabled, the stack boundary protection can be configured
to either reset the part or trigger an interrupt when a stack viola-
tion occurs. The value of the INT_RST bit of the STCON SFR
(Address 0xBF[2]) determines the response of the part. When
STCON[2] is set to 0x1 and the stack pointer exceeds the waterline,
the part resets immediately, no matter what other routines are
in progress. If an attempt is made to move the stack pointer below
the default stack starting address when STCON[2] is high, a reset
also occurs. If an interrupt response is selected, the watchdog
interrupt service routine is entered, assuming that there is no
higher level interrupt currently being serviced. Note that when
STCON[1] (SBE) is enabled, an interrupt (or reset) is triggered
if the stack boundary is violated, regardless of the status of the
EA bit in the interrupt enable SFR (IE, Address 0xA8[7]). This is
because the watchdog interrupt is automatically configured as a
high priority interrupt and, therefore, is not disabled by clearing
EA. When STCON[1] is low, the feature is completely disabled,
and no pending interrupts are generated.
There are two separate flags associated with the stack boundary
protection, allowing the cause of the violation to be determined.
When the waterline is exceeded, a flag is set in WTRLFG of the
stack boundary SFR (STCON, Address 0xBF[0]), indicating that
the reset/interrupt was initiated by the stack waterline monitor.
This flag remains high until the stack pointer falls below the water-
line and the user clears the flag in software. A waterline or
watchdog reset alone does not clear the flag. To successfully clear
the flag, the software clear must occur while the stack pointer is
below the waterline.
Note that the stack pointer should never be altered while in the
interrupt service routine. Doing so causes the program to return
to a different section of the program and, therefore, malfunction.
An external reset also causes the waterline flag to reset.
When an attempt is made to move the stack pointer below the stack
starting address, a flag (SBFLG) is set in the stack pointer high
SFR (SPH, Address 0xB7[6]), indicating that the reset/interrupt
was initiated by the stack bottom monitor. Once again, a boundary
or watchdog reset alone does not clear this flag, and the user must
clear the flag in software to successfully acknowledge the event.
Note that if SPH[5:3] and SPH[2:0] are altered simultaneously
to reduce the default stack starting address, a stack violation
condition occurs when the stack boundary condition is enabled,
and SPH[6] (the stack bottom flag, SBFLG) is initiated. To avoid
this condition, it is recommended that the default stack starting
address remain at 0x100 or be increased to further up the XRAM.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 84 of 156
A useful implementation of the waterline feature is to determine
the amount of space required for the stack and allow a suitable
default starting address to be selected. This optimizes the use
of the additional XRAM space, allowing it to be used for data
storage. To obtain this information, the waterline should be set
to the estimated stack maximum and the interrupt enabled.
If the stack exceeds the estimated maximum, the interrupt is trig-
gered, and the waterline level should be increased in the interrupt
service routine. Before returning to the main program, the
waterline interrupt status flag (WTRLFG, Bit 0) of the stack
boundary SFR (STCON, Address 0xBF) should be cleared. This
program continues to jump to the waterline service routine
until the stack no longer exceeds the waterline level and the
maximum stack level is determined.
0xFF
0x7FF
256 BYT E S
OF RAM
(DATA)
0x00
{SPH[ 5: 3] , 0x00}
0x7FF-STCON[7:3]
2kB OF
ON-CHIP XRAM
STACK STARTING
ADDRESS
WATERLINE
0x00
07411-119
Figure 82. Extended Stack Pointer Operation
STANDARD 8052 SFRS
The standard 8052 SFRs include the accumulator (ACC), B, PSW,
DPTR, and SP SFRs, as described in the Basic 8052 Registers
section. The 8052 also defines standard timers, serial port inter-
faces, interrupts, I/O ports, and power-down modes.
Timer SFRs
The 8052 contains three 16-bit timers, the identical Timer 0 and
Timer 1, as well as a Timer 2. These timers can also function as
event counters. Timer 2 has a capture feature in which the value
of the timer can be captured in two 8-bit registers upon the
assertion of an external input signal (see the Timers section).
Serial Port SFRs
The two full-duplex serial port peripherals each require two
registers: one for setting up the baud rate and other communication
parameters, and another register for the transmit/receive buffer.
The ADE5166/ADE5169/ADE5566/ADE5569 also provide
enhanced serial port functionality with a dedicated timer for
baud rate generation with a fractional divisor and additional
error detec-tion (see the UART Serial Interface section and the
UART2 Serial Interface section.)
Interrupt SFR
A two-tiered interrupt system is standard in the 8052 core. The
priority level for each interrupt source is individually select-able
as high or low. The ADE5166/ADE5169/ADE5566/ADE5569
enhance this interrupt system by creating, in essence, a third
interrupt tier for a highest priority power supply management
interrupt, PSM (see the Interrupt System section).
I/O Port SFRs
The 8052 core supports four I/O ports, P0 through P3, where
Port 0 and Port 2 are typically used for access to external code
and data spaces. The ADE5166/ADE5169/ADE5566/ADE5569,
unlike standard 8052 products, provide internal nonvolatile
flash memory so that an external code space is unnecessary.
The on-chip LCD driver requires many pins, some of which are
dedicated for LCD functionality and others that can be configured
as LCD or general-purpose I/O. Due to the limited number of
I/O pins, the ADE5166/ADE5169/ADE5566/ADE5569 do not
allow access to external code and data spaces.
The ADE5166/ADE5169/ADE5566/ADE5569 provide 20 pins
that can be used for general-purpose I/O. These pins are mapped
to Port 0, Port 1, and Port 2 and are accessed through three bit-
addressable 8052 SFRs: P0, P1, and P2. Another enhanced
feature of the ADE5166/ADE5169/ADE5566/ADE5569 is that
the weak pull-ups standard on 8052 Port 1, Port 2, and Port 3
can be disabled to make open-drain outputs, as is standard on
Port 0. The weak pull-ups can be enabled on a pin-by-pin basis
(see the I/O Ports section).
Power Control Register (PCON, Address 0x87)
The 8052 core defines two power-down modes: power-down
and idle. The ADE5166/ADE5169/ADE5566/ADE5569
enhance the power control capability of the traditional 8052
MCU with additional power management functions. The
POWCON SFR (Address 0xC5) is used to define power control
specific functionality for the ADE5166/ADE5169/ADE5566/
ADE5569. The program control SFR (PCON, Address 0x87) is
not bit addressable (see the Power Management section).
The ADE5166/ADE5169/ADE5566/ADE5569 provide many
other peripherals not standard to the 8052 core, for example
• ADE energy measurement DSP
• Full RTC
• LCD driver
• Battery switchover/power management
• Temperature ADC
• Battery ADC
• SPI/I2C communication
• Flash memory controller
• Watchdog timer
• Secondary UART port
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 85 of 156
MEMORY OVERVIEW
The ADE5166/ADE5169/ADE5566/ADE5569 contain three
memory blocks, as follows:
• 62 kB of on-chip Flash/EE program and data memory
• 256 bytes of general-purpose RAM
• 2 kB of extended internal RAM (XRAM)
The 256 bytes of general-purpose RAM share the upper 128 bytes
of its address space with the SFRs. All of the memory spaces are
shown in Figure 81. The addressing mode specifies which
memory space to access.
General-Purpose RAM
General-purpose RAM resides in Memory Location 0x00
through Memory Location 0xFF. It contains the register banks.
11
10
01
00
RESET VALUE OF
ST ACK P OINTER
FOUR BANKS O F EIG HT
REG IST E RS R0 TO R7
BIT-ADDRESSABLE
(BIT ADDRESSES)
GENERAL-PURPOSE
AREA
BANKS
SELECTED
VIA
BITS IN PSW
0x
00
0x
08
0x
10
0x
18
0x
20
0x
30
0x
07
0x
0F
0x
17
0x
1F
0x
2F
0x
7F
07411-058
Figure 83. Lower 128 Bytes of Internal Data Memory
Address 0x80 through Address 0xFF of general-purpose RAM
are shared with the SFRs. The mode of addressing determines
which memory space is accessed, as shown in Figure 84.
ACCESS IBLE BY
INDIRECT ADDRESSING
ONLY
ACCESS IBLE BY
DIRECT AND
INDIRECT ADDRESSING
0×FF
GE NE RAL-PURP OSE RAM
0×00
0×80
0×7F
ACCESS IBLE BY
DIRECT ADDRESSING
ONLY
SPECIFIC FUNCTION REGISTERS (SFRs)
07411-120
Figure 84. General-Purpose RAM and SFR Memory Address Overlap
Both direct and indirect addressing can be used to access general-
purpose RAM from Address 0x00 through Address 0x7F, but
indirect addressing must be used to access general-purpose
RAM with addresses in the range from 0x80 through 0xFF
because they share the same address space with the SFRs.
The 8052 core also has the means to access individual bits of
certain addresses in the general-purpose RAM and special function
memory spaces. The individual bits of general-purpose RAM,
Address 0x20 to Address 0x2F, can be accessed through Bit
Address 0x00 to Bit Address 0x7F. The benefit of bit addressing is
that the individual bits can be accessed quickly, without the
need for bit masking, which takes more code memory and
execution time. The bit addresses for General-Purpose RAM
Address 0x20 through General-Purpose RAM Address 0x2F
can be seen in Figure 85.
BYTE
ADDRESS BIT ADDRESSES (HEXA)
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
7F
77
6F
67
5F
57
4F
47
3F
37
2F
27
1F
17
0F
07
7E
76
6E
66
5E
56
4E
46
3E
36
2E
26
1E
16
0E
06
7D
75
6D
65
5D
55
4D
45
3D
35
2D
25
1D
15
0D
05
7C
74
6C
64
5C
54
4C
44
3C
34
2C
24
1C
14
0C
04
7B
73
6B
63
5B
53
4B
43
3B
33
2B
23
1B
13
0B
03
7A
72
6A
62
5A
52
4A
42
3A
32
2A
22
1A
12
0A
02
79
71
69
61
59
51
49
41
39
31
29
21
19
11
09
01
78
70
68
60
58
50
48
40
38
30
28
20
18
10
08
00
07411-060
Figure 85. Bit-Addressable Area of General-Purpose RAM
Bit addressing can be used for instructions that involve Boolean
variable manipulation and program branching (see the Instruction
Set section).
Special Function Registers (SFRs)
Special function registers are registers that affect the function
of the 8052 core or its peripherals. These registers are located
in RAM at Address 0x80 through Address 0xFF. They are
accessible only through direct addressing, as shown in Figure 84.
The individual bits of some of the SFRs can be accessed for use
in Boolean and program branching instructions. These SFRs are
labeled as bit addressable, and the bit addresses are given in
Table 15.
Extended Internal RAM (XRAM)
The ADE5166/ADE5169/ADE5566/ADE5569 provide 2 kB of
extended on-chip RAM. No external RAM is supported. This
RAM is located in Address 0x00 through Address 0x7FF in the
extended RAM space. To select the extended RAM memory
space, the extended indirect addressing modes are used.
2kB OF
EXT E NDE D INT E RNAL
RAM (XRAM )
0x7FF
0x00
07411-061
Figure 86. Extended Internal RAM (XRAM) Space
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 86 of 156
Code Memory
Code and data memory is stored in the 62 kB flash memory
space. No external code memory is supported. To access code
memory, code indirect addressing is used.
ADDRESSING MODES
The 8052 core provides several addressing modes. The address-
ing mode determines how the core interprets the memory location
or data value specified in assembly language code. There are six
addressing modes, as shown in Table 67.
Table 67. 8052 Addressing Modes
Addressing Mode Example Bytes
Core Clock
Cycles
Immediate MOV A, #A8h 2 2
MOV DPTR, #A8h 3 3
Direct MOV A, A8h 2 2
MOV A, IE 2 2
MOV A, R0 1 1
Indirect MOV A, @R0 1 2
Extended Direct MOVX A, @DPTR 1 4
Extended Indirect MOVX A, @R0 1 4
Code Indirect
MOVC A, @A+DPTR
1
4
MOVC A, @A+PC 1 4
JMP @A+DPTR 1 3
Immediate Addressing
In immediate addressing, the expression entered after the number
sign (#) is evaluated by the assembler and stored in the memory
address specified. This number is referred to as a literal because
it refers only to a value and not to a memory location. Instructions
using this addressing mode are slower than those between two
registers because the literal must be stored and fetched from
memory. The expression can be entered as a symbolic variable or
an arithmetic expression; the value is computed by the assembler.
Direct Addressing
With direct addressing, the value at the source address is moved
to the destination address. Direct addressing provides the fastest
execution time of all the addressing modes when an instruction
is performed between registers using direct addressing. Note that
indirect or direct addressing modes can be used to access general-
purpose RAM Address 0x00 through Address 0x7F. An instruction
with direct addressing that uses an address between 0x80 and
0xFF is referring to a special function memory location.
Indirect Addressing
With indirect addressing, the value pointed to by the register is
moved to the destination address. For example, to move the
contents of internal RAM Address 0x82 to the accumulator, use
the following two instructions, which require a total of four
clock cycles and three bytes of storage in the program memory:
MOV R0,#82h
MOV A,@R0
Indirect addressing allows addresses to be computed and is
useful for indexing into data arrays stored in RAM.
Note that an instruction that refers to Address 0x00 through
Address 0x7F is referring to internal RAM, and indirect or direct
addressing modes can be used. An instruction with indirect
addressing that uses an address between 0x80 and 0xFF is
referring to internal RAM, not to an SFR.
Extended Direct Addressing
The DPTR register is used to access extended internal RAM in
extended indirect addressing mode. The ADE5166/ADE5169/
ADE5566/ADE5569 provide 2 kB of extended internal RAM
(XRAM), accessed through MOVX instructions. External
memory spaces are not supported on the ADE5166/ADE5169/
ADE5566/ADE5569.
In extended direct addressing mode, the DPTR register points
to the address of the byte of extended RAM. The following code
moves the contents of extended RAM Address 0x100 to the
accumulator:
MOV DPTR,#100h
MOVX A,@DPTR
These two instructions require a total of seven clock cycles and
four bytes of storage in the program memory.
Extended Indirect Addressing
The extended internal RAM is accessed through a pointer to the
address in indirect addressing mode. The ADE5166/ADE5169/
ADE5566/ADE5569 provide 2 kB of extended internal RAM,
accessed through MOVX instructions. External memory is not
supported on the ADE5166/ADE5169/ADE5566/ADE5569.
In extended indirect addressing mode, a register holds the
address of the byte of extended RAM. The following code
moves the contents of extended RAM Address 0x80 to the
accumulator:
MOV R0, #80h
MOVX A, @R0
These two instructions require six clock cycles and three bytes
of storage.
Note that there are 2 kB of extended RAM, so both extended
direct and extended indirect addressing can cover the whole
address range. There is a storage and speed advantage to using
extended indirect addressing because the additional byte of
addressing available through the DPTR register that is not
needed is not stored.
From the three examples demonstrating the access of internal
RAM from 0x80 through 0xFF and extended internal RAM
from 0x00 through 0xFF, it can be seen that it is most efficient
to use the entire internal RAM accessible through indirect
access before moving to extended RAM.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 87 of 156
Code Indirect Addressing
The internal code memory can be accessed indirectly. This can be
useful for implementing lookup tables and other arrays of constants
that are stored in flash memory. For example, to move the data
stored in flash memory at Address 0x8002 into the accumulator,
MOV DPTR,#8002h
CLR A
MOVX A,@A+DPTR
The accumulator can be used as a variable index into the array
of flash memory located at DPTR.
INSTRUCTION SET
Table 68 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles,
resulting in a 4-MIPS peak performance. Note that, throughout this section, A represents the accumulator.
Table 68. Instruction Set
Mnemonic Description Bytes Cycles
Arithmetic
ADD A, Rn Add register to A 1 1
ADD A, @Ri Add indirect memory to A 1 2
ADD A, dir Add direct byte to A 2 2
ADD A, #data Add immediate to A 2 2
ADDC A, Rn 1 1 Add register to A with carry 1 1
ADDC A, @Ri
Add indirect memory to A with carry
1
2
ADDC A, dir Add direct byte to A with carry 2 2
ADDC A, #data Add immediate to A with carry 2 2
SUBB A, Rn Subtract register from A with borrow 1 1
SUBB A, @Ri Subtract indirect memory from A with borrow 1 2
SUBB A, dir Subtract direct from A with borrow 2 2
SUBB A, #data Subtract immediate from A with borrow 2 2
INC A Increment A 1 1
INC Rn Increment register 1 1
INC @Ri Ri increment indirect memory 1 2
INC dir Increment direct byte 2 2
INC DPTR Increment data pointer 1 3
DEC A Decrement A 1 1
DEC Rn Decrement register 1 1
DEC @Ri Decrement indirect memory 1 2
DEC dir Decrement direct byte 2 2
MUL AB Multiply A by B 1 9
DIV AB
Divide A by B
1
9
DA A Decimal Adjust A 1 2
Logic
ANL A, Rn AND register to A 1 1
ANL A, @Ri AND indirect memory to A 1 2
ANL A, dir AND direct byte to A 2 2
ANL A, #data AND immediate to A 2 2
ANL dir, A AND A to direct byte 2 2
ANL dir, #data AND immediate data to direct byte 3 3
ORL A, Rn OR register to A 1 1
ORL A, @Ri OR indirect memory to A 1 2
ORL A, dir OR direct byte to A 2 2
ORL A, #data OR immediate to A 2 2
ORL dir, A OR A to direct byte 2 2
ORL dir, #data
OR immediate data to direct byte
3
3
XRL A, Rn Exclusive-OR register to A 1 1
XRL A, @Ri Exclusive-OR indirect memory to A 2 2
XRL A, #data Exclusive-OR immediate to A 2 2
XRL dir, A Exclusive-OR A to direct byte 2 2
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 88 of 156
Mnemonic Description Bytes Cycles
XRL A, dir Exclusive-OR indirect memory to A 2 2
XRL dir, #data Exclusive-OR immediate data to direct 3 3
CLR A Clear A 1 1
CPL A Complement A 1 1
SWAP A
Swap nibbles of A
1
1
RL A Rotate A left 1 1
RLC A Rotate A left through carry 1 1
RR A Rotate A right 1 1
RRC A Rotate A right through carry 1 1
Data Transfer
MOV A, Rn Move register to A 1 1
MOV A, @Ri Move indirect memory to A 1 2
MOV Rn, A Move A to register 1 1
MOV @Ri, A
Move A to indirect memory
1
2
MOV A, dir Move direct byte to A 2 2
MOV A, #data Move immediate to A 2 2
MOV Rn, #data Move register to immediate 2 2
MOV dir, A Move A to direct byte 2 2
MOV Rn, dir
Move register to direct byte
2
2
MOV dir, Rn Move direct to register 2 2
MOV @Ri, #data Move immediate to indirect memory 2 2
MOV dir, @Ri Move indirect to direct memory 2 2
MOV @Ri, dir Move direct to indirect memory 2 2
MOV dir, dir Move direct byte to direct byte 3 3
MOV dir, #data Move immediate to direct byte 3 3
MOV DPTR, #data Move immediate to data pointer 3 3
MOVC A, @A+DPTR Move code byte relative DPTR to A 1 4
MOVC A, @A+PC Move code byte relative PC to A 1 4
MOVX A, @Ri Move external (A8) data to A 1 4
MOVX A, @DPTR Move external (A16) data to A 1 4
MOVX @Ri, A Move A to external data (A8) 1 4
MOVX @DPTR, A Move A to external data (A16) 1 4
PUSH dir Push direct byte onto stack 2 2
POP dir Pop direct byte from stack 2 2
XCH A, Rn Exchange A and register 1 1
XCH A, @Ri
Exchange A and indirect memory
1
2
XCHD A, @Ri Exchange A and indirect memory nibble 1 2
XCH A, dir Exchange A and direct byte 2 2
Boolean
CLR C Clear carry 1 1
CLR bit Clear direct bit 2 2
SETB C Set carry 1 1
SETB bit Set direct bit 2 2
CPL C Complement carry 1 1
CPL bit Complement direct bit 2 2
ANL C, bit AND direct bit and carry 2 2
ANL C, /bit AND direct bit inverse to carry 2 2
ORL C, bit OR direct bit and carry 2 2
ORL C, /bit OR Direct bit inverse to carry 2 2
MOV C, bit
Move direct bit to carry
2
2
MOV bit, C Move carry to direct bit 2 2
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 89 of 156
Mnemonic Description Bytes Cycles
Branching
JMP @A+DPTR Jump indirect relative to DPTR 1 3
RET Return from subroutine 1 4
RETI Return from interrupt 1 4
ACALL addr11
Absolute jump to subroutine
2
3
AJMP addr11 Absolute jump unconditional 2 3
SJMP rel Short jump (relative address) 2 3
JC rel Jump on carry equal to 1 2 3
JNC rel Jump on carry = 0 2 3
JZ rel Jump on accumulator = 0 2 3
JNZ rel Jump on accumulator ≠ 0 2 3
DJNZ Rn, rel Decrement register, JNZ relative 2 3
LJMP Long jump unconditional 3 4
LCALL addr16 Long jump to subroutine 3 4
JB bit, rel Jump on direct bit = 1 3 4
JNB bit, rel Jump on direct bit = 0 3 4
JBC bit, rel Jump on direct bit = 1 and clear 3 4
CJNE A, dir, rel Compare A, direct JNE relative 3 4
CJNE A, #data, rel Compare A, immediate JNE relative 3 4
CJNE Rn, #data, rel Compare register, immediate JNE relative 3 4
CJNE @Ri, #data, rel Compare indirect, immediate JNE relative 3 4
DJNZ dir, rel
Decrement direct byte, JNZ relative
3
4
Miscellaneous
NOP No operation 1 1
READ-MODIFY-WRITE INSTRUCTIONS
Some 8052 instructions read the latch and others read the pin.
The state of the pin is read for instructions that input a port bit.
Instructions that read the latch rather than the pins are the ones
that read a value, possibly change it, and rewrite it to the latch.
Because these instructions involve modifying the port, it is
assumed that the pins being modified are outputs, so the output
state of the pin is read from the latch. This prevents a possible
misinterpretation of the voltage level of a pin. For example, if a
port pin is used to drive the base of a transistor, a 1 is written to
the bit to turn on the transistor. If the CPU reads the same port
bit at the pin rather than the latch, it reads the base voltage of
the transistor and interprets it as Logic 0. Reading the latch
rather than the pin returns the correct value of 1.
The instructions that read the latch rather than the pins are called
read-modify-write instructions and are listed in Table 69. When
the destination operand is a port or a port bit, these instructions
read the latch rather than the pin.
Table 69. Read-Modify-Write Instructions
Instruction Example Description
ANL ANL P0, A Logic AND
ORL ORL P1, A Logic OR
XRL XRL P2, A Logic XOR
JBC JBC P1.1, LABEL Jump if Bit = 1 and clear bit
CPL CPL P2.0 Complement bit
INC
INC P2
Increment
DEC DEC P2 Decrement
DJNZ DJNZ P0, LABEL Decrement and jump if not zero
MOV PX.Y, C1 MOV P0.0, C Move carry to Bit Y of Port X
CLR PX.Y1 CLR P0.0 Clear Bit Y of Port X
SETB PX.Y1 SETB P0.0 Set Bit Y of Port X
1 These instructions read the port byte (all eight bits), modify the addressed
bit, and write the new byte back to the latch.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 90 of 156
INSTRUCTIONS THAT AFFECT FLAGS
Many instructions explicitly modify the carry bit, such as the
MOV C bit and CLR C instructions. Other instructions that
affect status flags are listed in this section.
ADD A, Source
This instruction adds the source to the accumulator. No status
flags are referenced by the instruction.
Table 70. ADD A (Source) Affected Status Flags
Flag Description
C
Set if there is a carry out of Bit 7. Cleared otherwise. Used
to indicate an overflow if the operands are unsigned.
OV Set if there is a carry out of Bit 6 or a carry out of Bit 7, but
not if both are set. Used to indicate an overflow for
signed addition. This flag is set if two positive operands
yield a negative resu