FUNCTIONAL DESCRIPTION
CORRELATED DOUBLE SAMPLING
All photodetector elements (photodiodes, photomultiplier tubes, focal
plane arrays, charge coupled devices, etc.) have unique output character-
istics that call for specifi c analog-signalprocessing (ASP) functions at their
outputs. Charge coupled devices (CCD’s), in particular, display a number
of unique characteristics. Among them is the fact that the “offset error”
associated with each individual pixel (i.e., the apparent photonic content
of that pixel after having had no light incident upon it) changes each and
every time that particular pixel is accessed.
Most of us think of an offset as a constant parameter that either can
be compensated for (by performing an offset adjustment) or can be
measured, recorded, and subtracted from subsequent readings to yield
more accurate data. Contending with an offset that varies from reading to
reading requires measuring and recording (or capturing and storing) the
offset each and every time, so it can be subtracted from each subsequent
data reading.
The “double sampling” aspect of CDS refers to the operation of sampling
and storing/recording a given pixel’s offset and then sampling the same
pixel’s output an instant later (with both the offset and the video signal
present) and subsequently subtracting the two values to yield what is
referred to as the “valid video” output for that pixel.
The “correlated” in CDS refers to the fact that the two samples must be
taken close together in time because the offset is constantly varying.
Reasons for this phenomena are discussed below.
At the output of all CCD’s, transported pixel charge (electrons) is converted
to a voltage by depositing the charge onto a capacitor (usually called
the output or “fl oating” capacitor). The voltage that develops across this
capacitor is obviously proportional to the amount of deposited charge
(i.e., the number of electrons) according to ΔV = ΔQ/C. Once settled, the
resulting capacitor voltage is buffered and brought to the CCD’s output pin
as a signal whose amplitude is proportional to the total number of photons
incident upon the relevant pixel.
After the output signal has been recorded, the fl oating capacitor is
discharged (“reset”, “clamped”, “dumped”) and made ready to accept
charge from the next pixel. This is when the problems begin. (This is a
somewhat oversimplifi ed explanation in that the fl oating capacitor is not
usually “discharged” but, in fact, “recharged” to some predetermined dc
voltage, usually called the “reference level”. The pixel offset appears as an
output deviation from that reference level.)
The fl oating capacitor is normally discharged (charged) via a shunt switch
(typically a FET structure) that has a non-zero “on” resistance. When the
switch is on, its effective series resistance exhibits thermal noise (Johnson
noise) due to the random motion of thermally energized charge. Because
the shunt switch is in parallel with the fl oating capacitor, the instanta-
neous value of the thermal noise (expressed in either Volts or electrons)
appears across the cap. When the shunt switch is opened, charge/voltage
is left on the fl oating cap.
The magnitude of this “captured noise voltage” is a function of absolute
temperature (T), the value of the fl oating capacitor (C) and Boltzman’s
constant (k). It is commonly referred to as “kTC” noise.
The second contributor to the constantly varying pixel offsets is the fact
that, at high pixel rates, the fl oating capacitor never has time to fully
discharge (charge) during the period in which its shunt switch is closed.
There is always some “residual” charge left on the cap, and the amount of
this charge varies as a function of what was the total charge held during
the previous pixel. This amount of residual charge is, in fact, deterministic
(if you know the previous charge and the number of time constants in the
discharge period), however, it is less of a contributor than kTC noise.
The third major contributor to pixel offset is the fact that as the shunt FET
is turned off, the voltage across (and the charge stored on) its parasitic
junction capacitances changes. The result is an “injection” of excess
charge onto the fl oating cap causing a voltage step normally called a
“pedestal.”
The fourth major contributor to pixel offset is a low-frequency noise com-
ponent (usually called 1/f noise or pink noise) associated with the CCD’s
output buffer amplifi er. Due to all of these contributing factors, "pixel
offsets" vary from sample to sample in an inconsistent, unpredictable
manner.
TRADITIONAL APPROACH TO CDS
There are a number of techniques for dealing with the varyingoffset
idiosyncrasy of CCD’s. The most prevalent has been what can be called
the “sample-sample-subtract” technique. This approach requires the use
of two high-speed sample-hold (S/H) amplifi ers and a difference amplifi er.
The fi rst S/H is used to acquire and hold a given pixel’s offset. Imme-
diately after that, the second S/H acquires and holds the same pixel’s
offset+video signal. After both the S/H outputs have fully settled, the
difference amplifi er subtracts the offset from the offset+video yielding the
valid video signal.
CDS-1401 APPROACH (SEE FIGURE 1)
The DATEL CDS-1401 takes a slightly different, though clearly superior,
approach to CDS. It can be called the “samplesubtract- sample” approach.
Note that the CDS-1401 has been confi gured to offer the greatest amount
of user fl exibility. Its two S/H circuits function independently. They have
separate input and output pins. Each has its own independent control
lines. The control-line signals are delayed, buffered, and brought back out
of the package so they can be used to control other circuit functions. Each
S/H has two pins for offset adjusting (if required), one for current and one
for voltage.
In normal operation, the output signal of the CCD is applied simultane-
ously to the inputs (pins 3 and 4) of both S/H amplifi ers. S/H1 will normally
be used to capture and hold each pixel’s offset signal. Therefore, S/H1
is initially in its signal-acquisition mode (logic “1” applied to pin 11, S/
H1 COMMAND). This is also called the sample or track mode. Following a
brief interval during which the output of the CCD and the output of S/H1
are allowed to settle, S/H1 is driven into its hold mode by applying a logic
“0” to pin 11. S/H1 is now holding the pixel’s offset value.
In most straightforward confi gurations, the output of S/H1 is connected to
the summing node of S/H2 by connecting pin 7 (S/H1 ROUT) to pin 8 (S/H2
SUMMING NODE).
When the offset+video signal appears at the output of the CCD, S/H2
is driven into its signal acquisition mode by applying a logic “1” to pin
12 (S/H2 COMMAND). S/H2 employs a current-summing architecture
that subtracts the output of S/H1 (the offset) from the output of the CCD
(offset+video) while acquiring only the difference signal (i.e., the valid
video). A logic “0” subsequently applied to pin 12 drives S/H2 into its hold
mode, and after a brief transient settling time, the valid video signal ap-
pears at pin 22 (V OUT).
CDS-1401
14-Bit, Fast-Settling Correlated Double Sampling Circuit
®®
DATEL • 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
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