UTRON UT62L2568
Rev. 1.1 256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
REVISION HISTORY
REVISION DESCRIPTION Release Date
Preliminary Rev. 0.1 Original. Jun 18, 2001
Rev. 1.0 1. Revised Power supply
a、 55ns (max.) for Vcc=2.7V~3.6V
b、 70/100ns (max.) for Vcc=2.5V~3.6V
2. Revised DC ELECTRICAL CHARACTERISTICS：
a、 Revised VIH as 2.2V
b、 Revised standby current ISB1 of LL-version
Typical : 3uAB2uA
Maximum : 25uAB20uA
3. Revised AC ELECTRICAL CHARACTERISTICS：
a、 Revised tOH as 10ns (min.)
4. Revised 36-pin TFBGA package outline dimension：
a、 Rev. 0.1 ball diameter=0.3mm
b、 Rev. 1.0 ball diameter=0.35mm
Jul 30, 2002
Rev. 1.1 1.Revised “FEATURES” Operating current :
40/35/25mA(ICC max)20/18/15mA (ICC typ.)
2.TRUTH TABLE & DC ELECTRICAL : Delete ISB2
3.Revised VTERM : -0.5 to Vcc+0.3V -0.5 to 4.6V
4.Added VOH : 2.7V at Vcc=3.0V
5.Revised DC (ICC max) 45/35/25mA35/30/25mA
(I
CC typ.) 30/25/20mA20/18/15mA
6.Add under/overshoot range of VIL & VIH
7.Revised AC tOHZ*@100ns (max): 35ns30ns
t
WHZ*(max) :30/30/4020/25/30ns
8.Revised “Data retention Characteristics” :
I
DR-LL (Typ.) : NA1uA, IDR-L (Typ.) : NA10uA
I
DR-LL (Max.) : 25uA6uA
t
R(min) : 5ns”tRC”
9.Add order information for lead free product
Apr 28, 2003
UTRON UT62L2568
Rev. 1.1 256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 2
FEATURES
Fast access time :
55ns(max.) for Vcc=2.7V~3.6V
70/100ns(max.) for Vcc=2.5V~3.6V
CMOS low power operation
Operating : 20/18/15mA (TYP.)
Standby : 20 uA(TYP.) L -version
2 uA(TYP.) LL-version
Single 2.5V~3.6V power supply
Operating temperature:
Commercial : 0℃~70℃
Extended : -20℃~80℃
All TTL compatible inputs and outputs
Fully static operation
Three state outputs
Data retention voltage: 1.5V (min)
Package : 32-pin 8mm x 20mm TSOP-Ⅰ
32-pin 8mm x 13.4mm STSOP
36-pin 6mm × 8mm TFBGA
GENERAL DESCRIPTION
The UT62L2568 is a 2,097,152-bit low power CMOS
static random access memory organized as 262,144
words by 8 bits. It is fabricated using high performance,
high reliability CMOS technology.
The UT62L2568 is designed for very low power system
applications. It is particularly well suited for battery
back-up nonvolatile memory applications.
It operates from a wide range of 2.5V~ 3.6V supply
voltage. Easy memory expansion is provided by using
two chip enable input (CE,CE2). And all inputs and
three-state outputs are fully TTL compatible.
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O D A TA
CIRCUIT
CONTROL
CIRCUIT
256K ×8
MEMORY
ARRAY
COLU M N I/O
A0-A17
Vcc
Vss
I/O1-I/O8
CE2
CE
WE
OE
UTRON UT62L2568
Rev. 1.1 256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 3
PIN CONFIGURATION
OE
WE
A12
A11 A13
NC
A17
A10 A14
A15
I/O6
I/O7
I/O8
A9
Vss
A8
A16
I/O5
Vcc
Vcc
I/O4
Vss
A7
A0
I/O3
I/O2
I/O1
NC
A6
A1 A3
A5
A4A2
123456
H
G
C
D
E
F
A
B
TFBGA
CE2
CE
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4 A3
UT62L2568
TSO P -1 / S T SO P
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
WE
OE
CE
CE2
A17
A15
32
31
30
29
A16
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A17 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
CE,CE2 Chip Enable Inputs
WE Write Enable Input
OE Output Enable Input
VCC Power Supply
VSS Ground
NC No Connection
UTRON UT62L2568
Rev. 1.1 256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 4
TRUTH TABLE
MODE CE CE2 OE WE I/O OPERATION SUPPLY CURRENT
H X X X High - Z ISB,ISB1
Standby X L X X High - Z ISB,ISB1
Output Disable L H H H High - Z ICC,ICC1,ICC2
Read L H L H DOUT ICC,ICC1,ICC2
Write L H X L DIN ICC,ICC1,ICC2
Note: H = VIH, L=VIL, X = Don't care.
ABSOLUTE MAXIMUM RATINGS*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS V
TERM -0.5 to 4.6 V
Commercial TA 0 to 70 ℃
Operating Temperature
Extended TA -20 to 80 ℃
Storage Temperature TSTG -65 to 150 ℃
Power Dissipation PD 1 W
DC Output Current IOUT 50 mA
Soldering Temperature (under 10 secs) Tsolder 260 ℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
DC ELECTRICAL CHARACTERISTICS (VCC =2.5V~3.6V, TA =0℃ to 70℃ / -20℃ to 80℃(E))
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
55 2.7 3.0 3.6 V
Power Voltage VCC 70/100 2.5 3.0 3.6 V
Input High Voltage VIH＊1 2.2 - Vcc+0.3 V
Input Low Voltage VIL＊2 - 0.2 - 0.6 V
Input Leakage Current ILI VSS ≦VIN ≦VCC - 1 - 1 µA
Output Leakage Current ILO VSS ≦VI/O ≦VCC, Output Disabled - 1 - 1 µA
Output High Voltage VOH IOH= - 1mA (IOH= -0.5mA when Vcc<2.7V) 2.2 2.7 - V
Output Low Voltage VOL IOL= 2.1mA - - 0.4 V
55 - 20 35 mA
70 - 18 30 mA
ICC Cycle time=Min.100% duty,
CE=VIL and CE2 = VIH,
II/O =0mA 100 - 15 25 mA
ICC1 TCycle=
1µs - 4 5
mA
Operating Current
ICC2
100%duty, II/O=0mA, CE≦0.2V
and CE2≧Vcc-0.2V, other pins
at 0.2V or Vcc-0.2V TCycle=
500ns - 8 10
mA
Standby Current (TTL) ISB CE=VIH or CE2 = VIL - 0.3 0.5 mA
-L - 20 80 µA
Standby Current (CMOS) ISB1 CE=VCC-0.2V or CE2=0.2V,
other pins at 0.2V or Vcc-0.2V -LL - 2 20 µA
Notes:
1. Overshoot : Vcc+3.0v for pulse width less than 10ns.
2. Undershoot : Vss-3.0v for pulse width less than 10ns.
3. Overshoot and Undershoot are sampled, not 100% tested.
UTRON UT62L2568
Rev. 1.1 256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 5
CAPACITANCE (TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance CIN - 6 pF
Input/Output Capacitance CI/O - 8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF+1TTL, IOH= -1mA, IOL= 2.1mA
AC ELECTRICAL CHARACTERISTICS ( TA = 0℃ to 70℃ / -20℃ to 80℃(E))
(1) READ CYCLE
PARAMETER SYMBOL UT62L2568-55
VCC = 2.7V~3.6V UT62L2568-70
VCC = 2.5V~3.6V UT62L2568-100
VCC = 2.5V~3.6V UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time tRC 55 - 70 - 100 - ns
Address Access Time tAA - 55 - 70 - 100 ns
Chip Enable Access Time tACE - 55 - 70 - 100 ns
Output Enable Access Time tOE - 30 - 35 - 50 ns
Chip Enable to Output in Low Z tCLZ* 10 - 10 - 10 - ns
Output Enable to Output in Low Z tOLZ* 5 - 5 - 5 - ns
Chip Disable to Output in High Z tCHZ* - 20 - 25 - 30 ns
Output Disable to Output in High Z tOHZ* - 20 - 25 - 30 ns
Output Hold from Address Change tOH 10 - 10 - 10 - ns
(2) WRITE CYCLE
PARAMETER SYMBOL UT62L2568-55
VCC = 2.7V~3.6V UT62L2568-70
VCC = 2.5V~3.6V UT62L2568-100
VCC = 2.5V~3.6V UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time tWC 55 - 70 - 100 - ns
Address Valid to End of Write tAW 50 - 60 - 80 - ns
Chip Enable to End of Write tCW 50 - 60 - 80 - ns
Address Set-up Time tAS 0 - 0 - 0 - ns
Write Pulse Width tWP 45 - 55 - 70 - ns
Write Recovery Time tWR 0 - 0 - 0 - ns
Data to Write Time Overlap tDW 25 - 30 - 40 - ns
Data Hold from End of Write Time tDH 0 - 0 - 0 - ns
Output Active from End of Write tOW* 5 - 5 - 5 - ns
Write to Output in High Z tWHZ* - 20 - 25 - 30 ns
*These parameters are guaranteed by device characterization, but not production tested.
UTRON UT62L2568
Rev. 1.1 256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 6
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2) tRC
tAA
Data V alid
Address
Dout
tOH tOH
Previous data valid
READ CYCLE 2 (CEand CE2 and OE Controlled) (1,3,4,5)
tRC
tAA
tACE
tOE
tOHZ
tCLZ tOH
tOLZ
High-Z D a ta Valid High-Z
tCHZ
Address
CE2
Dout
CE
OE
Notes :
1. WE is high for read cycle.
2.Device is continuously selectedOE =low,CE =low, CE2=high.
3.Address must be valid prior to or coincident withCE =low, CE2=high; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL=5pF. Transition is measured±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ is less than tOHZ is less than tOLZ.
UTRON UT62L2568
Rev. 1.1 256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 7
WRITE CYCLE 1 (WE Controlled) (1,2,3,5,6)
tWC
tAW
tCW
tAS tWP
tWHZ tOW
tWR
High-Z
(4) (4)
Address
CE2
CE
WE
Dout
Din D a ta Va lid
tDW tDH
WRITE CYCLE 2 (CEand CE2 Controlled) (1,2,5,6) tWC
tAW
tCW
tAS tWR
tWP
tWHZ
tDW tDH
D ata Va lid
High-Z
(4)
Address
CE2
CE
WE
Dout
Din
UTRON UT62L2568
Rev. 1.1 256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 8
Notes :
1. WE ,CE must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a lowCE , high CE2, low WE .
3.During a WE controlled write cycle withOE low, tWP must be greater than tWHZ+tDW to allow the drivers to turn off and data to be placed
on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If theCE low transition and CE2 high transition occurs simultaneously with or after WE low transition, the outputs remain in a high
impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
DATA RETENTION CHARACTERISTICS (TA =0℃ to 70℃ / -20℃ to 80℃(E))
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Vcc for Data Retention
VDR CE≧VCC-0.2V
or CE2≦0.2V 1.5 - 3.6 V
Data Retention Current IDR - L - 10 80 µA
V
CC=1.5V
CE≧VCC-0.2V
or CE2≦0.2V - LL - 1 10 µA
Chip Disable to Data tCDR See Data Retention
Retention Time Waveforms (below) 0 - - ns
Recovery Time
t
R t
RC - - ns
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE controlled)
VDR ≧ 1.5V
CE ≧ VCC-0.2V
Vcc(min.) Vcc(min.)
VIH VIH
VCC
tR
tCDR
CE
Low Vcc Data Retention Waveform (2) (CE2 controlled)
VDR ≧ 1.5V
VCC(min.)
VCC
tR
tCDR
CE2 ≦ 0.2V VIL
CE2
VCC(min.)
VIL
UTRON UT62L2568
Rev. 1.1 256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 9
PACKAGE OUTLINE DIMENSION
32 pin 8mm x 20mm TSOP-I Package Outline Dimension
UNIT
SYMBOL INCH(BASE) MM(REF)
A 0.047 (MAX) 1.20 (MAX)
A1 0.004 ±0.002 0.10
±0.05
A2 0.039 ±0.002 1.00
±0.05
b 0.008 + 0.002
- 0.001
0.20 + 0.05
-0.03
c 0.005 (TYP) 0.127 (TYP)
D 0.724 ±0.004 18.40
±0.10
E 0.315 ±0.004 8.00
±0.10
e 0.020 (TYP) 0.50 (TYP)
HD 0.787 ±0.008 20.00
±0.20
L 0.0197 ±0.004 0.50
±0.10
L1 0.0315 ±0.004 0.08
±0.10
y 0.003 (MAX) 0.076 (MAX)
Θ 0
o∼5o 0
o∼5o
UTRON UT62L2568
Rev. 1.1 256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 10
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
1
16 17
32
c
L
HD
D"A"
E
e
12°(2x)12°(2x)
Seating Plane y
32
17
16
1
c
A2A1
L
A
0.254
0
GAUGE PLANE
12°(2X)
12°(2X)
SEATING PLANE
"A" DATAIL VIEW L1
b
UNIT
SYMBOL INCH(BASE) MM(REF)
A 0.049 (MAX) 1.25 (MAX)
A1 0.005 ±0.002 0.130
±0.05
A2 0.039 ±0.002 1.00
±0.05
b 0.008 ±0.01 0.20±0.025
c 0.005 (TYP) 0.127 (TYP)
D 0.465 ±0.004 11.80
±0.10
E 0.315 ±0.004 8.00
±0.10
e 0.020 (TYP) 0.50 (TYP)
HD 0.528±0.008 13.40
±0.20.
L 0.0197 ±0.004 0.50
±0.10
L1 0.0315 ±0.004 0.8
±0.10
y 0.003 (MAX) 0.076 (MAX)
Θ 0
o∼5o 0
o∼5o
UTRON UT62L2568
Rev. 1.1 256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 11
36 pin 6mm×8mm TFBGA Package Outline Dimension
UTRON UT62L2568
Rev. 1.1 256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 12
ORDERING INFORMATION
COMMERCIAL TEMPERATURE
PART NO. ACCESS TIME
(ns) STANDBY CURRENT
(µA) TYP. PACKAGE
UT62L2568LC-55L 55 20 32 PIN TSOP-I
UT62L2568LC-55LL 55 2 32 PIN TSOP-I
UT62L2568LC-70L 70 20 32 PIN TSOP-I
UT62L2568LC-70LL 70 2 32 PIN TSOP-I
UT62L2568LC-100L 100 20 32 PIN TSOP-I
UT62L2568LC-100LL 100 2 32 PIN TSOP-I
UT62L2568LS-55L 55 20 32 PIN STSOP
UT62L2568LS-55LL 55 2 32 PIN STSOP
UT62L2568LS-70L 70 20 32 PIN STSOP
UT62L2568LS-70LL 70 2 32 PIN STSOP
UT62L2568LS-100L 100 20 32 PIN STSOP
UT62L2568LS-100LL 100 2 32 PIN STSOP
UT62L2568BS-55L 55 20 36 PIN TFBGA
UT62L2568BS-55LL 55 2 36 PIN TFBGA
UT62L2568BS-70L 70 20 36 PIN TFBGA
UT62L2568BS-70LL 70 2 36 PIN TFBGA
UT62L2568BS-100L 100 20 36 PIN TFBGA
UT62L2568BS-100LL 100 2 36 PIN TFBGA
EXTENDED TEMPERATURE
PART NO. ACCESS TIME
(ns) STANDBY CURRENT
(µA) TYP. PACKAGE
UT62L2568LC-55LE 55 20 32 PIN TSOP-I
UT62L2568LC-55LLE 55 2 32 PIN TSOP-I
UT62L2568LC-70LE 70 20 32 PIN TSOP-I
UT62L2568LC-70LLE 70 2 32 PIN TSOP-I
UT62L2568LC-100LE 100 20 32 PIN TSOP-I
UT62L2568LC-100LLE 100 2 32 PIN TSOP-I
UT62L2568LS-55LE 55 20 32 PIN STSOP
UT62L2568LS-55LLE 55 2 32 PIN STSOP
UT62L2568LS-70LE 70 20 32 PIN STSOP
UT62L2568LS-70LLE 70 2 32 PIN STSOP
UT62L2568LS-100LE 100 20 32 PIN STSOP
UT62L2568LS-100LLE 100 2 32 PIN STSOP
UT62L2568BS-55LE 55 20 36 PIN TFBGA
UT62L2568BS-55LLE 55 2 36 PIN TFBGA
UT62L2568BS-70LE 70 20 36 PIN TFBGA
UT62L2568BS-70LLE 70 2 36 PIN TFBGA
UT62L2568BS-100LE 100 20 36 PIN TFBGA
UT62L2568BS-100LLE 100 2 36 PIN TFBGA
UTRON UT62L2568
Rev. 1.1 256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 13
ORDERING INFORMATION (for lead free product)
COMMERCIAL TEMPERATURE
PART NO. ACCESS TIME
(ns) STANDBY CURRENT
(µA) TYP. PACKAGE
UT62L2568LCL-55L 55 20 32 PIN TSOP-I
UT62L2568LCL-55LL 55 2 32 PIN TSOP-I
UT62L2568LCL-70L 70 20 32 PIN TSOP-I
UT62L2568LCL-70LL 70 2 32 PIN TSOP-I
UT62L2568LCL-100L 100 20 32 PIN TSOP-I
UT62L2568LCL-100LL 100 2 32 PIN TSOP-I
UT62L2568LSL-55L 55 20 32 PIN STSOP
UT62L2568LSL-55LL 55 2 32 PIN STSOP
UT62L2568LSL-70L 70 20 32 PIN STSOP
UT62L2568LSL-70LL 70 2 32 PIN STSOP
UT62L2568LSL-100L 100 20 32 PIN STSOP
UT62L2568LSL-100LL 100 2 32 PIN STSOP
UT62L2568BSL-55L 55 20 36 PIN TFBGA
UT62L2568BSL-55LL 55 2 36 PIN TFBGA
UT62L2568BSL-70L 70 20 36 PIN TFBGA
UT62L2568BSL-70LL 70 2 36 PIN TFBGA
UT62L2568BSL-100L 100 20 36 PIN TFBGA
UT62L2568BSL-100LL 100 2 36 PIN TFBGA
EXTENDED TEMPERATURE
PART NO. ACCESS TIME
(ns) STANDBY CURRENT
(µA) TYP. PACKAGE
UT62L2568LCL-55LE 55 20 32 PIN TSOP-I
UT62L2568LCL-55LLE 55 2 32 PIN TSOP-I
UT62L2568LCL-70LE 70 20 32 PIN TSOP-I
UT62L2568LCL-70LLE 70 2 32 PIN TSOP-I
UT62L2568LCL-100LE 100 20 32 PIN TSOP-I
UT62L2568LCL-100LLE 100 2 32 PIN TSOP-I
UT62L2568LSL-55LE 55 20 32 PIN STSOP
UT62L2568LSL-55LLE 55 2 32 PIN STSOP
UT62L2568LSL-70LE 70 20 32 PIN STSOP
UT62L2568LSL-70LLE 70 2 32 PIN STSOP
UT62L2568LSL-100LE 100 20 32 PIN STSOP
UT62L2568LSL-100LLE 100 2 32 PIN STSOP
UT62L2568BSL-55LE 55 20 36 PIN TFBGA
UT62L2568BSL-55LLE 55 2 36 PIN TFBGA
UT62L2568BSL-70LE 70 20 36 PIN TFBGA
UT62L2568BSL-70LLE 70 2 36 PIN TFBGA
UT62L2568BSL-100LE 100 20 36 PIN TFBGA
UT62L2568BSL-100LLE 100 2 36 PIN TFBGA
UTRON UT62L2568
Rev. 1.1 256K X 8 BIT LOW POWER CMOS SRAM
UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919 14
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