Data Sheet V850ES/FE3 32-bit Single-Chip Microcontroller Hardware PD70F3370A(A) PD70F3371(A) PD70F3370A(A1) PD70F3371(A1) PD70F3370A(A2) PD70F3371(A2) Document No. U18564EE1V2DS00 Date Published March 2008 (c) NEC Electronics 2008 Printed in Germany V850ES/FE3 Notes for CMOS Devices 1. Precaution against ESD for semiconductors Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2. Handling of unused input pins for CMOS No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3. Status before initialization of MOS devices Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 2 Data Sheet U18564EE1V2DS00 V850ES/FE3 Legal Notes * The information in this document is current as of January 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such NEC Electronics products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact NEC Electronics sales representative in advance to determine NEC Electronics 's willingness to support a given application. Notes: 1. "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. 2. "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). 3. SuperFlash(R) is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. Data Sheet U18564EE1V2DS00 3 V850ES/FE3 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. 4 Data Sheet U18564EE1V2DS00 V850ES/FE3 For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [America] [Europe] [Asia & Oceania] NEC Electronics America, Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ NEC Electronics (Europe) GmbH Arcadiastrasse 10 40472 Dusseldorf, Germany Tel: 0211-65030 http://www.eu.necel.com/ NEC Electronics (China) Co., Ltd 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian District, Beijing 100083, P.R.China TEL: 010-8235-1155 http://www.cn.necel.com/ Hanover Office Podbielski Strasse 166 B 30177 Hanover Tel: 0 511 33 40 2-0 NEC Electronics Shanghai Ltd. Room 2509-2510, Bank of China Tower, 200 Yincheng Road Central, Pudong New Area, Shanghai P.R. China P.C:200120 Tel: 021-5888-5400 http://www.cn.necel.com/ Munich Office Werner-Eckert-Strasse 9 81829 Munchen Tel: 0 89 92 10 03-0 Stuttgart Office Industriestrasse 3 70565 Stuttgart Tel: 0 711 99 01 0-0 United Kingdom Branch Cygnus House, Sunrise Parkway Linford Wood, Milton Keynes MK14 6NP, U.K. Tel: 01908-691-133 Succursale Francaise 9, rue Paul Dautier, B.P. 52180 78142 Velizy-Villacoublay Cedex France Tel: 01-3067-5800 Sucursal en Espana Juan Esplandiu, 15 28007 Madrid, Spain Tel: 091-504-2787 NEC Electronics Hong Kong Ltd. 12/F., Cityplaza 4, 12 Taikoo Wan Road, Hong Kong Tel: 2886-9318 http://www.hk.necel.com/ Seoul Branch 11F., Samik Lavied'or Bldg., 720-2, Yeoksam-Dong, Kangnam-Ku, Seoul, 135-080, Korea Tel: 02-558-3737 NEC Electronics Taiwan Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R. O. C. Tel: 02-8175-9600 NEC Electronics Singapore Pte. Ltd. 238A Thomson Road, #12-08 Novena Square, Singapore 307684 Tel: 6253-8311 http://www.sg.necel.com/ Tyskland Filial Taby Centrum Entrance S (7th floor) 18322 Taby, Sweden Tel: 08 638 72 00 Filiale Italiana Via Fabio Filzi, 25/A 20124 Milano, Italy Tel: 02-667541 Branch The Netherlands Steijgerweg 6 5616 HS Eindhoven The Netherlands Tel: 040 265 40 10 G06.6-1A Data Sheet U18564EE1V2DS00 5 V850ES/FE3 Table of Contents 1. Pin Group Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2. Device package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Groups 1x: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Groups 2x: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin Groups 3x: Pins supplied by BVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Groups 4: Pins supplied by AVREF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Groups 5: Pins supplied by AVREF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Groups 6: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pin Groups 7: Pins supplied by VRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Electrical Specifications of (A)-Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 2.2 2.3 2.4 2.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5.1 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5.2 Sub System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5.3 Internal-OSC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5.4 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.5 SSCG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.2 PIN leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6.3 Power supply current (A-grade). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6.3.1 FE3 128KB mPD70F3370A, FE3 256KB mPD70F3371 . . . . . . . . . . . . . . . . . . . . . . 18 2.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.7.1 CLKOUT Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.7.2 RESET, Interrupt, ADTRG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.7.3 Key Return Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.7.4 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.7.5 CSI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.7.6 UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.7.7 IIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.7.8 CAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.8 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.9 POC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.10 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.11 RAM Retention Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.12 Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.13 Flash Memory Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3. Electrical Specifications of (A1)-Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.1 3.2 3.3 3.4 3.5 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 6 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32 Sub System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 33 Internal-OSC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SSCG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Data Sheet U18564EE1V2DS00 V850ES/FE3 Table of Contents 3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.6.2 PIN leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3.6.3 Power supply current (A1-grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.6.3.1 FE3 128KB mPD70F3370A, FE3 256KB mPD70F3371 . . . . . . . . . . . . . . . . . . . . . . 36 3.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.7.1 CLKOUT Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.7.2 RESET, Interrupt, ADTRG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.7.3 Key Return Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.7.4 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.7.5 CSI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.7.6 UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.7.7 IIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.7.8 CAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 3.8 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.9 POC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.10 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.11 RAM Retention Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.12 Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.13 Flash Memory Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4. Electrical Specifications of (A2)-Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 4.1 4.2 4.3 4.4 4.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5.1 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42 4.5.2 Sub System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.5.3 Internal-OSC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.5.4 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.5.5 SSCG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.6.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.6.2 PIN leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4.6.3 Power supply current (A2-grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.6.3.1 FE3 128KB mPD70F3370A, FE3 256KB mPD70F3371 . . . . . . . . . . . . . . . . . . . . . . 45 4.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.7.1 CLKOUT Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.7.2 RESET, Interrupt, ADTRG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.7.3 Key Return Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.7.4 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.7.5 CSI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.7.6 UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.7.7 IIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.7.8 CAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.8 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.9 POC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.10 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.11 RAM Retention Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.12 Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4.13 Flash Memory Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Data Sheet U18564EE1V2DS00 7 V850ES/FE3 Table of Contents 5. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.1 5.2 6. 8 Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Product Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.1 Marking of pin 1 at a QFP (Quad Flat Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.2 Identification of Lead-Free Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Change History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Data Sheet U18564EE1V2DS00 V850ES/FE3 1. Pin Group Information 1.1 Device package information The V850ES/Fx3 device series comprises several members. An overview with the pin and package information is given in the following table: Series Member PD70F3370A PD70F3371 PD70F3372 PD70F3373 PD70F3374 PD70F3375 PD70F3376A PD70F3377A PD70F3378 PD70F3379 PD70F3380 PD70F3381 PD70F3382 PD70F3383 PD70F3384 PD70F3385 # Pins Device package information 64 FE3 80 FF3 100 FG3 144 FJ3 176 FK3 This document describes the specification for the V850ES/FE3. 1.2 Pin Groups 1x: Pins supplied by EVDD 1B: (SHMT1) - P04, P30-31, P34; P40, P91, P913-915 (FE3) - P04, P30-31, P34; P38-39, P40, P91, P913-915 (FF3) - P04, P30-31, P34; P36-39, P40, P91, P911, P913-915 (FG3) - P04, P30-31, P34; P36-39, P40, P63-69, P614-615, P80-81, P91, P911, P913-915 (FJ3) - P04, P30-31, P34; P36-39, P40, P63-69, P614-615, P80-81, P91, P911, P913-915, P156-157 (FK3) 1D: (SHMT3) - P00-03, P05-P06, P32-33, P35, P41-42, P50-55, P90, P96-99 (FE3) - P00-03, P05-P06, P32-33, P35, P41-42, P50-55, P90, P96-99 (FF3) - P00-03, P05-P06, P10-11, P32-33, P35, P41-42, P50-55, P90, P92-910, P912 (FG3) - P00-03, P05-P06, P10-11, P32-33, P35, P41-42, P50-55, P60-62, P610-613, P90, P92-910, P912 (FJ3) - P00-03, P05-P06, P10-11, P32-33, P35, P41-42, P50-55, P60-62, P610-613, P90, P92-910, P912, P150-155 (FK3) 1.3 Pin Groups 2x: Pins supplied by EVDD 2A: (CMOS) - PCM0-1 (FE3) - PCM0-3, PCS0-1, PCT0-1, PCT4, PCT6 (FF3) 2D: (SHMT3) - PDL0-7 (FE3) - PDL0-11 (FF3) Data Sheet U18564EE1V2DS00 9 V850ES/FE3 1.4 Pin Groups 3x: Pins supplied by BVDD 3A: (CMOS) - PCM0-3, PCS0-1, PCT0-1, PCT4, PCT6 (FG3) - PCD0-3, PCM0-5, PCS0-7, PCT0-7 (FJ3 + FK3) 3D: (SHMT3) - PDL0-13 (FG3) - PDL0-15 (FJ3 + FK3) 1.5 Pin Groups 4: Pins supplied by AVREF0 4: (CMOS) - P70-79 (FE3) - P70-711 (FF3) - P70-715 (FG3) - P70-715, P120-127 (FJ3 + FK3) 1.6 Pin Groups 5: Pins supplied by AVREF1 - P20-P215 (FK3) (CMOS) 1.7 Pin Groups 6: Pins supplied by EVDD - RESET (SHMT2) - IC, FLMD0 1.8 Pin Groups 7: Pins supplied by VRO - X1, X2, XT1, XT2 10 Data Sheet U18564EE1V2DS00 V850ES/FE3 2. Electrical Specifications of (A)-Grade This product has to be used only under the conditions of VDD=EVDD. Operation is not ensured at the time of using this product except this condition. 2.1 Absolute Maximum Ratings Absolute Maximum Ratings (Ta=25C) Parameter Supply voltage Symbol VDD EVDD AVREF0 VSS EVSS AVSS Input voltage Analog input voltage High level output current Conditions VDD=EVDD, VDD=EVDD VSS=EVSS=AVSS VSS=EVSS=AVSS VSS=EVSS=AVSS VI1 Pin Group 1x, 2x, 6 VI3 Pin Group 7 -0.5 to VRO+0.5 VIAN Pin Group 4 -0.5 to AVREF0+0.5 Note1 Pin Group 1x, 2x IOH Pin Group 4 IOL Pin Group 4 Operating ambient temperature Storage temperature Note1 Note1 Pin Group 1x, 2x Low level output current Rating -0.5 to +6.5 -0.5 to +6.5 -0.5 to +6.5 -0.5 to +0.5 -0.5 to +0.5 -0.5 to +0.5 -0.5 to EVDD+0.5 1 pin Total 1 pin Total 1 pin Total 1 pin Total -4 -50 -4 -20Note2 4 50 4 20Note2 -40 to +85 -40 to +85 -40 to +125 Normal operating mode Flash programming mode Ta Tstg Unit V V V V V V V V V mA mA mA mA mA mA mA mA C C Remarks: 1. The characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified Notes: 1. Be sure not to exceed the absolute maximum ratings (Max. value) of each supply voltage. 2. Excluding ADC IAREF0 current. 2.2 Capacities (Ta = 25C, VDD = EVDD = AVREF0 = VSS = EVSS = AVSS = 0V) Parameter Input/output capacitance Symbol CIO Conditions f=1MHz, Not measured pins is 0V. Data Sheet U18564EE1V2DS00 MIN. TYP. MAX. 10 Unit pF 11 V850ES/FE3 2.3 Operating condition (Ta = -40 to +85C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Internal System clock frequency (fVBCLK) Supply voltage 4.0VVDD5.5VNote2 3.5VVDD<4.0VNote2 4.0fxx32MHz Note1 32kHzfXT35kHz (Crystal) 12.5kHzfXT27.5kHz Note3(RC) fRL (240kHz Internal-OSC) Operating Condition Operation of functions is usable under following conditions: * Peripheral clock frequency * fXP1 32MHz * fXP2 32MHz * AC characteristics: * Refer to chapter '2.7 AC Characteristics' for details. Operation of functions is usable under following conditions: * Peripheral clock frequency * fXP1 20MHz * fXP2 20MHz * AC characteristics: * Refer to chapter '2.7 AC Characteristics' for details. Only operation of the following functions is assured: * CPU * Flash (include programming) * RAM * IO Buffer * Port 3.3VVDD<3.5VNote2 * WT * WDT * INT * CLM * POC * LVI * A/D Converter * Refer to chapter '2.8 A/D Converter' for 3.3VAVREF05.5V details. * stop ADC for AVREF0 < 4.0V (ADA0CE bit =0) 3.3VVDD<5.5VNote2 - 3.3VVDD<5.5VNote2 - Notes: 1. For using SSCG please refer to '2.5.5 SSCG Characteristics' for details 2. VDD = EVDD 3. RC Oscillation frequency is min. 25kHz max. 55kHz. This clock is divided by 2 internally. 12 Data Sheet U18564EE1V2DS00 V850ES/FE3 2.4 Voltage Regulator Characteristics (Ta = -40 to +85C, C=4.7uF, VDD = EVDD, VSS = EVSS = AVSS = 0V)) Parameter Symbol Input voltage VDD Output voltage Output voltage stabilization time VRO Conditions Limited function see '2.3 Operating condition' tREGNote MIN. 3.5 3.3 TYP. MAX. 5.5 2.5 After VDD reaches voltage range min. 3.3V To connect C=4.7uF on REGC terminal 1 Unit V V V ms Note: In case of non-POC device, be sure to start VDD in the state of RESET=VSS=0V. For POC devices there is no need to control external RESET terminal. For decives with POC function the internal RESET signal will automatically controlled until VRO is stable. VDD tREG VRO RESET 2.5 Clock Generator Circuit 2.5.1 Main System Clock Oscillation Circuit Characteristics (Ta = -40 to +85C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Resonator Crystal / Ceramic resonator Recommended Circuit Refer to figure below Parameter Oscillator frequency (fx)Note1 Conditions MIN. TYP. MAX. Oscillation stabilization time Note2 After STOP mode 64Note4 Note3 After IDLE2 mode 54Note4 Note3 4 16 Unit MHz s s Notes: 1. Indicates only oscillation circuit characteristics. Refer to '2.7 AC Characteristics' for CPU operation clock. 2. Time required to stabilize oscillation after VDD reaches oscillator voltage range MIN. 3.3V 3. Depends on the setting of the oscillation stabilization time select register (OSTS) 4. Minimum time required to stabilize flash. Time has to be secured by setting the oscillation stabilization time select register (OSTS) X1 X2 Data Sheet U18564EE1V2DS00 13 V850ES/FE3 2.5.2 Sub System Clock Oscillation Circuit Characteristics (Ta = -40 to +85C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Resonator Recommended Circuit Crystal resonator Refer to Figure 1 RC resonator Refer to Figure 2 Parameter Conditions Oscillator frequency (fxt)Note1 Oscillation stabilization time Note2 Oscillator R=390K 5% Note3, Note1,4 C=47pF10% Note3 frequency Oscillation stabilization time Note2 MIN. TYP. MAX. Unit 32 32.768 35 kHz 10 s 55 kHz 100 s 25 40 Notes: 1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristic" for cpu operation clock. 2. Time required to stabilize oscillation after VDD reaches oscillator voltage range min. 3.3V 3. In order to avoid the influence of wiring capacity, shorten wiring as much as possible. 4. RC Oscillation frequency is typ. 40kHz. This clock is divided by 2 internally. In case of RC Oscillator, internal system clock frequency (fxt) is min. 12.5kHz, typ. 20kHz, max. 27.5kHz. XT1 XT2 XT1 XT2 R 2.5.3 Internal-OSC Characteristics (Ta = -40 to +85C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter Output frequency Oscillation stabilization time 14 Symbol fRL Conditions 240kHz Internal-OSC MIN. 204 TYP. 240 MAX. 276 Unit kHz fRH 8MHz Internal-OSC 240kHz Internal-OSC 7.2 8.0 10 8.8 36 MHz s 8MHz Internal-OSC 51 92 256 s Data Sheet U18564EE1V2DS00 V850ES/FE3 2.5.4 PLL Characteristics (Ta = -40 to +85C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter Input frequency Output frequency Lock time Output period jitter Note2 Symbol fx fPLLI Conditions fxx tPLL 256KB product After VDD reaches voltage range min. 3.3V tpj Peak to peak Note1 MIN. 4 3 12 TYP. MAX. Unit 16 MHz 6 MHz 32 MHz 800 s 2.0 ns Notes: 1. The input of the PLL (fPLLI) can be set to fX, fX/2, or fX/4. The divider is set through an option byte in the code flash memory. 2. Not tested in production. 2.5.5 SSCG Characteristics (Ta = -40 to +85C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter Input frequency Output frequency Symbol fx fXX 256KB product Lock time tSSCG After VDD reaches voltage range min. 3.3V Remark: Conditions MIN. 4 12 TYP. MAX. Unit 16 MHz 32 MHz 1000 s The SSCG MAX output frequency indicates the case without modulation. If modulation is enabled the average SSCG frequency has to be set lower. The maximum achievable average operating frequency with modulation is as follows: Maximum average operating freSSCG input clock divider selector Percent modulation Unit quency SFC1[6:4] TYP MAX 256KB product 000B 0.5% 2.0% 31.4 001B 1.0% 2.5% 31.2 010B 2.0% 4.0% 30.7 MHz 011B 3.0% 6.0% 30.1 100B 4.0% 8.0% 29.4 101B 5.0% 10.0% 28.8 Data Sheet U18564EE1V2DS00 15 V850ES/FE3 2.6 DC Characteristics 2.6.1 Input/Output Level (Ta = -40 to +85C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter High level input voltage Low level input voltage Symbol VIH1 VIH2 Conditions MIN. Pin Group 1B 0.7EVDD EVDD Uni t V Pin Group 1D 0.8EVDD EVDD V Pin Group 2D 0.8EVDD EVDD V MAX. VIH3 Pin Group 2A 0.7EVDD EVDD V VIH4 Pin Group 4 0.7AVREF0 AVREF0 V VIH5 Pin Group 6 0.8EVDD EVDD V VIL1 Pin Group 1B EVSS 0.3EVDD V Pin Group 1D EVSS 0.4EVDD V Pin Group 2D EVSS 0.4EVDD V VIL3 Pin Group 2A EVSS 0.3EVDD V VIL4 Pin Group 4 AVSS VIL2 VIL5 Pin Group 6 Center point at VHYS1 Pin Group 1B 0.5 x EVDD Note3 Center point at Pin Group 1D 0.6 x EVDD Note3 Input hysteresis VHYS2 Center point at Pin Group 2D 0.6 x EVDD Note3 Center point at VHYS5 Pin Group 6 0.5 x EVDD Note3 IOH=-1.0mA Pin Group VOH1 High level 1x, 2x IOH=-100uA output voltage IOH=-1.0mA Note2 VOH3 Pin Group 4 IOH=-100uA Pin Group 1x, IOL=1.0mA 2x Low level output VOL1 P914, 915 IOL=3.0mA voltageNote2 VOL3 Pin Group 4 IOL=1.0mA Software pull-up R1 VI=0V resistor Software Note1 R2 VI=VDD pull-down resistor Remark: TYP. 0.3AVREF0 V 0.2EVDD EVSS 0.267 x EVDD - 0.51V V 0.192 x EVDD - 0.31V V 0.192 x EVDD - 0.31V V 0.535 x EVDD - 0.9V V EVDD-1.0 EVDD-0.5 AVREF0-1.0 AVREF0-0.5 EVDD EVDD AVREF0 AVREF0 V V V V 0 0.4 V 0 0.4 V 10 30 100 k 10 30 100 k The characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. Notes: 1. DRST terminal only. (Control register is OCDM) 2. Total IOH/IOL max is 20mA/-20mA each power supply line (EVDD and AVREF0). AVREF0 IOH/IOL current is excluding ADC0 current IAREF0. 3. Typical value. Not tested and guaranteed 16 V Data Sheet U18564EE1V2DS00 V850ES/FE3 2.6.2 PIN leakage current (Ta = -40 to +85C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter High level input leakage current Low level input leakage current High level output leakage current Low level output leakage current Symbol Conditions ILIH1 VI=VDD ILIL1 VI=0V ILOH1 VO=VDD ILOL1 VO=0V MIN. Analog pins Other pins Note1 Analog pins Other pins Note1 Analog pins Other pins Analog pins Other pins TYP. MAX. 0.2 0.5 -0.2 -0.5 0.2 0.5 -0.2 -0.5 Unit uA Notes: 1. The input leakage current of FLMD0 is as follows: High level input leakage current : 2.0uA Low level input leakage current : -2.0uA Data Sheet U18564EE1V2DS00 17 V850ES/FE3 2.6.3 Power supply current (A-grade) 2.6.3.1 FE3 128KB PD70F3370A, FE3 256KB PD70F3371 (a) Absolute values (Ta = -40 to +85C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0VNote1) Mode Symbol Condition PLL: ON 12MHzfxx32MHz All peripherals running Operating mode Peripheral: fxx PRSI option: 0 PLL: OFF 4MHzfxx16MHz Peripheral: fxx/2 PLL: ON PRSI option: 1 12MHzfxx32MHz IDD1 Note2,8 PLL: ON 12MHzfxx32MHz All peripherals stopped Peripheral: fxx PRSI option: 0 PLL: OFF 4MHzfxx16MHz PLL: ON Peripheral: fxx/2 PRSI option: 1 12MHzfxx32MHz PLL: ON 12MHzfxx32MHz All peripherals running HALT mode Peripheral: fxx PRSI option: 0 PLL: OFF 4MHzfxx16MHz PLL: ON Peripheral: fxx/2 PRSI option: 1 12MHzfxx32MHz IDD2 Note8 PLL: ON 12MHzfxx32MHz All peripherals stopped Peripheral: fxx PRSI option: 0 PLL: OFF 4MHzfxx16MHz PLL: ON Peripheral: fxx/2 PRSI option: 1 12MHzfxx32MHz 18 Data Sheet U18564EE1V2DS00 TYP. MAX. Unit fxx=20MHz fx=5MHz 27 37 mA fxx=32MHz fx=16MHz 39 51 mA 13 20 mA 21 30 mA fxx=32MHz fx=16MHz 35 47 mA fxx=20MHz fx=5MHz 22 mA fxx=32MHz fx=16MHz 32 mA 12 mA 19 mA fxx=32MHz fx=16MHz 31 mA fxx=20MHz fx=5MHz 16 23 mA fxx=32MHz fx=16MHz 24 34 mA 8 12 mA 13 20 mA fxx=32MHz fx=16MHz 20 27 mA fxx=20MHz fx=5MHz 12 mA fxx=32MHz fx=16MHz 18 mA 5 mA 9 mA 17 mA fxx=8MHz 8MHz InternalOSC Note3 fxx=16MHz fx=16MHz fxx=8MHz 8MHz InternalOSC Note3 fxx=16MHz fx=16MHz fxx=8MHz 8MHz InternalOSC Note3 fxx=16MHz fx=16MHz fxx=8MHz 8MHz InternalOSC Note3 fxx=16MHz fx=16MHz fxx=32MHz fx=16MHz V850ES/FE3 Mode Symbol Condition Peripheral (TAA, UARTD) running IDLE1 mode IDD3 All peripherals stopped TYP. MAX. Unit PLL: OFF 4MHzfxx16MHz Note7 fxx=5MHz fx=5MHz 1.4 2.2 mA fxx=12MHz fx=12MHz 2.0 3.1 mA fxx=16MHz fx=16MHz 2.4 3.6 mA 1.5 2.3 mA fxx=8MHz, 8MHz Internal-OSCNote3 fxx=5MHz fx=5MHz PLL: OFF fxx=12MHz 4MHzfxx16MHz fx=12MHz Note7 fxx=16MHz fx=16MHz fxx=8MHz, 8MHz Internal-OSCNote3 fxx=5MHz fx=5MHz IDLE2 mode SUB operating modeNote5 SubIDLE mode PLL: OFF 4MHzfxx16MHz IDD4 Note7 STOP mode Note3,4 mA 1.1 mA 0.7 1.0 mA fxx=16MHz fx=16MHz 0.8 1.2 mA RC resonator (fxt=20kHz) Note6 240kHz Internal-OSC (SubOSC stopped) 240kHz Internal-OSC stop 240kHz Internal-OSC working 240kHz Internal-OSC stop 240kHz Internal-OSC working Data Sheet U18564EE1V2DS00 1.6 fxx=12MHz fx=12MHz IDD6 POC work mA mA RC resonator (fxt=20kHz) Note6 240 kHz Internal-OSC (SubOSC stopped) Crystal resonator (fxt = 32,768kHz) POC stop 1.4 0.7 IDD5 IDD7 mA 0.4 fxx=8MHz, 8MHz Internal-OSC Note3 Crystal resonator (fxt = 32,768kHz) Note3,5 1.2 0.2 80 80 220 20 40 25 7.5 15.5 10.5 18.5 0.5 mA 400 A 400 A 1000 A 190 A 220 A 180 A 80 A 95 A 85 A 100 A 19 V850ES/FE3 (b) Calculation formulas (Ta = -40 to +85C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0VNote1)) Mode Symbol Condition PLL: ON 12MHzfxx32MHz Operating mode IDD1 Note2,8 Peripheral: fxx PLL: OFF All peripherals PRSI option: 0 4MHzfxx16MHz running PLL: ON Peripheral: fxx/2 PRSI option: 1 12MHzfxx32MHz PLL: ON Peripheral: ffxx- 12MHzfxx32MHz PLL: OFF All peripherals PRSI option: 0 4MHzfxx16MHz stopped Peripheral: fxx/2 PLL: ON PRSI option: 1 12MHzfxx32MHz PLL: ON Peripheral: ffxx- 16MHzfxx32MHz HALT mode IDD2 Note8 IDLE1 mode IDD3 IDLE2 mode IDD4 PLL: OFF All peripherals PRSI option: 0 4MHzfxx16MHz running PLL: ON Peripheral: fxx/2 PRSI option: 1 16MHzfxx32MHz PLL: ON Peripheral: fxx 16MHzfxx32MHz All peripherals PRSI option: 0 stopped Peripheral: fxx/2 PRSI option: 1 Peripheral (TAA, UARTD) running All peripherals stopped PLL: OFF 4MHz fxx16MHz TYP. Note9 MAX. Note9 Unit 0.98fxx+7.1 1.18fxx+13.6 mA 0.98fxx+5.5 1.18fxx+10.6 mA 0.90fxx+6.0 1.08fxx+12.2 mA 0.81fxx+6.2 mA 0.83fxx+5.7 mA 0.79fxx+6.2 mA 0.67fxx+3.0 0.90*fxx+5.4 mA 0.70fxx+1.9 1.00*fxx+4.0 mA 0.55fxx+2.8 0.64*fxx+7.0 mA 0.46fxx+2.8 mA PLL: OFF 4MHzfxx16MHz 0.44fxx+1.6 mA PLL: ON 16MHzfxx32MHz 0.46fxx+1.8 mA PLL: OFF 4MHzfxx16MHz Note7 Note7 0.092fxx+0.90 0.128fxx+ 1.35 mA 0.035fxx+1.01 mA 0.037fxx+0.21 0.049fxx+ 0.43 mA Notes: 1. VDD and EVDD total current. (Ports are stopped). AVREF0 current, port buffer current (including a current flowing in the on-chip pull-up/pulldown resistor) are not included. 2. The code flash and the data flash are in read mode. When the device is in programming mode (Self-programming mode or data flash programming mode), the current value (MAX. value) adds by the following value: 3. 4. 5. 6. 7. 8. 9. 20 * Self-programming mode: + In case of PLL OFF: 7-(0.33*fxx+0.1) [mA] + In case of PLL ON: 7-(0.18*fxx+3.0) [mA] * Data flash programming mode: + 7-(0.18*fxx/4+3.0) [mA] Main OSC is stopped. Do not use SubOSC. POC is working. 240kHz Internal-OSC is working. 8MHz Internal-OSC is stopped. RC Oscillation frequency is typ.40kHz. This clock is divided by 2 internally. 8MHz Internal-OSC is stopped When the SSCG is running, the current value adds typ +2.5mA, max +4mA. The formulas are for reference only. Not all possible values for fxx are tested in the outgoing device inspection. Data Sheet U18564EE1V2DS00 V850ES/FE3 2.7 AC Characteristics AC test Input measurement points ( VDD, AVREF0, EVDD) VDD VIH(min) VIH(min) measure point VIL(max) VSS VIL(max) AC test output measurement points VOH(min) VOH(min) measure point VOL(max) VOL(max) Load conditions DUT ( Device under test ) Caution: CL = 50 pF If the load capacitance exceeds 50pF due to the circuit configuration, reduce the load capacitance of the device to 50pF or less by inserting a buffer or by some other means. 2.7.1 CLKOUT Output Timing (Ta = -40 to +85C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF) Parameter Symbol Conditions VDD = EVDD = 4.0V ~ 5.5V tCYK VDD = EVDD = 3.5V ~ 5.5V VDD = EVDD = 4.0V ~ 5.5V tWKH VDD = EVDD = 3.5V ~ 5.5V VDD = EVDD = 4.0V ~ 5.5V tWKL VDD = EVDD = 3.5V ~ 5.5V VDD = EVDD = 4.0V ~ 5.5V tKR VDD = EVDD = 3.5V ~ 5.5V VDD = EVDD = 4.0V ~ 5.5V tKF VDD = EVDD = 3.5V ~ 5.5V Output cycle High level width Low level width Rise time Fall time MIN. 31.25ns 50ns tCYK/2-13 tCYK/2-15 tCYK/2-13 tCYK/2-15 MAX. Unit 80s ns ns 13 15 13 15 ns ns CLKOUT output timing tCYK tWKH tWKL CLKOUT tKR tKF * Data Sheet U18564EE1V2DS00 21 V850ES/FE3 2.7.2 RESET, Interrupt, ADTRG Timing (Ta = -40 to +85C, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF) Parameter _RESET input low level width NMI input high level width NMI input low level width Symbol tWRSL tWNIH tWNIL INTPnNote1 input high level width tWITH INTPn Note1 input low level width tWITL Conditions analog filter analog filter analog filter analog filter ,n=0-8 digital filter ,n=3 analog filter ,n=0-8 digital filter ,n=3 MIN. 250 250 250 250 TYP. MAX. Note2 250 Note2 Unit ns ns ns ns ns ns ns Notes: 1. ADTRG is same spec (P03/INTP0/ADTRG). DRST is same spec (P05/INTP2/DRST) 2. 2Tsamp+20 or 3Tsamp+20 ("Tsamp" is Noise reject sampling clock (NF macro)) Remarks: 1. The above minimum values show pulse widths that are surely detected as an effective edge. An effective may also be detected even if the input pulse width is less than the above minimum specification. 2. RESET, NMI, INTPn, ADTRG and DRST have analog noise filter. The typical filter time is typ=60ns. 2.7.3 Key Return Timing (Ta = -40 to +85C, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF) Parameter KRn input high level width KRn input low level width Symbol tWKRH tWKRL Conditions analog filter ,n=0-7 analog filter ,n=0-7 MIN. 250 250 TYP. MAX. Unit ns ns Remarks: 1. The above minimum values show pulse widths that are surely detected as an effective edge. An effective may also be detected even if the input pulse width is less than the above minimum specification. 2. KRn inputs have analog noise filter. The typical filter time is typ=60ns. 2.7.4 Timer Timing (Ta = -40 to +85C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF) Parameter TI input high level width TI input low level width TO output cycle Symbol Conditions TIAA00-01,10-11,20-21,30-31,40-41 Note1 tTIH TIAB00-03 Note1 TIAA00-01,10-11,20-21,30-31,40-41 Note1 tTIL TIAB00-03 Note1 4.0VVDD5.5V TIAA00-01,10-11,20-21,30-31, tTCYK 40-41 Note1 3.5VVDD<4.0V TIAB00-03 Note1 MIN. TYP. MAX. Unit 250 ns 250 ns 16 MHz 10 MHz Notes: 1. Except for the external trigger and external event function. Remarks: 1. The above minimum values show pulse widths that are surely detected as an effective edge. An effective may also be detected even if the input pulse width is less than the above minimum specification. 2. TIAAn and TIABn inputs have analog noise filter. The typical filter time is typ=60ns. 22 Data Sheet U18564EE1V2DS00 V850ES/FE3 2.7.5 CSI Timing (a) Master mode (Ta = -40 to +85C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF) Parameter SCKBn cycle time SCKBn high level width SCKBn low level width SIBn setup time ( to SCKBn ) SIBn hold time ( from SCKBn ) Delay time from SCKBn to SOBn Symbol tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1 Conditions MIN. 125 tKCY1/2-15 tKCY1/2-15 30 25 MAX. 25 Unit ns ns ns ns ns ns (b) Slave mode (Ta = -40 to +85C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF) Parameter SCKBn cycle time SCKBn high level width SCKBn low level width SIBn setup time ( to SCKBn ) SIBn hold time ( from SCKBn ) Delay time from SCKBn to SOBn CSIBn Symbol tKCY1 tKH1 tKL1 tSIK1 tKSI1 tKSO1 n=0-2 Conditions MIN. 200 90 90 50 50 MAX. 50 Unit ns ns ns ns ns ns tKCYn tKLn tKHn SCKBn tSIKn SIBn tKSIn Input data tKSOn SOBn Output data 2.7.6 UART Timing (Ta = -40 to +85C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF) Parameter Transfer rate ASCK0 frequency Symbol Conditions MIN. Data Sheet U18564EE1V2DS00 TYP. MAX. 1.5 10 Unit Mbps MHz 23 V850ES/FE3 2.7.7 IIC Timing (Ta = -40 to +85C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF) Parameter Symbol SCL00 clock frequency Bus-free time (between stop/start conditions) Hold timeNote1 SCL00 clock low-level width SCL00 clock high-level width Setup time for start/restart conditions CBUS compatible master Data hold time IIC mode Data setup time fCLK Normal mode min. max. 0 100 Unit kHz tBUF 4.7 1.3 us tHD:STA tLOW tHIGH tSU:STA 4.0 4.7 4.0 4.7 5.0 0.6 1.3 0.6 0.6 0Note2 250 0Note2 us us us us us us tHD:DAT tSU:DAT SDA00 and SCL00 signal rise time tR 1000 SDA00 and SCL00 signal fall time tF 300 Stop condition setup time Pilse width with spike supporessed by input filter Capacitance load of each bus line High-speed mode min. max. 0 400 tSU:STO 4.0 20+0.1Cb ns 300 ns 300 ns 0.6 tSP Cb 100Note4 20+0.1Cb 0.9Note3 0 400 us 50 ns 400 pF Notes: 1. At the start condition, the first clock pulse is generated after the hold time 2. The system requires a minimum of 300ns hold time Internally for the SDA signal ( at VIHmin. of SCL00 signal ) In order to occupy the undefined area at the falling edge of SCL00. 3. If the system does not extend the SCL00 signal low hold time ( tlow ), only the maximum data hold time (tHD:DAT ) needs to be satisfied. 4. The high-speed-mode IIC bus can be used In a normal-mode IIC bus system. In this case, set the high-speed-mode IIC bus so that It meets the following conditions. - If the system does not extend the SCL00 signal's low state hold time: SU:DAT?250ns - If the system extends the SCL00 signal's low state hold time: Transmit the following data bit to the SDA00 line prior to releasing the SCL00 line (tRmax.+tSU:DAT=1000+250=1250ns: Normal mode IIC bus specification ). 5. Cb: Total capacitance of one bus line (unit: pF) 24 Data Sheet U18564EE1V2DS00 V850ES/FE3 IIC bus interface timing tLOW tHIGH tR tF SCL00 tHD:STA tSU:DAT tHD:DAT SDA00 tBUF P S tSU:STA tHD:STA Sr Remark: tSP tSU:STO P P: Stop condition S: Start condition Sr: Restart condition Data Sheet U18564EE1V2DS00 25 V850ES/FE3 2.7.8 CAN Timing (Ta = -40 to +85C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF) Parameter Transfer rate Internal delay time Symbol Conditions MIN. TYP. MAX. 1 100 CAN Internal clock* toutput CTXDn pin ( Transfer data ) tinput CRXDn pin ( Receive data ) Internal delay time (tNODE)= Internal Transfer Delay(toutput) + Internal Receive Delay(tinput) *) CAN Internal clock (fCAN) :CAN baud rate clock V850ES/Fx3 Internal Transfer delay CTXDn pin CAN macro Internal Receive delay CRXDn pin Image figure of Internal delay 26 Data Sheet U18564EE1V2DS00 Unit Mbps ns V850ES/FE3 2.8 A/D Converter (Ta = -40 to +85C, C=4.7uF, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 4.0 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter Resolution Overall errorNote1 Conversion time Stabilization time Recovery time for power down mode Zero-scale errorNote1 Conditions MIN. 4.0VAVREF0<5.5V tCONV tSTA After ADA0PS bit = 0 -> 1 tDPU TYP. 0.15 3.10 2 Full-scale error errorNote2 errorNote2 Differential non-liniearity Analog input voltage Analog input equivalent circuit capacitance Note3,4 Analog input equivalent circuit resistance Note3 AVREF0 current Conversion rusult when using Diagnostic function MAX. 10 0.3 16 1 Unit bit %FSR s s s ZSE Note1 Integral non-liniearity Symbol 0.3 %FSR FSE 0.3 %FSR INL 2.5 LSB 1.5 AVREF0 LSB V CINA 6.19 pF RINA 2.55 k 7 10 3FF 003 mA uA HEX HEX DNL VIAN IAREF0 AVSS A/D operating A/D operation stop AVREF0 conversion AVSS conversion 4 1 3FC 000 Notes: 1. Overall error excluding quantization error (0.05%FSE). It is indicated as a ratio to the fullscale value. 2. Excluding quantization error (1/2 LSB) 3. Not tested in production. 4. Does not include input/output capacitance CIO Data Sheet U18564EE1V2DS00 27 V850ES/FE3 2.9 POC (Ta = -40 to +85C, C=4.7uF, VDD = EVDD, VSS = EVSS = AVSS = 0V) Parameter Detect voltage Symbol VPOC0 Supply voltage rise time tPTH tPTHD Response time1 Note1 Response time2 tPD Note2 VDD minimum width Conditions MIN. 3.3 From VDD=0V to VDD=3.3V In case of power on. After VDD reaches 3.7V. In case of power off. After VDD drop 3.3V. TYP. 3.5 MAX. 3.7 0.002 ms 0.2 tPW Unit V 0.2 2.0 ms 1.0 ms ms Notes: 1. From detect voltage to release reset signal 2. From detect voltage to occurrence of reset signal VDD Detect voltag(MAX.) (TYP.) (MIN.) tPW tPTH tPTHD tPD tPTHD T Note: POC is available only in M2 devices. Refer to 'Ordering information' in the V850ES/Fx3 User's Manual. 28 Data Sheet U18564EE1V2DS00 V850ES/FE3 2.10 LVI (Ta = -40 to +85C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter Symbol VLVI0 VLVI1 Detect voltage Response time Note1 tLD VDD minimum width Reference voltage stabilization wait time Note2 tLW tLWAIT Conditions MIN. 3.8 3.5 TYP. MAX. 4.0 4.2 3.7 3.9 After VDD reaches VLVI0/1(max). After VDD drop VLVI0/1(min). 0.2 2.0 0.2 Unit V V ms ms After VDD reaches 3.3V. After LVION bit (LVIM.bit7) = 0->1 0.1 0.2 ms Notes: 1. From detect voltage to occurrence interrupt/reset signal 2. If POC functionality is available, the wait time is not needed. VDD Detect voltag(MAX.) (TYP.) (MIN.) Operation voltage (MIN.) tLW tLD tLWAIT LVION bit=0 tLD T 1(LVI function work) 2.11 RAM Retention Flag (Ta = -40 to +85C, C=4.7uF, VDD = EVDD = 1.9 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter Detect voltage Supply voltage rise time Response time Note1 VDD minimum width Symbol VRAMH tRAMHTH tRAMHD tRAMHW Conditions From VDD=0V to VDD=3.3V After VDD reaches 2.1V. MIN. 1.9 0.002 TYP. 2.0 0.2 0.2 MAX. 2.1 1800 2.0 Unit V ms ms ms Notes: 1. From detect voltage to set RAMFbit (RAMS.bit0) VDD Operation voltage (MIN.) Detect voltag(MAX.) (TYP.) (MIN.) tRAMHTH tRAMHD tRAMHW tRAMHD T Data Sheet U18564EE1V2DS00 29 V850ES/FE3 2.12 Data Retention Characteristics (Ta = -40 to +85C, C=4.7uF, VDD = EVDD = 1.9 to 5.5V, VSS = EVSS = AVSS = 0V) ( Parameter Data retention power supply voltage Data retention power supply current Supply voltage rise time Supply voltage fall time Supply voltage hold time Symbol VDDDR IDDDR tRVD tFVD tHVD STOP release signal input time tDREL Data retention high-level input voltage Data retention low-level input voltage Remark: Conditions STOP mode (All function is stopped) VDDDR=2.0V( All function is stopped) MIN. TYP. 1.9 6.5 After STOP mode After VDD reaches operating voltage range MIN. 3.3V MAX. Unit 5.5 V 70 A 1 1 0 s s ms 0 ms VIHDR All input port 0.9VDDDR VDDDR V VILDR All input port 0 0.1VDDDR V When STOP mode is entered/released operation voltage range must be controlled. Setting STOP mode tFVD tRVD Operation voltage(min.) VDD/EVDD/BVDD tHVD VDDDR VIHDR _RESET NMI,INTPn(Input) (When STOP mode is released at falling edge) NMI,INTPn(Input) (When STOP mode is released at rising edge) 30 VIHDR VILDR Data Sheet U18564EE1V2DS00 tDREL V850ES/FE3 2.13 Flash Memory Programming Characteristics (a) Basic Characteristics (C=4.7uF, VDD = EVDD, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter Operation frequency Supply voltage Number of rewrites High level input voltage Low level input voltage Programming temperature Symbol fCPU VDD Conditions MIN. 4 3.3 Code Flash CWRT1 MAX. 32 5.5 1000 Data Flash CWRT2 VIH VIL tPRG TYP. count 10000 0.8EVDD EVSS -40 FLMD0 FLMD0 EVDD 0.2EVDD +85 Code Flash Data retention Unit MHz V 15Note1 Data Flash V V C year 5Note2 Notes: 1. Under the condition of CWRT1 2. Under the condition of CWRT2 Remark: The initial write when the product is shipped, any erase write set of operations, or any programming operation is counted as one rewrite. Example: P: Program(write) E: Erase Product is shipped P E P E P : Rewrite count: 3 Product is shipped E P E P E P : Rewrite count: 3 (b) Serial Writing Operation Characteristics (Ta = -40 to +85C, C=4.7uF, VDD = EVDD, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF) Parameter FLMD0 setup time (from VDD) RESET release (from FLMD0) FLMD0 pulse input start (from raise edge of _RESET) FLMD0 high level width / low level width FLMD0 raise time FLMD0 fall time Symbol tDP tPR Conditions MIN. 1 2 tRP 800 tPW 10 tR tF Data Sheet U18564EE1V2DS00 TYP. MAX. Unit ms ms s 100 s 50 50 ns ns 31 V850ES/FE3 3. Electrical Specifications of (A1)-Grade This product has to be used only under the conditions of VDD=EVDD. Operation is not ensured at the time of using this product except this condition. 3.1 Absolute Maximum Ratings Absolute Maximum Ratings (Ta=25C) Parameter Supply voltage Input voltage Analog input voltage High level output current Symbol VDD EVDD AVREF0 VSS EVSS AVSS Conditions VDD=EVDD, VDD=EVDD VSS=EVSS=AVSS VSS=EVSS=AVSS VSS=EVSS=AVSS VI1 Pin Group 1x, 2x, 6 VI3 Pin Group 7 -0.5 to VRO+0.5 VIAN Pin Group 4 -0.5 to AVREF0+0.5 Note1 Pin Group 1x, 2x IOH Pin Group 4 IOL Pin Group 4 Operating ambient temperature Storage temperature Ta Note1 Note1 Pin Group 1x, 2x Low level output current Rating -0.5 to +6.5 -0.5 to +6.5 -0.5 to +6.5 -0.5 to +0.5 -0.5 to +0.5 -0.5 to +0.5 -0.5 to EVDD+0.5 Normal operating mode Flash programming mode Tstg 1 pin Total 1 pin Total 1 pin Total 1 pin Total -4 -20 -4 -10Note2 4 20 4 10Note2 -40 to +110 -40 to +110 -40 to +125 Unit V V V V V V V V V mA mA mA mA mA mA mA mA C C Remarks: 1. The characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified Notes: 1. Be sure not to exceed the absolute maximum ratings (Max. value) of each supply voltage. 2. Excluding ADC0 IAREF0 current. 3.2 Capacities Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.3 Operating condition Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.4 Voltage Regulator Characteristics Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.5 Clock Generator Circuit 3.5.1 Main System Clock Oscillation Circuit Characteristics Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 32 Data Sheet U18564EE1V2DS00 V850ES/FE3 3.5.2 Sub System Clock Oscillation Circuit Characteristics (Ta = -40 to +110C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Resonator Recommended Circuit RC resonator Refer to Figure 2 Parameter Conditions Oscillator R=390K 5% Note3, C=47pF10% Note3 frequencyNote1,4 Oscillation stabilization time Note2 MIN. TYP. MAX. Unit 25 40 55 kHz 100 s Notes: 1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristic" for cpu operation clock. 2. Time required to stabilize oscillation after VDD reaches oscillator voltage range min. 3.3V 3. In order to avoid the influence of wiring capacity, shorten wiring as much as possible. 4. RC Oscillation frequency is typ. 40kHz. This clock is divided by 2 internally. In case of RC Oscillator, internal system clock frequency(fxt) is min. 12.5kHz, typ. 20kHz, max. 27.5kHz. XT1 XT2 R 3.5.3 Internal-OSC Characteristics Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.5.4 PLL Characteristics Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.5.5 SSCG Characteristics Specification is identical to that from (A)-Grade except Ta=-40 to +110C. Data Sheet U18564EE1V2DS00 33 V850ES/FE3 3.6 DC Characteristics 3.6.1 Input/Output Level (Ta = -40 to +110C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter High level input voltage Low level input voltage Symbol VIH1 VIH2 Conditions MIN. Pin Group 1B 0.7EVDD EVDD Uni t V Pin Group 1D 0.8EVDD EVDD V Pin Group 2D 0.8EVDD EVDD V Pin Group 2A 0.7EVDD EVDD V VIH4 Pin Group 4 0.7AVREF0 AVREF0 V VIH5 Pin Group 6 0.8EVDD EVDD V VIL1 Pin Group 1B EVSS 0.3EVDD V Pin Group 1D EVSS 0.4EVDD V Pin Group 2D EVSS 0.4EVDD V VIL3 Pin Group 2A EVSS 0.3EVDD V VIL4 Pin Group 4 AVSS VIL2 Pin Group 6 Center point at VHYS1 Pin Group 1B 0.5 x EVDD Note3 Center point at Pin Group 1D 0.6 x EVDD Note3 Input hysteresis VHYS2 Center point at Pin Group 2D 0.6 x EVDD Note3 Center point at VHYS5 Pin Group 6 0.5 x EVDD Note3 IOH=-1.0mA Pin Group VOH1 High level 1x, 2x IOH=-100uA output voltage IOH=-1.0mA Note2 VOH3 Pin Group 4 IOH=-100uA Pin Group 1x, IOL=1.0mA 2x Low level output VOL1 P914, 915 IOL=3.0mA voltageNote2 VOL3 Pin Group 4 IOL=1.0mA Software pull-up R1 VI=0V resistor Software Note1 R2 VI=VDD pull-down resistor 0.3AVREF0 V 0.2EVDD EVSS V 0.267 x EVDD - 0.51V V 0.192 x EVDD - 0.31V V 0.192 x EVDD - 0.31V V 0.535 x EVDD - 0.9V V EVDD-1.0 EVDD-0.5 AVREF0-1.0 AVREF0-0.5 EVDD EVDD AVREF0 AVREF0 V V V V 0 0.4 V 0 0.4 V 10 30 100 k 10 30 100 k The characteristics of the dual-function pins are the same as those of the port pins unless otherwise specified. Notes: 1. DRST terminal only. (Control register is OCDM) 2. Total IOH/IOL max is 20mA/-20mA for the power supply line EVDD. Total IOH/IOL max is 10mA/-10mA for the power supply line AVREF0. AVREF0 IOH/IOL current is excluding ADC0 current IAREF0. 3. Typical value. Not tested and guaranteed 34 MAX. VIH3 VIL5 Remark: TYP. Data Sheet U18564EE1V2DS00 V850ES/FE3 3.6.2 PIN leakage current (Ta = -40 to +110C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter High level input leakage current Low level input leakage current High level output leakage current Low level output leakage current Symbol Conditions ILIH1 VI=VDD ILIL1 VI=0V ILOH1 VO=VDD ILOL1 VO=0V MIN. Analog pins Other pins Note1 Analog pins Other pins Note1 Analog pins Other pins Analog pins Other pins TYP. MAX. 0.4 0.8 -0.4 -0.8 0.4 0.8 -0.4 -0.8 Unit uA Notes: 1. The input leakage current of FLMD0 is as follows: High level input leakage current : 4.0uA Low level input leakage current : -4.0uA Data Sheet U18564EE1V2DS00 35 V850ES/FE3 3.6.3 Power supply current (A1-grade) 3.6.3.1 FE3 128KB PD70F3370A, FE3 256KB PD70F3371 (a) Absolute values (Ta = -40 to +110C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0VNote1) Mode Symbol Condition PLL: ON 12MHzfxx32MHz All peripherals running Operating mode Peripheral: fxx PRSI option: 0 PLL: OFF 4MHzfxx16MHz PLL: ON Peripheral: fxx/2 PRSI option: 1 12MHzfxx32MHz IDD1 Note2,8 PLL: ON 12MHzfxx32MHz All peripherals stopped Peripheral: fxx PRSI option: 0 PLL: OFF 4MHzfxx16MHz PLL: ON Peripheral: fxx/2 PRSI option: 1 12MHzfxx32MHz PLL: ON 12MHzfxx32MHz All peripherals running HALT mode Peripheral: fxx PRSI option: 0 PLL: OFF 4MHzfxx16MHz PLL: ON Peripheral: fxx/2 PRSI option: 1 12MHzfxx32MHz IDD2 Note8 PLL: ON 12MHzfxx32MHz All peripherals stopped Peripheral: fxx PRSI option: 0 PLL: OFF 4MHzfxx16MHz PLL: ON Peripheral: fxx/2 PRSI option: 1 12MHzfxx32MHz 36 Data Sheet U18564EE1V2DS00 TYP. MAX. Unit fxx=20MHz fx=5MHz 27 37 mA fxx=32MHz fx=16MHz 39 51 mA 13 20 mA 21 30 mA fxx=32MHz fx=16MHz 35 47 mA fxx=20MHz fx=5MHz 22 mA fxx=32MHz fx=16MHz 32 mA 12 mA 19 mA fxx=32MHz fx=16MHz 31 mA fxx=20MHz fx=5MHz 16 23 mA fxx=32MHz fx=16MHz 24 34 mA 8 12 mA fxx=16MHz fx=16MHz 13 20 mA fxx=32MHz fx=16MHz 20 27 mA fxx=20MHz fx=5MHz 12 mA fxx=32MHz fx=16MHz 18 mA 5 mA 9 mA 17 mA fxx=8MHz 8MHz InternalOSC Note3 fxx=16MHz fx=16MHz fxx=8MHz 8MHz InternalOSC Note3 fxx=16MHz fx=16MHz fxx=8MHz 8MHz InternalOSC Note3 fxx=8MHz 8MHz InternalOSC Note3 fxx=16MHz fx=16MHz fxx=32MHz fx=16MHz V850ES/FE3 Mode Symbol Condition Peripheral (TAA, UARTD) running IDLE1 mode TYP. MAX. Unit PLL: OFF 4MHzfxx16MHz Note7 fxx=5MHz fx=5MHz 1.4 2.5 mA fxx=12MHz fx=12MHz 2.0 3.4 mA fxx=16MHz fx=16MHz 2.4 3.9 mA 1.5 2.6 mA fxx=8MHz, 8MHz Internal-OSCNote3 fxx=5MHz fx=5MHz PLL: OFF fxx=12MHz 4MHzfxx16MHz fx=12MHz IDD3 All peripherals stopped Note7 fxx=16MHz fx=16MHz fxx=8MHz, 8MHz Internal-OSCNote3 fxx=5MHz fx=5MHz IDLE2 mode STOP mode Note3,4 POC stop IDD7 POC work 1.6 mA 1.1 mA fxx=12MHz fx=12MHz 0.7 1.2 mA fxx=16MHz fx=16MHz 0.8 1.4 mA 0.2 0.7 mA 80 600 A 240 kHz Internal-OSC (SubOSC stopped) 220 1200 A RC resonator (fxt=20kHz) Note6 40 420 A 240kHz Internal-OSC (SubOSC stopped) 25 380 A 7.5 15.5 10.5 18.5 280 295 285 300 A A A A RC resonator (fxt=20kHz) IDD6 mA mA Note7 IDD5 1.4 0.9 fxx=8MHz, 8MHz Internal-OSC Note3 SUB operating modeNote5 SubIDLE modeNote3, mA 0.4 PLL: OFF 4MHzfxx16MHz IDD4 1.2 Note6 240kHz Internal-OSC stop 240kHz Internal-OSC working 240kHz Internal-OSC stop 240kHz Internal-OSC working Data Sheet U18564EE1V2DS00 37 V850ES/FE3 (b) Calculation formulas (Ta = -40 to +110C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0VNote1) Mode Symbol Condition PLL: ON 12MHzfxx32MHz Operating mode IDD1 Note2,8 Peripheral: fxx PLL: OFF PRSI option: 0 All peripherals 4MHzfxx16MHz running PLL: ON Peripheral: fxx/2 PRSI option: 1 12MHzfxx32MHz PLL: ON Peripheral: ffxx- 12MHzfxx32MHz PLL: OFF All peripherals PRSI option: 0 4MHzfxx16MHz stopped Peripheral: fxx/2 PLL: ON PRSI option: 1 12MHzfxx32MHz PLL: ON Peripheral: ffxx- 16MHzfxx32MHz HALT mode IDD2 Note8 IDLE1 mode IDD3 IDLE2 mode IDD4 PLL: OFF All peripherals PRSI option: 0 4MHzfxx16MHz running PLL: ON Peripheral: fxx/2 PRSI option: 1 16MHzfxx32MHz PLL: ON Peripheral: fxx 16MHzfxx32MHz PLL: OFF All peripherals PRSI option: 0 4MHzfxx16MHz stopped TYP. Note9 MAX. Note3 Unit 0.98fxx+7.1 1.18fxx+13.6 mA 0.98fxx+5.5 1.18fxx+10.6 mA 0.90fxx+6.0 1.08fxx+12.2 mA 0.81fxx+6.2 mA 0.83fxx+5.7 mA 0.79fxx+6.2 mA 0.67fxx+3.0 0.90*fxx+5.4 mA 0.70fxx+1.9 1.00*fxx+4.0 mA 0.55fxx+2.8 0.64*fxx+7.0 mA 0.46fxx+2.8 mA 0.44fxx+1.6 mA Peripheral: fxx/2 PLL: ON 0.46fxx+1.8 PRSI option: 1 16MHzfxx32MHz Peripheral (TAA, UARTD) runPLL: OFF 0.092fxx+0.90 0.128fxx+ 1.82 ning 4MHzfxx16MHz 0.035fxx+1.01 All peripherals stopped Note7 PLL: OFF 0.037fxx+0.21 0.049fxx+ 0.63 4MHz fxx16MHz Note7 mA mA mA mA Notes: 1. VDD and EVDD total current. (Ports are stopped). AVREF0 current, port buffer current (including a current flowing in the on-chip pull-up/pulldown resistor) are not included. 2. The code flash and the data flash are in read mode. When the device is in programming mode (Self-programming mode or data flash programming mode), the current value (MAX. value) adds by the following value: 3. 4. 5. 6. 7. 8. 9. 38 * Self-programming mode: + In case of PLL OFF: 7-(0.33*fxx+0.1) [mA] + In case of PLL ON: 7-(0.18*fxx+3.0) [mA] * Data flash programming mode: + 7-(0.18*fxx/4+3.0) [mA] Main OSC is stopped. Do not use SubOSC. POC is working. 240kHz Internal-OSC is working. 8MHz Internal-OSC is stopped. RC Oscillation frequency is typ.40kHz. This clock is divided by 2 internally. 8MHz Internal-OSC is stopped When the SSCG is running, the current value adds typ +2.5mA, max +4mA. The formulas are for reference only. Not all possible values for fxx are tested in the outgoing device inspection. Data Sheet U18564EE1V2DS00 V850ES/FE3 3.7 AC Characteristics AC test Input measurement points ( VDD, AVREF0, EVDD) VDD VIH(min) VIH(min) measure point VIL(max) VSS VIL(max) AC test output measurement points VOH(min) VOH(min) measure point VOL(max) VOL(max) Load conditions DUT ( Device under test ) Caution: CL = 50 pF If the load capacitance exceeds 50pF due to the circuit configuration, reduce the load capacitance of the device to 50pF or less by inserting a buffer or by some other means. 3.7.1 CLKOUT Output Timing Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.7.2 RESET, Interrupt, ADTRG Timing Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.7.3 Key Return Timing Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.7.4 Timer Timing Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.7.5 CSI Timing Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.7.6 UART Timing Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.7.7 IIC Timing Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.7.8 CAN Timing Specification is identical to that from (A)-Grade except Ta=-40 to +110C. Data Sheet U18564EE1V2DS00 39 V850ES/FE3 3.8 A/D Converter Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.9 POC Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.10 LVI Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.11 RAM Retention Flag Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.12 Data Retention Characteristics Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 3.13 Flash Memory Programming Characteristics (a) Basic Characteristics (C=4.7uF, VDD = EVDD, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter Operation frequency Supply voltage Number of rewrites High level input voltage Low level input voltage Programming temperature Symbol fCPU VDD Conditions Code Flash CWRT1 Data Flash CWRT2 VIH VIL tPRG FLMD0 FLMD0 MIN. 4 3.3 MAX. 32 5.5 1000 10000 0.8EVDD EVSS -40 Code Flash Data retention TYP. Data Flash Unit MHz V count EVDD 0.2EVDD +110 15Note1 V V C year Note2 5 Notes: 1. Under the condition of CWRT1 2. Under the condition of CWRT2 Remark: The initial write when the product is shipped, any erase write set of operations, or any programming operation is counted as one rewrite. Example: P: Program(write) E: Erase Product is shipped P E P E P : Rewrite count: 3 Product is shipped E P E P E P : Rewrite count: 3 (b) Serial Writing Operation Characteristics Specification is identical to that from (A)-Grade except Ta=-40 to +110C. 40 Data Sheet U18564EE1V2DS00 V850ES/FE3 4. Electrical Specifications of (A2)-Grade This product has to be used only under the conditions of VDD=EVDD. Operation is not ensured at the time of using this product except this condition. 4.1 Absolute Maximum Ratings Specification is identical to that from (A1)-Grade except * * Operating ambient temperature Ta = -40 to +125C Note2: AVREF0 IOH/IOL current is including ADC0 max. current IAREF0. 4.2 Capacities Specification is identical to that from (A)-Grade except Ta=-40 to +125C. Data Sheet U18564EE1V2DS00 41 V850ES/FE3 4.3 Operating condition (Ta = -40 to +125C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Internal System clock frequency (fVBCLK) Supply voltage 4.0VVDD5.5VNote2 3.5VVDD<4.0VNote2 4.0fxx24MHz Note1 12.5kHzfXT27.5kHz Note3(RC) fRL (240kHz Internal-OSC) Operating Condition Operation of functions is usable under following conditions: * Peripheral clock frequency * fXP1 fXX * fXP2 fXX * AC characteristics: * Refer to chapter '4.7 AC Characteristics' for details. Operation of functions is usable under following conditions: * Peripheral clock frequency * fXP1 20MHz * fXP2 20MHz * AC characteristics: * Refer to chapter '4.7 AC Characteristics' for details. Only operation of the following functions is assured: * CPU * Flash (include programming) * RAM * IO Buffer * Port 3.3VVDD<3.5VNote2 * WT * WDT * INT * CLM * POC * LVI * A/D Converter * Refer to chapter '4.8 A/D Converter' for 3.3VAVREF05.5V details. * stop ADC for AVREF0 < 4.0V (ADA0CE bit =0) 3.3VVDD<5.5VNote2 - Note2 - 3.3VVDD<5.5V Notes: 1. For using SSCG please refer to '4.5.5 SSCG Characteristics' for details 2. VDD = EVDD 3. RC Oscillation frequency is min. 25kHz max. 55kHz. This clock is divided by 2 internally. 4.4 Voltage Regulator Characteristics Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 4.5 Clock Generator Circuit 4.5.1 Main System Clock Oscillation Circuit Characteristics Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 42 Data Sheet U18564EE1V2DS00 V850ES/FE3 4.5.2 Sub System Clock Oscillation Circuit Characteristics Specification is identical to that from (A1)-Grade except Ta=-40 to +125C. 4.5.3 Internal-OSC Characteristics Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 4.5.4 PLL Characteristics (Ta = -40 to +125C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter Input frequency Output frequency Lock time Output period jitter Note2 Symbol fx fPLLI Conditions fxx tPLL 256KB product After VDD reaches voltage range min. 3.3V tpj Peak to peak Note MIN. 4 3 12 TYP. MAX. Unit 16 MHz 6 MHz 24 MHz 800 s 2.0 ns Notes: 1. The input of the PLL (fPLLI) can be set to fX, fX/2, or fX/4. The divider is set through an option byte in the code flash memory. 2. Not tested in production. 4.5.5 SSCG Characteristics (Ta = -40 to +125C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter Input frequency Output frequency Lock time Remark: Symbol fx fxx tSSCG Conditions 256KB product After VDD reaches voltage range min. 3.3V MIN. 4 12 TYP. MAX. Unit 16 MHz 24 MHz 1000 s The SSCG MAX output frequency indicates the case without modulation. If modulation is enabled the average SSCG frequency has to be set lower. The maximum achievable average operating frequency with modulation is as follows: Maximum average operating freSSCG input clock divider selector Percent modulation Unit quency SFC1[6:4] TYP MAX 256KB product 000B 0.5% 2.0% 23.5 001B 1.0% 2.5% 23.4 010B 2.0% 4.0% 23.0 MHz 011B 3.0% 6.0% 22.6 100B 4.0% 8.0% 22.1 101B 5.0% 10.0% 21.6 Data Sheet U18564EE1V2DS00 43 V850ES/FE3 4.6 DC Characteristics 4.6.1 Input/Output Level Specification is identical to that from (A1)-Grade except * * Ta = -40 to +125C. Note 2:Total IOH/IOL max is 20mA/-20mA for the power supply lines EVDD. Total IOH/IOL max is 3mA/-3mA for the power supply line AVREF0. AVREF0 IOH/IOL current is excluding ADC0 current IAREF0. If ADC0 is not used total IOH/IOL max is 10mA/-10mA for the power supply line AVREF0. 4.6.2 PIN leakage current (Ta = -40 to +125C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter High level input leakage current Low level input leakage current High level output leakage current Low level output leakage current Symbol Conditions ILIH1 VI=VDD ILIL1 VI=0V ILOH1 VO=VDD ILOL1 VO=0V MIN. Analog pins Other pins Note1 Analog pins Other pins Note1 Analog pins Other pins Analog pins Other pins Notes: 1. The input leakage current of FLMD0 is as follows: High level input leakage current: 5.0uA Low level input leakage current: -5.0uA 44 Data Sheet U18564EE1V2DS00 TYP. MAX. 0.5 1.0 -0.5 -1.0 0.5 1.0 -0.5 -1.0 Unit uA V850ES/FE3 4.6.3 Power supply current (A2-grade) 4.6.3.1 FE3 128KB PD70F3370A, FE3 256KB PD70F3371 (a) Absolute values (Ta = -40 to +125C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0VNote1) Mode Symbol Condition PLL: ON 12MHzfxx24MHz All peripherals running Operating mode Peripheral: fxx PRSI option: 0 IDD1 Note2,8 All peripherals stopped All peripherals running HALT mode Peripheral: fxx PRSI option: 0 Peripheral: fxx PRSI option: 0 IDD2 Note8 All peripherals stopped Peripheral: fxx PRSI option: 0 Peripheral (TAA, UARTD) running IDLE1 mode IDD3 All peripherals stopped PLL: OFF 4MHzfxx16MHz TYP. MAX. Unit fxx=20MHz fx=5MHz fxx=8MHz 8MHz InternalOSC Note3 fxx=16MHz fx=16MHz PLL: ON 12MHzfxx24MHz fxx=20MHz fx=5MHz PLL: OFF 4MHzfxx16MHz fxx=8MHz 8MHz InternalOSC Note3 fxx=16MHz fx=16MHz PLL: ON 12MHzfxx24MHz fxx=20MHz fx=5MHz PLL: OFF 4MHzfxx16MHz fxx=8MHz 8MHz InternalOSC Note3 fxx=16MHz fx=16MHz PLL: ON 12MHzfxx24MHz fxx=20MHz fx=5MHz PLL: OFF 4MHzfxx16MHz fxx=8MHz 8MHz InternalOSC Note3 fxx=16MHz fx=16MHz PLL: OFF 4MHzfxx16MHz Note7 mA 13 20 mA 21 30 mA 22 mA 12 mA 19 mA 16 23 mA 8 12 mA 13 20 mA 12 mA 5 mA 9 mA 1.4 2.8 mA fxx=12MHz fx=12MHz 2.0 3.7 mA fxx=16MHz fx=16MHz 2.4 4.2 mA 1.5 2.9 mA fxx=16MHz fx=16MHz fxx=8MHz, 8MHz Internal-OSCNote3 Data Sheet U18564EE1V2DS00 37 fxx=5MHz fx=5MHz fxx=8MHz, 8MHz Internal-OSCNote3 fxx=5MHz fx=5MHz PLL: OFF fxx=12MHz 4MHzfxx16MHz fx=12MHz Note7 27 1.2 mA 1.4 mA 1.6 mA 1.1 mA 45 V850ES/FE3 Mode IDLE2 mode Symbol Condition TYP. MAX. Unit fxx=5MHz fx=5MHz 0.4 1.1 mA fxx=12MHz fx=12MHz 0.7 1.5 mA fxx=16MHz fx=16MHz 0.8 1.7 mA 0.2 1.0 mA 80 850 A 240 kHz Internal-OSC (SubOSC stopped) 220 1450 A RC resonator (fxt=20kHz) Note6 40 670 A 240kHz Internal-OSC (SubOSC stopped) 25 630 A 7.5 15.5 10.5 18.5 530 545 535 550 A A A A PLL: OFF 4MHzfxx16MHz IDD4 Note7 fxx=8MHz, 8MHz Internal-OSC Note3 SUB operating modeNote5 SubIDLE mode Note3,5 STOP mode Note3,4 46 RC resonator (fxt=20kHz) IDD5 IDD6 POC stop IDD7 POC work Note6 240kHz Internal-OSC stop 240kHz Internal-OSC working 240kHz Internal-OSC stop 240kHz Internal-OSC working Data Sheet U18564EE1V2DS00 V850ES/FE3 (b) Calculation formulas (Ta = -40 to +125C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0VNote1) Mode Symbol Condition PLL: ON 12MHzfxx24MHz Operating mode IDD1 Note2,8 Peripheral: fxx PLL: OFF PRSI option: 0 All peripherals 4MHzfxx16MHz running PLL: ON Peripheral: fxx/2 PRSI option: 1 12MHzfxx24MHz PLL: ON Peripheral: ffxx- 12MHzfxx24MHz PLL: OFF All peripherals PRSI option: 0 4MHzfxx16MHz stopped Peripheral: fxx/2 PLL: ON PRSI option: 1 12MHzfxx24MHz PLL: ON Peripheral: ffxx- 16MHzfxx24MHz HALT mode IDD2 Note8 IDLE1 mode IDD3 IDLE2 mode IDD4 PLL: OFF All peripherals PRSI option: 0 4MHzfxx16MHz running PLL: ON Peripheral: fxx/2 PRSI option: 1 16MHzfxx24MHz PLL: ON Peripheral: fxx 16MHzfxx24MHz PLL: OFF All peripherals PRSI option: 0 4MHzfxx16MHz stopped TYP. Note9 MAX. Note9 Unit 0.98fxx+7.1 1.18fxx+13.6 mA 0.98fxx+5.5 1.18fxx+10.6 mA 0.90fxx+6.0 1.08fxx+12.2 mA 0.81fxx+6.2 mA 0.83fxx+5.7 mA 0.79fxx+6.2 mA 0.67fxx+3.0 0.90*fxx+5.4 mA 0.70fxx+1.9 1.00*fxx+4.0 mA 0.55fxx+2.8 0.64*fxx+7.0 mA 0.46fxx+2.8 mA 0.44fxx+1.6 mA Peripheral: fxx/2 PLL: ON 0.46fxx+1.8 PRSI option: 1 16MHzfxx24MHz Peripheral (TAA, UARTD) runPLL: OFF 0.092fxx+0.90 0.128fxx+ 2.12 ning 4MHzfxx16MHz 0.035fxx+1.01 All peripherals stopped Note7 PLL: OFF 0.037fxx+0.21 0.049fxx+ 0.88 4MHz fxx16MHz Note7 mA mA mA mA Notes: 1. VDD and EVDD total current. (Ports are stopped). AVREF0 current, port buffer current (including a current flowing in the on-chip pull-up/pulldown resistor) are not included. 2. The code flash and the data flash are in read mode. When the device is in programming mode (Self-programming mode or data flash programming mode), the current value (MAX. value) adds by the following value: 3. 4. 5. 6. 7. 8. 9. * Self-programming mode: + In case of PLL OFF: 7-(0.33*fxx+0.1) [mA] + In case of PLL ON: 7-(0.18*fxx+3.0) [mA] * Data flash programming mode: + 7-(0.18*fxx/4+3.0) [mA] Main OSC is stopped. Do not use SubOSC. POC is working. 240kHz Internal-OSC is working. 8MHz Internal-OSC is stopped. RC Oscillation frequency is typ.40kHz. This clock is divided by 2 internally. 8MHz Internal-OSC is stopped When the SSCG is running, the current value adds typ +2.5mA, max +4mA. The formulas are for reference only. Not all possible values for fxx are tested in the outgoing device inspection. Data Sheet U18564EE1V2DS00 47 V850ES/FE3 4.7 AC Characteristics AC test Input measurement points ( VDD, AVREF0, EVDD) VDD VIH(min) VIH(min) measure point VIL(max) VSS VIL(max) AC test output measurement points VOH(min) VOH(min) measure point VOL(max) VOL(max) Load conditions DUT ( Device under test ) Caution: CL = 50 pF If the load capacitance exceeds 50pF due to the circuit configuration, reduce the load capacitance of the device to 50pF or less by inserting a buffer or by some other means. 4.7.1 CLKOUT Output Timing Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 4.7.2 RESET, Interrupt, ADTRG Timing Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 4.7.3 Key Return Timing Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 4.7.4 Timer Timing Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 4.7.5 CSI Timing Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 4.7.6 UART Timing Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 4.7.7 IIC Timing Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 4.7.8 CAN Timing Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 48 Data Sheet U18564EE1V2DS00 V850ES/FE3 4.8 A/D Converter (Ta = -40 to +125C, C=4.7uF, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 4.0 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter Resolution Overall errorNote1 Conversion time Stabilization time Recovery time for power down mode Zero-scale errorNote1 Note1 Full-scale error Integral non-liniearity errorNote2 errorNote2 Differential non-liniearity Analog input voltage Analog input equivalent circuit capacitance Note3,4 Analog input equivalent circuit resistance Note3 AVREF0 current Conversion rusult when using Diagnostic function Symbol Conditions MIN. 4.0VAVREF0<5.5V tCONV tSTA After ADA0PS bit = 0 -> 1 tDPU TYP. 0.15 3.10 2 MAX. 10 0.35 16 1 Unit bit %FSR s s s ZSE 0.35 %FSR FSE 0.35 %FSR INL 2.5 LSB 1.5 AVREF0 LSB V CINA 6.19 pF RINA 2.55 k 7 10 3FF 003 mA uA HEX HEX DNL VIAN IAREF0 AVSS A/D operating A/D operation stop AVREF0 conversion AVSS conversion 4 1 3FC 000 Notes: 1. Overall error excluding quantization error (0.05%FSE). It is indicated as a ratio to the fullscale value. 2. Excluding quantization error (1/2 LSB) 3. Not tested in production. 4. Does not include input/output capacitance CIO 4.9 POC Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 4.10 LVI Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 4.11 RAM Retention Flag Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 4.12 Data Retention Characteristics Specification is identical to that from (A)-Grade except Ta=-40 to +125C. Data Sheet U18564EE1V2DS00 49 V850ES/FE3 4.13 Flash Memory Programming Characteristics (a) Basic Characteristics (C=4.7uF, VDD = EVDD, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V) Parameter Operation frequency Supply voltage Number of rewrites High level input voltage Low level input voltage Programming temperature Symbol fCPU VDD Conditions Code Flash CWRT1 Data Flash CWRT2 VIH VIL tPRG FLMD0 FLMD0 MIN. 4 3.3 MAX. 32 5.5 1000 10000 0.8EVDD EVSS -40 Code Flash Data retention TYP. Data Flash Unit MHz V count EVDD 0.2EVDD +125 15Not1 V V C year 5Note2 Notes: 1. Under the condition of CWRT1 2. Under the condition of CWRT2 Remark: The initial write when the product is shipped, any erase write set of operations, or any programming operation is counted as one rewrite. Example: P: Program(write) E: Erase Product is shipped P E P E P : Rewrite count: 3 Product is shipped E P E P E P : Rewrite count: 3 (b) Serial Writing Operation Characteristics Specification is identical to that from (A)-Grade except Ta=-40 to +125C. 50 Data Sheet U18564EE1V2DS00 V850ES/FE3 5. Package 5.1 Package Dimension 64-PIN PLASTIC LQFP(FINE PITCH)(10x10) ITEM DIMENSIONS + - + - NOTE + - P64GB-50-GAH Data Sheet U18564EE1V2DS00 51 V850ES/FE3 5.2 Product Marking 5.2.1 Marking of pin 1 at a QFP (Quad Flat Package) Example 1: The index mark for pin 1 is the beveled edge of the package Example 2: The index mark for pin 1 is a round notch at one of the 4 edges. In this case, the shape of all edges is identical (usually beveled). Example 3: For production reasons, two or more similar notches may be located at the top of the package. In such a case the index marker for pin 1 is a round notch with an additional mark in it. Note: RoHS compliant devices have an additional dot at the top side. Do not mix it up with the marking for pin 1. For details see 5.2.2 "Identification of Lead-Free Products" on page 53. 52 Data Sheet U18564EE1V2DS00 V850ES/FE3 5.2.2 Identification of Lead-Free Products Lead-Free products are marked with a dot "*". The marking methods are the paint or the laser (It doesn't sink in). The shape of lead-free marks is a circle. Example: Data Sheet U18564EE1V2DS00 53 V850ES/FE3 6. Change History The following revision list shows all major changes of the different datasheet versions. Version Chapter V1.0 V1.1 Comment Initial release 2.13 3.13 2.8 4.8 Removed 'Target Specification' for (A)- and (A1)-Grade Devices in the Flash Programming specifications. Changed specification of 'Number of rewrites' from MAX. to MIN. Remove Caution (Described in User's Manual) Changed document status from 'Preliminary Datasheet' to 'Datasheet'. V1.2 54 4.12 Removed 'Target Specification' for (A2)-Grade Devices in the Flash Programming specifications. Data Sheet U18564EE1V2DS00 Facsimile Message From: Name Company Tel. Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. Despite all the care and precautions we've taken, you may encounter problems in the documentation. Please complete this form whenever you'd like to report errors or suggest improvements to us. FAX Address Thank you for your kind support. North America Hong Kong, Philippines, Oceania NEC Electronics America Inc. NEC Electronics Hong Kong Ltd. Corporate Communications Dept. Fax: +852-2886-9022/9044 Fax: 1-800-729-9288 1-408-588-6130 Korea Europe NEC Electronics Hong Kong Ltd. NEC Electronics (Europe) GmbH Seoul Branch Market Communication Dept. Fax: 02-528-4411 Fax: +49(0)-211-6503-1344 Asian Nations except Philippines NEC Electronics Singapore Pte. Ltd. Fax: +65-6250-3583 Japan NEC Semiconductor Technical Hotline Fax: +81- 44-435-9608 Taiwan NEC Electronics Taiwan Ltd. Fax: 02-2719-5951 I would like to report the following error/make the following suggestion: Document title: Document number: Page number: If possible, please fax the referenced page or drawing. Document Rating Excellent Good Acceptable Poor Clarity Technical Accuracy Organization CS 99.1 [MEMO]