Data Sheet
V850ES/FE3
32-bit Single-Chip Microcontroller
Hardware
µPD70F3370A(A) µPD70F3371(A)
µPD70F3370A(A1) µPD70F3371(A1)
µPD70F3370A(A2) µPD70F3371(A2)
Document No. U18564EE1V2DS00
Date Published March 2008
© NEC Electronics 2008
Printed in Germany
2Data Sheet U18564EE1V2DS00
V850ES/FE3
Notes for CMOS Devices
1. Precaution against ESD for semiconductors
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2. Handling of unused input pins for CMOS
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to
the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3. Status before initialization of MOS devices
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not
guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset
signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
3
Data Sheet U18564EE1V2DS00
V850ES/FE3
Legal Notes
The information in this document is current as of January 2007. The information is subject to change
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must check the quality grade of each NEC Electronics product before using it in a particular
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The quality grade of NEC Electronics products is “Standard” unless otherwise expressly specified in
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Electronics (as defined above).
3. SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several coun-
tries including the United States and Japan. This product uses SuperFlash® technology
licensed from Silicon Storage Technology, Inc.
4Data Sheet U18564EE1V2DS00
V850ES/FE3
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
5
Data Sheet U18564EE1V2DS00
V850ES/FE3
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6Data Sheet U18564EE1V2DS00
V850ES/FE3
Table of Contents
1. Pin Group Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 Device package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Pin Groups 1x: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Pin Groups 2x: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Pin Groups 3x: Pins supplied by BVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.5 Pin Groups 4: Pins supplied by AVREF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.6 Pin Groups 5: Pins supplied by AVREF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.7 Pin Groups 6: Pins supplied by EVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.8 Pin Groups 7: Pins supplied by VRO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2. Electrical Specifications of (A)-Grade. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5 Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.1 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.2 Sub System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.3 Internal-OSC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.5.4 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5.5 SSCG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6.2 PIN leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.3 Power supply current (A-grade). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.6.3.1 FE3 128KB mPD70F3370A, FE3 256KB mPD70F3371 . . . . . . . . . . . . . . . . . . . . . . 18
2.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.7.1 CLKOUT Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.7.2 RESET, Interrupt, ADTRG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.7.3 Key Return Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.7.4 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.7.5 CSI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.7.6 UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.7.7 IIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.7.8 CAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
2.8 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.9 POC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.10 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.11 RAM Retention Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.12 Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.13 Flash Memory Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3. Electrical Specifications of (A1)-Grade. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.2 Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.3 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5 Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5.1 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32
3.5.2 Sub System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.3 Internal-OSC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.4 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.5.5 SSCG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7
Data Sheet U18564EE1V2DS00
V850ES/FE3
Table of Contents
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.6.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.6.2 PIN leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.6.3 Power supply current (A1-grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.6.3.1 FE3 128KB mPD70F3370A, FE3 256KB mPD70F3371 . . . . . . . . . . . . . . . . . . . . . . 36
3.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.1 CLKOUT Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.2 RESET, Interrupt, ADTRG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.3 Key Return Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.4 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.7.5 CSI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.6 UART Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.7 IIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.7.8 CAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
3.8 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.9 POC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.10 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11 RAM Retention Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.12 Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.13 Flash Memory Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4. Electrical Specifications of (A2)-Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2 Capacities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.3 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.4 Voltage Regulator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.5 Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
4.5.1 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
4.5.2 Sub System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.5.3 Internal-OSC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.5.4 PLL Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.5.5 SSCG Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.6.1 Input/Output Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.6.2 PIN leakage current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
4.6.3 Power supply current (A2-grade) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.6.3.1 FE3 128KB mPD70F3370A, FE3 256KB mPD70F3371 . . . . . . . . . . . . . . . . . . . . . . 45
4.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7.1 CLKOUT Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7.2 RESET, Interrupt, ADTRG Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7.3 Key Return Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7.4 Timer Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.7.5 CSI Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7.6 UART Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7.7 IIC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
4.7.8 CAN Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
4.8 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
4.9 POC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.10 LVI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.11 RAM Retention Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.12 Data Retention Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.13 Flash Memory Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8Data Sheet U18564EE1V2DS00
V850ES/FE3
Table of Contents
5. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.1 Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5.2 Product Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2.1 Marking of pin 1 at a QFP (Quad Flat Package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2.2 Identification of Lead-Free Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6. Change History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9
Data Sheet U18564EE1V2DS00
V850ES/FE3
1. Pin Group Information
1.1 Device package information
The V850ES/Fx3 device series comprises several members. An overview with the pin and package
information is given in the following table:
This document describes the specification for the V850ES/FE3.
1.2 Pin Groups 1x: Pins supplied by EVDD
1B: (SHMT1)
- P04, P30-31, P34; P40, P91, P913-915 (FE3)
- P04, P30-31, P34; P38-39, P40, P91, P913-915 (FF3)
- P04, P30-31, P34; P36-39, P40, P91, P911, P913-915 (FG3)
- P04, P30-31, P34; P36-39, P40, P63-69, P614-615, P80-81, P91, P911, P913-915 (FJ3)
- P04, P30-31, P34; P36-39, P40, P63-69, P614-615, P80-81, P91, P911, P913-915, P156-157
(FK3)
1D: (SHMT3)
- P00-03, P05-P06, P32-33, P35, P41-42, P50-55, P90, P96-99 (FE3)
- P00-03, P05-P06, P32-33, P35, P41-42, P50-55, P90, P96-99 (FF3)
- P00-03, P05-P06, P10-11, P32-33, P35, P41-42, P50-55, P90, P92-910, P912 (FG3)
- P00-03, P05-P06, P10-11, P32-33, P35, P41-42, P50-55, P60-62, P610-613, P90, P92-910,
P912 (FJ3)
- P00-03, P05-P06, P10-11, P32-33, P35, P41-42, P50-55, P60-62, P610-613, P90, P92-910,
P912, P150-155 (FK3)
1.3 Pin Groups 2x: Pins supplied by EVDD
2A: (CMOS)
- PCM0-1 (FE3)
- PCM0-3, PCS0-1, PCT0-1, PCT4, PCT6 (FF3)
2D: (SHMT3)
- PDL0-7 (FE3)
- PDL0-11 (FF3)
Series Member # Pins Device package information
μPD70F3370A
μPD70F3371 64 FE3
μPD70F3372
μPD70F3373 80 FF3
μPD70F3374
μPD70F3375
μPD70F3376A
μPD70F3377A
100 FG3
μPD70F3378
μPD70F3379
μPD70F3380
μPD70F3381
μPD70F3382
144 FJ3
μPD70F3383
μPD70F3384
μPD70F3385
176 FK3
10 Data Sheet U18564EE1V2DS00
V850ES/FE3
1.4 Pin Groups 3x: Pins supplied by BVDD
3A: (CMOS)
- PCM0-3, PCS0-1, PCT0-1, PCT4, PCT6 (FG3)
- PCD0-3, PCM0-5, PCS0-7, PCT0-7 (FJ3 + FK3)
3D: (SHMT3)
- PDL0-13 (FG3)
- PDL0-15 (FJ3 + FK3)
1.5 Pin Groups 4: Pins supplied by AVREF0
4: (CMOS)
- P70-79 (FE3)
-P70-711 (FF3)
- P70-715 (FG3)
- P70-715, P120-127 (FJ3 + FK3)
1.6 Pin Groups 5: Pins supplied by AVREF1
- P20-P215 (FK3) (CMOS)
1.7 Pin Groups 6: Pins supplied by EVDD
- RESET (SHMT2)
-IC, FLMD0
1.8 Pin Groups 7: Pins supplied by VRO
- X1, X2, XT1, XT2
11
Data Sheet U18564EE1V2DS00
V850ES/FE3
2. Electrical Specifications of (A)-Grade
This product has to be used only under the conditions of VDD=EVDD. Operation is not ensured at the
time of using this product except this condition.
2.1 Absolute Maximum Ratings
Absolute Maximum Ratings (Ta=25°C)
Remarks: 1. The characteristics of the dual-function pins are the same as those of the port pins
unless otherwise specified
Notes: 1. Be sure not to exceed the absolute maximum ratings (Max. value) of each supply voltage.
2. Excluding ADC IAREF0 current.
2.2 Capacities
(Ta = 25°C, VDD = EVDD = AVREF0 = VSS = EVSS = AVSS = 0V)
Parameter Symbol Conditions Rating Unit
Supply voltage
VDD VDD=EVDD, -0.5 to +6.5 V
EVDD VDD=EVDD -0.5 to +6.5 V
AVREF0 -0.5 to +6.5 V
VSS VSS=EVSS=AVSS -0.5 to +0.5 V
EVSS VSS=EVSS=AVSS -0.5 to +0.5 V
AVSS VSS=EVSS=AVSS -0.5 to +0.5 V
Input voltage
VI1 Pin Group 1x, 2x, 6 -0.5 to EVDD+0.5
Note1 V
VI3 Pin Group 7 -0.5 to VRO+0.5
Note1 V
Analog input voltage VIAN Pin Group 4 -0.5 to AVREF0+0.5
Note1 V
High level output cur-
rent IOH
Pin Group 1x, 2x 1 pin -4 mA
Tot al - 5 0 m A
Pin Group 4 1 pin -4 mA
Tot al -20Note2 mA
Low level output current IOL
Pin Group 1x, 2x 1 pin 4 mA
Tot al 5 0 mA
Pin Group 4 1 pin 4 mA
Tot al 20Note2 mA
Operating ambient
temperature Ta Normal operating mode -40 to +85 °C
Flash programming mode -40 to +85
Storage temperature Tstg -40 to +125 °C
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input/output capacitance CIO f=1MHz, Not measured pins is 0V. 10 pF
12 Data Sheet U18564EE1V2DS00
V850ES/FE3
2.3 Operating condition
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. For using SSCG please refer to ’2.5.5 SSCG Characteristics’ for details
2. VDD = EVDD
3. RC Oscillation frequency is min. 25kHz max. 55kHz. This clock is divided by 2 internally.
Internal System clock frequency (fVBCLK)Supply voltage Operating Condition
4.0fxx32MHz
Note1
4.0VVDD5.5VNote2
Operation of functions is usable under following
conditions:
Peripheral clock frequency
fXP1 32MHz
fXP2 32MHz
AC characteristics:
Refer to chapter ’2.7 AC Characteris-
tics’ for details.
3.5VVDD<4.0VNote2
Operation of functions is usable under following
conditions:
Peripheral clock frequency
fXP1 20MHz
fXP2 20MHz
AC characteristics:
Refer to chapter ’2.7 AC Characteris-
tics’ for details.
3.3VVDD<3.5VNote2
Only operation of the following functions is
assured:
CPU
Flash (include programming)
RAM
IO Buffer
Port
WT
WDT
INT
CLM
POC
LVI
3.3VAVREF05.5V
A/D Converter
Refer to chapter ’2.8 A/D Converter’ for
details.
stop ADC for AVREF0 < 4.0V
(ADA0CE bit =0)
32kHzfXT35kHz (Crystal)
3.3VVDD<5.5VNote2 -
12.5kHzfXT27.5kHz Note3(RC)
fRL (240kHz Internal-OSC) 3.3VVDD<5.5VNote2 -
13
Data Sheet U18564EE1V2DS00
V850ES/FE3
2.4 Voltage Regulator Characteristics
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD, VSS = EVSS = AVSS = 0V))
Note: In case of non-POC device, be sure to start VDD in the state of RESET=VSS=0V.
For POC devices there is no need to control external RESET terminal. For decives with POC
function the internal RESET signal will automatically controlled until VRO is stable.
2.5 Clock Generator Circuit
2.5.1 Main System Clock Oscillation Circuit Characteristics
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. Indicates only oscillation circuit characteristics. Refer to ’2.7 AC Characteristics’ for CPU
operation clock.
2. Time required to stabilize oscillation after VDD reaches oscillator voltage range MIN. 3.3V
3. Depends on the setting of the oscillation stabilization time select register (OSTS)
4. Minimum time required to stabilize flash. Time has to be secured by setting the oscillation
stabilization time select register (OSTS)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage VDD 3.5 5.5 V
Limited function see ’2.3 Operating condition’ 3.3 V
Output voltage VRO 2.5 V
Output voltage
stabilization time tREGNote After VDD reaches voltage range min. 3.3V
To connect C=4.7uF on REGC terminal 1ms
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Crystal /
Ceramic resona-
tor
Refer to figure below
Oscillator fre-
quency (fx)Note1 416MHz
Oscillation stabili-
zation time Note2
After STOP mode 64Note4 Note3 μs
After IDLE2 mode 54Note4 Note3 μs
VDD
tREG
VRO
RESET
X1 X2
14 Data Sheet U18564EE1V2DS00
V850ES/FE3
2.5.2 Sub System Clock Oscillation Circuit Characteristics
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristic" for cpu opera-
tion clock.
2. Time required to stabilize oscillation after VDD reaches oscillator voltage range min. 3.3V
3. In order to avoid the influence of wiring capacity, shorten wiring as much as possible.
4. RC Oscillation frequency is typ. 40kHz. This clock is divided by 2 internally. In case of RC
Oscillator, internal system clock frequency (fxt) is min. 12.5kHz, typ. 20kHz, max. 27.5kHz.
2.5.3 Internal-OSC Characteristics
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Crystal
resonator Refer to Figure 1
Oscillator fre-
quency (fxt)Note1 32 32.768 35 kHz
Oscillation stabiliza-
tion time Note2 10 s
RC
resonator Refer to Figure 2
Oscillator
frequencyNote1,4
R=390KΩ ±5% Note3,
C=47pF±10% Note3 25 40 55 kHz
Oscillation stabiliza-
tion time Note2 100 μs
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Output
frequency
fRL 240kHz Internal-OSC 204 240 276 kHz
fRH 8MHz Internal-OSC 7.2 8.0 8.8 MHz
Oscillation
stabilization
time
240kHz Internal-OSC 10 36 µs
8MHz Internal-OSC 51 92 256 µs
XT1 XT2 XT1 XT2
R
15
Data Sheet U18564EE1V2DS00
V850ES/FE3
2.5.4 PLL Characteristics
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. The input of the PLL (fPLLI) can be set to fX, fX/2, or fX/4. The divider is set through an option
byte in the code flash memory.
2. Not tested in production.
2.5.5 SSCG Characteristics
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Remark: The SSCG MAX output frequency indicates the case without modulation. If modulation is
enabled the average SSCG frequency has to be set lower. The maximum achievable aver-
age operating frequency with modulation is as follows:
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input frequency fx 4 16 MHz
fPLLI Note1 36MHz
Output frequency fxx 256KB product 12 32 MHz
Lock time tPLL After VDD reaches voltage range min. 3.3V 800 μs
Output period jitter
Note2 tpj Peak to peak 2.0 ns
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input frequency fx 4 16 MHz
Output frequency fXX 256KB product 12 32 MHz
Lock time tSSCG After VDD reaches voltage range min. 3.3V 1000 μs
SSCG input clock divider selector
SFC1[6:4]
Percent modulation Maximum average operating fre-
quency Unit
TYP MAX 256KB product
000B ± 0.5% ± 2.0% 31.4
MHz
001B ± 1.0% ± 2.5% 31.2
010B ± 2.0% ± 4.0% 30.7
011B ± 3.0% ± 6.0% 30.1
100B ± 4.0% ± 8.0% 29.4
101B ± 5.0% ± 10.0% 28.8
16 Data Sheet U18564EE1V2DS00
V850ES/FE3
2.6 DC Characteristics
2.6.1 Input/Output Level
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Remark: The characteristics of the dual-function pins are the same as those of the port pins unless
otherwise specified.
Notes: 1. DRST terminal only. (Control register is OCDM)
2. Total IOH/IOL max is 20mA/-20mA each power supply line (EVDD and AVREF0).
AVREF0 IOH/IOL current is excluding ADC0 current IAREF0.
3. Typical value. Not tested and guaranteed
Parameter Sym-
bol Conditions MIN. TYP. MAX. Uni
t
High level
input voltage
VIH1 Pin Group 1B 0.7EVDD EVDD V
VIH2 Pin Group 1D 0.8EVDD EVDD V
Pin Group 2D 0.8EVDD EVDD V
VIH3 Pin Group 2A 0.7EVDD EVDD V
VIH4 Pin Group 4 0.7AVREF0 AVREF0 V
VIH5 Pin Group 6 0.8EVDD EVDD V
Low level
input voltage
VIL1 Pin Group 1B EVSS 0.3EVDD V
VIL2 Pin Group 1D EVSS 0.4EVDD V
Pin Group 2D EVSS 0.4EVDD V
VIL3 Pin Group 2A EVSS 0.3EVDD V
VIL4 Pin Group 4 AVSS 0.3AVREF0 V
VIL5 Pin Group 6 EVSS 0.2EVDD V
Input hysteresis
VHYS1 Pin Group 1B Center point at
0.5 x EVDD Note3 0.267 x EVDD - 0.51V V
VHYS2
Pin Group 1D Center point at
0.6 x EVDD Note3 0.192 x EVDD - 0.31V V
Pin Group 2D Center point at
0.6 x EVDD Note3 0.192 x EVDD - 0.31V V
VHYS5 Pin Group 6 Center point at
0.5 x EVDD Note3 0.535 x EVDD - 0.9V V
High level
output voltage
Note2
VOH1 Pin Group
1x, 2x
IOH=-1.0mA EVDD-1.0 EVDD V
IOH=-100uA EVDD-0.5 EVDD V
VOH3 Pin Group 4 IOH=-1.0mA AVREF0-1.0 AVREF0 V
IOH=-100uA AVREF0-0.5 AVREF0 V
Low level output
voltageNote2
VOL1
Pin Group 1x,
2x IOL=1.0mA 00.4V
P914, 915 IOL=3.0mA
VOL3 Pin Group 4 IOL=1.0mA 0 0.4 V
Software pull-up
resistor R1 VI=0V 10 30 100 kΩ
Software Note1
pull-down resistor R2 VI=VDD 10 30 100 kΩ
17
Data Sheet U18564EE1V2DS00
V850ES/FE3
2.6.2 PIN leakage current
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. The input leakage current of FLMD0 is as follows:
High level input leakage current : 2.0uA
Low level input leakage current : -2.0uA
Parameter Symbol Conditions MIN. TYP. MAX. Unit
High level input
leakage current ILIH1 VI=VDD Analog pins 0.2
uA
Other pins Note1 0.5
Low level input
leakage current ILIL1 VI=0V Analog pins -0.2
Other pins Note1 -0.5
High level output
leakage current ILOH1 VO=VDD Analog pins 0.2
Other pins 0.5
Low level output
leakage current ILOL1 VO=0V Analog pins -0.2
Other pins -0.5
18 Data Sheet U18564EE1V2DS00
V850ES/FE3
2.6.3 Power supply current (A-grade)
2.6.3.1 FE3 128KB μPD70F3370A, FE3 256KB μPD70F3371
(a) Absolute values
(Ta = -40 to +85°C, C=4.7uF,
VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0VNote1)
Mode Symbol Condition TYP. MAX. Unit
Operating
mode
Note2,8
IDD1
All peripherals
running
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx32MHz
fxx=20MHz
fx=5MHz 27 37 mA
fxx=32MHz
fx=16MHz 39 51 mA
PLL: OFF
4MHzfxx16MHz
fxx=8MHz
8MHz Internal-
OSC Note3
13 20 mA
fxx=16MHz
fx=16MHz 21 30 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
12MHzfxx32MHz
fxx=32MHz
fx=16MHz 35 47 mA
All peripherals
stopped
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx32MHz
fxx=20MHz
fx=5MHz 22 mA
fxx=32MHz
fx=16MHz 32 mA
PLL: OFF
4MHzfxx16MHz
fxx=8MHz
8MHz Internal-
OSC Note3
12 mA
fxx=16MHz
fx=16MHz 19 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
12MHzfxx32MHz
fxx=32MHz
fx=16MHz 31 mA
HALT
mode
Note8
IDD2
All peripherals
running
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx32MHz
fxx=20MHz
fx=5MHz 16 23 mA
fxx=32MHz
fx=16MHz 24 34 mA
PLL: OFF
4MHzfxx16MHz
fxx=8MHz
8MHz Internal-
OSC Note3
812mA
fxx=16MHz
fx=16MHz 13 20 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
12MHzfxx32MHz
fxx=32MHz
fx=16MHz 20 27 mA
All peripherals
stopped
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx32MHz
fxx=20MHz
fx=5MHz 12 mA
fxx=32MHz
fx=16MHz 18 mA
PLL: OFF
4MHzfxx16MHz
fxx=8MHz
8MHz Internal-
OSC Note3
5mA
fxx=16MHz
fx=16MHz 9mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
12MHzfxx32MHz
fxx=32MHz
fx=16MHz 17 mA
19
Data Sheet U18564EE1V2DS00
V850ES/FE3
IDLE1
mode IDD3
Peripheral (TAA, UARTD) run-
ning
PLL: OFF
4MHzfxx16MHz
Note7
fxx=5MHz
fx=5MHz 1.4 2.2 mA
fxx=12MHz
fx=12MHz 2.0 3.1 mA
fxx=16MHz
fx=16MHz 2.4 3.6 mA
fxx=8MHz, 8MHz Internal-OSCNote3 1.5 2.3 mA
All peripherals stopped
PLL: OFF
4MHzfxx16MHz
Note7
fxx=5MHz
fx=5MHz 1.2 mA
fxx=12MHz
fx=12MHz 1.4 mA
fxx=16MHz
fx=16MHz 1.6 mA
fxx=8MHz, 8MHz Internal-OSCNote3 1.1 mA
IDLE2
mode IDD4
PLL: OFF
4MHzfxx16MHz
Note7
fxx=5MHz
fx=5MHz 0.4 0.7 mA
fxx=12MHz
fx=12MHz 0.7 1.0 mA
fxx=16MHz
fx=16MHz 0.8 1.2 mA
fxx=8MHz, 8MHz Internal-OSC Note3 0.2 0.5 mA
SUB
operating
modeNote5
IDD5
Crystal resonator (fxt = 32,768kHz) 80 400 μA
RC resonator (fxt=20kHz) Note6 80 400 µA
240 kHz Internal-OSC (SubOSC stopped) 220 1000 µA
SubIDLE
mode
Note3,5
IDD6
Crystal resonator (fxt = 32,768kHz) 20 190 μA
RC resonator (fxt=20kHz) Note6 40 220 μA
240kHz Internal-OSC (SubOSC stopped) 25 180 μA
STOP
mode
Note3,4
IDD7
POC stop 240kHz Internal-OSC stop 7.5 80 μA
240kHz Internal-OSC working 15.5 95 μA
POC work 240kHz Internal-OSC stop 10.5 85 μA
240kHz Internal-OSC working 18.5 100 μA
Mode Symbol Condition TYP. MAX. Unit
20 Data Sheet U18564EE1V2DS00
V850ES/FE3
(b) Calculation formulas
(Ta = -40 to +85°C, C=4.7uF,
VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0VNote1))
Notes: 1. VDD and EVDD total current. (Ports are stopped).
AVREF0 current, port buffer current (including a current flowing in the on-chip pull-up/pull-
down resistor) are not included.
2. The code flash and the data flash are in read mode.
When the device is in programming mode (Self-programming mode or data flash program-
ming mode), the current value (MAX. value) adds by the following value:
Self-programming mode:
+ In case of PLL OFF: 7-(0.33*fxx+0.1) [mA]
+ In case of PLL ON: 7-(0.18*fxx+3.0) [mA]
Data flash programming mode:
+ 7-(0.18*fxx/4+3.0) [mA]
3. Main OSC is stopped.
4. Do not use SubOSC.
5. POC is working. 240kHz Internal-OSC is working. 8MHz Internal-OSC is stopped.
6. RC Oscillation frequency is typ.40kHz. This clock is divided by 2 internally.
7. 8MHz Internal-OSC is stopped
8. When the SSCG is running, the current value adds typ +2.5mA, max +4mA.
9. The formulas are for reference only. Not all possible values for fxx are tested in the outgoing
device inspection.
Mode Symbol Condition TYP. Note9 MAX. Note9 Unit
Operating
mode
Note2,8
IDD1
All peripherals
running
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx32MHz 0.98fxx+7.1 1.18fxx+13.6 mA
PLL: OFF
4MHzfxx16MHz 0.98fxx+5.5 1.18fxx+10.6 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
12MHzfxx32MHz 0.90fxx+6.0 1.08fxx+12.2 mA
All peripherals
stopped
Peripheral: ffxx-
PRSI option: 0
PLL: ON
12MHzfxx32MHz 0.81fxx+6.2 mA
PLL: OFF
4MHzfxx16MHz 0.83fxx+5.7 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
12MHzfxx32MHz 0.79fxx+6.2 mA
HALT
mode
Note8
IDD2
All peripherals
running
Peripheral: ffxx-
PRSI option: 0
PLL: ON
16MHzfxx32MHz 0.67fxx+3.0 0.90*fxx+5.4 mA
PLL: OFF
4MHzfxx16MHz 0.70fxx+1.9 1.00*fxx+4.0 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
16MHzfxx32MHz 0.55fxx+2.8 0.64*fxx+7.0 mA
All peripherals
stopped
Peripheral: fxx
PRSI option: 0
PLL: ON
16MHzfxx32MHz 0.46fxx+2.8 mA
PLL: OFF
4MHzfxx16MHz 0.44fxx+1.6 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
16MHzfxx32MHz 0.46fxx+1.8 mA
IDLE1
mode IDD3
Peripheral (TAA, UARTD) run-
ning
PLL: OFF
4MHzfxx16MHz
Note7
0.092fxx+0.90 0.128fxx+ 1.35 mA
All peripherals stopped 0.035fxx+1.01 mA
IDLE2
mode IDD4 PLL: OFF
4MHz fxx16MHz Note7 0.037fxx+0.21 0.049fxx+ 0.43 mA
21
Data Sheet U18564EE1V2DS00
V850ES/FE3
2.7 AC Characteristics
AC test Input measurement points ( VDD, AVREF0, EVDD)
AC test output measurement points
Load conditions
Caution: If the load capacitance exceeds 50pF due to the circuit configuration, reduce the load
capacitance of the device to 50pF or less by inserting a buffer or by some other means.
2.7.1 CLKOUT Output Timing
(Ta = -40 to +85°C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)
CLKOUT output timing
Parameter Symbol Conditions MIN. MAX. Unit
Output cycle tCYK VDD = EVDD = 4.0V ~ 5.5V 31.25ns 80μs
VDD = EVDD = 3.5V ~ 5.5V 50ns
High level width tWKH VDD = EVDD = 4.0V ~ 5.5V tCYK/2-13 ns
VDD = EVDD = 3.5V ~ 5.5V tCYK/2-15
Low level width tWKL VDD = EVDD = 4.0V ~ 5.5V tCYK/2-13 ns
VDD = EVDD = 3.5V ~ 5.5V tCYK/2-15
Rise time tKR VDD = EVDD = 4.0V ~ 5.5V 13 ns
VDD = EVDD = 3.5V ~ 5.5V 15
Fall time tKF VDD = EVDD = 4.0V ~ 5.5V 13 ns
VDD = EVDD = 3.5V ~ 5.5V 15
measure point
VIH(min)
VIL(max)
VIH(min)
VIL(max)
VDD
VSS
measure point
VOH(min)
VOL(max)
VOH(min)
VOL(max)
CL = 50 pF
DUT
( Device under
test )
t
KR t
KF
t
WKH t
WKL
t
CYK
CLKOUT
22 Data Sheet U18564EE1V2DS00
V850ES/FE3
2.7.2 RESET, Interrupt, ADTRG Timing
(Ta = -40 to +85°C, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)
Notes: 1. ADTRG is same spec (P03/INTP0/ADTRG). DRST is same spec (P05/INTP2/DRST)
2. 2Tsamp+20 or 3Tsamp+20 ("Tsamp" is Noise reject sampling clock (NF macro))
Remarks: 1. The above minimum values show pulse widths that are surely detected as an effective
edge. An effective may also be detected even if the input pulse width is less than the
above minimum specification.
2. RESET, NMI, INTPn, ADTRG and DRST have analog noise filter. The typical filter time
is typ=60ns.
2.7.3 Key Return Timing
(Ta = -40 to +85°C, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)
Remarks: 1. The above minimum values show pulse widths that are surely detected as an effective
edge. An effective may also be detected even if the input pulse width is less than the
above minimum specification.
2. KRn inputs have analog noise filter. The typical filter time is typ=60ns.
2.7.4 Timer Timing
(Ta = -40 to +85°C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)
Notes: 1. Except for the external trigger and external event function.
Remarks: 1. The above minimum values show pulse widths that are surely detected as an effective
edge. An effective may also be detected even if the input pulse width is less than the
above minimum specification.
2. TIAAn and TIABn inputs have analog noise filter. The typical filter time is typ=60ns.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
_RESET input low level width tWRSL analog filter 250 ns
NMI input high level width tWNIH analog filter 250 ns
NMI input low level width tWNIL analog filter 250 ns
INTPnNote1 input high level width tWITH analog filter ,n=0-8 250 ns
digital filter ,n=3 Note2 ns
INTPn Note1 input low level width tWITL analog filter ,n=0-8 250 ns
digital filter ,n=3 Note2 ns
Parameter Symbol Conditions MIN. TYP. MAX. Unit
KRn input high level width tWKRH analog filter ,n=0-7 250 ns
KRn input low level width tWKRL analog filter ,n=0-7 250 ns
Parameter Symbol Conditions MIN. TYP. MAX. Unit
TI input high level
width tTIH TIAA00-01,10-11,20-21,30-31,40-41 Note1
TIAB00-03 Note1 250 ns
TI input low level
width tTIL TIAA00-01,10-11,20-21,30-31,40-41 Note1
TIAB00-03 Note1 250 ns
TO output cycle tTCYK
TIAA00-01,10-11,20-21,30-31,
40-41 Note1
TIAB00-03 Note1
4.0VVDD5.5V 16 MHz
3.5VVDD<4.0V 10 MHz
23
Data Sheet U18564EE1V2DS00
V850ES/FE3
2.7.5 CSI Timing
(a) Master mode
(Ta = -40 to +85°C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)
(b) Slave mode
(Ta = -40 to +85°C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)
2.7.6 UART Timing
(Ta = -40 to +85°C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)
Parameter Symbol Conditions MIN. MAX. Unit
SCKBn cycle time tKCY1 125 ns
SCKBn high level width tKH1 tKCY1/2-15 ns
SCKBn low level width tKL1 tKCY1/2-15 ns
SIBn setup time ( to SCKBn ) tSIK1 30 ns
SIBn hold time ( from SCKBn ) tKSI1 25 ns
Delay time from SCKBn to SOBn tKSO1 25 ns
Parameter Symbol Conditions MIN. MAX. Unit
SCKBn cycle time tKCY1 200 ns
SCKBn high level width tKH1 90 ns
SCKBn low level width tKL1 90 ns
SIBn setup time ( to SCKBn ) tSIK1 50 ns
SIBn hold time ( from SCKBn ) tKSI1 50 ns
Delay time from SCKBn to SOBn tKSO1 50 ns
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 1.5 Mbps
ASCK0 frequency 10 MHz
tSIKn tKSIn
tKCYn
CSIBn n=0
2
tKLn tKHn
tKSOn
Output data
Input data
SOBn
SIBn
SCKBn
24 Data Sheet U18564EE1V2DS00
V850ES/FE3
2.7.7 IIC Timing
(Ta = -40 to +85°C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)
Notes: 1. At the start condition, the first clock pulse is generated after the hold time
2. The system requires a minimum of 300ns hold time Internally for the SDA signal ( at VIH-
min. of SCL00 signal )
In order to occupy the undefined area at the falling edge of SCL00.
3. If the system does not extend the SCL00 signal low hold time ( tlow ), only the maximum
data hold time (tHD:DAT ) needs to be satisfied.
4. The high-speed-mode IIC bus can be used In a normal-mode IIC bus system.
In this case, set the high-speed-mode IIC bus so that It meets the following conditions.
- If the system does not extend the SCL00 signal's low state hold time:
SU:DAT?250ns
- If the system extends the SCL00 signal's low state hold time:
Transmit the following data bit to the SDA00 line prior to releasing the SCL00 line
(tRmax.+tSU:DAT=1000+250=1250ns: Normal mode IIC bus specification ).
5. Cb: Total capacitance of one bus line (unit: pF)
Parameter Symbol Normal mode High-speed mode Unit
min. max. min. max.
SCL00 clock frequency fCLK 0 100 0 400 kHz
Bus-free time (between stop/start condi-
tions) tBUF 4.7 1.3 us
Hold timeNote1 tHD:STA 4.0 0.6 us
SCL00 clock low-level width tLOW 4.7 1.3 us
SCL00 clock high-level width tHIGH 4.0 0.6 us
Setup time for start/restart conditions tSU:STA 4.7 0.6 us
Data hold
time
CBUS compatible master tHD:DAT 5.0 us
IIC mode 0Note2 0Note2 0.9Note3 us
Data setup time tSU:DAT 250 100Note4 ns
SDA00 and SCL00 signal rise time tR 1000 20+0.1Cb 300 ns
SDA00 and SCL00 signal fall time tF 300 20+0.1Cb 300 ns
Stop condition setup time tSU:STO 4.0 0.6 us
Pilse width with spike supporessed by
input filter tSP 0 50 ns
Capacitance load of each bus line Cb 400 400 pF
25
Data Sheet U18564EE1V2DS00
V850ES/FE3
IIC bus interface timing
Remark: P: Stop condition
S: Start condition
Sr: Restart condition
P Sr
tSU:STO tSP tHD:STA
S P
tBUF
tHD:DAT tHD:STA
tR tLOW
SCL00
tSU:STA
tHIGH
SDA00
tF
tSU:DAT
26 Data Sheet U18564EE1V2DS00
V850ES/FE3
2.7.8 CAN Timing
(Ta = -40 to +85°C, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 1Mbps
Internal delay time 100 ns
CRXDn pin
( Receive data )
Internal delay time (tNODE)= Internal Transfer Delay(toutput) + Internal Receive Delay(tinput)
tinput
toutput
CTXDn pin
( Transfer data )
CAN Internal clock*
*) CAN Internal clock (fCAN) :CAN baud rate clock
CTXDn pin
CRXDn pin
Image figure of Internal delay
CAN
macro
Internal Transfer delay
Internal Receive delay
V850ES/Fx3
27
Data Sheet U18564EE1V2DS00
V850ES/FE3
2.8 A/D Converter
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 4.0 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. Overall error excluding quantization error (±0.05%FSE). It is indicated as a ratio to the full-
scale value.
2. Excluding quantization error (±1/2 LSB)
3. Not tested in production.
4. Does not include input/output capacitance CIO
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 bit
Overall errorNote1 4.0VAVREF0<5.5V ±0.15 ±0.3 %FSR
Conversion time tCONV 3.10 16 μs
Stabilization time tSTA After ADA0PS bit = 0 -> 1 2 μs
Recovery time for power down
mode tDPU 1 µs
Zero-scale errorNote1 ZSE ±0.3 %FSR
Full-scale errorNote1 FSE ±0.3 %FSR
Integral non-liniearity errorNote2 INL ±2.5 LSB
Differential non-liniearity errorNote2 DNL ±1.5 LSB
Analog input voltage VIAN AVSS AVREF0 V
Analog input equivalent
circuit capacitance Note3,4 CINA 6.19 pF
Analog input equivalent
circuit resistance Note3 RINA 2.55 kΩ
AVREF0 current IAREF0 A/D operating 4 7 mA
A/D operation stop 1 10 uA
Conversion rusult when using
Diagnostic function
AVREF0 conversion 3FC 3FF HEX
AVSS conversion 000 003 HEX
28 Data Sheet U18564EE1V2DS00
V850ES/FE3
2.9 POC
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD, VSS = EVSS = AVSS = 0V)
Notes: 1. From detect voltage to release reset signal
2. From detect voltage to occurrence of reset signal
Note: POC is available only in M2 devices. Refer to ’Ordering information’ in the V850ES/Fx3 User’s
Manual.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detect voltage VPOC0 3.3 3.5 3.7 V
Supply voltage rise time tPTH From VDD=0V to
VDD=3.3V 0.002 ms
Response time1 Note1 tPTHD In case of power on.
After VDD reaches 3.7V. 2.0 ms
Response time2 Note2 tPD In case of power off.
After VDD drop 3.3V. 0.2 1.0 ms
VDD minimum width tPW 0.2 ms
tPTH tPTHD tPD
tPW
T
VDD
(TYP.)
(MIN.)
Detect voltag(MAX.)
tPTHD
29
Data Sheet U18564EE1V2DS00
V850ES/FE3
2.10 LVI
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. From detect voltage to occurrence interrupt/reset signal
2. If POC functionality is available, the wait time is not needed.
2.11 RAM Retention Flag
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 1.9 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. From detect voltage to set RAMFbit (RAMS.bit0)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detect voltage VLVI0 3.8 4.0 4.2 V
VLVI1 3.5 3.7 3.9 V
Response time Note1 tLD After VDD reaches VLVI0/1(max).
After VDD drop VLVI0/1(min). 0.2 2.0 ms
VDD minimum width tLW 0.2 ms
Reference voltage stabilization
wait time Note2 tLWAIT After VDD reaches 3.3V.
After LVION bit (LVIM.bit7) = 0->1 0.1 0.2 ms
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detect voltage VRAMH 1.9 2.0 2.1 V
Supply voltage rise time tRAMHTH From VDD=0V to VDD=3.3V 0.002 1800 ms
Response time Note1 tRAMHD After VDD reaches 2.1V. 0.2 2.0 ms
VDD minimum width tRAMHW 0.2 ms
tLWAIT tLD
tLW
T
VDD
(TYP.)
(MIN.)
Detect voltag(MAX.)
Operation voltage (MIN.)
LVION bit=0 1(LVI function work)
tLD
tRAMHTH
tRAMHD tRAMHW
T
VDD
(TYP.)
(MIN.)
Detect voltag(MAX.)
Operation voltage (MIN.)
tRAMHD
30 Data Sheet U18564EE1V2DS00
V850ES/FE3
2.12 Data Retention Characteristics
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD = 1.9 to 5.5V, VSS = EVSS = AVSS = 0V) (
Remark: When STOP mode is entered/released operation voltage range must be controlled.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention power
supply voltage VDDDR STOP mode
(All function is stopped) 1.9 5.5 V
Data retention power
supply current IDDDR VDDDR=2.0V(
All function is stopped) 6.5 70 μA
Supply voltage rise time tRVD 1 μs
Supply voltage fall time tFVD 1 μs
Supply voltage hold time tHVD After STOP mode 0 ms
STOP release signal input
time tDREL
After VDD reaches operat-
ing voltage range MIN.
3.3V
0ms
Data retention high-level
input voltage VIHDR All input port 0.9VDDDR VDDDR V
Data retention low-level
input voltage VILDR All input port 0 0.1VDDDR V
Operation voltage(min.)
Setting STOP mode
tHVD VDDDR
VIHDR
VIHDR
tDREL
VILDR
NMI,INTPn(Input)
(When STOP mode is
released at rising edge)
NMI,INTPn(Input)
(When STOP mode is
released at falling edge)
_RESET
VDD/EVDD/BVDD
tFVD tRVD
31
Data Sheet U18564EE1V2DS00
V850ES/FE3
2.13 Flash Memory Programming Characteristics
(a) Basic Characteristics
(C=4.7uF, VDD = EVDD, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. Under the condition of CWRT1
2. Under the condition of CWRT2
Remark: The initial write when the product is shipped, any erase write set of operations, or any
programming operation is counted as one rewrite.
Example: P: Program(write) E: Erase
Product is shipped P E P E P : Rewrite count: 3
Product is shipped E P E P E P : Rewrite count: 3
(b) Serial Writing Operation Characteristics
(Ta = -40 to +85°C, C=4.7uF, VDD = EVDD, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V, CL=50pF)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Operation frequency fCPU 4 32 MHz
Supply voltage VDD 3.3 5.5 V
Number of rewrites CWRT1 Code Flash 1000 count
Data Flash
CWRT2 10000
High level input voltage VIH FLMD0 0.8EVDD EVDD V
Low level input voltage VIL FLMD0 EVSS 0.2EVDD V
Programming temperature tPRG -40 +85 °C
Data retention
Code Flash 15Note1
year
Data Flash 5Note2
Parameter Symbol Conditions MIN. TYP. MAX. Unit
FLMD0 setup time (from VDD) tDP 1 ms
RESET release (from FLMD0) tPR 2 ms
FLMD0 pulse input start
(from raise edge of _RESET) tRP 800 μs
FLMD0 high level width /
low level width tPW 10 100 μs
FLMD0 raise time tR 50 ns
FLMD0 fall time tF 50 ns
32 Data Sheet U18564EE1V2DS00
V850ES/FE3
3. Electrical Specifications of (A1)-Grade
This product has to be used only under the conditions of VDD=EVDD. Operation is not ensured at the
time of using this product except this condition.
3.1 Absolute Maximum Ratings
Absolute Maximum Ratings (Ta=25°C)
Remarks: 1. The characteristics of the dual-function pins are the same as those of the port pins
unless otherwise specified
Notes: 1. Be sure not to exceed the absolute maximum ratings (Max. value) of each supply voltage.
2. Excluding ADC0 IAREF0 current.
3.2 Capacities
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.3 Operating condition
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.4 Voltage Regulator Characteristics
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.5 Clock Generator Circuit
3.5.1 Main System Clock Oscillation Circuit Characteristics
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
Parameter Symbol Conditions Rating Unit
Supply voltage
VDD VDD=EVDD, -0.5 to +6.5 V
EVDD VDD=EVDD -0.5 to +6.5 V
AVREF0 -0.5 to +6.5 V
VSS VSS=EVSS=AVSS -0.5 to +0.5 V
EVSS VSS=EVSS=AVSS -0.5 to +0.5 V
AVSS VSS=EVSS=AVSS -0.5 to +0.5 V
Input voltage
VI1 Pin Group 1x, 2x, 6 -0.5 to EVDD+0.5
Note1 V
VI3 Pin Group 7 -0.5 to VRO+0.5
Note1 V
Analog input voltage VIAN Pin Group 4 -0.5 to AVREF0+0.5
Note1 V
High level output cur-
rent IOH
Pin Group 1x, 2x 1 pin -4 mA
To t a l - 2 0 m A
Pin Group 4 1 pin -4 mA
To t a l -10Note2 mA
Low level output current IOL
Pin Group 1x, 2x 1 pin 4 mA
To t a l 2 0 m A
Pin Group 4 1 pin 4 mA
To t a l 10Note2 mA
Operating ambient
temperature Ta Normal operating mode -40 to +110 °C
Flash programming mode -40 to +110
Storage temperature Tstg -40 to +125 °C
33
Data Sheet U18564EE1V2DS00
V850ES/FE3
3.5.2 Sub System Clock Oscillation Circuit Characteristics
(Ta = -40 to +110°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristic" for cpu opera-
tion clock.
2. Time required to stabilize oscillation after VDD reaches oscillator voltage range min. 3.3V
3. In order to avoid the influence of wiring capacity, shorten wiring as much as possible.
4. RC Oscillation frequency is typ. 40kHz. This clock is divided by 2 internally. In case of RC
Oscillator, internal system clock frequency(fxt) is min. 12.5kHz, typ. 20kHz, max. 27.5kHz.
3.5.3 Internal-OSC Characteristics
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.5.4 PLL Characteristics
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.5.5 SSCG Characteristics
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
RC
resonator Refer to Figure 2
Oscillator
frequencyNote1,4
R=390KΩ ±5% Note3,
C=47pF±10% Note3 25 40 55 kHz
Oscillation stabiliza-
tion time Note2 100 μs
XT1 XT2
R
34 Data Sheet U18564EE1V2DS00
V850ES/FE3
3.6 DC Characteristics
3.6.1 Input/Output Level
(Ta = -40 to +110°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Remark: The characteristics of the dual-function pins are the same as those of the port pins unless
otherwise specified.
Notes: 1. DRST terminal only. (Control register is OCDM)
2. Total IOH/IOL max is 20mA/-20mA for the power supply line EVDD.
Total IOH/IOL max is 10mA/-10mA for the power supply line AVREF0.
AVREF0 IOH/IOL current is excluding ADC0 current IAREF0.
3. Typical value. Not tested and guaranteed
Parameter Sym-
bol Conditions MIN. TYP. MAX. Uni
t
High level
input voltage
VIH1 Pin Group 1B 0.7EVDD EVDD V
VIH2 Pin Group 1D 0.8EVDD EVDD V
Pin Group 2D 0.8EVDD EVDD V
VIH3 Pin Group 2A 0.7EVDD EVDD V
VIH4 Pin Group 4 0.7AVREF0 AVREF0 V
VIH5 Pin Group 6 0.8EVDD EVDD V
Low level
input voltage
VIL1 Pin Group 1B EVSS 0.3EVDD V
VIL2 Pin Group 1D EVSS 0.4EVDD V
Pin Group 2D EVSS 0.4EVDD V
VIL3 Pin Group 2A EVSS 0.3EVDD V
VIL4 Pin Group 4 AVSS 0.3AVREF0 V
VIL5 Pin Group 6 EVSS 0.2EVDD V
Input hysteresis
VHYS1 Pin Group 1B Center point at
0.5 x EVDD Note3 0.267 x EVDD - 0.51V V
VHYS2
Pin Group 1D Center point at
0.6 x EVDD Note3 0.192 x EVDD - 0.31V V
Pin Group 2D Center point at
0.6 x EVDD Note3 0.192 x EVDD - 0.31V V
VHYS5 Pin Group 6 Center point at
0.5 x EVDD Note3 0.535 x EVDD - 0.9V V
High level
output voltage
Note2
VOH1 Pin Group
1x, 2x
IOH=-1.0mA EVDD-1.0 EVDD V
IOH=-100uA EVDD-0.5 EVDD V
VOH3 Pin Group 4 IOH=-1.0mA AVREF0-1.0 AVREF0 V
IOH=-100uA AVREF0-0.5 AVREF0 V
Low level output
voltageNote2
VOL1
Pin Group 1x,
2x IOL=1.0mA 00.4V
P914, 915 IOL=3.0mA
VOL3 Pin Group 4 IOL=1.0mA 0 0.4 V
Software pull-up
resistor R1 VI=0V 10 30 100 kΩ
Software Note1
pull-down resistor R2 VI=VDD 10 30 100 kΩ
35
Data Sheet U18564EE1V2DS00
V850ES/FE3
3.6.2 PIN leakage current
(Ta = -40 to +110°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. The input leakage current of FLMD0 is as follows:
High level input leakage current : 4.0uA
Low level input leakage current : -4.0uA
Parameter Symbol Conditions MIN. TYP. MAX. Unit
High level input
leakage current ILIH1 VI=VDD Analog pins 0.4
uA
Other pins Note1 0.8
Low level input
leakage current ILIL1 VI=0V Analog pins -0.4
Other pins Note1 -0.8
High level output
leakage current ILOH1 VO=VDD Analog pins 0.4
Other pins 0.8
Low level output
leakage current ILOL1 VO=0V Analog pins -0.4
Other pins -0.8
36 Data Sheet U18564EE1V2DS00
V850ES/FE3
3.6.3 Power supply current (A1-grade)
3.6.3.1 FE3 128KB μPD70F3370A, FE3 256KB μPD70F3371
(a) Absolute values
(Ta = -40 to +110°C, C=4.7uF,
VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0VNote1)
Mode Symbol Condition TYP. MAX. Unit
Operating
mode
Note2,8
IDD1
All peripherals
running
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx32MHz
fxx=20MHz
fx=5MHz 27 37 mA
fxx=32MHz
fx=16MHz 39 51 mA
PLL: OFF
4MHzfxx16MHz
fxx=8MHz
8MHz Internal-
OSC Note3
13 20 mA
fxx=16MHz
fx=16MHz 21 30 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
12MHzfxx32MHz
fxx=32MHz
fx=16MHz 35 47 mA
All peripherals
stopped
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx32MHz
fxx=20MHz
fx=5MHz 22 mA
fxx=32MHz
fx=16MHz 32 mA
PLL: OFF
4MHzfxx16MHz
fxx=8MHz
8MHz Internal-
OSC Note3
12 mA
fxx=16MHz
fx=16MHz 19 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
12MHzfxx32MHz
fxx=32MHz
fx=16MHz 31 mA
HALT
mode
Note8
IDD2
All peripherals
running
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx32MHz
fxx=20MHz
fx=5MHz 16 23 mA
fxx=32MHz
fx=16MHz 24 34 mA
PLL: OFF
4MHzfxx16MHz
fxx=8MHz
8MHz Internal-
OSC
Note3
812mA
fxx=16MHz
fx=16MHz 13 20 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
12MHzfxx32MHz
fxx=32MHz
fx=16MHz 20 27 mA
All peripherals
stopped
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx32MHz
fxx=20MHz
fx=5MHz 12 mA
fxx=32MHz
fx=16MHz 18 mA
PLL: OFF
4MHzfxx16MHz
fxx=8MHz
8MHz Internal-
OSC Note3
5mA
fxx=16MHz
fx=16MHz 9mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
12MHzfxx32MHz
fxx=32MHz
fx=16MHz 17 mA
37
Data Sheet U18564EE1V2DS00
V850ES/FE3
IDLE1
mode IDD3
Peripheral (TAA, UARTD) run-
ning
PLL: OFF
4MHzfxx16MHz
Note7
fxx=5MHz
fx=5MHz 1.4 2.5 mA
fxx=12MHz
fx=12MHz 2.0 3.4 mA
fxx=16MHz
fx=16MHz 2.4 3.9 mA
fxx=8MHz, 8MHz Internal-OSCNote3 1.5 2.6 mA
All peripherals stopped
PLL: OFF
4MHzfxx16MHz
Note7
fxx=5MHz
fx=5MHz 1.2 mA
fxx=12MHz
fx=12MHz 1.4 mA
fxx=16MHz
fx=16MHz 1.6 mA
fxx=8MHz, 8MHz Internal-OSCNote3 1.1 mA
IDLE2
mode IDD4
PLL: OFF
4MHzfxx16MHz
Note7
fxx=5MHz
fx=5MHz 0.4 0.9 mA
fxx=12MHz
fx=12MHz 0.7 1.2 mA
fxx=16MHz
fx=16MHz 0.8 1.4 mA
fxx=8MHz, 8MHz Internal-OSC Note3 0.2 0.7 mA
SUB
operating
modeNote5
IDD5
RC resonator (fxt=20kHz) Note6 80 600 µA
240 kHz Internal-OSC (SubOSC stopped) 220 1200 µA
SubIDLE
modeNote3, IDD6
RC resonator (fxt=20kHz) Note6 40 420 μA
240kHz Internal-OSC (SubOSC stopped) 25 380 μA
STOP
mode
Note3,4
IDD7
POC stop 240kHz Internal-OSC stop 7.5 280 μA
240kHz Internal-OSC working 15.5 295 μA
POC work 240kHz Internal-OSC stop 10.5 285 μA
240kHz Internal-OSC working 18.5 300 μA
Mode Symbol Condition TYP. MAX. Unit
38 Data Sheet U18564EE1V2DS00
V850ES/FE3
(b) Calculation formulas
(Ta = -40 to +110°C, C=4.7uF,
VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0VNote1)
Notes: 1. VDD and EVDD total current. (Ports are stopped).
AVREF0 current, port buffer current (including a current flowing in the on-chip pull-up/pull-
down resistor) are not included.
2. The code flash and the data flash are in read mode.
When the device is in programming mode (Self-programming mode or data flash program-
ming mode), the current value (MAX. value) adds by the following value:
Self-programming mode:
+ In case of PLL OFF: 7-(0.33*fxx+0.1) [mA]
+ In case of PLL ON: 7-(0.18*fxx+3.0) [mA]
Data flash programming mode:
+ 7-(0.18*fxx/4+3.0) [mA]
3. Main OSC is stopped.
4. Do not use SubOSC.
5. POC is working. 240kHz Internal-OSC is working. 8MHz Internal-OSC is stopped.
6. RC Oscillation frequency is typ.40kHz. This clock is divided by 2 internally.
7. 8MHz Internal-OSC is stopped
8. When the SSCG is running, the current value adds typ +2.5mA, max +4mA.
9. The formulas are for reference only. Not all possible values for fxx are tested in the outgoing
device inspection.
Mode Symbol Condition TYP. Note9 MAX. Note3 Unit
Operating
mode
Note2,8
IDD1
All peripherals
running
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx32MHz 0.98fxx+7.1 1.18fxx+13.6 mA
PLL: OFF
4MHzfxx16MHz 0.98fxx+5.5 1.18fxx+10.6 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
12MHzfxx32MHz 0.90fxx+6.0 1.08fxx+12.2 mA
All peripherals
stopped
Peripheral: ffxx-
PRSI option: 0
PLL: ON
12MHzfxx32MHz 0.81fxx+6.2 mA
PLL: OFF
4MHzfxx16MHz 0.83fxx+5.7 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
12MHzfxx32MHz 0.79fxx+6.2 mA
HALT
mode
Note8
IDD2
All peripherals
running
Peripheral: ffxx-
PRSI option: 0
PLL: ON
16MHzfxx32MHz 0.67fxx+3.0 0.90*fxx+5.4 mA
PLL: OFF
4MHzfxx16MHz 0.70fxx+1.9 1.00*fxx+4.0 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
16MHzfxx32MHz 0.55fxx+2.8 0.64*fxx+7.0 mA
All peripherals
stopped
Peripheral: fxx
PRSI option: 0
PLL: ON
16MHzfxx32MHz 0.46fxx+2.8 mA
PLL: OFF
4MHzfxx16MHz 0.44fxx+1.6 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
16MHzfxx32MHz 0.46fxx+1.8 mA
IDLE1
mode IDD3
Peripheral (TAA, UARTD) run-
ning
PLL: OFF
4MHzfxx16MHz
Note7
0.092fxx+0.90 0.128fxx+ 1.82 mA
All peripherals stopped 0.035fxx+1.01 mA
IDLE2
mode IDD4 PLL: OFF
4MHz fxx16MHz Note7 0.037fxx+0.21 0.049fxx+ 0.63 mA
39
Data Sheet U18564EE1V2DS00
V850ES/FE3
3.7 AC Characteristics
AC test Input measurement points ( VDD, AVREF0, EVDD)
AC test output measurement points
Load conditions
Caution: If the load capacitance exceeds 50pF due to the circuit configuration, reduce the load
capacitance of the device to 50pF or less by inserting a buffer or by some other means.
3.7.1 CLKOUT Output Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.7.2 RESET, Interrupt, ADTRG Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.7.3 Key Return Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.7.4 Timer Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.7.5 CSI Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.7.6 UART Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.7.7 IIC Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.7.8 CAN Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
measure point
VIH(min)
VIL(max)
VIH(min)
VIL(max)
VDD
VSS
measure point
VOH(min)
VOL(max)
VOH(min)
VOL(max)
CL = 50 pF
DUT
( Device under
test )
40 Data Sheet U18564EE1V2DS00
V850ES/FE3
3.8 A/D Converter
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.9 POC
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.10 LVI
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.11 RAM Retention Flag
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.12 Data Retention Characteristics
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
3.13 Flash Memory Programming Characteristics
(a) Basic Characteristics
(C=4.7uF, VDD = EVDD, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. Under the condition of CWRT1
2. Under the condition of CWRT2
Remark: The initial write when the product is shipped, any erase write set of operations, or any
programming operation is counted as one rewrite.
Example: P: Program(write) E: Erase
Product is shipped P E P E P : Rewrite count: 3
Product is shipped E P E P E P : Rewrite count: 3
(b) Serial Writing Operation Characteristics
Specification is identical to that from (A)-Grade except Ta=-40 to +110°C.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Operation frequency fCPU 4 32 MHz
Supply voltage VDD 3.3 5.5 V
Number of rewrites CWRT1 Code Flash 1000 count
Data Flash
CWRT2 10000
High level input voltage VIH FLMD0 0.8EVDD EVDD V
Low level input voltage VIL FLMD0 EVSS 0.2EVDD V
Programming temperature tPRG -40 +110 °C
Data retention
Code Flash 15Note1
year
Data Flash 5Note2
41
Data Sheet U18564EE1V2DS00
V850ES/FE3
4. Electrical Specifications of (A2)-Grade
This product has to be used only under the conditions of VDD=EVDD. Operation is not ensured at the
time of using this product except this condition.
4.1 Absolute Maximum Ratings
Specification is identical to that from (A1)-Grade except
Operating ambient temperature Ta = -40 to +125°C
•Note2: AVREF0 IOH/IOL current is including ADC0 max. current IAREF0.
4.2 Capacities
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
42 Data Sheet U18564EE1V2DS00
V850ES/FE3
4.3 Operating condition
(Ta = -40 to +125°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. For using SSCG please refer to ’4.5.5 SSCG Characteristics’ for details
2. VDD = EVDD
3. RC Oscillation frequency is min. 25kHz max. 55kHz. This clock is divided by 2 internally.
4.4 Voltage Regulator Characteristics
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
4.5 Clock Generator Circuit
4.5.1 Main System Clock Oscillation Circuit Characteristics
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
Internal System clock frequency (fVBCLK)Supply voltage Operating Condition
4.0fxx24MHz
Note1
4.0VVDD5.5VNote2
Operation of functions is usable under following
conditions:
Peripheral clock frequency
fXP1 fXX
fXP2 fXX
AC characteristics:
Refer to chapter ’4.7 AC Characteris-
tics’ for details.
3.5VVDD<4.0VNote2
Operation of functions is usable under following
conditions:
Peripheral clock frequency
fXP1 20MHz
fXP2 20MHz
AC characteristics:
Refer to chapter ’4.7 AC Characteris-
tics’ for details.
3.3VVDD<3.5VNote2
Only operation of the following functions is
assured:
CPU
Flash (include programming)
RAM
IO Buffer
Port
WT
WDT
INT
CLM
POC
LVI
3.3VAVREF05.5V
A/D Converter
Refer to chapter ’4.8 A/D Converter’ for
details.
stop ADC for AVREF0 < 4.0V
(ADA0CE bit =0)
12.5kHzfXT27.5kHz Note3(RC) 3.3VVDD<5.5VNote2 -
fRL (240kHz Internal-OSC) 3.3VVDD<5.5VNote2 -
43
Data Sheet U18564EE1V2DS00
V850ES/FE3
4.5.2 Sub System Clock Oscillation Circuit Characteristics
Specification is identical to that from (A1)-Grade except Ta=-40 to +125°C.
4.5.3 Internal-OSC Characteristics
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
4.5.4 PLL Characteristics
(Ta = -40 to +125°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. The input of the PLL (fPLLI) can be set to fX, fX/2, or fX/4. The divider is set through an option
byte in the code flash memory.
2. Not tested in production.
4.5.5 SSCG Characteristics
(Ta = -40 to +125°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Remark: The SSCG MAX output frequency indicates the case without modulation. If modulation is
enabled the average SSCG frequency has to be set lower. The maximum achievable aver-
age operating frequency with modulation is as follows:
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input frequency fx 4 16 MHz
fPLLI Note 36MHz
Output frequency fxx 256KB product 12 24 MHz
Lock time tPLL After VDD reaches voltage range min. 3.3V 800 μs
Output period jitter
Note2 tpj Peak to peak 2.0 ns
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input frequency fx 4 16 MHz
Output frequency fxx 256KB product 12 24 MHz
Lock time tSSCG After VDD reaches voltage range min. 3.3V 1000 μs
SSCG input clock divider selector
SFC1[6:4]
Percent modulation Maximum average operating fre-
quency Unit
TYP MAX 256KB product
000B ± 0.5% ± 2.0% 23.5
MHz
001B ± 1.0% ± 2.5% 23.4
010B ± 2.0% ± 4.0% 23.0
011B ± 3.0% ± 6.0% 22.6
100B ± 4.0% ± 8.0% 22.1
101B ± 5.0% ± 10.0% 21.6
44 Data Sheet U18564EE1V2DS00
V850ES/FE3
4.6 DC Characteristics
4.6.1 Input/Output Level
Specification is identical to that from (A1)-Grade except
Ta = -40 to +125°C.
Note 2:Total IOH/IOL max is 20mA/-20mA for the power supply lines EVDD.
Total IOH/IOL max is 3mA/-3mA for the power supply line AVREF0.
AVREF0 IOH/IOL current is excluding ADC0 current IAREF0.
If ADC0 is not used total IOH/IOL max is 10mA/-10mA for the power supply line AVREF0.
4.6.2 PIN leakage current
(Ta = -40 to +125°C, C=4.7uF, VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. The input leakage current of FLMD0 is as follows:
High level input leakage current: 5.0uA
Low level input leakage current: -5.0uA
Parameter Symbol Conditions MIN. TYP. MAX. Unit
High level input
leakage current ILIH1 VI=VDD Analog pins 0.5
uA
Other pins Note1 1.0
Low level input
leakage current ILIL1 VI=0V Analog pins -0.5
Other pins Note1 -1.0
High level output
leakage current ILOH1 VO=VDD Analog pins 0.5
Other pins 1.0
Low level output
leakage current ILOL1 VO=0V Analog pins -0.5
Other pins -1.0
45
Data Sheet U18564EE1V2DS00
V850ES/FE3
4.6.3 Power supply current (A2-grade)
4.6.3.1 FE3 128KB μPD70F3370A, FE3 256KB μPD70F3371
(a) Absolute values
(Ta = -40 to +125°C, C=4.7uF,
VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0VNote1)
Mode Symbol Condition TYP. MAX. Unit
Operating
mode
Note2,8
IDD1
All peripherals
running
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx24MHz
fxx=20MHz
fx=5MHz 27 37 mA
PLL: OFF
4MHzfxx16MHz
fxx=8MHz
8MHz Internal-
OSC Note3
13 20 mA
fxx=16MHz
fx=16MHz 21 30 mA
All peripherals
stopped
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx24MHz
fxx=20MHz
fx=5MHz 22 mA
PLL: OFF
4MHzfxx16MHz
fxx=8MHz
8MHz Internal-
OSC Note3
12 mA
fxx=16MHz
fx=16MHz 19 mA
HALT
mode
Note8
IDD2
All peripherals
running
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx24MHz
fxx=20MHz
fx=5MHz 16 23 mA
PLL: OFF
4MHzfxx16MHz
fxx=8MHz
8MHz Internal-
OSC Note3
812mA
fxx=16MHz
fx=16MHz 13 20 mA
All peripherals
stopped
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx24MHz
fxx=20MHz
fx=5MHz 12 mA
PLL: OFF
4MHzfxx16MHz
fxx=8MHz
8MHz Internal-
OSC Note3
5mA
fxx=16MHz
fx=16MHz 9mA
IDLE1
mode IDD3
Peripheral (TAA, UARTD) run-
ning
PLL: OFF
4MHzfxx16MHz
Note7
fxx=5MHz
fx=5MHz 1.4 2.8 mA
fxx=12MHz
fx=12MHz 2.0 3.7 mA
fxx=16MHz
fx=16MHz 2.4 4.2 mA
fxx=8MHz, 8MHz Internal-OSCNote3 1.5 2.9 mA
All peripherals stopped
PLL: OFF
4MHzfxx16MHz
Note7
fxx=5MHz
fx=5MHz 1.2 mA
fxx=12MHz
fx=12MHz 1.4 mA
fxx=16MHz
fx=16MHz 1.6 mA
fxx=8MHz, 8MHz Internal-OSCNote3 1.1 mA
46 Data Sheet U18564EE1V2DS00
V850ES/FE3
IDLE2
mode IDD4
PLL: OFF
4MHzfxx16MHz
Note7
fxx=5MHz
fx=5MHz 0.4 1.1 mA
fxx=12MHz
fx=12MHz 0.7 1.5 mA
fxx=16MHz
fx=16MHz 0.8 1.7 mA
fxx=8MHz, 8MHz Internal-OSC Note3 0.2 1.0 mA
SUB
operating
modeNote5
IDD5
RC resonator (fxt=20kHz) Note6 80 850 µA
240 kHz Internal-OSC (SubOSC stopped) 220 1450 µA
SubIDLE
mode
Note3,5
IDD6
RC resonator (fxt=20kHz) Note6 40 670 μA
240kHz Internal-OSC (SubOSC stopped) 25 630 μA
STOP
mode
Note3,4
IDD7
POC stop 240kHz Internal-OSC stop 7.5 530 μA
240kHz Internal-OSC working 15.5 545 μA
POC work 240kHz Internal-OSC stop 10.5 535 μA
240kHz Internal-OSC working 18.5 550 μA
Mode Symbol Condition TYP. MAX. Unit
47
Data Sheet U18564EE1V2DS00
V850ES/FE3
(b) Calculation formulas
(Ta = -40 to +125°C, C=4.7uF,
VDD = EVDD = 3.3 to 5.5V, AVREF0 = 3.3 to 5.5V, VSS = EVSS = AVSS = 0VNote1)
Notes: 1. VDD and EVDD total current. (Ports are stopped).
AVREF0 current, port buffer current (including a current flowing in the on-chip pull-up/pull-
down resistor) are not included.
2. The code flash and the data flash are in read mode.
When the device is in programming mode (Self-programming mode or data flash program-
ming mode), the current value (MAX. value) adds by the following value:
Self-programming mode:
+ In case of PLL OFF: 7-(0.33*fxx+0.1) [mA]
+ In case of PLL ON: 7-(0.18*fxx+3.0) [mA]
Data flash programming mode:
+ 7-(0.18*fxx/4+3.0) [mA]
3. Main OSC is stopped.
4. Do not use SubOSC.
5. POC is working. 240kHz Internal-OSC is working. 8MHz Internal-OSC is stopped.
6. RC Oscillation frequency is typ.40kHz. This clock is divided by 2 internally.
7. 8MHz Internal-OSC is stopped
8. When the SSCG is running, the current value adds typ +2.5mA, max +4mA.
9. The formulas are for reference only. Not all possible values for fxx are tested in the outgoing
device inspection.
Mode Symbol Condition TYP. Note9 MAX. Note9 Unit
Operating
mode
Note2,8
IDD1
All peripherals
running
Peripheral: fxx
PRSI option: 0
PLL: ON
12MHzfxx24MHz 0.98fxx+7.1 1.18fxx+13.6 mA
PLL: OFF
4MHzfxx16MHz 0.98fxx+5.5 1.18fxx+10.6 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
12MHzfxx24MHz 0.90fxx+6.0 1.08fxx+12.2 mA
All peripherals
stopped
Peripheral: ffxx-
PRSI option: 0
PLL: ON
12MHzfxx24MHz 0.81fxx+6.2 mA
PLL: OFF
4MHzfxx16MHz 0.83fxx+5.7 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
12MHzfxx24MHz 0.79fxx+6.2 mA
HALT
mode
Note8
IDD2
All peripherals
running
Peripheral: ffxx-
PRSI option: 0
PLL: ON
16MHzfxx24MHz 0.67fxx+3.0 0.90*fxx+5.4 mA
PLL: OFF
4MHzfxx16MHz 0.70fxx+1.9 1.00*fxx+4.0 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
16MHzfxx24MHz 0.55fxx+2.8 0.64*fxx+7.0 mA
All peripherals
stopped
Peripheral: fxx
PRSI option: 0
PLL: ON
16MHzfxx24MHz 0.46fxx+2.8 mA
PLL: OFF
4MHzfxx16MHz 0.44fxx+1.6 mA
Peripheral: fxx/2
PRSI option: 1
PLL: ON
16MHzfxx24MHz 0.46fxx+1.8 mA
IDLE1
mode IDD3
Peripheral (TAA, UARTD) run-
ning
PLL: OFF
4MHzfxx16MHz
Note7
0.092fxx+0.90 0.128fxx+ 2.12 mA
All peripherals stopped 0.035fxx+1.01 mA
IDLE2
mode IDD4 PLL: OFF
4MHz fxx16MHz Note7 0.037fxx+0.21 0.049fxx+ 0.88 mA
48 Data Sheet U18564EE1V2DS00
V850ES/FE3
4.7 AC Characteristics
AC test Input measurement points ( VDD, AVREF0, EVDD)
AC test output measurement points
Load conditions
Caution: If the load capacitance exceeds 50pF due to the circuit configuration, reduce the load
capacitance of the device to 50pF or less by inserting a buffer or by some other means.
4.7.1 CLKOUT Output Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
4.7.2 RESET, Interrupt, ADTRG Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
4.7.3 Key Return Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
4.7.4 Timer Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
4.7.5 CSI Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
4.7.6 UART Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
4.7.7 IIC Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
4.7.8 CAN Timing
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
measure point
VIH(min)
VIL(max)
VIH(min)
VIL(max)
VDD
VSS
measure point
VOH(min)
VOL(max)
VOH(min)
VOL(max)
CL = 50 pF
DUT
( Device under
test )
49
Data Sheet U18564EE1V2DS00
V850ES/FE3
4.8 A/D Converter
(Ta = -40 to +125°C, C=4.7uF, VDD = EVDD = 3.5 to 5.5V, AVREF0 = 4.0 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. Overall error excluding quantization error (±0.05%FSE). It is indicated as a ratio to the full-
scale value.
2. Excluding quantization error (±1/2 LSB)
3. Not tested in production.
4. Does not include input/output capacitance CIO
4.9 POC
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
4.10 LVI
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
4.11 RAM Retention Flag
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
4.12 Data Retention Characteristics
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 bit
Overall errorNote1 4.0VAVREF0<5.5V ±0.15 ±0.35 %FSR
Conversion time tCONV 3.10 16 μs
Stabilization time tSTA After ADA0PS bit = 0 -> 1 2 μs
Recovery time for power down
mode tDPU 1 µs
Zero-scale errorNote1 ZSE ±0.35 %FSR
Full-scale errorNote1 FSE ±0.35 %FSR
Integral non-liniearity errorNote2 INL ±2.5 LSB
Differential non-liniearity errorNote2 DNL ±1.5 LSB
Analog input voltage VIAN AVSS AVREF0 V
Analog input equivalent
circuit capacitance Note3,4 CINA 6.19 pF
Analog input equivalent
circuit resistance Note3 RINA 2.55 kΩ
AVREF0 current IAREF0 A/D operating 4 7 mA
A/D operation stop 1 10 uA
Conversion rusult when using
Diagnostic function
AVREF0 conversion 3FC 3FF HEX
AVSS conversion 000 003 HEX
50 Data Sheet U18564EE1V2DS00
V850ES/FE3
4.13 Flash Memory Programming Characteristics
(a) Basic Characteristics
(C=4.7uF, VDD = EVDD, AVREF0 = 3.5 to 5.5V, VSS = EVSS = AVSS = 0V)
Notes: 1. Under the condition of CWRT1
2. Under the condition of CWRT2
Remark: The initial write when the product is shipped, any erase write set of operations, or any
programming operation is counted as one rewrite.
Example: P: Program(write) E: Erase
Product is shipped P E P E P : Rewrite count: 3
Product is shipped E P E P E P : Rewrite count: 3
(b) Serial Writing Operation Characteristics
Specification is identical to that from (A)-Grade except Ta=-40 to +125°C.
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Operation frequency fCPU 4 32 MHz
Supply voltage VDD 3.3 5.5 V
Number of rewrites CWRT1 Code Flash 1000 count
Data Flash
CWRT2 10000
High level input voltage VIH FLMD0 0.8EVDD EVDD V
Low level input voltage VIL FLMD0 EVSS 0.2EVDD V
Programming temperature tPRG -40 +125 °C
Data retention
Code Flash 15Not1
year
Data Flash 5Note2
51
Data Sheet U18564EE1V2DS00
V850ES/FE3
5. Package
5.1 Package Dimension
θ
+
ITEM DIMENSIONS
±
±
±
±
±
±
θ
±
±
P64GB-50-GAH
°+°
°
NOTE
64-PIN PLASTIC LQFP(FINE PITCH)(10x10)
+
52 Data Sheet U18564EE1V2DS00
V850ES/FE3
5.2 Product Marking
5.2.1 Marking of pin 1 at a QFP (Quad Flat Package)
Example 1: The index mark for pin 1 is the beveled edge of the package
Example 2: The index mark for pin 1 is a round notch at one of the 4 edges. In this case, the shape of
all edges is identical (usually beveled).
Example 3: For production reasons, two or more similar notches may be located at the top of the pack-
age. In such a case the index marker for pin 1 is a round notch with an additional mark in it.
Note: RoHS compliant devices have an additional dot at the top side. Do not mix it up with the mark-
ing for pin 1. For details see 5.2.2 "Identification of Lead-Free Products" on page 53.
53
Data Sheet U18564EE1V2DS00
V850ES/FE3
5.2.2 Identification of Lead-Free Products
Lead-Free products are marked with a dot "•". The marking methods are the paint or the laser (It
doesn't sink in). The shape of lead-free marks is a circle.
Example:
54 Data Sheet U18564EE1V2DS00
V850ES/FE3
6. Change History
The following revision list shows all major changes of the different datasheet versions.
Version Chapter Comment
V1.0 Initial release
V1.1
2.13
3.13
Removed ’Target Specification’ for (A)- and (A1)-Grade Devices in the Flash Pro-
gramming specifications.
Changed specification of ’Number of rewrites’ from MAX. to MIN.
2.8
4.8 Remove Caution (Described in User’s Manual)
V1.2
Changed document status from ’Preliminary Datasheet’ to ’Datasheet’.
4.12 Removed ’Target Specification’ for (A2)-Grade Devices in the Flash Programming
specifications.
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