ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com DUAL DIGITAL ISOLATORS Check for Samples: ISO7220A, ISO7220B, ISO7220C, ISO7220M, ISO7221A, ISO7221B, ISO7221C, ISO7221M FEATURES 1 * 2 * * * * * 1, 5, 25, and 150-Mbps Signaling Rate Options - Low Channel-to-Channel Output Skew; 1 ns max - Low Pulse-Width Distortion (PWD); 1 ns max - Low Jitter Content; 1 ns Typ at 150 Mbps Typical 25-Year Life at Rated Voltage (see app. note SLLA197 and Figure 20) 4000-VPK VIOTM, 560 VPK VIORM per IEC 60747-5-2 (VDE 0884, Rev2) UL 1577, IEC 61010-1, IEC 60950-1 and CSA Approved 50 kV/s Typical Transient Immunity Operates with 2.8-V (C-Grade), 3.3-V or 5-V Supplies * * * 4 kV ESD Protection High Electromagnetic Immunity -40C to 125C Operating Range APPLICATIONS * * * * Industrial Fieldbus - Modbus - ProfibusTM - DeviceNetTM Data Buses Computer Peripheral Interface Servo Control Interface Data Acquisition DESCRIPTION The ISO7220 and ISO7221 are dual-channel digital isolators. To facilitate PCB layout, the channels are oriented in the same direction in the ISO7220 and in opposite directions in the ISO7221. These devices have a logic input and output buffer separated by TI's silicon-dioxide (SiO2) isolation barrier, providing galvanic isolation of up to 4000 VPK. Used in conjunction with isolated power supplies, these devices block high voltage, isolate grounds, and prevent noise currents on a data bus or other circuits from entering the local ground and interfering with or damaging sensitive circuitry. A binary input signal is conditioned, translated to a balanced signal, then differentiated by the capacitive isolation barrier. Across the isolation barrier, a differential comparator receives the logic transition information, then sets or resets a flip-flop and the output circuit accordingly. A periodic update pulse is sent across the barrier to ensure the proper dc level of the output. If this dc-refresh pulse is not received every 4 s, the input is assumed to be unpowered or not being actively driven, and the failsafe circuit drives the output to a logic high state. The small capacitance and resulting time constant provide fast operation with signaling rates available from 0 Mbps (dc) to 150 Mbps. (1) The A-, B- and C-option devices have TTL input thresholds and a noise filter at the input that prevents transient pulses from being passed to the output of the device. The M-option devices have CMOS VCC/2 input thresholds and do not have the input noise-filter and the additional propagation delay. (1) 1 INA INB 2 GND1 4 3 Isolation VCC1 8 VCC2 7 OUTA OUTB GND2 6 5 VCC1 1 OUTA INB 2 GND1 4 3 Isolation ISO7221xD ISO7220xD 8 VCC2 7 INA OUTB GND2 6 5 The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second). 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DeviceNet is a trademark of Open DeviceNet Vendors Association. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006-2012, Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION CONTINUED These devices require two supply voltages of 2.8 V (C-Grade), 3.3 V, 5 V, or any combination. All inputs are 5-V tolerant when supplied from a 2.8-V or 3.3-V supply and all outputs are 4-mA CMOS. These devices are characterized for operation over the ambient temperature range of -40C to 125C. SINGLE-CHANNEL FUNCTION DIAGRAM Galvanic Isolation Barrier DC Channel Filter OSC + PWM IN Pulse Width Demodulation Vref Carrier Detect Input + Filter Data MUX AC Detect Vref OUT Output Buffer AC Channel AVAILABLE OPTIONS PRODUCT MAX SIGNALING RATE PACKAGE INPUT THRESHOLD ISO7220A 1 Mbps SOIC-8 1.5 V (TTL) (CMOS compatible) I7220A I7220B CHANNEL DIRECTION MARKED AS ISO7220B 5 Mbps SOIC-8 1.5 V (TTL) (CMOS compatible ISO7220C 25 Mbps SOIC-8 1.5 V (TTL) (CMOS compatible) I7220C ISO7220M 150 Mbps SOIC-8 VCC/2 (CMOS) I7220M ISO7221A 1 Mbps SOIC-8 1.5 V (TTL) (CMOS compatible) I7221A ISO7221B 5 Mbps SOIC-8 1.5 V (TTL) (CMOS compatible) I7221B ISO7221C 25 Mbps SOIC-8 1.5 V (TTL) (CMOS compatible) I7221C ISO7221M 150 Mbps SOIC-8 VCC/2 (CMOS) I7221M Same direction Opposite directions 2 ORDERING NUMBER ISO7220AD (rail) ISO7220ADR (reel) ISO7220BD (rail) ISO7220BDR (reel) ISO7220CD (rail) ISO7220CDR (reel) ISO7220MD (rail) ISO7220MDR (reel) ISO7221AD (rail) ISO7221ADR (reel) ISO7221BD (rail) ISO7221ABR (reel) ISO7221CD (rail) ISO7221CDR (reel) ISO7221MD (rail) ISO7221MDR (reel) Copyright (c) 2006-2012, Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com REGULATORY INFORMATION VDE CSA UL Certified according to IEC 60747-5-2 Approved under CSA Component Acceptance Notice 5A Recognized under UL 1577 Component Recognition Program Basic Insulation Maximum Transient Overvoltage, 4000 VPK Maximum Surge Voltage, 4000 VPK Maximum Working Voltage, 560 VPK Evaluated to CSA 60950-1-07 and IEC 60950-1 (2nd Ed.) for products with working voltages 125 VRMS for reinforced insulation or 400 VRMS for basic insulation Single Protection, 2500 VRMS (1) File Number: 40016131 File Number: 220991 File Number: E181974 (1) Production tested 3000 VRMS for 1 second in accordance with UL 1577. ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT VCC Supply voltage (2), VCC1, VCC2 -0.5 to 6 V VI Voltage at IN, OUT -0.5 to 6 V IO Output current 15 mA ESD Electrostatic discharge Human Body Model TJ (1) (2) Electrostatic discharge JEDEC Standard 22, Test Method A114-C.01 Field-Induced-Charged Device Model JEDEC Standard 22, Test Method C101 Machine Model ANSI/ESDS5.2-1996 4 All pins kV 1 Maximum junction temperature 200 V 170 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. RECOMMENDED OPERATING CONDITIONS MIN VCC Supply voltage (1), VCC1, VCC2 ISO722xA, ISO722xB, ISO722xM ISO722xC IOH High-level output current IOL Low-level output current tui 1/tui Input pulse width (2) Signaling rate (2) 3 5.5 2.8 5.5 UNIT V mA 4 mA s ISO722xA 1 0.67 ISO722xB 200 100 ISO722xC 40 33 ISO722xM 6.67 5 ISO722xA 0 1500 1000 ISO722xB 0 10 5 ISO722xC 0 30 25 ISO722xM 0 200 150 ISO722xA, ISO722xB, ISO722xC 2 VCC V 0 0.8 V 0.7 VCC VCC V 0 0.3 VCC V -40 150 C 1000 A/m High-level input voltage VIL Low-level input voltage VIH High-level input voltage VIL Low-level input voltage TJ Junction temperature H External magnetic field-strength immunity per IEC 61000-4-8 & IEC 61000-4-9 certification (2) MAX -4 VIH (1) TYP ISO722xM ns kbps Mbps For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. For the 2.8-V operation, VCC1 or VCC2 is specified at 2.8 V. Typical signaling rate and Input pulse width are measured at ideal conditions at 25C. Copyright (c) 2006-2012, Texas Instruments Incorporated 3 ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7220x ISO7221 ISO7220A, ISO7220B ICC1 ISO7221A, ISO7221B ISO7220C, ISO7220M ISO7221C, ISO7221M ISO7220x ISO7221x ISO7220A, ISO7220B ICC2 ISO7221A, ISO7221B ISO7220C, ISO7220M ISO7221C, ISO7221M VOH High-level output voltage VOL Low-level output voltage Quiescent VI = VCC or 0 V, no load 1 Mbps 0.5 MHz Input Clock Signal, no load 25 Mbps 12.5 MHz Input Clock Signal, no load Quiescent VI = VCC or 0 V, no load 1 Mbps 0.5 MHz Input Clock Signal, no load 25 Mbps 12.5 MHz Input Clock Signal, no load 2 17 2 3 10 18 4 9 12 22 16 31 8.5 17 17 32 10 18 20 34 12 22 IOH = -4 mA, See Figure 1 VCC - 0.8 4.6 IOH = -20 A, See Figure 1 VCC - 0.1 5 0.2 0.4 IOL = 20 A, See Figure 1 0 0.1 150 IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6t) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 -10 25 V mV 10 IN from 0 V to VCC mA V IOL = 4 mA, See Figure 1 VI(HYS) Input voltage hysteresis (1) 1 8.5 A 1 pF 50 kV/s For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL - tpLH| (1) tpLH, tpHL Propagation delay ISO722xA Pulse-width distortion |tpHL - tpLH| Propagation delay PWD Pulse-width distortion |tpHL - tpLH| (1) tpLH, tpHL Propagation delay tsk(pp) (1) (2) 4 Part-to-part skew (2) TYP MAX 280 405 475 1 14 55 70 1 3 32 42 1 2 10 16 42 ISO722xB tpLH, tpHL Pulse-width distortion |tpHL - tpLH| MIN (1) PWD PWD TEST CONDITIONS See Figure 1 ISO722xC ISO722xM (1) 22 6 0.5 UNIT ns 1 ISO722xA 180 ISO722xB 17 ISO722xC 10 ISO722xM 3 ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Copyright (c) 2006-2012, Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS (3) TYP MAX ISO722xA MIN 3 15 ISO722xB 0.6 3 ISO722xC/M 0.2 1 tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss See Figure 2 3 1 Peak-to-peak eye-pattern jitter 150 Mbps PRBS NRZ data, 5-bit max same polarity input, both channels, See Figure 4, Figure 17 150 Mbps unrestricted bit run length data input, both channels, See Figure 4 2 tjit(pp) (3) 1 See Figure 1 ISO722xM UNIT ns ns 1 s ns tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7220x ISO7221x ISO7220A, ISO7220B ICC1 ISO7221A, ISO7221B ISO7220C, ISO7220M ISO7221C, ISO7221M ISO7220x ISO7221x ISO7220A, ISO7220B ICC2 ISO7221A, ISO7221B ISO7220C, ISO7220M ISO7221C, ISO7221M VOH High-level output voltage 2 17 VI = VCC or 0 V, no load 1 Mbps 0.5 MHz Input Clock Signal, no load 2 3 10 18 25 Mbps 12.5 MHz Input Clock Signal, no load 4 9 12 22 Quiescent VI = VCC or 0 V, no load 8 18 4.3 9.5 9 19 5 11 10 20 6 12 1 Mbps 0.5 MHz Input Clock Signal, no load 25 Mbps 12.5 MHz Input Clock Signal, no load ISO7220x IOH = -4 mA, See Figure 1 V VCC - 0.1 IOL = 4 mA, See Figure 1 0.4 IOL = 20 A, See Figure 1 0.1 VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6t) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 150 IN from 0 V to VCC mA VCC - 0.4 VCC - 0.8 ISO7221x (5-V side) IOH = -20 A, See Figure 1 (1) 1 8.5 Quiescent mV 10 -10 15 V A 1 pF 40 kV/s For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. Copyright (c) 2006-2012, Texas Instruments Incorporated 5 ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL - tpLH| tpLH, tpHL Propagation delay ISO722xA TYP MAX 285 410 480 1 14 58 75 1 3 36 48 1 2 12 20 45 ISO722xB (1) Pulse-width distortion |tpHL - tpLH| tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL - tpLH| (1) tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL - tpLH| (1) Part-to-part skew MIN (1) PWD tsk(pp) TEST CONDITIONS See Figure 1 25 ISO722xC 7 ISO722xM (2) 0.5 tsk(o) Channel-to-channel output skew (3) 180 ISO722xB 17 ISO722xC 10 5 ISO722xA 3 15 ISO722xB 0.6 3 ISO722xC/M 0.2 1 tr Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss See Figure 2 3 1 Peak-to-peak eye-pattern jitter 150 Mbps PRBS NRZ data, 5-bit max same polarity input, both channels, See Figure 4, Figure 17 150 Mbps unrestricted bit run length data input, both channels, See Figure 4 2 tjit(pp) (1) (2) (3) 6 2 See Figure 1 ISO722xM 2 ns 1 ISO722xA ISO722xM UNIT ns ns s ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Copyright (c) 2006-2012, Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7220x ISO7221x ISO7220A, ISO7220B ICC1 ISO7221A, ISO7221B ISO7220C, ISO7220M ISO7221C, ISO7221M ISO7220x ISO7221x ISO7220A, ISO7220B ICC2 ISO7221A, ISO7221B ISO7220C, ISO7220M ISO7221C, ISO7221M Quiescent VI = VCC or 0 V, no load 1 Mbps 0.5 MHz Input Clock Signal, no load 25 Mbps 12.5 MHz Input Clock Signal, no load Quiescent VI = VCC or 0 V, no load 1 Mbps 25 Mbps 0.5 MHz Input Clock Signal, no load 12.5 MHz Input Clock Signal, no load High-level output voltage ISO7221x (3.3-V side) IOH = -4 mA, See Figure 1 IOH = -20 A, See Figure 1 9.5 1 2 5 11 2 4 6 12 16 31 8.5 17 18 32 10 18 20 34 12 22 mA VCC - 0.4 V VCC - 0.1 IOL = 4 mA, See Figure 1 VOL Low-level output voltage VI(HYS) Input threshold voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6t) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 (1) 1 4.3 VCC - 0.8 ISO7220x VOH 0.6 0.4 IOL = 20 A, See Figure 1 0 0.1 150 IN from 0 V or VCC mV 10 -10 15 A 1 pF 40 kV/s For the 5-V operation, VCC1 or VCC2 is specified from 4.5 V to 5.5 V. For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. Copyright (c) 2006-2012, Texas Instruments Incorporated 7 ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERTAION over recommended operating conditions (unless otherwise noted) PARAMETER tpLH, tpHL TEST CONDITIONS Propagation delay PWD Pulse-width distortion |tpHL - tpLH| tpLH, tpHL Propagation delay ISO722xA MAX 285 395 480 1 18 58 75 1 4 36 48 1 3 12 21 0.5 1 45 ISO722xB (1) Pulse-width distortion |tpHL - tpLH| tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL - tpLH| (1) tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL - tpLH| (1) Part-to-part skew TYP (1) PWD tsk(pp) MIN See Figure 1 25 ISO722xC 7 ISO722xM (2) ISO722xA 190 ISO722xB 17 ISO722xC 10 ISO722xM tsk(o) Channel-to-channel output skew (3) 3 15 ISO722xB 0.6 3 ISO7220C/M 0.2 1 Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss See Figure 2 3 1 Peak-to-peak eye-pattern jitter 150 Mbps PRBS NRZ data, 5-bit max same polarity input, both channels, See Figure 4, Figure 17 150 Mbps unrestricted bit run length data input, both channels, See Figure 4 2 (1) (2) (3) 8 1 See Figure 1 ISO722xM ns 5 ISO722xA tr tjit(pp) UNIT 1 s ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Copyright (c) 2006-2012, Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY CURRENT ISO7220x ISO7221x ISO7220A, ISO7220B ICC1 ISO7221A, ISO7221B ISO7220C, ISO7220M ISO7221C, ISO7221M ISO7220x ISO7221x ISO7220A, ISO7220B ICC2 ISO7221A, ISO7221B ISO7220C, ISO7220M ISO7221C, ISO7221M VOH Quiescent VI = VCC or 0 V, no load 1 Mbps 0.5 MHz Input Clock Signal, no load 25 Mbps 12.5 MHz Input Clock Signal, no load Quiescent VI = VCC or 0 V, no load 1 Mbps 25 Mbps High-level output voltage 0.5 MHz Input Clock Signal, no load 12.5 MHz Input Clock Signal, no load 1 4.3 9.5 1 2 5 11 2 4 6 12 8 18 4.3 9.5 9 19 5 11 10 20 6 12 IOH = -4 mA, See Figure 1 VCC - 0.4 3 IOH = -20 A, See Figure 1 VCC - 0.1 3.3 IOL = 4 mA, See Figure 1 VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6t) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 (1) 0.6 IOL = 20 A, See Figure 1 0.2 0.4 0 0.1 150 IN from 0 V or VCC 15 V mV 10 -10 mA A 1 pF 40 kV/s For the 3.3-V operation, VCC1 or VCC2 is specified from 3 V to 3.6 V. Copyright (c) 2006-2012, Texas Instruments Incorporated 9 ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com SWITCHING CHARACTERISTICS VCC1 and VCC2 at 3.3 V operation, over recommended operating conditions (unless otherwise noted) PARAMETER tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL - tpLH| tpLH, tpHL Propagation delay ISO722xA MIN TYP MAX 290 400 485 1 18 62 78 1 4 40 52 1 3 16 25 0.5 1 (1) 46 ISO722xB (1) PWD Pulse-width distortion |tpHL - tpLH| tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL - tpLH| (1) tpLH, tpHL Propagation delay PWD Pulse-width distortion |tpHL - tpLH| (1) tsk(pp) TEST CONDITIONS See Figure 1 26 ISO722xC 8 ISO722xM Part-to-part skew (2) ISO722xA 190 ISO722xB 17 ISO722xC 10 ISO722xM tsk(o) Channel-to-channel output skew (3) 3 15 ISO722xB 0.6 3 ISO722xC/M 0.2 1 Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss See Figure 2 3 1 Peak-to-peak eye-pattern jitter 150 Mbps PRBS NRZ data, 5-bit max same polarity input, both channels, See Figure 4, Figure 17 150 Mbps unrestricted bit run length data input, both channels, See Figure 4 2 (1) (2) (3) 10 2 See Figure 1 ISO722xM ns 5 ISO722xA tr tjit(pp) UNIT 2 s ns Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Copyright (c) 2006-2012, Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 2.8 V (ISO722xC-only) (1) OPERATION over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 0.4 0.9 3.7 7.5 1.5 3.5 4.5 10 6.8 15 3.7 7.5 9 17 4.5 10 UNIT SUPPLY CURRENT ISO7220C ISO7221C ICC1 ISO7220C ISO7221C ISO7220C ISO7221C ICC2 ISO7220C ISO7221C VOH Quiescent 25 Mbps Quiescent 25 Mbps High-level output voltage VI = VCC or 0 V, no load 12.5 MHz Input Clock Signal, no load VI = VCC or 0 V, no load 12.5 MHz Input Clock Signal, no load IOH = -4 mA, See Figure 1 VCC - 0.6 IOH = -20 A, See Figure 1 VCC - 0.1 IOL = 4 mA, See Figure 1 VOL Low-level output voltage VI(HYS) Input voltage hysteresis IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6t) CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 3 (1) IOL = 20 A, See Figure 1 2.55 2.8 0.25 0.6 0 0.1 150 IN from 0 V or VCC -10 V mV 10 10 mA A 1 pF 30 kV/s 2.8-V operation is only guaranteed for ISO722xC with production screening starting in January 2012. The first two digits of the Lot Trace Code (YMSLLLLG4) written on top of each device can be used to identify year and month of production respectively. Copyright (c) 2006-2012, Texas Instruments Incorporated 11 ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com SWITCHING CHARACTERISTICS VCC1 and VCC2 at 2.8 V operation, over recommended operating conditions (unless otherwise noted) PARAMETER tpLH, tpHL Propagation delay ISO722xC Pulse-width distortion |tpHL - tpLH| tsk(pp) Part-to-part skew (2) tsk(o) Channel-to-channel output skew tr Output signal rise time tf Output signal fall time tfs Failsafe output delay time from input power loss (3) 12 See Figure 1 (1) PWD (1) (2) TEST CONDITIONS MIN TYP MAX 26 45 65 1.5 ISO722xC (3) 5 12 ISO722xC 0.2 See Figure 1 See Figure 2 UNIT ns 5 2 2 4.6 s Also referred to as pulse skew. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical specified loads. Copyright (c) 2006-2012, Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com ISOLATION BARRIER PARAMETER MEASUREMENT INFORMATION IN Input Generator VI 50 W NOTE A VCC VI VCC/2 VCC/2 OUT 0V tPHL tPLH CL NOTE B VO VO VOH 90% 50% 50% 10% tr VOL tf A. The input pulse is supplied by a generator having the following characteristics: PRR 50 kHz, 50% duty cycle, tr 3 ns, tf 3 ns, ZO = 50. B. CL = 15 pF and includes instrumentation and fixture capacitance within 20%. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms VI ISOLATION BARRIER VCC IN = 0 V A. VCC OUT VI 2.7 V VO 0V VOH tfs CL NOTE A VO 50% FAILSAFE HIGH VOL CL = 15 pF and includes instrumentation and fixture capacitance within 20%. Figure 2. Failsafe Delay Time Test Circuit and Voltage Waveforms VCC1 VCC2 S1 ISOLATION BARRIER C = 0.1 mF 1% IN GND1 C = 0.1 mF 1% Pass-fail criteria: Output must remain stable OUT NOTE A VOH or VOL GND2 VCM A. CL = 15 pF and includes instrumentation and fixture capacitance within 20%. Figure 3. Common-Mode Transient Immunity Test Circuit VCC DUT Tektronix HFS9009 IN OUT 0V Tektronix 784D PATTERN GENERATOR VCC/2 Jitter NOTE: PRBS bit pattern run length is 216 - 1. Transition time is 800 ps. Figure 4. Peak-to-Peak Eye-Pattern Jitter Test Circuit and Voltage Waveform Copyright (c) 2006-2012, Texas Instruments Incorporated 13 ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com DEVICE INFORMATION IEC PACKAGE CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (Clearance) Shortest terminal-to-terminal distance through air L(I02) Minimum external tracking (Creepage) Shortest terminal-to-terminal distance across the package surface CTI Tracking resistance (Comparative Tracking Index) DIN IEC 60112 / VDE 0303 Part 1 400 V Minimum Internal Gap (Internal Clearance) Distance through the insulation 0.008 mm RIO Isolation resistance SOIC-8 4.8 mm 4.3 mm Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device, TA < 100C >1012 Input to output, VIO = 500 V, 100C TA max >1011 CIO Barrier capacitance Input to output VI = 0.4 sin (4E6t) 1 pF CI Input capacitance to ground VI = 0.4 sin (4E6t) 1 pF NOTE: Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board do not reduce this distance. Creepage and clearance on a printed circuit board become equal according to the measurement techniques shown in the Isolation Glossary . Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. IEC 60664-1 RATINGS TABLE PARAMETER Basic isolation group Installation classification TEST CONDITIONS SPECIFICATION Material group II Rated mains voltage 150 VRMS I-IV Rated mains voltage 300 VRMS I-III Rated mains voltage 400 VRMS I-II IEC 60747-5-2 INSULATION CHARACTERISTICS (1) PARAMETER TEST CONDITIONS SPECIFICATION VIORM Maximum working insulation voltage VPR Input to output test voltage Method b1, VPR = VIORM x 1.875, 100% Production test with t = 1 s, Partial discharge <5 pC 1050 VIOTM Transient overvoltage t = 60 s 4000 RS Insulation resistance VIO = 500 V at TS >109 Pollution degree (1) 14 UNIT 560 VPK 2 Climatic Classification 40/125/21 Copyright (c) 2006-2012, Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com DEVICE I/O SCHEMATICS Input VCC1 VCC1 VCC1 Output VCC2 750 kW IN 8W 500 W OUT 13 W IEC SAFETY LIMITING VALUES Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures. PARAMETER TEST CONDITIONS IS Safety input, output, or supply current SOIC-8 TS Maximum case temperature SOIC-8 MIN TYP MAX JA = 212C/W, VI = 5.5 V, TJ = 170C, TA = 25C 124 JA = 212C/W, VI = 3.6 V, TJ = 170C, TA = 25C 190 150 UNIT mA C The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. Copyright (c) 2006-2012, Texas Instruments Incorporated 15 ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com SOIC-8 PACKAGE THERMAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Low-K Thermal Resistance JA Junction-to-air JB Junction-to-Board Thermal Resistance JC Junction-to-Case Thermal Resistance PD Device Power Dissipation (1) MIN (1) TYP MAX UNIT 212 High-K Thermal Resistance 122 C/W 37 69.1 ISO722xM VCC1 = VCC2 = 5.5 V, TJ = 150C, CL = 15 pF, Input a 150 Mbps 50% duty cycle square wave 390 mW Tested in accordance with the Low-K or High-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages. 250 Safety Limiting Current - mA 225 VCC1,2 at 3.6 V 200 175 150 125 VCC1,2 at 5.5 V 100 75 50 25 0 0 50 100 150 TC - Case Temperature - C 200 Figure 5. SOIC-8 JC THERMAL DERATING CURVE per IEC 60747-5-2 DEVICE FUNCTION TABLE Table 1. ISO7220x or ISO7221x (1) INPUT SIDE VCC (1) 16 OUTPUT SIDE VCC PU PU PD PU INPUT IN OUTPUT OUT H H L L Open H X H PU = Powered Up(Vcc 3.0V); PD = Powered Down (Vcc 2.5V); X = Irrelevant; H = High Level; L = Low Level Copyright (c) 2006-2012, Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTIC CURVES 3.3-V RMS SUPPLY CURRENT vs SIGNALING RATE (Mbps) 5-V RMS SUPPLY CURRENT vs SIGNALING RATE (Mbps) 20 30 TA = 25C, 15 pF Load 18 26 ICC - Supply Current - mA 14 ISO7220x ICC2 12 10 ISO7221x ICC1&2 8 6 4 ISO7220x ICC1 22 20 14 12 10 25 50 ISO7220x ICC1 8 6 2 0 0 0 ISO7221x ICC1&2 18 16 4 2 75 100 0 25 Signaling Rate - Mbps 50 75 Signaling Rate - Mbps Figure 6. Figure 7. PROPAGATION DELAY vs FREE-AIR TEMPERATURE, ISO722xA PROPAGATION DELAY vs FREE-AIR TEMPERATURE, ISO722xB 450 100 70 TA = 25C, 15 pF Load 15 pF Load 440 65 Propagation Delay - ns 430 Propagation Delay - ns ISO7220x ICC2 24 16 ICC - Supply Current - mA TA = 25C, 15 pF Load 28 420 VCC = 3.3 V 410 tpLH & tpHL 400 VCC = 5 V 390 tpLH & tpHL 380 370 VCC = 3.3 V tPLH & tPHL 60 55 VCC = 5 V tPLH & tPHL 50 360 350 -40 -15 10 35 60 Temperature - C Figure 8. Copyright (c) 2006-2012, Texas Instruments Incorporated 85 110 125 45 -40 25 Temperature - C 125 Figure 9. 17 ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTIC CURVES (continued) PROPAGATION DELAY vs FREE-AIR TEMPERATURE, ISO722xC PROPAGATION DELAY vs FREE-AIR TEMPERATURE, ISO722xM 30 20 VCC = 3.3 V 25 VCC = 3.3 V 15 Propagation Delay - ns Propagation Delay - ns tpLH & tpHL 20 15 VCC = 5 V tpLH & tpHL 10 tpLH & tpHL 10 VCC = 5 V tpLH & tpHL 5 5 15 pF Load 0 -40 -15 10 35 60 15 pF Load 0 -40 110 125 85 -15 10 Temperature - C 35 60 110 125 85 Temperature - C Figure 10. Figure 11. ISO722xA, ISO722xB AND ISO722xC INPUT VOLTAGE LOW-TO-HIGH SWITCHING THRESHOLD vs FREE-AIR TEMPERATURE ISO722xM INPUT VOLTAGE HIGH-TO-LOW vs FREE-AIR TEMPERATURE 2.5 1.4 2.4 5-V Vth+ 1.35 5-V Vth+ 3.3-V Vth+ 1.25 15 pF Load 1.2 1.15 5-V Vth1.1 Input Voltage Threshold - V Input Voltage Threshold - V 2.3 1.3 2.2 5-V Vth- 2.1 2 15 pF Load 1.9 1.8 1.7 3.3-V Vth+ 1.6 1.05 1.5 3.3-V Vth1 -40 -25 -10 5 20 35 50 65 Temperature - C Figure 12. 18 80 95 110 125 3.3-V Vth- 1.4 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature - C Figure 13. Copyright (c) 2006-2012, Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTIC CURVES (continued) VCC UNDERVOLTAGE THRESHOLD vs FREE-AIR TEMPERATURE HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE -80 15 pF Load TA = 25C -70 2.64 -60 VCC = 5 V VCC Rising -50 2.6 IOUT - mA Power Supply Undervoltage Threshold - V 2.68 2.56 -40 -30 VCC Falling VCC = 3.3 V -20 2.52 -10 2.48 -40 -25 -10 0 5 20 35 50 65 80 95 110 125 0 2 Free-Air Temperature - C Figure 14. Figure 15. LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE ISO722xM JITTER vs SIGNALING RATE 70 6 2000 15 pF Load TA = 25C 60 15 pF Load TA = 25C 1800 VCC = 5 V 1600 50 1400 1200 40 Jitter - ps IOUT - mA 4 VOUT - V VCC = 3.3 V 30 VCC1 = VCC2 = 5 V 1000 800 600 20 VCC1 = VCC2 = 3.3 V 400 10 200 0 0 0 1 2 3 VOUT - V Figure 16. Copyright (c) 2006-2012, Texas Instruments Incorporated 4 5 0 50 100 150 200 Signaling Rate - Mbps Figure 17. 19 ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com APPLICATION INFORMATION Typical Applications V CC 1 V CC 2 0.1mF 2 mm max . from Vcc 1 INPUT 1 INA 2 INB INPUT 3 4 8 OUTA 7 OUTB 6 5 2 mm max . from Vcc 2 0.1mF OUTPUT OUTPUT ISO 7220 GND 1 GND 2 Figure 18. Typical ISO7220 Application Circuit V CC 1 V CC 2 0.1mF 2 mm max . from Vcc 1 OUTA OUTPUT INB INPUT 1 2 3 4 8 INA 7 OUTB 6 5 2 mm max . from Vcc 2 0.1mF INPUT OUTPUT ISO 7221 GND 1 GND 2 Figure 19. Typical ISO7221 Application Circuit WORKING LIFE -- YEARS 100 VIORM at 560 V 28 10 0 120 250 500 750 880 1000 WORKING VOLTAGE (V IORM ) -- V Figure 20. Time Dependent Dielectric Breakdown Test Results 20 Copyright (c) 2006-2012, Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com ISOLATION GLOSSARY Creepage Distance -- The shortest path between two conductive input to output leads measured along the surface of the insulation. The shortest distance path is found around the end of the package body. Clearance -- The shortest distance between two conductive input to output leads measured through air (line of sight). Input-to Output Barrier Capacitance -- The total capacitance between all input terminals connected together, and all output terminals connected together. Input-to Output Barrier Resistance -- The total resistance between all input terminals connected together, and all output terminals connected together. Primary Circuit -- An internal circuit directly connected to an external supply mains or other equivalent source which supplies the primary circuit electric power. Secondary Circuit -- A circuit with no direct connection to primary power, and derives its power from a separate isolated source. Comparative Tracking Index (CTI) -- CTI is an index used for electrical insulating materials which is defined as the numerical value of the voltage which causes failure by tracking during standard testing. Tracking is the process that produces a partially conducting path of localized deterioration on or through the surface of an insulating material as a result of the action of electric discharges on or close to an insulation surface -- the higher CTI value of the insulating material, the smaller the minimum creepage distance. Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is generated. These sparks often cause carbonization on insulation material and lead to a carbon track between points of different potential. This process is known as tracking. Copyright (c) 2006-2012, Texas Instruments Incorporated 21 ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 www.ti.com Insulation: Operational insulation -- Insulation needed for the correct operation of the equipment. Basic insulation -- Insulation to provide basic protection against electric shock. Supplementary insulation -- Independent insulation applied in addition to basic insulation in order to ensure protection against electric shock in the event of a failure of the basic insulation. Double insulation -- Insulation comprising both basic and supplementary insulation. Reinforced insulation -- A single insulation system which provides a degree of protection against electric shock equivalent to double insulation. Pollution Degree: Pollution Degree 1 -- No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence. Pollution Degree 2 -- Normally, only nonconductive pollution occurs. However, a temporary conductivity caused by condensation must be expected. Pollution Degree 3 -- Conductive pollution occurs or dry nonconductive pollution occurs which becomes conductive due to condensation which is to be expected. Pollution Degree 4 - Continuous conductivity occurs due to conductive dust, rain, or other wet conditions. Installation Category: Overvoltage Category -- This section is directed at insulation co-ordination by identifying the transient overvoltages which may occur, and by assigning 4 different levels as indicated in IEC 60664. I: Signal Level -- Special equipment or parts of equipment. II: Local Level -- Portable equipment etc. III: Distribution Level -- Fixed installation IV: Primary Supply Level -- Overhead lines, cable systems Each category should be subject to smaller transients than the category above. SPACER REVISION HISTORY Changes from Original (July 2006) to Revision A Page * Deleted "and CSA Apporved" from the UL 1577 FEATURES bullet .................................................................................... 1 * Added option A to the AVAILABLE OPTIONS table ............................................................................................................ 2 Changes from Revision A (August 2006) to Revision B Page * Added the ELECTICAL CHARACTERISTICS tables to the data sheet ............................................................................... 3 * Added the PARAMETER MEASUREMENT INFORMATION to the data sheet ................................................................. 13 * Added the DEVICE INFORMATION section to the data sheet .......................................................................................... 14 * Added the TYPICAL CHARACTERISTIC CURVES to the data sheet. .............................................................................. 17 * Added the APPLICATION INFORMATION section to the data sheet ................................................................................ 20 * Added the ISOLATION GLOSSARY section to the data sheet .......................................................................................... 21 22 Copyright (c) 2006-2012, Texas Instruments Incorporated ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M www.ti.com Changes from Revision B (May 2007) to Revision C SLLS755L - JULY 2006 - REVISED JANUARY 2012 Page * Added the Signaling rate values to the RECOMMENDED OPERATING CONDITIONS table ............................................ 3 * Added Figure 17 cross reference to the Peak-to-peak eye-pattern jitter of the SWITCHING CHARACTERISTICS table ...................................................................................................................................................................................... 5 * Added Figure 17 cross reference to the Peak-to-peak eye-pattern jitter of the SWITCHING CHARACTERISTICS table ...................................................................................................................................................................................... 6 * Added Figure 17 cross reference to the Peak-to-peak eye-pattern jitter of the SWITCHING CHARACTERISTICS table ...................................................................................................................................................................................... 8 * Added Figure 17 cross reference to the Peak-to-peak eye-pattern jitter of the SWITCHING CHARACTERISTICS table .................................................................................................................................................................................... 10 * Changed the IEC 60664-1 RATINGS TABLE - Specification I-III test conditions From: Rated mains voltage 150 VRMS To: Rated mains voltage 300 VRMS. Added a row for the I-II specifications ....................................................... 14 * Added Figure 20 - Time Dependent Dielectric Breakdown Test Results ........................................................................... 20 Changes from Revision C (May 2007) to Revision D * Page Changed Figure 18 - Pin 2 (INA) label From: OUTPUT to INPUT ..................................................................................... 20 Changes from Revision D (June 2007) to Revision E Page * Changed Figure 6 - New Curves ........................................................................................................................................ 17 * Changed Figure 7- Re-scaled the Y-axis ........................................................................................................................... 17 Changes from Revision E (July 2007) to Revision F Page * Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION table ....................... 4 * Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 and VCC2 at 5-V OPERATION table ......................... 5 * Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION table ................ 6 * Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V OPERATION table ................. 6 * Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERTAION table ................ 8 * Added tsk(o) footnote to the SWITCHING CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V OPERTAION table ................. 8 * Added tsk(pp) footnote to the SWITCHING CHARACTERISTICS table ............................................................................... 10 * Added tsk(o) footnote to the SWITCHING CHARACTERISTICS table ................................................................................ 10 * Changed Figure 6 - Re-scaled the Y-axis .......................................................................................................................... 17 * Changed Figure 7 - New Curves ........................................................................................................................................ 17 Changes from Revision F (August 2007) to Revision G Page * Added Part Numbers ISO7220B and ISO7221B to the data sheet ...................................................................................... 1 * Added 5-Mbps Signaling rate to the FEATURES list ............................................................................................................ 1 * Added Part Numbers ISO720B and ISO7221B to the AVAILABLE OPTIONS table ........................................................... 2 * Added Part Numbers ISO720B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V table ...................................................................................................................................................................................... 4 * Added Part Numbers ISO720B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V table ...................................................................................................................................................................................... 5 * Added Part Numbers ISO720B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V table ...................................................................................................................................................................................... 7 * Added Part Numbers ISO720B and ISO7221B to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V ......... 9 * Added PROPAGATION DELAY vs FREE-AIR TEMPERATURE, ISO722xB, Figure 9 ..................................................... 17 Copyright (c) 2006-2012, Texas Instruments Incorporated 23 ISO7220A, ISO7220B, ISO7220C, ISO7220M ISO7221A, ISO7221B, ISO7221C, ISO7221M SLLS755L - JULY 2006 - REVISED JANUARY 2012 Changes from Revision G (March 2008) to Revision H www.ti.com Page * Added Note: (1) to the RECOMMENDED OPERATING CONDITIONS table ..................................................................... 3 * Added Note: (1) to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 5-V table .................................................... 4 * Added Note: (1) to the ELECTRICAL CHARACTERISTICS: VCC1 at 5 V, VCC2 at 3.3 V table ............................................ 5 * Added Note (1): to the ELECTRICAL CHARACTERISTICS: VCC1 at 3.3 V, VCC2 at 5 V table ............................................ 7 * Added Note (1): to the ELECTRICAL CHARACTERISTICS: VCC1 and VCC2 at 3.3 V .......................................................... 9 Changes from Revision H (May 2008) to Revision I * Added "IEC 61010-1, IEC 60950-1 and CSA Approved" to the UL 1577 FEATURES bullet .............................................. 1 Changes from Revision I (December 2008) to Revision J * Page Page Changed ISO7221C Marked As column From: TI7221C To: I7221C in the AVAILABLE OPTIONS table .......................... 2 Changes from Revision J (May 2009) to Revision K Page * Changed column 2 of the AVAILABLE OPTIONS table From: Signaling Rate To: Max Signaling Rate ............................. 2 * Changed the the RECOMMENDED OPERATING CONDITIONS so that Note (2) is associated with all device options in the Input pulse width and Signaling rate .............................................................................................................. 3 * Changed Note (2) From: Typical signaling rate under ideal conditions at 25C. To: Typical signaling rate and Input pulse width are measured at ideal conditions at 25C. ........................................................................................................ 3 Changes from Revision K (January 2010) to Revision L Page * Changed Feature From: 4000-Vpeak Isolation, 560 Vpeak VIORM To: 4000-VPK VIOTM, 560 VPK VIORM per IEC 60747-5-2 (VDE 0884, Rev2) ................................................................................................................................................................. 1 * Changed Feature From: Operates with 3.3-V or 5-V Supplies To: Operates with 2.8-V (C-Grade), 3.3-V or 5-V Supplies ................................................................................................................................................................................ 1 * Changed the REGULATORY INFORMATION table ............................................................................................................ 3 * Added device options to VCC in the RECOMMENDED OPERATING CONDITIONS table .................................................. 3 * Changed Note: (1) in the RECOMMENDED OPERATING CONDITIONS table ................................................................. 3 * Changed ICC1 and ICC2 test conditions in the 5-V table ......................................................................................................... 4 * Changed Table Note: (1) ...................................................................................................................................................... 4 * Changed ICC1 and ICC2 test conditions in the VCC1 at 5 V, VCC2 at 3.3 V table ...................................................................... 5 * Changed Table Note: (1) ...................................................................................................................................................... 5 * Changed ICC1 and ICC2 test conditions in the VCC1 at 3.3 V, VCC2 at 5 V table ...................................................................... 7 * Changed Table Note (1) ....................................................................................................................................................... 7 * Changed ICC1 and ICC2 test conditions in the VCC1 and VCC2 at 3.3 V table .......................................................................... 9 * Changed Table Note (1) ....................................................................................................................................................... 9 * Added ELECTRICAL and Switching CHARACTERISTICS table for VCC1 and VCC2 at 2.8 V (ISO722xC-only) ................ 11 * Changed Figure 2 ............................................................................................................................................................... 13 * Changed the CTI MIN value From: 175 V To: 400 V ..................................................................................................... 14 * Changed Figure 14 ............................................................................................................................................................. 19 24 Copyright (c) 2006-2012, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 4-Jan-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ISO7220AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220ADG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220BD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220BDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220BDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220MD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220MDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220MDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7220MDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221AD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 4-Jan-2012 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ISO7221ADG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221ADR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221BD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221BDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221BDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221BDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221CDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221MD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221MDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221MDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ISO7221MDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 2 (3) Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 4-Jan-2012 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF ISO7220A, ISO7221A, ISO7221C : * Automotive: ISO7220A-Q1, ISO7221A-Q1, ISO7221C-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 21-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ISO7220ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7220CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7220MDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7221ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 ISO7221MDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7220ADR SOIC D 8 2500 367.0 367.0 35.0 ISO7220CDR SOIC D 8 2500 367.0 367.0 35.0 ISO7220MDR SOIC D 8 2500 533.4 186.0 36.0 ISO7221ADR SOIC D 8 2500 367.0 367.0 35.0 ISO7221MDR SOIC D 8 2500 533.4 186.0 36.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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