This document is a general product description and is subject to change without noti ce. Hynix semiconducto r does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.1 / Nov. 2003 1
HY5DU1G422(L)T
HY5DU1G822(L)T
1Gb DDR SDRAM
HY5DU1G422(L)T
HY5DU1G822(L)T
Rev. 0.1 / Nov. 2003 2
HY5DU1G422(L)T
HY5DU1G822(L)T
Revision History
Revision No. History Draft Date Remark
0.1 Initial Draft Nov. 01.2003
Rev. 0.1 / Nov. 2003 3
HY5DU1G422(L)T
HY5DU1G822(L)T
DESCRIPTION
The HY5DU1G422(L)T, HY5DU1G822(L)T are a 1,073,741,824-bit CMOS Double Data Rate(DDR) Synchronous DRAM,
ideally suited for the main memory applications which requires large memory density and high bandwidth.
This Hynix 1Gb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edge s of the /CK), Data,
Data strobes and Write data mask s inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit pr efetched to achieve very high bandwidth. All input and ou tput voltage levels ar e compatible
with SSTL_2.
FEATURES
•VDD, VDDQ = 2.5V +/- 0.2V
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
• On chip DLL align DQ and DQS transition with CK
transition
• DM mask write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
• Programmable /CAS latency 2 / 2.5 /(3) supported
• Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
• Internal four bank operations with single pulsed
/RAS
• Auto refresh and self refresh supported
• tRAS lock out function supported
• 8192 refresh cycles / 64ms,
120ns minimum Refresh Cycle
• JEDEC standard 4 00mil 66pin TSOP-II with 0.65mm
pin pitch
• Full and Half strength driver option controlled by
EMRS
ORDERING INFORMATION
* X means speed grade
Part No. Configuration Package
HY5DU1G422(L)T-X* 256Mx4 400mil
66Pin
TSOP-II
HY5DU1G822(L)T-X* 128Mx8
OPERATING FREQUENCY
Grade CL2 CL2.5 Remark
(CL-tRCD-tRP)
- J 133MHz 166MHz DDR333 (2.5-3-3)
- M 133MHz 133MHz DDR266 (2-2-2)
- K 133MHz 133MHz DDR266A (2-3-3)
- H 100MHz 133MHz DDR266B (2.5-3-3)
- L 100MHz 125MHz DDR200 (2-2-2)
Rev. 0.1 / Nov. 2003 4
HY5DU1G422(L)T
HY5DU1G822(L)T
PIN CONFIGURATION
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
A13
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
A13
VDD
NC
NC
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x8 x4x4 x8
400mil X 875mil
66pin TSOP -II
0.65mm pin pitch
ROW AND COLUMN ADDRESS TABLE
ITEMS 256Mx4 128Mx8
Organization 64M x 4 x 4banks 32M x 8 x 4banks
Row Address A0 - A13 A0 - A13
Column Address A0-A9, A11, A12 A0-A9, A11
Bank Address BA0, BA1 BA0, BA1
Auto Precharge Flag A10 A10
Refresh 8K 8K
Rev. 0.1 / Nov. 2003 5
HY5DU1G422(L)T
HY5DU1G822(L)T
PIN DESCRIPTION
PIN TYPE DESCRIPTION
CK, /CK Input Clock: CK and /CK are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and negative edge of /CK. Output
(read) data is referenced to the crossings of CK and /CK (both directions of crossi ng).
CKE Input
Clock Enable: CKE HIGH activates, and CKE LOW deactiva tes in tern al cl ock signals, and
device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER
DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF
REFRESH entry and exit. CKE is asynchronous for output disable. CKE must be main-
tained high thr ougho ut READ and WRI TE acc e sses. Input buffers, excl uding CK, /CK and
CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during
SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd
is applied.
/CS Input Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All com-
mands are masked when CS is registered high. CS provides for external bank selection on
systems with multiple banks. CS is considered part of the command code.
BA0, BA1 Input Bank Address In puts : BA 0 and BA1 def ine to which bank an ACTIVE, Read, Write or PRE-
CHARGE command is being applied.
A0 ~ A13 Input
Address Input s: Provid e the row ad dress f or ACTIVE co mmands, and the column address
and AUT O PR ECHARGE bit f o r READ/WRITE comman ds, to s elect one lo cati on ou t of the
memory array in the respective bank. A10 is sampled during a precharge command to
determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The
address inputs also provide the op code during a MODE REGISTER SET command. BA0
and BA1 define which mod e register is loaded during th e MODE REGISTER SET command
(MRS or EMRS).
/RAS, /CAS, /WE Input Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being
entered.
DM Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with that inpu t data during a WRITE access. DM is sample d
on both ed ges of D QS . Al thou gh D M pi ns are input only, the DM loading matches the DQ
and DQS loading.
DQS I/O Data Strobe: Output with read data, input with write data. Edge aligned with read data,
centered in write data. Used to capture write data.
DQ I/O Data input / output pin : Data bus
VDD/VSS Supply Power supply for internal circuits and input buffers.
VDDQ/VSSQ Supply Power supply for output buffers for noise immunity.
VREF Supply Reference voltage for inputs for SSTL2 interface.
NC NC No connection.
Rev. 0.1 / Nov. 2003 6
HY5DU1G422(L)T
HY5DU1G822(L)T
FUNCTIONAL BLOCK DIAGRAM (256Mx4)
4Banks x 64Mbit x 4 I/O Double Data Rate Synchronous DRAM
Bank
Control
Write Data Regis ter
2-bit Prefetch Unit
CLK
CKE
DM
/WE
/RAS
/CAS
/CS
/CLK
Mode
Register Row
Decoder
Sense AMP
32Mx8/Bank0
32Mx8/Bank3
32Mx8/Bank2
32Mx8/Bank1
2-bit Prefetch Unit
Output Buff erInput Buffer
Data Strobe
Transmitter
DLL
Block
BA0,BA1
A0~A13
Column Address
Counter
Column Decoder
Data Strobe
Receiver
Command
Decoder
Address
Buffer
8
4
4
CLK
/CLK
8
DS
DQ[0:3]
DQS
CLK_DLL
DS
Mode
Register
Rev. 0.1 / Nov. 2003 7
HY5DU1G422(L)T
HY5DU1G822(L)T
FUNCTIONAL BLOCK DIAGRAM (128Mx8)
4Banks x 32Mbit x 8 I/O Double Data Rate Synchronous DRAM
Bank
Control
Write Data Register
2-bit Prefe tch Uni t
CLK
CKE
DM
/WE
/RAS
/CAS
/CS
/CLK
Mode
Register Row
Decoder
Sense AMP
16Mx16/Bank0
16Mx16/Bank3
16Mx16/Bank2
16Mx16/Bank1
2-bit Prefetch Unit
Output Buff erInput Buffer
Data Strobe
Transmitter
DLL
Block
BA0,BA1
A0~A13
Column Address
Counter
Column Decoder
Data Strobe
Receiver
Command
Decoder
Address
Buffer
16
8
8
CLK
/CLK
16
DS
DQ[0:7]
DQS
CLK_DLL
DS
Mode
Register
Rev. 0.1 / Nov. 2003 8
HY5DU1G422(L)T
HY5DU1G822(L)T
SIMPLIFIED COMMAND TRUTH TABLE
Command CKEn-1 CKEn CS RAS CAS WE ADDR A10/
AP BA Note
Extended Mode Register SetH XLLLL OP code 1,2
Mode Register Set H XLLLL OP code 1,2
Device Deselect HX
HXXX X1
No Operation L H H H
Bank Active H X L L H H RA V 1
Read HXLHLHCA
LV1
Read with Autoprecharge H1,3
Write HXLHLLCA
LV1
Write with Au to precharge H1,4
Precharge All Banks HXLLHLX
HX1,5
Precharge selected Bank LV1
Read Burst Stop H X L H H L X 1
Auto Refresh H HLLLH X 1
Self Refresh
EntryH LLLLH
X
1
Exit L H HXXX 1
LHHH
Precharge Power
Down Mode
Entry H L HXXX
X
1
LHHH 1
Exit L H HXXX 1
LHHH 1
Active Power
Down Mode Entry H L HXXX
X
1
LVVV 1
Exit L H X 1
Note :
1. DM states are Don’t Care. Refer to below Write Mask Truth Table.
2. OP Code(Operand Code) consists of A0~A13 and BA0~BA1 used for Mode Register setting duing Extended MRS or MRS.
Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP
period from Prechagre command.
3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL /2+ t RP).
4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented
to activated bank until CK(n+BL/2+1+ tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time
(tWR) is needed to guarantee that the last data has been completely written.
5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be
precharged.
( H=Logic High Level, L=Logic Low Level, X=Do n’t Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation )
Rev. 0.1 / Nov. 2003 9
HY5DU1G422(L)T
HY5DU1G822(L)T
WRITE MASK TRUTH TABLE
Function CKEn-1 CKEn /CS, /RAS,
/CAS, /WE DM ADDR A10/
AP BA Note
Data Write H X X L X 1
Data-In Mask H X X H X 1
Note :
1. Write Mask command masks burst write data with reference to DQS and it is not related with read data.
Rev. 0.1 / Nov. 2003 10
HY5DU1G422(L)T
HY5DU1G822(L)T
OPERATION COMMAND TRUTH TABLE-I
Current
State /CS /RAS /CAS /WE Address Command Action
IDLE
HXXX X DSEL NOP or power down3
LHHH X NOP NOP or power down3
LHHL X BST ILLEGAL4
L H L H BA, CA, AP READ/READAP ILLEGAL4
L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4
L L H H BA, RA ACT Row Activ ation
LLHLBA, AP PRE/PALL NOP
LLLH X AREF/SREF Auto Re fresh or Self Ref resh5
L L L L OPCODE MRS Mode Register Set
ROW
ACTIVE
HXXX X DSEL NOP
LHHH X NOP NOP
LHHL X BST ILLEGAL4
L H L H BA, CA, AP READ/READAP Begin read : optional AP6
L H L L BA, CA, AP WRITE/WRITEAP Begin write : optional AP6
LLHHBA, RA ACT ILLEGAL4
LLHLBA, AP PRE/PALL Precharge7
LLLH X AREF/SREF ILLEGAL11
LLLLOPCODE MRS ILLEGAL11
READ
H X X X X DSEL Continue burst t o end
L H H H X NOP Continue burst to end
L H H L X BST Terminate burst
L H L H BA, CA, AP READ/READAP Term burst, new read:optional AP8
L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL
LLHHBA, RA ACT ILLEGAL4
L L H L BA, AP PRE/PALL Term burst, precharge
LLLH X AREF/SREF ILLEGAL11
LLLLOPCODE MRS ILLEGAL11
WRITE
H X X X X DSEL Continue burst t o end
L H H H X NOP Continue burst to end
LHHL X BST ILLEGAL4
L H L H BA, CA, AP READ/READAP Term burst, new read:optional AP8
L H L L BA, CA, AP WRITE/WRITEAP Term burst, new write:optional AP
Rev. 0.1 / Nov. 2003 11
HY5DU1G422(L)T
HY5DU1G822(L)T
OPERATION COMMAND TRUTH TABLE-II
Current
State /CS /RAS /CAS /WE Address Command Action
WRITE
LLHHBA, RA ACT ILLEGAL4
L L H L BA, AP PRE/PALL Term burst, precharge
LLLH X AREF/SREF ILLEGAL11
LLLLOPCODE MRS ILLEGAL11
READ
WITH
AUTOPRE-
CHARGE
H X X X X DSEL Continue burst t o end
L H H H X NOP Continue burst to end
LHHL X BST ILLEGAL
L H L H BA, CA, AP READ/READAP ILLEGAL10
L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL10
LLHHBA, RA ACT ILLEGAL4,10
LLHLBA, AP PRE/PALL ILLEGAL4,10
LLLH X AREF/SREF ILLEGAL11
LLLLOPCODE MRS ILLEGAL11
WRITE
AUTOPRE-
CHARGE
H X X X X DSEL Continue burst t o end
L H H H X NOP Continue burst to end
LHHL X BST ILLEGAL
L H L H BA, CA, AP READ/READAP ILLEGAL10
L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL10
LLHHBA, RA ACT ILLEGAL4,10
LLHLBA, AP PRE/PALL ILLEGAL4,10
LLLH X AREF/SREF ILLEGAL11
LLLLOPCODE MRS ILLEGAL11
PRE-
CHARGE
H X X X X DSEL NOP-Enter IDLE after tRP
L H H H X NOP NOP-Enter IDLE after tRP
LHHL X BST ILLEGAL4
L H L H BA, CA, AP READ/READAP ILLEGAL4,10
L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4,10
LLHHBA, RA ACT ILLEGAL4,10
L L H L BA, AP PRE/PALL NOP-Enter IDLE after tRP
LLLH X AREF/SREF ILLEGAL11
LLLLOPCODE MRS ILLEGAL11
Rev. 0.1 / Nov. 2003 12
HY5DU1G422(L)T
HY5DU1G822(L)T
OPERATION COMMAND TRUTH TABLE-III
Current
State /CS /RAS /CAS /WE Address Command Action
ROW
ACTIVATING
H X X X X DSEL NOP - Enter ROW ACT after tRCD
L H H H X NOP NOP - Enter ROW ACT after tRCD
LHHL X BST ILLEGAL4
L H L H BA, CA, AP READ/READAP ILLEGAL4,10
L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4,10
LLHHBA, RA ACT ILLEGAL4,9,10
LLHLBA, AP PRE/PALL ILLEGAL4,10
LLLH X AREF/SREF ILLEGAL11
LLLLOPCODE MRS ILLEGAL11
WRITE
RECOVERING
H X X X X DSEL NOP - Enter ROW ACT after tWR
L H H H X NOP NOP - Enter ROW ACT after tWR
LHHL X BST ILLEGAL4
L H L H BA, CA, AP READ/READAP ILLEGAL
L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL
LLHHBA, RA ACT ILLEGAL4,10
LLHLBA, AP PRE/PALL ILLEGAL4,11
LLLH X AREF/SREF ILLEGAL11
LLLLOPCODE MRS ILLEGAL11
WRITE
RECOVERING
WITH
AUTOPRE-
CHARGE
H X X X X DSEL NOP - Enter precharge after tDPL
L H H H X NOP NOP - Enter precharge after tDPL
LHHL X BST ILLEGAL4
L H L H BA, CA, AP READ/READAP ILLEGAL4,8,10
L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL4,10
LLHHBA, RA ACT ILLEGAL4,10
LLHLBA, AP PRE/PALL ILLEGAL4,11
LLLH X AREF/SREF ILLEGAL11
LLLLOPCODE MRS ILLEGAL11
REFRESHING
H X X X X DSEL NOP - Enter IDLE after tRC
L H H H X NOP NOP - Enter IDLE after tRC
LHHL X BST ILLEGAL11
L H L H BA, CA, AP READ/READAP ILLEGAL11
Rev. 0.1 / Nov. 2003 13
HY5DU1G422(L)T
HY5DU1G822(L)T
OPERATION COMMAND TRUTH TABLE-IV
Note :
1. H - Logic High Level, L - Logi c Low Level, X - Don’t Care, V - Valid Data Input,
BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.
2. All entries assume that CKE was active(high level) during the preceding clock cycle.
3. If both banks are idle and CKE is inactive(low level), then in power down mode.
4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Ad dress(BA) depending on the state of
that bank.
5. If both banks are idle and CKE is inactive(low level), then self refresh mode.
6. Illegal if tRCD is not met.
7. Illegal if tRAS is not met.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Illegal if tRRD is not met.
10. Illegal for single bank, but legal for other banks in multi-bank devices.
11. Illegal for all banks.
Current
State /CS /RAS /CAS /WE Address Command Action
WRITE
L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL11
LLHHBA, RA ACT ILLEGAL11
LLHLBA, AP PRE/PALL ILLEGAL11
LLLH X AREF/SREF ILLEGAL11
LLLLOPCODE MRS ILLEGAL11
MODE
REGISTER
ACCESSING
H X X X X DSEL NOP - Enter IDLE after tMRD
L H H H X N OP NOP - Enter IDLE after tMR D
LHHL X BST ILLEGAL11
L H L H BA, CA, AP READ/READAP ILLEGAL11
L H L L BA, CA, AP WRITE/WRITEAP ILLEGAL11
LLHHBA, RA ACT ILLEGAL11
LLHLBA, AP PRE/PALL ILLEGAL11
LLLH X AREF/SREF ILLEGAL11
LLLLOPCODE MRS ILLEGAL11
Rev. 0.1 / Nov. 2003 14
HY5DU1G422(L)T
HY5DU1G822(L)T
CKE FUNCTION TRUTH TABLE
Note :
When CKE=L, all DQ and DQS must be in Hi-Z state.
1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command.
2. All command can be stored after 2 clocks from low to high transition of CKE.
3. Illegal if CK is suspended or stopped during the power down mode.
4. Self refresh can be entered only from the all banks idle state.
5. Disabling CK may cause malfunction of any bank which is in active state.
Current
State CKEn-
1CKEn /CS /RAS /CAS /WE /ADD Action
SELF
REFRESH1
HXXXXXX INVALID
L H H X X X X Exit self refresh, enter idle afte r tSR E X
L H L H H H X Exit self refresh, enter idle aft er tSREX
LHLHHLX ILLEGAL
LHLHLXX ILLEGAL
LHLLXXX ILLEGAL
L LXXXXX NOP, continue self refresh
POWER
DOWN2
HXXXXXX INVALID
L H H X X X X Exit power down, enter idle
L H L H H H X Exit power down, enter idle
LHLHHLX ILLEGAL
LHLHLXX ILLEGAL
LHLLXXX ILLEGAL
L L X X X X X NOP, continue power down mode
ALL BANKS
IDLE4
H H X X X X X See operation command truth table
HLLLLHX Enter self refresh
H L H X X X X Exit power down
H L L H H H X Exit power down
HLLHHLX ILLEGAL
HLLHLXX ILLEGAL
HLLLHXX ILLEGAL
HLLLLLX ILLEGAL
L LXXXXX NOP
ANY STATE
OTHER
THAN
ABOVE
H H X X X X X See operation command truth table
HLXXXXX ILLEGAL5
LHXXXXX INVALID
L LXXXXX INVALID
Rev. 0.1 / Nov. 2003 15
HY5DU1G422(L)T
HY5DU1G822(L)T
SIMPLIFIED STATE DIAGRAM
MRS SREF
SREX
PDEN
PDEX
ACT
AREF
PDEX
PDEN
BST
READWRITE
WRITE
WRITEAP
WRITEAP
READ
READAP READAP
PRE(PALL)
PRE(PALL)
PRE(PALL)
Command Input
Automatic Sequence
IDLE
AUTO
REFRESH
PRE-
CHARGE
POWER-UP
POWER APPLIED
MODE
REGISTER
SET
POWER
DOWN
WRITE
WITH
AUTOPRE-
CHARGE
POWER
DOWN
WRITE
READ
WITH
AUTOPRE-
CHARGE
BANK
ACTIVE
READ
SELF
REFRESH
Rev. 0.1 / Nov. 2003 16
HY5DU1G422(L)T
HY5DU1G822(L)T
POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those
specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF
(and to the system VTT). VTT mus t be applie d after VDDQ to a void dev ice latch-up , which m ay caus e permanent d am-
age to the device. VREF can be applied anytime after VDDQ, but is expected to be nominally coincident with VTT.
Except for CKE, inputs are not recognized as v alid until after VREF is applied. CKE is an SSTL_2 input, but will detect an
LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to
guarantee that the DQ and DQS outputs will be in the High- Z state, where they will remain until driven in normal oper-
ation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR
SDRAM requires a 200us delay prior to applying an executable command.
Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED
MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE
REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating
parameters. 200 clock cycles are required between the DLL reset and any command. During the 200 cycles of CK, for
DLL locking, executable commands are disallowed (a DESELECT or NOP command must be applied). After the 200
clock cycles, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command
for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without resetting the
DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at L VC-
MOS low state. (All the other input pins may be undefined.)
• VDD and VDDQ are driven from a single power converter output.
• VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation.
• VREF tracks VDDQ/2.
• A minimum resistance of 42 Ohms (22 ohm se ries r esistor + 22 ohm parallel resistor - 5% toler ance) limits the
input current from the VTT supply into any pin.
• If the above criteria cannot be met by the system design, then the following sequencing and voltage relation-
ship must be adhered to during power up.
2. Start clock and maintain stable clock for a minimum of 200usec.
3. After stable power and clock, apply NOP condition and take CKE high.
4. Issue Extended Mode Register Set (EMRS) to enable DLL.
5. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200
cycles of clock are required for locking DLL)
6. Issue Precharge commands for all banks of the device.
Voltage description Sequencing Voltage relationship to avoid latch-up
VDDQ After or with VDD < VDD + 0.3V
VTT After or with VDDQ < VDDQ + 0.3V
VREF After or with VDDQ < VDDQ + 0.3V
Rev. 0.1 / Nov. 2003 17
HY5DU1G422(L)T
HY5DU1G822(L)T
7. Issue 2 or more Auto Refresh commands.
8. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low
Power-Up Sequence
/CLK
CLK
VDD
DQS
DQ’s
MRSAREFPRENOPMRSEMRSPRENOP
CODE CODE CODE
CODE CODE CODE
CODE CODE CODE
VDDQ
VREF
CKE
CMD
BA0,BA1
A10
ADDR
DM
≈≈ ≈≈≈≈≈≈≈
≈≈ ≈≈≈ ≈≈≈≈
≈≈ ≈≈≈ ≈≈≈≈
≈≈≈≈≈ ≈≈≈≈
≈≈≈≈≈ ≈≈≈≈
tVTD
T=200usec tMRD 200 cy cles of CK * tRP tRFC
Power up
VDD and CK stable Precharge All EMRS Set M RS Set
Reset DLL
(with A8=H) Precharge All 2 or more
Auto Refre s h MRS Set
(with A8=L)
*200 cycles of CK are required (for DLL locking) before any executable comman d can be applied.
VTT
tRP
tIS tIH
Rev. 0.1 / Nov. 2003 18
HY5DU1G422(L)T
HY5DU1G822(L)T
MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length,
burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the
low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and
CKE must be high at least one cycle before the Mode Re gister Set Comm and can be issued. Two cycles are required to
write the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field is
determined, the information will be held until resetted by another MRS command.
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 RFU DR TM CAS Latency BT Burst Length
A2 A1 A0 Burst Length
Sequential Interleave
000ReservedReserved
001 2 2
010 4 4
011 8 8
100ReservedReserved
101ReservedReserved
110ReservedReserved
111ReservedReserved
A3 Burst Type
0Sequential
1Interleave
A6 A5 A4 CAS Latency
000 Reserved
001 Reserved
010 2
011 3
100 Reserved
101 Reserved
110 2.5
111 Reserved
A7 Test Mode
0Normal
1Test
A8 DLL Reset
0No
1Yes
BA0 MRS Type
0MRS
1EMRS
Rev. 0.1 / Nov. 2003 19
HY5DU1G422(L)T
HY5DU1G822(L)T
BURST DEFINITION
BURST LENGTH & TYPE
Read and write accesses to th e DD R SDRA M are bu rst orie nted, wi th the burst length being programmable. The burst
length determines the maximum number of column locations that can be accessed for a given Read or Write com-
mand. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2 -Ai when the burst length
is set to four and by A3 -Ai when the burst length is set to eight (where Ai is the most significant column address bit
for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location
within the block. The programmed burst length applies to both Read and Write bursts.
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in Burst Definitionon Table
Burst Length Starting Address (A2,A1,A0) Sequential Interleave
2XX0 0, 1 0, 1
XX1 1, 0 1, 0
4
X00 0, 1, 2, 3 0, 1, 2, 3
X01 1, 2, 3, 0 1, 0, 3, 2
X10 2, 3, 0, 1 2, 3, 0, 1
X11 3, 0, 1, 2 3, 2, 1, 0
8
000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4
100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3,0,1
111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
Rev. 0.1 / Nov. 2003 20
HY5DU1G422(L)T
HY5DU1G822(L)T
CAS LATENCY
The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the
availability of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.
If a Read comma nd is registered at clock ed ge n, and the latency is m clocks, the data is av aila ble nominally coinciden t
with clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
DLL RESET
The DLL must be enabled f or normal oper ation. DLL enable is requ ired during pow er up init ializat ion, an d upon ret urn-
ing to normal operation after having disabled the DLL fo r the purpose of debug or evaluation. The DLL is automatically
disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any
time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally
applied clock before an any command can be issued.
OUTPUT DRIVER IMPEDANCE CONTROL
The normal drive strength for all outputs is specified to be SSTL_2, Class II. Hynix also supports a half strength driver
option, intended for lighter load and/or point-to-point environments. Selection of the half strength driver option will
reduce the output drive strength by 50% of that of the full strength driver. I-V curves for both the full strength driver
and the half strength driver are included in this document.
Rev. 0.1 / Nov. 2003 21
HY5DU1G422(L)T
HY5DU1G822(L)T
EXTENDED MODE REGISTER SET (EMRS)
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional func-
tions include DLL enable/disable, output driver strength se lection(optional). These f unctions are contr olled via the bits
shown below. The Extended Mode R egister is pr ogrammed via the M ode Register Set comm and ( BA0=1 an d BA1=0)
and will retain the stored information until it is programmed again or the device loses power.
The Extended Mode Register mus t be loaded when all banks are idle and no bursts are in progress, and the contro ller
must wait the specified time before initiating any subsequent operation. Violating either of these requirements will
result in unspecified operation.
ㅈ
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 RFU* 0** DS DLL
A0 DLL enable
0Enable
1Diable
BA0 MRS Type
0MRS
1EMRS
A1 Output Driver
Impedance Control
0 Full Strength Driver
1 Half Strength Driver
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage
** This part do not support /QFC function, A2 must be programmed to Zero.
Rev. 0.1 / Nov. 2003 22
HY5DU1G422(L)T
HY5DU1G822(L)T
ABSOLUTE MAXIMUM RATINGS
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Note :
1. VDDQ must not exceed the level of VDD.
2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same.
Peak to peak noise on VREF may not exceed +/- 2% of the DC value.
DC CHARACTERISTICS I (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Note : 1. VIN = 0 to 2.7V, All other pins are not tested under VIN =0V. 2. DOUT is disabled, VOUT=0 to 2.7V
Parameter Symbol Rating Unit
Ambient Temperature TA0 ~ 70 oC
Storage Temperature TSTG - 55 ~ 125 oC
Voltage on Any Pin relative to VSS VIN, VOUT -0.5 ~ 3.6 V
Voltage on VDD relative to VSS VDD -0.5 ~ 3.6 V
Voltage on VDDQ relative to VSS VDDQ -0.5 ~ 3.6 V
Output Short Circuit Current IOS 50 mA
Power Dissipation PD1.5 W
Soldering Temperature Þ Time TSOLDER 260 Þ 10 oC Þ sec
Parameter Symbol Min Typ. Max Unit Note
Power Supply Voltage VDD 2.3 2.5 2.7 V
Power Supply Voltage VDDQ 2.3 2.5 2.7 V 1
Input High Vo ltage VIH VREF + 0.15 - VDDQ + 0.3 V
Input Low Voltage VIL -0.3 - VREF - 0.15 V 2
Termination Voltage VTT VREF - 0.04 VREF VREF + 0.04 V
Refer en ce Voltage VREF 0.49*VDDQ 0.5*VDDQ 0.51*VDDQ V 3
Parameter Symbol Min. Max Unit Note
Input Leakage Current ILI -2 2 uA 1
Output Leakage Current ILO -5 5 uA 2
Output High Voltage VOH VTT + 0.76 - V IOH = -15.2mA
Output Low Voltage VOL -VTT - 0.76 V IOL = +15.2mA
Rev. 0.1 / Nov. 2003 23
HY5DU1G422(L)T
HY5DU1G822(L)T
DC CHARACTERISTICS II (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
256Mx4
Parameter Symbol Test Condition Speed Unit Note
-J -M -K -H -L
Operating Current IDD0
One bank; Active - Precharge ; tRC=tRC(min);
tCK=tCK(min) ; DQ ,DM and DQS inputs changing twice
per clock cycle; address and control inputs changing
once per clock cycle
TBD TBD TBD TBD TBD mA
Operating Current IDD1
One bank; Activ e - Read - Precharge;
Burst Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per clock
cycle
TBD TBD TBD TBD TBD mA
Precharge Power
Down Standby
Current IDD2P All banks idle ; Power down mode; CKE=Low,
tCK=tCK(min) TBD TBD TBD TBD TBD mA
Idle Standby
Current IDD2N Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and DM TBD TBD TBD TBD TBD mA
Idle Standby
Current IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing once
per clock cycle.
VIN=VREF for DQ, DQS and DM
TBD TBD TBD TBD TBD mA
Idle Quiet Standby
Current IDD2Q /CS>=Vih(min); All banks idle; CKE>=Vih(min);
Addresses and othe r control inputs st able, Vin=Vref f or
DQ, DQS and DM TBD TBD TBD TBD TBD mA
Active Power
Down
Standby Current IDD3P One bank active; Power down mode; CKE=Low,
tCK=tCK(min) TBD TBD TBD TBD TBD mA
Active Standby
Current IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing once
per clock cycle
TBD TBD TBD TBD TBD mA
Operating Current IDD4R Bu rst = 2; Reads; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min ); IOUT=0mA TBD TBD TBD TBD TBD
mA
Operating Current IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
TBD TBD TBD TBD TBD
Auto Refresh
Current IDD5 tRC=tRFC(min) - 8*tCK f or DDR200 at 100Mhz, 10*tCK
for DDR266A & DDR266B at 133Mhz; distributed
refresh TBD TBD TBD TBD TBD
Self Refresh
Current IDD6 CKE =< 0.2V; External clock on;
tCK=tCK(min) Normal TBD TBD TBD TBD TBD mA
Low Power TBD TBD TBD TBD TBD mA
Operating Current
- Fou r Bank
Operation IDD7 Four bank interleaving with BL=4, Refer to the
following page for detailed test condition TBD TBD TBD TBD TBD mA
Random Read
Current IDD7A
4banks active read with activate every 20ns, AP(Auto
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0
mA, 100% DQ, DM and DQS inputs changing twice per
clock cycle; 100% addresses changing once per clock
cycle
TBD TBD TBD TBD TBD mA
Rev. 0.1 / Nov. 2003 24
HY5DU1G422(L)T
HY5DU1G822(L)T
DC CHARACTERISTICS II (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
128Mx8
Parameter Symbol Test Condition Speed Unit Note
-J -M -K -H -L
Operating Current IDD0
One bank; Active - Precharge ; tRC=tRC(min);
tCK=tCK(min) ; DQ,DM and DQS inputs changing
twice per clock cycle; address and control inputs
changing once per clock cycle
TBDTBDTBDTBDTBD mA
Operating Current IDD1
One bank; Active - Read - Precharge;
Burst Length=2; tRC=tRC(min); tCK=tCK(min);
address and control inputs changing once per clock
cycle
TBDTBDTBDTBDTBD mA
Precharge Power
Down Standby
Current IDD2P All banks idle ; Power down mode; CKE= Low,
tCK=tCK(min) TBDTBDTBDTBDTBD mA
Idle Standby
Current IDD2N Vin>=Vih(min) or Vin=<Vil(max) for DQ, DQS and
DM TBDTBDTBDTBDTBD mA
Idle Standby
Current IDD2F
/CS=High, All banks idle; tCK=tCK(min);
CKE=High; address and control inputs changing onc e
per clock cycle.
VIN=VREF for DQ, DQS and DM
TBDTBDTBDTBDTBD mA
Idle Quiet Standby
Current IDD2Q /CS>=Vih(min); All banks idle; CKE>=Vih(min);
Addresses and other control inputs stable, Vin=Vref
for DQ, DQS and DM TBDTBDTBDTBDTBD mA
Active Power
Down
Standby Current IDD3P One bank active; Power down mode; CKE=Low,
tCK=tCK(min) TBDTBDTBDTBDTBD mA
Active Standby
Current IDD3N
/CS=HIGH; CKE=HIGH; One bank; Active-Precharge;
tRC=tRAS(max); tCK=tCK(min);
DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing
once per clock cycle
TBDTBDTBDTBDTBD mA
Operating Current IDD4R Burst=2; Reads; Continuous burs t; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); IOUT=0mA TBDTBDTBDTBDTBD
mA
Operating Current IDD4W
Burst=2; Writes; Continuous burst; One bank active;
Address and control inputs changing once per clock
cycle; tCK=tCK(min); DQ, DM and DQS inputs
changing twice per clock cycle
TBDTBDTBDTBDTBD
Auto Refresh
Current IDD5 tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz;
distributed refresh TBDTBDTBDTBDTBD
Self Refresh
Current IDD6 CKE =< 0.2V; External clock on;
tCK=tCK(min) Normal TBDTBDTBDTBDTBD mA
Low Power TBD TBD TBD TBD TBD mA
Operating Current
- Fou r Bank
Operation IDD7 Four bank interleaving with BL=4, Refer to the
following page for detailed test condition TBDTBDTBDTBDTBD mA
Random Read
Current IDD7A
4banks active read with activ ate ev er y 20n s, AP(Au to
Precharge) read every 20ns, BL=4, tRCD=3, IOUT=0
mA, 100% DQ, DM and DQS inputs changing twice
per clock cycle; 100% addresses changing once per
clock cycle
TBDTBDTBDTBDTBD mA
Rev. 0.1 / Nov. 2003 25
HY5DU1G422(L)T
HY5DU1G822(L)T
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7
IDD1 : Operating current: One bank operation
1. Typical Case : VDD = 2.5V, T=25 oC
2. Worst Case : VDD = 2.7V, T= 0 oC
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lout = 0mA
4. Timing patterns
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
- DDR333(166Mhz, CL=2.5) : tCK = 6ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 10*tCK, tRAS = 7*tCK
Read : A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7 : Operating current: Four bank operation
1. Typical Case : VDD = 2.5V, T=25 oC
2. Worst Case : VDD = 2.7V, T= 0 oC
3. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not
changing. lout = 0mA
4. Timing patterns
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecha rg e
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
- DDR333(166Mhz, CL=2.5) : tCK = 6ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing
50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
Rev. 0.1 / Nov. 2003 26
HY5DU1G422(L)T
HY5DU1G822(L)T
AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter Symbol Min Max Unit Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.31 V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.31 V
Input Differential Voltage, CK and /CK inputs VID(AC) 0.7 VDDQ + 0.6 V 1
Input Crossin g Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2
Parameter Value Unit
Refer en ce Voltage VDDQ x 0.5 V
Termination Voltage VDDQ x 0.5 V
AC Input High Level Voltage (VIH, min) VREF + 0.31 V
AC Input Low Level Voltage (VIL, max) VREF - 0.31 V
Input Timing Measurement Reference Level Voltage VREF V
Output Timing Meas urement Refere nce Level Voltage VTT V
Input Signal maximum peak swing 1.5 V
Input minimum Signal Slew Rate 1 V/ns
Termination Resistor (RT)50W
Series Resistor (RS)25W
Output Load Capacitance for Access Time Measurement (CL)30 pF
Rev. 0.1 / Nov. 2003 27
HY5DU1G422(L)T
HY5DU1G822(L)T
AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter Symbol DDR333 DDR266 UNIT NOTE
Min Max Min Max
Row Cycle Time tRC 60 - 60 - ns
Auto Refresh Row Cycle Time tRFC 120 -120 -ns
Row Active Time tRAS 42 70K 45 120K ns
Active to Read with Aut o Precharge
Delay tRAP tRCD or
tRPmin -tRCD or
tRPmin -ns16
Row Address to Column Address Delay tRCD 18 - 15 - ns
Row Active to Row Active Delay tRRD 12 - 15 - ns
Column Address to Column Address
Delay tCCD 1 - 1 - CK
Row Precharge Time tRP 18 - 15 - ns
Write Recovery T ime tWR 15 - 15 - ns
Internal Write to Read Command Delay tWTR 1 - 1 - CK
Auto Precharge Write Recovery +
Precharge Time tDAL (tWR/tCK)
+
(tRP/tCK) -(tWR/tCK)
+
(tRP/tCK) -CK15
System Clock Cycle
Time CL = 2.5 tCK 6127.512ns
CL = 2 7.5 12 7.5 12 ns
Clock High Level Width tCH 0.45 0.55 0.45 0.55 CK
Clock Low Level Width tCL 0.45 0.55 0.45 0.55 CK
Data-Out edge to Clock edge S kew tAC -0.7 0.7 -0.75 0.75 ns
DQS-Out edge to Clock edge Skew tDQSCK -0.6 0.6 -0.75 0.75 ns
DQS-Out edge to Data-Out edge Skew tDQSQ - 0.45 - 0.5 ns
Data-Out hold time from DQS tQH tHP
-tQHS -tHP
-tQHS -ns1,10
Clock Half Period tHP min
(tCL,tCH) -min
(tCL,tCH) -ns1,9
Data Hold Skew Factor tQHS - 0.55 - 0.75 ns 10
Valid Data Output Window tDV tQH-tDQSQ tQH-tDQSQ ns
Data-out high-impedance window from
CK,/CK tHZ -0.7 0.7 -0.75 0.75 ns 17
Data-out low - impedance window from
CK, /CK tLZ -0.7 0.7 -0.75 0.75 ns
Input Setup T im e (fast slew rate) tIS 0.75 - 0.9 - ns 2,3,5,6
Input Hold Time (fast slew rate) tIH 0.75 - 0.9 - ns
Rev. 0.1 / Nov. 2003 28
HY5DU1G422(L)T
HY5DU1G822(L)T
-Continue-
Parameter Symbol DDR333 DDR266 UNIT NOTE
Min Max Min Max
Input Setup Time (slow slew rate) tIS 0.8 - 1.0 - ns 2,4,5,6
Input Hold Time (slow slew rate) t IH 0.8 - 1.0 - ns
Input Pulse Width tIPW 2.2 - 2.2 - ns 6
Write DQS High Level Width tDQSH 0.35 - 0.35 - CK
Write DQS Low Level Width tDQSL 0.35 - 0.35 - CK
Clock to First Rising edge of DQS-In tDQSS 0.75 1.25 0.72 1.28 CK
DQS falling edge to CK setup time tDSS 0.2 0.2 CK
DQS fallin g edge hold time from CK tDSH 0.2 0.2 CK
Data-In Setup Time to DQS-In
(DQ & DM) tDS 0.45 - 0.5 - ns 6,7,11,
12,13
Data-in Hold Time to DQS-In
(DQ & DM) tDH 0.45 - 0.5 - ns
DQ & DM Input Pulse Width tDIPW 1.75 - 1.75 - ns
Read DQS Pre amb le Time tRPRE 0.9 1.1 0.9 1.1 CK
Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 CK
Write DQS Preamble Setup Time tWPRES 0-0-CK
Write DQS Preamble Hold Time tWPREH 0.25 - 0.25 - CK
Write DQS Postamble Time tWPST 0.4 0.6 0.4 0.6 CK
Mode Register Set Delay tMRD 2-2-CK
Exit Self Refresh to Any Execute
Command tXSC 200 - 200 - CK 8
Average Periodic Refresh Interval tREFI -7.8-7.8us
Rev. 0.1 / Nov. 2003 29
HY5DU1G422(L)T
HY5DU1G822(L)T
AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter Symbol DDR266A DDR266B DDR200 UNIT NOTE
Min Max Min Max Min Max
Row Cycle Time tRC65-65-70-ns
Auto Refresh Row Cycle Time tRFC 120 -120 -120 -ns
Row Active Time tRAS 45 120K 45 120K 50 120K n s
Active to Read with Auto
Precharge Delay tRAP tRCD or
tRPmin -tRCD or
tRPmin -tRCD or
tRPmin -ns16
Row Addr ess to C olu mn
Address Delay tRCD 20 - 20 - 20 - ns
Row Active to Row Active
Delay tRRD 15 - 15 - 15 - ns
Column Address to Column
Address Delay tCCD1-1-1-CK
Row Precharge Time tRP 20 - 20 - 20 - ns
Write Recovery Time tWR15-15-15-ns
Internal Write to Read
Command Delay tWTR1-1-1-CK
Auto Precharge Write
Recovery + Precharge Time tDAL (tWR/tCK)
+
(tRP/tCK) -(tWR/tCK)
+
(tRP/tCK) -(tWR/tCK)
+
(tRP/tCK) -CK15
Syste m Clock
Cycle Time CL = 2.5 tCK 7.5 12 7.5 12 8.0 12 ns
CL = 2 7.5 12 10 12 10 12 ns
Clock High Level Width tCH 0.45 0.55 0.45 0.55 0.45 0.55 CK
Clock Low Level Width tCL 0.45 0.55 0.45 0.55 0.45 0.55 CK
Data-Out edge to Clock edge
Skew tAC -0.75 0.75 -0.75 0.75 -0.75 0.75 ns
DQS-Out edge to Clock edge
Skew tDQSCK -0.75 0.75 -0.75 0.75 -0.75 0.75 ns
DQS-Out ed ge to Data-Out
edge Skew tDQSQ - 0.5 - 0.5 - 0.6 ns
Data-Out hold time from DQS tQH tHP
-tQHS -tHP
-tQHS -tHP
-tQHS -ns1,10
Clock Half Period tHP min
(tCL,tCH) -min
(tCL,tCH) -min
(tCL,tCH) -ns1,9
Data Hold Skew Factor tQHS - 0.75 - 0.75 - 0.75 ns 10
Valid Data Output Window tDV tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ ns
Data-out high -i mpe dan ce
window from CK,/CK tHZ -0.75 0.75 -0.75 0.75 -0.8 0.8 ns 17
Data-out low - impedance
window from CK, /CK tLZ -0.75 0.75 -0.75 0.75 -0.8 0.8 ns 17
Rev. 0.1 / Nov. 2003 30
HY5DU1G422(L)T
HY5DU1G822(L)T
- Continue
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2. Data sampled at the ri sing edges of the clock : A0~A13, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3. For command/address input slew rate >=1.0V/ns
4. For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
Parameter Symbol DDR266A DDR266B DDR200 UNIT NOTE
Min Max Min Max Min Max
Input Setup Time
(fast slew rate) tIS 0.9 - 0.9 - 1.1 - ns 2,3,5,
6
Input Hold Time
(fast slew rate) tIH 0.9 - 0.9 - 1.1 - ns
Input Setup Time
(slow slew rate) tIS 1.0 - 1.0 - 1.1 - ns 2,4,5,
6
Input Hold Time
(slow slew rate) tIH 1.0 - 1.0 - 1.1 - ns
Input Pulse Width tIPW 2.2 - 2.2 - 2.5 - ns 6
Write DQS High Level Width tDQSH 0.35 - 0.35 - 0.35 - CK
Write DQS Low Level Width tDQSL 0.35 - 0.35 - 0.35 - CK
Clock to First Ris ing edge of
DQS-In tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 CK
DQSfalling edge to CK
setup time tDSS 0.2 0.2 0.2 CK
DQS falling edge hold time from C K tDSH 0.2 0.2 0.2 CK
Data-In Setup Time to DQS-
In (DQ & DM) tDS 0.5 - 0.5 - 0.6 - ns 6,7,
11,12,
13
Data-in Hold Time to DQS-In
(DQ & DM) tDH 0.5 - 0.5 - 0.6 - ns
DQ & DM Input Pulse Width tDIPW 1.75 - 1.75 - 2 - ns
Read DQS Pre amb le Time tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 CK
Read DQS Postamble Time tRPST 0.4 0.6 0.4 0.6 0.4 0.6 CK
Write DQS Preamble Setup Time tWPRES 0-0-0-CK
Write DQS Preamble Hold Time tWPREH 0.25 - 0.25 - 0.25 - CK
Write DQS Postamble Time tWPST 0.4 0.6 0.4 0.6 0.4 0.6 CK
Mode Register Set Delay tMRD 2-2-2-CK
Exit Self Refr es h to An y
Execute Command tXSC 200 - 200 - 200 - CK 8
Average Periodic Refresh
Interval tREFI -7.8-7.8-7.8us
Input Setup / Hold Slew-rate Delta tIS Delta tIH
V/ns ps ps
0.5 0 0
0.4 +50 0
0.3 +100 0
Rev. 0.1 / Nov. 2003 31
HY5DU1G422(L)T
HY5DU1G822(L)T
5. CK, /CK slew rates are >=1.0V/ns
6. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed
by design or tester correlation.
7. Data latched at both rising and falling edges of Data Strobes : DQS, DM.
8. Minimum of 2 0 0 cycles of stable input clocks after Self Refresh Exit com mand, where CKE is held high, is required to
complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
9. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the devic e
(i.e. this value can be greater than the minimum specification limits for tCL and tCH).
10. tHP = minimum half clock period for any given cycle and is defined by cl ock high or clock low (tCH, tCL).
tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern
effects and p-channel to n-channel variation of the outp ut drivers.
11 .This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is
flat below VREF +/-310mV for a duration of up to 2ns.
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and
DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example,
if slew rate 1 = 0.5V/ns and Slew Rate2 = 0.4V/n then the Delta Inverse Slew Rate = -0.5ns/V.
14. DQS, DM and DQ input slew rate is specified to prevent doub le clocking of da ta a n d preserve setup and ho ld times.
Signal transitions through the DC region must be monotonic.
15. tDAL = 2 clocks + (tRP / tCK ). For each of the terms above, if not already an integer, round to the next highest integer.
tCK is equal to the actual system clock cycle time.
Example: For DDR266B at CL=2.5 and tCK = 7.5 ns,
tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67)
Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clocks
16. For the parts which do not has internal RAS loc kout circuit, Active to Read with Auto precharge delay
should be tRAS - BL/2 x tCK.
Input Setup / Hold Slew-rate Delta tDS Delta tDH
V/ns ps ps
0.5 0 0
0.4 +75 +75
0.3 +150 +150
I/O Input Level Delta tDS Delta tDH
mV ps ps
+280 +50 +50
(1/SlewRate1)-(1/SlewRate2) Delta tDS Delta tDH
ns/V ps ps
000
+/-0.25 +50 +50
+/- 0. 5 +100 +100
Rev. 0.1 / Nov. 2003 32
HY5DU1G422(L)T
HY5DU1G822(L)T
CAPACITANCE (TA=25oC, f=100MHz )
Note :
1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V
2. Pins not under test are tied to GND.
3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
Parameter Pin Symbol Min Max Unit
Input Clock Capacitance CK, /CK CI1 2.0 3.0 pF
Delta Input Clock Capacitance CK, /CK Delta CI1 -0.25pF
Input Capacita n ce All other input-on ly pins CI1 2.0 3.0 pF
Delta Input Capacit ance All other input-only pins Delta CI2 -0.5pF
Input / Output Capacitanc DQ, DQS, DM CIO 4.0 5.0 pF
Delta Input / Output Capa citance DQ, DQS, DM Delta CIO -0.5pF
VREF
VTT
RT=50Ω
Zo=50Ω
CL=30pF
Output
Rev. 0.1 / Nov. 2003 33
HY5DU1G422(L)T
HY5DU1G822(L)T
PACKAGE INFORMATION
400mil 66pin Thin Small Outline Package
10.26 (0.404)
10.05 (0.396)
11.94 (0.470)
11.79 (0.462)
22.33 (0.879)
22.12 (0.871)
1.194 (0.0470)
0.991 (0.0390)
0.65 (0.0256) BSC 0.35 (0.0138)
0.25 (0.0098)
0.15 (0.0059)
0.05 (0.0020)
BASE PLANE
SEATING PLANE
0.597 (0.0235)
0.406 (0.0160) 0.210 (0.0083)
0.120 (0.0047)
0 ~ 5 Deg.
U nit : mm (Inch )
