CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Features Functional Description Select one of two differential (LVPECL, LVDS, HCSL, or CML) input pairs to distribute to four LVDS output pairs 30-ps maximum output-to-output skew 480-ps maximum propagation delay 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset) Up to 1.5-GHz operation Output enable and synchronous clock enable functions 20-pin TSSOP The CY2DL1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 differential LVDS fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DL1504 can select between two separate differential (LVPECL, LVDS, HCSL, or CML) input clock pairs using the IN_SEL pin. The synchronous clock enable function ensures glitch-free output transitions during enable and disable periods. The output enable function allows the outputs to be asynchronously driven to a high-impedance state. The device has a fully differential internal architecture that is optimized to achieve low-additive jitter and low-skew at operating frequencies of up to 1.5 GHz. 2.5-V or 3.3-V operating voltage[1] Commercial and industrial operating temperature range Logic Block Diagram VDD VSS Q0 Q0# IN0 IN0# Q1 Q1# IN1 IN1# Q2 Q2# IN_SEL Q3 Q3# RP VDD Q RP CLK_EN D VDD RP OE Note 1. Input AC-coupling capacitors are required for voltage-translation applications. Cypress Semiconductor Corporation Document Number: 001-56312 Rev. *H * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised October 5, 2011 CY2DL1504 Contents Pinouts .............................................................................. 3 Absolute Maximum Ratings ............................................ 4 Operating Conditions....................................................... 4 DC Electrical Specifications ............................................ 5 AC Electrical Specifications ............................................ 6 Ordering Information........................................................ 9 Ordering Code Definition............................................. 9 Package Diagram............................................................ 10 Acronyms ........................................................................ 11 Document Number: 001-56312 Rev. *H Document Conventions ................................................. Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 11 12 14 14 14 14 Page 2 of 14 CY2DL1504 Pinouts Figure 1. Pin Diagram - CY2DL1504 20-Pin TSSOP Package 1 20 Q0 2 19 Q0# IN_SEL 3 18 VDD IN0 4 17 Q1 IN0# 5 16 Q1# IN1 6 15 Q2 IN1# 14 13 Q2# OE 7 8 VSS 9 12 Q3 VDD 10 11 Q3# CY2DL1504 VSS CLK_EN VSS Table 1. Pin Definitions Pin No. Pin Name Pin Type Description 1,9,13 VSS Power Ground 2 CLK_EN Input Synchronous clock enable. LVCMOS/LVTTL; When CLK_EN = Low, Q(0:3) outputs are held low and Q(0:3)# outputs are held high 3 IN_SEL Input Input clock select pin. LVCMOS/LVTTL; When IN_SEL = Low, the IN0/IN0# differential input pair is active When IN_SEL = High, the IN1/IN1# differential input pair is active 4 IN0 Input Differential (LVPECL, HCSL, LVDS, or CML) input clock. Active when IN_SEL = Low 5 IN0# Input Differential (LVPECL, HCSL, LVDS, or CML) complementary input clock. Active when IN_SEL = Low 6 IN1 Input Differential (LVPECL, HCSL, LVDS, or CML) input clock. Active when IN_SEL = High 7 IN1# Input Differential (LVPECL, HCSL, LVDS, or CML) complementary input clock. Active when IN_SEL = High 8 OE Input Output enable. LVCMOS/LVTTL; When OE = Low, Q(0:3) and Q(0:3)# outputs are disabled (see IOZ) 10,18 VDD Power Power supply 11,14,16,19 Q(0:3)# Output LVDS complementary output clocks 12,15,17,20 Q(0:3) Output LVDS output clocks Document Number: 001-56312 Rev. *H Page 3 of 14 CY2DL1504 Absolute Maximum Ratings Min Max Unit VDD Parameter Supply voltage Description Nonfunctional Condition -0.5 4.6 V VIN[2] Input voltage, relative to VSS Nonfunctional -0.5 Lesser of 4.0 or VDD + 0.4 V VOUT[2] DC output or I/O voltage, relative to VSS Nonfunctional -0.5 Lesser of 4.0 or VDD + 0.4 V TS Storage temperature Nonfunctional -55 150 C ESDHBM Electrostatic discharge (ESD) protection (Human body model) JEDEC STD 22-A114-B 2000 - V LU Latch up UL-94 Flammability rating MSL Moisture sensitivity level Meets or exceeds JEDEC Spec JESD78B IC latch up test At 1/8 in. V-0 3 Operating Conditions Parameter VDD TA tPU Description Supply voltage Ambient operating temperature Power ramp time Condition Min Max Unit 2.5-V supply 2.375 2.625 V 3.3-V supply 3.135 3.465 V Commercial 0 70 C Industrial -40 85 C Power-up time for VDD to reach minimum specified voltage. (Power ramp must be monotonic) 0.05 500 ms Note 2. The voltage on any I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. Document Number: 001-56312 Rev. *H Page 4 of 14 CY2DL1504 DC Electrical Specifications (VDD = 3.3 V 5% or 2.5 V 5%; TA = 0 C to 70 C (Commercial) or -40 C to 85 C (Industrial)) Parameter Description Condition Min Max Unit All LVDS outputs terminated with a load of 100 [3, 4] - 61 mA IDD Operating supply current VIH1 Input high voltage, differential input clocks, IN0, IN0#, IN1, and IN1# - VDD + 0.3 V VIL1 Input low voltage, differential input clocks, IN0, IN0#, IN1, and IN1# -0.3 - V VIH2 Input high voltage, CLK_EN, IN_SEL, and OE VDD = 3.3 V 2.0 VDD + 0.3 V VIL2 Input low voltage, CLK_EN, IN_SEL, and OE VDD = 3.3 V -0.3 0.8 V VIH3 Input high voltage, CLK_EN, IN_SEL, and OE VDD = 2.5 V 1.7 VDD + 0.3 V VIL3 Input low voltage, CLK_EN, IN_SEL, and OE VDD = 2.5 V -0.3 0.7 V VID_LVDS[5] LVDS input differential amplitude See Figure 3 on page 7 0.4 0.8 V VID_LVPECL[5] LVPECL/CML/HCSL input differential See Figure 3 on page 7 amplitude 0.4 1.0 V VICM Input common mode voltage 0.2 VDD - 0.2 V - 150 A -150 - A 250 470 mV 1.125 1.375 V - 50 mV -15 15 A See Figure 3 on page 7 VDD[6] VSS[6] IIH Input high current, All inputs Input = IIL Input low current, All inputs Input = VPP LVDS differential output voltage peak VDD = 3.3 V or 2.5 V, to Peak, Single-ended RTERM = 100 between Q and Q# pairs[3, 7] LVDS differential output common VDD = 3.3 V or 2.5 V, mode voltage RTERM = 100 between Q and Q# pairs[3, 7] VOCM VOCM Change in VOCM between complementary output states VDD = 3.3 V or 2.5 V, RTERM = 100 between Q and Q# pairs[3, 7] IOZ Output leakage current OE = VSS, VOUT = 0.75V - 1.75V RP Internal pull-up/pull-down resistance, CLK_EN has pull-up only LVCMOS logic inputs IN_SEL has pull-down only OE has pull-up only 60 165 k CIN Input capacitance - 3 pF Measured at 10 MHz; per pin Notes 3. Refer to Figure 2 on page 7. 4. IDD includes current that is dissipated externally in the output termination resistors. 5. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV. 6. Positive current flows into the input pin, negative current flows out of the input pin. 7. Refer to Figure 4 on page 7. Document Number: 001-56312 Rev. *H Page 5 of 14 CY2DL1504 AC Electrical Specifications (VDD = 3.3 V 5% or 2.5 V 5%; TA = 0 C to 70 C (Commercial) or -40 C to 85 C (Industrial)) Parameter FIN FOUT tPD[8] tODC[9] Description Input frequency Output frequency Propagation delay input pair to output pair Output duty cycle tSK1[10] Output-to-output skew tSK1 D[10] Device-to-device output skew PNADD Additive RMS phase noise 156.25 MHz Input Rise/fall time < 150 ps (20% to 80%) VID > 400 mV tJIT[11] Additive RMS phase jitter (Random) tR, tF[12] Output rise/fall time, single-ended tSOD Time from clock edge to outputs disabled Time from clock edge to outputs enabled tSOE Condition FOUT = FIN Input rise/fall time < 1.5 ns (20% to 80%) Diff input at 50% duty cycle Frequency range up to 1 GHz Any output to any output, with same load conditions at DUT Any output to any output between two or more devices. Devices must have the same input and have the same output load. Offset = 1 kHz Offset = 10 kHz Offset = 100 kHz Offset = 1 MHz Offset = 10 MHz Offset = 20 MHz 156.25 MHz, 12 kHz to 20 MHz offset; input rise/fall time < 150 ps (20% to 80%), VID > 400 mV 50% duty cycle at input, 20% to 80% of full swing (VOL to VOH) Input rise/fall time < 1.5 ns (20% to 80%) Measured at 1 GHz. Synchronous clock enable (CLK_EN) switched low Synchronous clock enable (CLK_EN) switched high Min DC DC - Typ - - - Max 1.5 1.5 480 Unit GHz GHz ps 48 - 52 % - - 30 ps - - 150 ps - - - - - - - - - - - - - - -120 -135 -135 -150 -154 -155 0.11 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz ps - - 300 ps - - 700 ps - - 700 ps Notes 8. Refer to Figure 5 on page 7. 9. Refer to Figure 6 on page 7. 10. Refer to Figure 7 on page 8. 11. Refer to Figure 8 on page 8. 12. Refer to Figure 9 on page 8. Document Number: 001-56312 Rev. *H Page 6 of 14 CY2DL1504 Figure 2. LVDS Output Termination Z=50 BUF Q 100 Z=50 Q# Figure 3. Input Differential and Common Mode Voltages VA IN VICM = (VA + VB)/2 VID IN# VB Figure 4. Output Differential and Common Mode Voltages Q VA VOCM = (VA + VB)/2 VB VOCM = | VOCM1 - VOCM2 | VPP Q# Figure 5. Input to Any Output Pair Propagation Delay IN IN # QX Q X# t PD Figure 6. Output Duty Cycle QX QX# tPW tPERIOD t tODC = PW tPERIOD Document Number: 001-56312 Rev. *H Page 7 of 14 CY2DL1504 Figure 7. Output-to-output and Device-to-device Skew QX QX# Device 1 QY Q Y# tSK1 QZ Device 2 QZ# tSK1 D Figure 8. RMS Phase Jitter Phase noise Noise Power Phase noise mark Offset Frequency f2 f1 RMS Jitter Area Under the Masked Phase Noise Plot Figure 9. Output Rise/Fall Time QX 80% 80% VPP 20% 20% QX # tR tF Figure 10. Synchronous Clock Enable Timing CLK_EN IN IN# tSOD tPD tSOE QX QX# Document Number: 001-56312 Rev. *H Page 8 of 14 CY2DL1504 Ordering Information Part Number Type Production Flow Pb-free CY2DL1504ZXC 20-Pin TSSOP Commercial, 0 C to 70 C CY2DL1504ZXCT 20-Pin TSSOP Commercial, 0 C to 70 C CY2DL1504ZXI 20-Pin TSSOP Industrial, -40 C to 85 C CY2DL1504ZXIT 20-Pin TSSOP Industrial, -40 C to 85 C Ordering Code Definitions CY 2DL15 04 ZX C/I T Tape and reel Temperature range C = Commercial I = Industrial Pb-free TSSOP package Number of differential output pairs Base part number Company ID: CY = Cypress Document Number: 001-56312 Rev. *H Page 9 of 14 CY2DL1504 Package Diagram Figure 11. 20-Pin Thin Shrunk Small Outline Package (4.40 mm Body) ZZ20 51-85118 *D Document Number: 001-56312 Rev. *H Page 10 of 14 CY2DL1504 Acronyms Document Conventions Table 2. Acronyms Used in this Document Table 3. Units of Measure Acronym Description Symbol Unit of Measure ESD Electrostatic discharge C degree Celsius HBM Human body model dBc decibels relative to the carrier HCSL high-speed current steering logic GHz giga hertz JEDEC Joint electron devices engineering council Hz hertz LVDS Low-voltage differential signal k kilo ohm LVCMOS Low-voltage complementary metal oxide semiconductor A micro ampere F micro Farad LVPECL Low-voltage positive emitter-coupled logic LVTTL Low-voltage transistor-transistor logic OE Output enable RMS Root mean square TSSOP Thin shrunk small outline package Document Number: 001-56312 Rev. *H s micro second mA milliamperes ms millisecond mV millivolt MHz megahertz ns nano second ohm pF pico Farad ps pico second V volt W watt Page 11 of 14 CY2DL1504 Document History Page Document Title: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Document Number: 001-56312 Revision ECN Orig. of Change Submission Date 10/09/09 Description of Change ** 2782891 CXQ *A 2838613 CXQ 01/05/2010 Changed status from "ADVANCE" to "PRELIMINARY". Changed from 0.34 ps to 0.25 ps maximum additive jitter in "Features" on page 1 and in tJIT in the AC Electrical Specs table on page 5. Added tPU spec to the Operating Conditions table on page 3. Changed max IDD spec in the DC Electrical Specs table on page 4 from 60 mA to 61 mA. Removed VOD and VOD specs from the DC Electrical Specs table on page 4. Changed IOZ in the DC Electrical Specs table on page 4 from min of -10 uA to -15 uA and from max of 10 uA to 15 uA. Added RP spec in the DC Electrical Specs table on page 4. Min = 60 k, Max = 140 k. Added a measurement definition for CIN in the DC Electrical Specs table on page 4. Added VPP and VPP specs to the AC Electrical Specs table on page 5. VPP min = 250 mV and max = 470 mV; VPP max = 50 mV. Changed letter case and some names of all the timing parameters in the AC Electrical Specs table on page 5 to be consistent with EROS. Lowered all additive phase noise mask specs by 3 dB in the AC Electrical Specs table on page 5. Added condition to tR and tF specs in the AC Electrical specs table on page 5 that input rise/fall time must be less than 1.5 ns (20% to 80%). Changed letter case and some names of all the timing parameters in Figures 4, 5, 6, 7 and 9, to be consistent with EROS. Updated Figure 4 with definition for VPP and VPP. *B 3010332 CXQ 08/18/2010 Changed from 0.25 ps to 0.11 ps maximum additive jitter in "Features" on page 1 and in tJIT in the AC Electrical Specs table on page 5. Added "Functional equivalent to ICS8543i" to the "Features" section. Changed pin 13 in Figure 1 and Table 1 from VDD to VSS. Changed pin 8 description in Table 1 from "high impedance" to "disabled". Added note 6 to describe IIH and IIL specs. Removed reference to data distribution from "Functional Description". Changed RP for diff inputs from 100 k to 150 k in the Logic Block Diagram and from 60 k min / 140 k max to 90 k min / 210 k max in the DC Electrical Specs table. Split VID into separate specs in DC Electrical Specs table: 0.4 V min and 0.8 V max for LVDS, 0.4 V min and 1.0 V max for LVPECL. Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to -120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical Specs table. Added "Frequency range up to 1 GHz" condition to tODC spec. Changed tOD in the AC Electrical Specs table from 3 ns max to 5 ns max. Added Acronyms and Ordering Code Definition. *C 3090644 CXQ 11/19/2010 Document Number: 001-56312 Rev. *H New Datasheet. Changed VIN and VOUT specs from 4.0V to "lesser of 4.0 or VDD + 0.4" Removed 200mA min LU spec, replaced with "Meets or exceeds JEDEC Spec JESD78B IC Latchup Test" Added "VOUT = 0.75V - 1.75V" to IOZ comments. Moved VPP from AC spec table to DC spec table, removed VPP. Removed RP spec for differential input clock pins INX and INX#. Changed CIN condition to "Measured at 10 MHz". Changed PNADD specs for 10kHz, 10MHz, and 20MHz offsets. Added "Measured at 1 GHz" to tR, tF spec condition. Removed specs tS, tH, tOD, and tOE from AC spec table. Removed VPP reference from Figure 4. Page 12 of 14 CY2DL1504 Document Title: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Document Number: 001-56312 Revision ECN Orig. of Change Submission Date *D 3135189 CXQ 01/12/2011 *E 3090938 CXQ 02/25/11 *F 3208968 CXQ 03/29/2011 Changed RP max from 140 k to 165 k and updated RP in Logic Block Diagram. *G 3308039 CXQ 07/11/2011 Updated supported differential input clock types to include CML in Features, Functional Description, Pin Definitions, and DC specs table sections. *H 3395868 PURU 10/05/11 Updated supported differential input clock types to include HCSL in Features, Pinouts, and DC Electrical Specifications table. Changed Min value of VICM. Document Number: 001-56312 Rev. *H Description of Change Removed "Preliminary" status heading. Removed "Functional equivalent" bullet on page 1. Added "(see IOZ)" note to pin 8 description in Pin Definitions. Fixed typo and removed resistors from INX/INX# in Logic Block Diagram. Added Figure 10 to describe TSOE and TSOD. Post to external web. Page 13 of 14 CY2DL1504 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless (c) Cypress Semiconductor Corporation, 2009-2011. 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Document Number: 001-56312 Rev. *H Revised October 5, 2011 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 14 of 14