CY2DL1504ZXC - Cypress Semiconductor

CY2DL1504

1:4 Differential LVDS Fanout Buffer

with Selectable Clock Input

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-56312 Rev. *H Revised October 5, 2011

Features

■Select one of two differential (L VPECL, LVDS, HCSL, or CML)

input pairs to distribute to four LVDS output pairs

■30-ps maximum output-to-output skew

■480-ps maximum propagation delay

■0.11-ps maximum additive RMS phase jitter at 156.25 MHz

(12-kHz to 20-MHz offset)

■Up to 1.5-GHz operation

■Output enable and synchronous clock enable functions

■20-pin TSSOP

■2.5-V or 3.3-V operating voltage[1]

■Commercial and industrial operating temperature range

Functional Description

The CY2DL1504 is an ultra-low noise, low-skew,

low-propagation delay 1:4 differential LVDS fanout buffer

targeted to meet the requirements of high-speed clock

distribution applications. The CY2DL1504 can select between

two separate differential (LVPECL, LVDS, HCSL, or CML) input

clock pairs using the IN_SEL pin. The synchronous clock enable

function ensures glitch-free output transitions during enable and

disable periods. The output enable function allows the outputs to

be asynchronously driven to a high-impedance state. The device

has a fully differential internal architecture that is optimized to

achieve low-additive jitter and low-skew at operating frequencies

of up to 1.5 GHz.

Note

1. Input AC-coupling capacitors are required for voltage-translation applications.

Logic Block Diagram

Q0#

Q1#

Q2#

Q3#

IN0

IN0#

IN1

IN1#

IN_SEL

VDD

VSS

CLK_EN RP

VDD

OE RP

VDD

CY2DL1504

Document Number: 001-56312 Rev. *H Page 2 of 14

Contents

Pinouts .............................................................................. 3

Absolute Maximum Ratings ............................................ 4

Operating Conditi ons......................... .............. .............. .. 4

DC Electrical Specifications............................................ 5

AC Electrical Specifications............................................ 6

Ordering Information........................................................ 9

Ordering Code Definition............................................. 9

Package Diagram............................................................ 10

Acronyms.............................. .............. ... .............. ........... 11

Document Conventions.............. .............. ... .............. .. .. 11

Document History Page................ ... ... .............. ............. 12

Sales, Solutions, and Legal Information...................... 14

Worldwide Sales and Design Support....................... 14

Products.................................................................... 14

PSoC Solutions................... ... .. ............... .. ... ............. 14

CY2DL1504

Document Number: 001-56312 Rev. *H Page 3 of 14

Pinouts

Figure 1. Pin Diagram – CY2DL1504 20-Pin TSSOP Package

CY2DL1504

Q0#

VDD

Q1#

Q2#

VSS

Q3#

VSS

CLK_EN

IN_SEL

IN0

IN0#

IN1

IN1#

VSS

VDD

Table 1. Pin Definitions

Pin No. Pin Name Pin Type Description

1,9,13 VSS Power Ground

2 CLK_EN Input Synchronous clock enable. LVCMOS/LVTTL;

When CLK_EN = Low, Q(0:3) outputs are held low and Q(0:3)# outputs are

held high

3 IN_SEL Input Input clock select pin. LVCMOS/LVTTL;

When IN_SEL = Low, the IN0/IN0# differential input pair is active

When IN_SEL = High, the IN1/IN1# differential input pair is active

4 IN0 Input Dif ferential (LVPECL, HCSL, LVDS, or CML) input clock. Active when IN_SEL

= Low

5 IN0# Input Differential (LVPECL, HCSL, LVDS, or CML) complementary input clock. Active

when IN_SEL = Low

6 IN1 Input Dif ferential (LVPECL, HCSL, LVDS, or CML) input clock. Active when IN_SEL

= High

7 IN1# Input Differential (LVPECL, HCSL, LVDS, or CML) complementary input clock. Active

when IN_SEL = High

8 OE Input Output enable. LVCMOS/LVTTL;

When OE = Low, Q(0:3) and Q(0:3)# outputs are disabled (see IOZ)

10,18 VDD Power Power supply

11,14,16,19 Q(0:3)# Output LVDS complementary output clocks

12,15,17,20 Q(0:3) Output LVDS output clocks

CY2DL1504

Document Number: 001-56312 Rev. *H Page 4 of 14

Absolute Maximum Ratings

Parameter Description Condition Min Max Unit

VDD Supply voltage Nonfunctional –0.5 4.6 V

VIN[2] Input voltage, relative to VSS Nonfunctional –0.5 Lesser of 4.0

or VDD + 0.4 V

VOUT[2] DC output or I/O voltage, relative to VSS Nonfunctional –0.5 Lesser of 4.0

or VDD + 0.4 V

TSStorage temperature Nonfunctional –55 150 °C

ESDHBM Electrostatic discharge (ESD) protection

(Human body model) JEDEC STD 22-A114-B 2000 – V

LULatch up Meets or exceeds JEDEC Spec

JESD78B IC latch up test

UL–94 Flammability rating At 1/8 in. V–0

MSL Moisture sensitivity level 3

Operating Conditions

Parameter Description Condition Min Max Unit

VDD Supply voltage 2.5-V supply 2.375 2.625 V

3.3-V supply 3.135 3.465 V

TAAmbient operating temperature Commercial 0 70 °C

Industrial –40 85 °C

tPU Power ramp time Power-up time for VDD to

reach minimum specified

voltage.

(Power ramp must be

monotonic)

0.05 500 ms

Note

2. The voltage on any I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.

CY2DL1504

Document Number: 001-56312 Rev. *H Page 5 of 14

DC Electrical Specifications

(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))

Parameter Description Condition Min Max Unit

IDD Operating supply current All LVDS outputs terminated with a load of

100 Ω[3, 4] –61mA

VIH1 Input high voltage,

differential input clocks,

IN0, IN0#, IN1, and IN1#

–V

DD + 0.3 V

VIL1 Input low voltage,

differential input clocks,

IN0, IN0#, IN1, and IN1#

–0.3 – V

VIH2 Input high voltage,

CLK_EN, IN_SEL, and OE VDD = 3.3 V 2.0 VDD + 0.3 V

VIL2 Input low voltage,

CLK_EN, IN_SEL, and OE VDD = 3.3 V –0.3 0.8 V

VIH3 Input high voltage,

CLK_EN, IN_SEL, and OE VDD = 2.5 V 1.7 VDD + 0.3 V

VIL3 Input low voltage,

CLK_EN, IN_SEL, and OE VDD = 2.5 V –0.3 0.7 V

VID_LVDS[5] LVDS input differential amplitude See Figure 3 on page 7 0.4 0.8 V

VID_LVPECL[5] LVPECL/CML/HCSL input differential

amplitude See Figure 3 on page 7 0.4 1.0 V

VICM Input common mode voltage See Figure 3 on page 7 0.2 VDD – 0.2 V

IIH Input high current, All inputs Input = VDD[6] –150μA

IIL Input low current, All inputs Input = VSS[6] –150 – μA

VPP LVDS differential output voltage peak

to Peak, Single-ended VDD = 3.3 V or 2.5 V,

RTERM = 100 Ω between Q and Q# pairs[3, 7] 250 470 mV

VOCM LV DS differential output common

mode voltage VDD = 3.3 V or 2.5 V,

RTERM = 100 Ω between Q and Q# pairs[3, 7] 1.125 1.375 V

ΔVOCM Change in VOCM between

complementary output states VDD = 3.3 V or 2.5 V,

RTERM = 100 Ω between Q and Q# pairs[3, 7] –50mV

IOZ Output leakage current OE = VSS, VOUT = 0.75V – 1.75V –15 15 μA

RPInternal pull-up/pull-down resistance,

LVCMOS logic inputs CLK_EN has pull-up only

IN_SEL has pull-down only

OE has pull-up only

60 165 kΩ

CIN Input capacitance Measured at 10 MHz; per pin – 3 pF

Notes

3. Refer to Figure 2 on page 7.

4. IDD includes current that is dissipated externally in the output termination resistors.

5. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of great er than 200 mV.

6. Positive current flows into the input pin, negative cur rent flows out of the input pin.

7. Refer to Figure 4 on page 7.

CY2DL1504

Document Number: 001-56312 Rev. *H Page 6 of 14

AC Electrical Specifications

(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))

Parameter Description Condition Min Typ Max Unit

FIN Input frequency DC – 1.5 GHz

FOUT Output frequency FOUT = FIN DC – 1.5 GHz

tPD[8] Propagation delay input pair to output

pair Input rise/fall time < 1.5 ns

(20% to 80%) ––480ps

tODC[9] Output duty cycle Diff input at 50% duty cycle

Frequency range up to 1 GHz 48–52%

tSK1[10] Output-to-output skew Any output to any output, with

same load conditions at DUT ––30ps

tSK1 D[10] Device-to-device output skew Any output to any output

between two or more devices.

Devices must have the same

input and have the same output

load.

––150ps

PNADD Additive RMS phase noise

156.25 MHz Input

Rise/fall time < 150 ps (20% to 80%)

VID > 400 mV

Offset = 1 kHz – – –120 dBc/Hz

Offset = 10 kHz – – –135 dBc/Hz

Offset = 100 kHz – – –135 dBc/Hz

Offset = 1 MHz – – –150 dBc/Hz

Offset = 10 MHz – – –154 dBc/H z

Offset = 20 MHz – – –155 dBc/H z

tJIT[11] Additive RMS phase jitter (Random) 156.25 MHz, 12 kHz to 20 MHz

offset; input rise/fall time <

150 ps (20% to 80%), VID >

400 mV

––0.11ps

tR, tF[12] Output rise/fall time, single-ended 50% duty cycle at input,

20% to 80% of full swing

(VOL to VOH)

Input rise/fall time < 1.5 ns

(20% to 80%)

Measured at 1 GHz.

––300ps

tSOD Time from clock edge to outputs

disabled Synchronous clock enable

(CLK_EN) switched low ––700ps

tSOE Time from clock edge to outputs

enabled Synchronous clock enable

(CLK_EN) switched high ––700ps

Notes

8. Refer to Figure 5 on pag e 7.

9. Refer to Figure 6 on pag e 7.

10.Refer to Figure 7 on page 8.

11. Refer to Figure 8 on page 8.

12.Refer to Figure 9 on page 8.

CY2DL1504

Document Number: 001-56312 Rev. *H Page 7 of 14

Figure 2. LVDS Output Termination

Figure 3. Input Differential and Common Mode Voltages

Figure 4. Output Differential and Common Mode Voltages

Figure 5. Input to Any Output Pair Propagation Delay

Figure 6. Output Duty Cycle

Z=50

100

BUF

Z=50

IN VA

IN# VICM = (VA + VB)/2

VID

OCM

= (V

+ V

)/2

ΔV

OCM

= | V

OCM1

– V

OCM2

IN#

tPD

QX#

tPW

tODC =tPW

tPERIOD

QX#

CY2DL1504

Document Number: 001-56312 Rev. *H Page 8 of 14

Figure 7. Output-to-output and Device-to-device Skew

Figure 8. RMS Phase Jitter

Figure 9. Output Rise/Fall Time

Figure 10. Synchronous Clock Enable Timing

QX#

QY#

QZ#

QZtSK1

tSK1 D

Device 1

Device 2

Phas e noise

Phase noise mar k

Offset Freq uency

f1 f2

r ea Under the M as k ed Phase Noi s e Plot

Noise Powe

RMS Jitter

∝

20%

80%

tRtF

20%

80% VPP

QX#

tPD

CLK_EN

IN#

QX#

tSOD tSOE

CY2DL1504

Document Number: 001-56312 Rev. *H Page 9 of 14

Ordering Information

Ordering Code Definitions

Part Number Type Productio n Fl ow

Pb-free

CY2DL1504ZXC 20-Pin TSSOP Commercial, 0 °C to 70 °C

CY2DL1504ZXCT 20-Pin TSSOP Commercial, 0 °C to 70 °C

CY2DL1504ZXI 20-Pin TSSOP Industrial, –40 °C to 85 °C

CY2DL1504ZXIT 20-Pin TSSOP Industrial, –40 °C to 85 °C

Base part number

2DL15 04

Number of differential output pairs

Company ID: CY = Cypress

Pb-free TSSOP package

Temperature range

C = Commercial

I = Industrial

C/I T

Tape and reel

CY2DL1504

Document Number: 001-56312 Rev. *H Page 10 of 14

Package Diagram

Figure 11. 20-Pin Thin Shrunk Small Outline Package (4.40 mm Body) ZZ20

51-85118 *D

CY2DL1504

Document Number: 001-56312 Rev. *H Page 11 of 14

Acronyms Document Conventions

Table 2. Acronyms Used in this Document

Acronym Description

ESD Electrostatic discharge

HBM Human body model

HCSL high-speed current steering logic

JEDEC Joint electron devices engineering council

LVDS Low-voltage differential signal

LVCMOS Low-voltage complementary metal oxide

semiconductor

LVPECL Low-voltage positive emitter-coupled logic

LVTTL Low-voltage transistor-transistor logic

OE Output enable

RMS Root mean square

TSSOP Thin shrunk small outline package

Table 3. Units of Measure

Symbol Unit of Measure

°C degree Celsius

dBc decibels relative to the carrier

GHz giga hertz

Hz hertz

kΩkilo ohm

µA micro ampere

µF micro Farad

µs micro second

mA milliamperes

ms millisecond

mV millivolt

MHz megahertz

ns nano second

Ωohm

pF pico Farad

ps pico second

Vvolt

Wwatt

CY2DL1504

Document Number: 001-56312 Rev. *H Page 12 of 14

Document History Page

Document Title: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input

Document Number: 001-56312

Revision ECN Orig. of

Change Submission

Date Description of Change

** 2782891 CXQ 10/09/09 New Datasheet.

*A 2838613 CXQ 0 1/05/2010 Changed status from “ADVANCE” to “PRELIMINARY”.

Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page

1 and in tJIT in the AC Electrical Specs table on page 5.

Added tPU spec to the Operating Conditions table on page 3.

Changed max IDD spec in the DC Electrical S pecs table on p age 4 from 60 mA

to 61 mA.

Removed VOD and ΔVOD specs from the DC Electrical Specs table on page 4.

Changed IOZ in the DC Electrical Specs table on page 4 from min of -10 uA to

-15 uA and from max of 10 uA to 15 uA.

Added RP spec in the DC Electrical Specs table on page 4. Min = 60 kΩ, Max =

140 kΩ.

Added a measurement definition for CIN in the DC Electrical Specs table on page

Added VPP and ΔVPP specs to the AC Electrical S pecs ta ble on page 5. VPP min

= 250 mV and max = 470 mV; ΔVPP max = 50 mV.

Changed letter case and some name s of all the timing parameters in the AC

Electrical Specs table on page 5 to be consistent with EROS.

Lowered all additive phase noise mask specs by 3 dB in the AC Electrical Specs

table on page 5.

Added condition to tR and tF specs in the AC Electrica l specs table on page 5

that input rise/fall time must be less th an 1.5 ns (20% to 80%).

Changed letter case and some names of all the timing parameters in Figures 4,

5, 6, 7 and 9, to be consistent with EROS. Updated Figure 4 with definition for

VPP and ΔVPP.

*B 3010332 CXQ 08/18/2010 Changed from 0.25 ps to 0.11 ps maximum additive jitter in “Features” on page

1 and in tJIT in the AC Electrical Specs table on page 5.

Added “Functional equivalent to ICS8543i” to the “Features” section.

Changed pin 13 in Figure 1 and Table 1 from VDD to VSS.

Changed pin 8 description in Table 1 from “high impedance” to “disabled”.

Added note 6 to describe IIH and IIL specs.

Removed reference to data distribution from “Functional Description”.

Changed RP for diff inputs from 100 kΩ to 150 kΩ in the Logic Block Diagram

and from 60 kΩ min / 140 kΩ max to 90 kΩ min / 210 kΩ max in the DC Electrical

Specs table.

Split VID into separate specs in DC Electrical Spe c s table: 0.4 V min and 0.8 V

max for LVDS, 0.4 V min and 1.0 V max for LVPECL.

Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to

-120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical Specs

table.

Added “Frequency range up to 1 GHz” condition to tODC spec.

Changed tOD in the AC Electrical Specs table from 3 ns max to 5 ns max.

Added Acronyms and Ordering Code Definition.

*C 3090644 C XQ 11/19/2010 Changed VIN and VOUT specs from 4.0V to “lesser of 4.0 or VDD + 0.4”

Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec

JESD78B IC Latchup Test”

Added “VOUT = 0.75V - 1.75V” to IOZ comments.

Moved VPP from AC spec table to DC spec table, removed ΔVPP.

Removed RP spec for differential input clock pins INX and INX#.

Changed CIN condition to “Measured at 10 MHz”.

Changed PNADD specs for 10kHz, 10MHz, and 20MHz offsets.

Added “Measured at 1 GHz” to tR, tF spec condition.

Removed specs tS, tH, tOD, and tOE from AC spec table.

Removed ΔVPP reference from Figure 4.

CY2DL1504

Document Number: 001-56312 Rev. *H Page 13 of 14

*D 3135189 C XQ 01/12/2011 Removed “Preliminary” status heading.

Removed “Functional equivalent” bullet on page 1.

Added “(see IOZ)” note to pin 8 description in Pin Defini tions.

Fixed typo and removed resistors from INX/INX# in Logic Block Diagram.

Added Figure 10 to describe TSOE and TSOD.

*E 3090938 CXQ 02/25/11 Post to external web.

*F 3208968 CXQ 03/29/2011 Changed RP max from 140 kΩ to 165 kΩ and updated RP in Logic Block

Diagram.

*G 3308039 CXQ 07/11/2011 Updated supported differential input clock types to include CML in Features,

Functional Description, Pin Definitio ns, and DC specs table sections.

*H 3395868 PURU 10/0 5/11 Updated supported differential input clock types to include HCSL in Features,

Pinouts, and DC Electrical Specifications table.

Changed Min value of VICM.

Document Title: CY2DL1504 1:4 Differential LVDS Fanout Buffer with Selectable Clock Input

Document Number: 001-56312

Revision ECN Orig. of

Change Submission

Date Description of Change

Document Number: 001-56312 Rev. *H Revised October 5, 2011 Page 14 of 14

All products and company names mentioned in this document may be the trademarks of their respective holders.

CY2DL1504

© Cypress Semico nducto r Co rpor ation , 20 09-2 011. The informa tion con ta ined her ein is subje ct to chang e with out no tice. Cypress S emiconductor Corporation assumes no responsibility for the use of

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress pro duc ts are n ot war ran ted no r inte nd ed to be us ed fo r

medical, life supp or t, l if e savin g, cr it ical control or saf ety ap pl ic at io ns, unless pursuant to an express writte n ag re em en t w it h Cy press. Fu rth er mor e, Cyp ress doe s not author iz e its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress p roducts in life -support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (United States and foreig n),

United S t ates copyright laws and international treaty provis ions. Cyp ress he reby gr ant s to l icense e a pers onal, no n-excl usive , non-tr ansfer able license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjuncti on with a Cypress

integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except as specified above is prohibited wi thout

the express written permis sion of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described h erein. Cypre ss does not

assume any liabil ity ar ising ou t of the a pplic ation or use o f any pr oduct or circ uit descri bed herein . Cypr ess does n ot author ize its p roducts fo r use as critical componen ts in life-su pport systems whe re

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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