STM6717/6718/6719/6720 STM6777/6778/6779/6780 Dual/triple ultra-low voltage supervisors with push-button reset (with delay option) Features Primary supply (VCC1) monitor. Fixed (factory-programmed) reset thresholds: 4.63 V to 1.58 V Secondary supply (VCC2) monitor (STM6717/18/19/20/77/78) Fixed (factory-programmed) reset thresholds: 3.08 V to 0.79 V Tertiary supply monitor (using externally adjustable RSTIN): 0.626 V internal reference RST outputs (push-pull or open drain); state guaranteed if VCC1 or VCC2 0.8 V Reset delay time (trec) on power-up: 13.2 ms, 210 ms, 900 ms (typ) Manual reset input (MR) Optional delayed manual reset input (MRC) with external capacitor (STM6777/78/79/80) Low supply current - 11 A (typ), VCC1 = VCC2 = 3.6 V Operating temperature: -40 C to 85 C (industrial grade) Table 1. SOT23-5 (WY) SOT23-6 (WB) Device summary Monitored voltages Part number VCC1 VCC2 STM6717 STM6718 STM6719 STM6720 STM6777 STM6778 STM6779 STM6780 August 2011 RSTIN Reset output (RST) Manual reset Delayed MR input (MR) pin (MRC) Active-low (push-pull) Active-low (open drain) Doc ID 11469 Rev 8 WY WY WB WB WB WB Package WB WB 1/30 www.st.com 1 Contents STM6717/6718/6719/6720/STM6777/6778/6779/6780 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.1 Active-low, push-pull reset output (RST) - STM6718/20/78/80 . . . . . . . . 7 1.1.2 Active-low, open drain reset output (RST) - STM6717/19/77/79 . . . . . . . 7 1.1.3 Push-button reset input (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.4 Manual reset delay input (MRC) - STM6777/78/79/80) . . . . . . . . . . . . . . 8 1.1.5 Primary supply voltage monitoring input (VCC1) . . . . . . . . . . . . . . . . . . . 8 1.1.6 Secondary supply voltage monitoring input (VCC2) . . . . . . . . . . . . . . . . . 8 1.1.7 Adjustable reset comparator input (RSTIN; STM6719/20/79/80) . . . . . . 8 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2/30 Doc ID 11469 Rev 8 STM6717/6718/6719/6720/STM6777/6778/6779/6780 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 tMLMH minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SOT23-5 - 5-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 23 SOT23-6 - 6-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 24 Carrier tape dimensions for SOT23-5L and SOT23-6L . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Doc ID 11469 Rev 8 3/30 List of figures STM6717/6718/6719/6720/STM6777/6778/6779/6780 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. 4/30 Logic diagram (STM6717/18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic diagram (STM6777/78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic diagram (STM6719/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Logic diagram (STM6779/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM6717/18 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STM6777/78 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STM6719/20 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STM6779/80 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 STM67xx interface to processor with bi-directional reset pins . . . . . . . . . . . . . . . . . . . . . . 10 Ensuring RST valid to VCC = 0 (active-low, push-pull outputs). . . . . . . . . . . . . . . . . . . . . . 10 Supply current vs. temperature (VCC1 = 5.5 V; VCC2 = 3.6 V) . . . . . . . . . . . . . . . . . . . . . . 11 Supply current vs. temperature (VCC1 = 3.6 V; VCC2 = 2.75 V) . . . . . . . . . . . . . . . . . . . . . 11 Supply current vs. temperature (VCC1 = 3.0 V; VCC2 = 2.0 V) . . . . . . . . . . . . . . . . . . . . . . 12 Supply current vs. temperature (VCC1 = 2.0 V; VCC2 = 1.0 V) . . . . . . . . . . . . . . . . . . . . . . 12 Normalized VCC reset time-out period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Maximum VCC transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . 13 Normalized VRST1 threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Normalized VRST2 threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Reset input threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VCC1-to-reset delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset input-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MR-to-reset output delay vs. temperature (VCC1 = 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MR timing waveform (STM6717/18/19/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 MR timing waveform (STM6777/78/79/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SOT23-5 - 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 23 SOT23-6 - 6-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 24 Carrier tape for SOT23-5L and SOT23-6L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Doc ID 11469 Rev 8 STM6717/6718/6719/6720/STM6777/6778/6779/6780 1 Description Description The STM6717/18/19/20 and STM6777/78/79/80 supervisors are a family of low-voltage/lowsupply current processor (micro or DSP) supervisors, designed to monitor two (or three) system power supply voltages. They are targeted at applications such as set-top boxes (STBs), portable, battery-powered systems, networking, and communication systems. All device options have a push-button-type manual reset input (MR). The STM6777/78/79/80 also includes an option which enables the user to delay the start of the manual reset process from 6 s (MRC pin left open) or more with external capacitor. The delay is implemented by connecting the appropriately sized capacitor between the MRC pin and VSS (typical 4 s delay with a 3.3 F capacitor, see Table 7 on page 21). Two of the three supplies monitored (VCC1 and VCC2) have fixed (customer-selectable, factory-trimmed) thresholds (VRST1 and VRST2). The third voltage is monitored using an externally adjustable RSTIN threshold (0.626 V internal reference). If any of the three monitored voltages drop below its factory-trimmed or adjustable thresholds, or if MR is asserted to logic low, a RST is asserted (driven low). Once asserted, RST is maintained at low for a minimum delay period (trec) after ALL supplies rise above their respective thresholds and MR returns to high. These devices are guaranteed to be in the correct reset output logic state when VCC1 and/or VCC2 is greater than 0.8 V. These devices are available in standard 5-pin or 6-pin SOT23 packages (see Table 1 on page 1). Doc ID 11469 Rev 8 5/30 Description Figure 1. STM6717/6718/6719/6720/STM6777/6778/6779/6780 Logic diagram (STM6717/18) Figure 2. Logic diagram (STM6777/78) VCC2 VCC1 VCC2 VCC1 MRC MR STM6717 STM6718 STM6777 STM6778 RST MR VSS RST VSS AI10413 Figure 3. Logic diagram (STM6719/20) AI10415 Figure 4. Logic diagram (STM6779/80) VCC VCC2 VCC1 RSTIN RSTIN MR STM6719 STM6720 MRC RST STM6779 STM6780 RST MR VSS VSS AI10414 Table 2. MR Push-button reset input MRC Manual reset delay input RST Active-low reset output VCC1 Primary supply voltage input VCC2 Secondary supply voltage input RSTIN VSS 6/30 Signal names Adjustable reset comparator input Ground Doc ID 11469 Rev 8 AI10416 STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 5. STM6717/18 SOT23-5 connections RST 1 VSS 2 MR 3 5 4 Figure 6. VCC1 VCC2 Description STM6777/78 SOT23-6 connections RST 1 6 VCC1 VSS 2 5 MRC MR 3 4 VCC2 AI10417 Figure 7. STM6719/20 SOT23-6 connections AI10418 Figure 8. STM6779/80 SOT23-6 connections RST 1 6 VCC1 RST 1 6 VCC1 VSS 2 5 RSTIN VSS 2 5 RSTIN MR 3 4 VCC2 MR 3 4 MRC AI10419 1.1 Pin descriptions 1.1.1 Active-low, push-pull reset output (RST) - STM6718/20/78/80 AI10420 The RST pin is driven low and stays low whenever VCC1 or VCC2 or RSTIN falls below its factory-trimmed or adjustable reset threshold or when MR goes to logic low. It remains low for trec after ALL supply voltages being monitored rise above their reset thresholds and MR goes from low to high. (Push-pull outputs are referenced to VCC1.) 1.1.2 Active-low, open drain reset output (RST) - STM6717/19/77/79 The RST pin is driven low and stays low whenever VCC1 or VCC2 or RSTIN falls below its factory-trimmed or adjustable reset threshold or when MR goes to logic low. It remains low for trec after ALL supply voltages being monitored rise above their reset thresholds and MR goes from low to high. Connect an external pull-up resistor to VCC1. A 10 k pull-up resistor should be sufficient for most applications. 1.1.3 Push-button reset input (MR) When MR goes low the RST output is driven low. RST remains low as long as MR is low and for trec after MR returns to high. This active-low input has an internal 50 k pull-up resistor to Doc ID 11469 Rev 8 7/30 Description STM6717/6718/6719/6720/STM6777/6778/6779/6780 VCC1. It can be driven from a TTL or CMOS logic line, or with open drain/collector outputs, or connected to VSS through a switch. If unused, leave this pin open or connect it to VCC1. Connect a normally open momentary switch from MR to VSS; external debounce circuitry is not required. (If MR is driven from long cables or if the device is used in noisy environments, connecting a 0.1F capacitor from MR to VSS provides additional noise immunity. 1.1.4 Manual reset delay input (MRC) - STM6777/78/79/80) This pin is either left open or connected to VSS via a capacitor. By selecting the appropriate capacitor, the manual reset process, initiated by pressing the push-button manual reset input, can be delayed by any value from 6 s or more (see Table 7 on page 21). 1.1.5 Primary supply voltage monitoring input (VCC1) It also is the input for the primary reset threshold monitor. Available fixed (customerselectable, factory-programmed) reset thresholds include 4.63 V to 1.58 V. 1.1.6 Secondary supply voltage monitoring input (VCC2) This function is available on the STM6717/18/19/20/77/78. Fixed (customer-selectable, factory-programmed) reset thresholds include 3.08 V to 0.79 V. 1.1.7 Adjustable reset comparator input (RSTIN; STM6719/20/79/80) This is a high impedance input. RST is driven low when the voltage at the RSTIN pin falls below 0.626 V (internal reference voltage at this comparator). The monitored voltage reset threshold is set with an external resistor-divider network. Table 3. Pin functions Pin 8/30 Name Function STM6717 STM6719 STM6777 STM6779 STM6718 STM6720 STM6778 STM6780 1 1 1 1 RST Active-low reset output 3 3 3 3 MR Push-button reset input -- -- 5 4 MRC Manual reset delay input 5 6 6 6 VCC1 Primary supply voltage input 4 4 4 -- VCC2 Secondary supply voltage input -- 5 -- 5 2 2 2 2 RSTIN Adjustable reset comparator input VSS Doc ID 11469 Rev 8 Ground STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 9. Description Block diagram VCC1 VCC2 VRST1 COMPARE VRST2 COMPARE VREF/2 = 0.626 COMPARE (1) RSTIN(2) VCC1 trec Generator RST Logic MR MRC(3) AI10421 1. VCC2 input is available on STM6717/18/19/20/77/78. 2. RSTIN available only on STM6719/20/79/80. 3. MRC available only on STM6777/78/79/80. Figure 10. Hardware hookup From DC/DC Converter VCC2(1) VCC1 VCC1 VCC3 = (626.5mV) R1 + R2 R2 ( ) 0.1F STM67xx VCC2 VCC3 0.1F R1 RSTIN(2) RST RST (To Processor Reset) R2 MR MRC(3) Push-button Switch C VSS AI10422 1. VCC2 is available only on STM6717/18/19/20/77/78. 2. RSTIN available only on STM6719/20/79/80. 3. MRC available only on STM6777/78/79/80. Doc ID 11469 Rev 8 9/30 Operation STM6717/6718/6719/6720/STM6777/6778/6779/6780 2 Operation 2.1 Applications information 1. Interfacing to processors with bi-directional reset pins Most processors with bi-directional reset pins can interface directly to the open drain RST outputs (STM6717/19/77/79). Systems simultaneously requiring a push-pull RST output and a bi-directional reset interface can be in logic contention. To prevent this contention, connect a 4.7 k resistor between RST and the processor's reset I/O as shown in Figure 11. 2. Ensuring a valid RST output down to VCC = 0 V The STM67xx supervisors are guaranteed to be in the correct RST output logic state when VCC1 and/or VCC2 is greater than 0.8 V. In applications which require valid reset levels down to VCC = 0, a pull-down resistor to active-low outputs (push-pull only, see Figure 12) will ensure that the reset line is valid while the reset output can no longer sink or source current. This scheme does NOT work with the open drain outputs of the STM6717/19/77/79. The resistor value used is not critical, but it must be large enough not to load the reset output when VCC is above the reset threshold. For most applications, 100 k is adequate. Figure 11. STM67xx interface to processor with bi-directional reset pins VCC2 VCC1 STM67xx Processor To other system components VCC1 VCC2 RESET RST 4.7k VSS VSS AI10425 Figure 12. Ensuring RST valid to VCC = 0 (active-low, push-pull outputs) STM67xx VCC1 VCC1 RST VSS R1 AI10426 10/30 Doc ID 11469 Rev 8 STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics 3 Typical operating characteristics Note: Typical values are at TA = 25 C unless otherwise noted. Figure 13. Supply current vs. temperature (VCC1 = 5.5 V; VCC2 = 3.6 V) 18 Supply current (A) 16 14 12 10 ITOTAL ICC1 8 6 4 ICC2 2 0 -40 -20 0 20 40 60 80 Temperature (C) AI11843 Figure 14. Supply current vs. temperature (VCC1 = 3.6 V; VCC2 = 2.75 V) 18 16 Supply current (A) 14 12 10 ITOTAL 8 ICC1 6 4 ICC2 2 0 -40 -20 0 20 40 Temperature (C) 60 80 AI11844 Doc ID 11469 Rev 8 11/30 Typical operating characteristics STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 15. Supply current vs. temperature (VCC1 = 3.0 V; VCC2 = 2.0 V) 18 Supply current (A) 16 14 12 10 8 ITOTAL 6 ICC1 4 2 ICC2 0 -40 -20 0 20 40 60 80 Temperature (C) AI11845 Figure 16. Supply current vs. temperature (VCC1 = 2.0 V; VCC2 = 1.0 V) 18 Supply current (A) 16 14 12 10 8 ITOTAL 6 ICC1 4 2 0 -40 ICC2 -20 0 20 40 60 80 Temperature (C) AI11846 12/30 Doc ID 11469 Rev 8 STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics Figure 17. Normalized VCC reset time-out period vs. temperature 1.07 Reset period 1.05 1.03 1.01 0.99 0.97 -40 -20 0 20 40 60 80 Temperature (C) AI11847 Maximum VCC transient duration (s) Figure 18. Maximum VCC transient duration vs. reset threshold overdrive 1000 100 10 1 1 10 100 1000 Reset threshold overdrive (mV) AI11848 Doc ID 11469 Rev 8 13/30 Typical operating characteristics STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 19. Normalized VRST1 threshold vs. temperature VRST1 reset threshold 1.004 1.002 1.000 0.998 0.996 -40 -20 0 20 40 60 80 Temperature (C) AI11849 Figure 20. Normalized VRST2 threshold vs. temperature VRST2 reset threshold 1.004 1.002 1.000 0.998 0.996 -40 -20 0 20 40 Temperature (C) 14/30 Doc ID 11469 Rev 8 60 80 AI11850 STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics Figure 21. Reset input threshold vs. temperature Reset input threshold (mV) 630 629 628 627 626 625 624 -40 -20 0 20 40 60 80 Temperature (C) AI11851 Figure 22. VCC1-to-reset delay vs. temperature VCC1-to-reset delay (s) 48 44 40 36 32 28 -40 -20 0 20 Temperature (C) Doc ID 11469 Rev 8 40 60 80 AI11852 15/30 Typical operating characteristics STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 23. Reset input-to-reset output delay vs. temperature RSTIN-to-reset output delay (s) 29.0 28.5 28.0 27.5 27.0 26.5 26.0 25.5 25.0 -40 -20 0 20 40 60 80 Temperature (C) AI11853 Figure 24. MR-to-reset output delay vs. temperature (VCC1 = 3.6V) MR-to-reset output delay (ns) 500 480 460 440 420 400 -40 -20 0 20 40 60 80 Temperature (C) AI11854 16/30 Doc ID 11469 Rev 8 STM6717/6718/6719/6720/STM6777/6778/6779/6780 4 Maximum rating Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4. Absolute maximum ratings Symbol TSTG TSLD(1) VIO VCC1, VCC2 Parameter Value Unit -55 to 150 C 260 C -0.3 to VCC1 + 0.3 V -0.3 to VCC2 + 0.3 V -0.3 to 7.0 V 20 mA SOT23-5 654 mW SOT23-6 675 mW Storage temperature (VCC off) Lead solder temperature for 10 seconds Input or output voltage Supply voltage IIO Input or output current (all pins) PD Power dissipation 1. Reflow at peak temperature of 260 C. The time above 255 C must not exceed 30 seconds. Doc ID 11469 Rev 8 17/30 DC and AC parameters 5 STM6717/6718/6719/6720/STM6777/6778/6779/6780 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 5: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and AC measurement conditions Parameter STM67xx Unit VCC supply voltage 0.8 to 5.5 V Ambient operating temperature (TA) -40 to 85 C 5 ns Input pulse voltages 0.2 to 0.8VCC V Input and output timing ref. voltages 0.3 to 0.7VCC V Input rise and fall times Figure 25. AC testing input/output waveforms 0.8VCC 0.7VCC 0.3VCC 0.2VCC AI02568 Figure 26. MR timing waveform (STM6717/18/19/20) tMLMH MR tMLRL RST trec AI10423a Figure 27. MR timing waveform (STM6777/78/79/80) tMLMH (1) MR tMLRL RST trec AI10424c 1. By connecting a certain capacitor between the MRC pin and VSS, the RST can be delayed from 6 s or more (tMLMH, see Table 7 on page 21). 18/30 Doc ID 11469 Rev 8 STM6717/6718/6719/6720/STM6777/6778/6779/6780 Table 6. Sym DC and AC characteristics Alternative Description VCC Operating voltage ICC1 VCC1 supply current ICC2 VCC2 supply current ILI DC and AC parameters (2) ILO 0.8 Max Unit 5.5 V VCC1 < 5.5 V, all I/O pins open 12 35 A VCC1 < 3.6 V, all I/O pins open 8 23 A VCC2 < 3.6 V, all I/O pins open 3 9 A VCC2 < 2.75 V, all I/O pins open 2.5 7 A +1 A Open drain RST output leakage current VCC1 > VRST1, VCC2 > VRST2; RST not asserted 0.5 A VCC1 or VCC2 0.8 V, ISINK = 1 A, RST asserted 0.3 V VCC1 or VCC2 1.0 V, ISINK = 50 A, RST asserted 0.3 V VCC1 or VCC2 1.2 V, ISINK = 100 A, RST asserted 0.3 V VCC1 or VCC2 2.7 V, ISINK = 1.2 mA, RST asserted 0.3 V VCC1 or VCC2 4.5 V, ISINK = 3.2 mA, RST asserted 0.4 V Push-pull RST rise time (STM6718/20/78/80) tR(3) Typ 0 V = VIN = VCC Output high voltage (RST; push-pull only) VOH Min Input leakage current Output low voltage (RST; push-pull or open drain) VOL Test condition(1) -1 VCC1 1.8 V, ISOURCE = 200 A, RST not asserted 0.8VCC1 V VCC1 2.7 V, ISOURCE = 500 A, RST not asserted 0.8VCC1 V VCC1 4.5 V, ISOURCE = 800 A, RST not asserted 0.8VCC1 V Rise time measured from 10% to 90% of VCC; CL = 5 pF, VCC = 3.3 V 5 25 ns Reset thresholds VRST(4) VTH1 VCC1 reset threshold L (falling) 4.500 4.625 4.750 V M (falling) 4.250 4.375 4.500 V T (falling) 3.000 3.075 3.150 V S (falling) 2.850 2.925 3.000 V R (falling) 2.550 2.625 2.700 V Z (falling) 2.250 2.313 2.375 V Y (falling) 2.125 2.188 2.250 V W (falling) 1.620 1.665 1.710 V V (falling) 1.530 1.575 1.620 V Doc ID 11469 Rev 8 19/30 DC and AC parameters Table 6. Sym VRST2 (4) DC and AC characteristics (continued) Alternative VTH2 Description tRD VCC to RST delay tRP Test condition(1) Min T (falling) 3.000 3.075 3.150 V S (falling) 2.850 2.925 3.000 V R (falling) 2.550 2.625 2.700 V Z (falling) 2.250 2.313 2.375 V Y (falling) 2.125 2.188 2.250 V W (falling) 1.620 1.665 1.710 V V (falling) 1.530 1.575 1.620 V I (falling) 1.350 1.388 1.425 V H (falling) 1.275 1.313 1.350 V G (falling) 1.080 1.110 1.140 V F (falling) 1.020 1.050 1.080 V K (falling) 0.895 0.925 0.955 V J (falling) 0.845 0.875 0.905 V E (falling) 0.810 0.833 0.855 V D (falling) 0.765 0.788 0.810 V VCC2 reset threshold Reset threshold hysteresis VHYST trec STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typ Max Unit Referenced to VRST typical 0.5 % VCC1 = (VRST1 + 100 mV) to (VRST - 100 mV) 20 s VCC2 = (VRST2 + 75 mV) to (VRST2 - 75 mV) 20 s RST pulse width blank 140 210 280 B 8.8 13.2 17.6 G 600 900 1200 626.5 642 mV +25 nA ms Adjustable reset comparator input (STM6719/20/79/80) VRSTIN RSTIN input threshold 611 IRSTIN RSTIN input current -25 RSTIN hysteresis tRSTIND 20/30 RSTIN to RST output delay VRSTIN to (VRSTIN - 30 mV) Doc ID 11469 Rev 8 3 mV 22 s STM6717/6718/6719/6720/STM6777/6778/6779/6780 Table 6. Sym DC and AC parameters DC and AC characteristics (continued) Alternative Description Test condition(1) Min Typ Max Unit 0.3VC V Manual (push-button) reset input VIL MR input voltage C1 VIH MR minimum pulse width (STM6717/18/19/20) tMLMH tMLRL tMR tMRD MR minimum pulse width (STM6777/78/79/80) 0.7VCC1 V 1 s MRC connected via capacitor to VSS 6 s MR to RST output delay 200 ns MR glitch immunity (STM6717/18/19/20) 100 ns MR pull-up resistance 25 50 80 k 1. Valid for ambient operating temperature: TA = -40 to 85 C; VCC1 = 0.8 to 5.5 V and VCC2 = 0.8 to 3.6 V (except where noted). 2. Input leakage for the MRC pin is not tested. 3. Guaranteed by design. 4. The leakage current measured on the RST pin is tested with the reset de-asserted (output high impedance). Table 7. tMLMH minimum pulse width Capacitor value(1) VCC1 100 pF 0.1 F 2.2 F 3.3 F 4.7 F 6.8 F 1.6 V 120 s 120 ms 2.6 s 4.0 s 5.6 s 8.2 s 2.0 V 122 s 122 ms 2.7 s 4.0 s 5.8 s 8.3 s 3.0 V 125 s 125 ms 2.7 s 4.1 s 5.9 s 8.5 s 4.0 V 128 s 129 ms 2.8 s 4.2 s 6.0 s 8.7 s 5.0 V 130 s 130 ms 2.8 s 4.3 s 6.1 s 8.8 s 1. At 25 C (typical) Doc ID 11469 Rev 8 21/30 Package mechanical data 6 STM6717/6718/6719/6720/STM6777/6778/6779/6780 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 22/30 Doc ID 11469 Rev 8 STM6717/6718/6719/6720/STM6777/6778/6779/6780 Package mechanical data Figure 28. SOT23-5 - 5-lead small outline transistor package mechanical drawing E A1 1 e e1 D 5x b 5x 0.20 M CAB C 0.10 A A2 C A Datum A 0.20 C L B E1 Note: 0133778 Drawing is not to scale. Table 8. SOT23-5 - 5-lead small outline transistor package mechanical data mm inches Symb Min Typ Max Min Typ Max A -- -- 1.45 -- -- 0.057 A1 -- -- 0.15 -- -- 0.006 A2 0.90 1.15 1.30 0.035 0.045 0.051 b 0.30 -- 0.50 0.012 -- 0.020 C 0.08 -- 0.22 0.003 -- 0.009 D -- 2.90 -- -- 0.114 -- E -- 2.80 -- -- 0.110 -- E1 -- 1.60 -- -- 0.063 -- e -- 0.95 -- -- 0.037 -- e1 -- 1.90 -- -- 0.075 -- L 0.30 0.45 0.60 0.012 0.018 0.024 Q 0 4 8 0 4 8 N Note: 5 5 Dimensions per JEDEC SOT/SOP product outline MO-178C, variation AA Doc ID 11469 Rev 8 23/30 Package mechanical data STM6717/6718/6719/6720/STM6777/6778/6779/6780 Figure 29. SOT23-6 - 6-lead small outline transistor package mechanical drawing E A1 1 e e1 D 6x b 0.10 6x M CAB C 0.10 A A2 C A Datum A 0.20 C L B E1 7049714 Note: Drawing is not to scale. Table 9. SOT23-6 - 6-lead small outline transistor package mechanical data mm inches Symb Min Typ Max Min Typ Max A -- -- 1.45 -- -- 0.057 A1 -- -- 0.15 -- -- 0.006 A2 0.90 1.15 1.30 0.035 0.045 0.051 b 0.30 -- 0.50 0.012 -- 0.020 C 0.08 -- 0.22 0.003 -- 0.009 D -- 2.90 -- -- 0.114 -- E -- 2.80 -- -- 0.110 -- E1 -- 1.60 -- -- 0.063 -- e -- 0.95 -- -- 0.037 -- e1 -- 1.90 -- -- 0.075 -- L 0.30 0.45 0.60 0.012 0.018 0.024 Q 0 4 8 0 4 8 N Note: 24/30 6 6 Dimensions per JEDEC SOT/SOP product outline MO-178C variation AB Doc ID 11469 Rev 8 STM6717/6718/6719/6720/STM6777/6778/6779/6780 Package mechanical data Figure 30. Carrier tape for SOT23-5L and SOT23-6L P0 E P2 D T A0 F TOP COVER TAPE W B0 P1 CENTER LINES OF CAVITY K0 USER DIRECTION OF FEED AM03073v1 Note: Part pin 1 indicator is on bottom left for shipping method "F" and is on top right for shipping method "R" see Section 7. Table 10. Carrier tape dimensions for SOT23-5L and SOT23-6L Package W D 8.00 1.50 SOT23-5 +0.30/ +0.10/ SOT23-6 -0.10 -0.00 E P0 P2 F 1.75 4.00 2.00 3.50 0.10 0.10 0.10 0.05 A0 B0 K0 3.23 0.10 3.17 0.10 1.37 0.10 Doc ID 11469 Rev 8 P1 T Unit Bulk Qty 4.00 0.254 mm 3000 0.10 0.013 25/30 Part numbering STM6717/6718/6719/6720/STM6777/6778/6779/6780 7 Part numbering Table 11. Ordering information scheme Example: Device type STM67xx STM67xx LT WY 6 F Reset thresholds (VRST1 and VRST2) for VCC1 and VCC2 STM6717/18/19/20/77/78 (VRST1 and VRST2) STM6779/80 (VRST1 only) VRST2 Suffix VRST1 Suffix VRST1 LT 4.625 3.075 L-(1) 4.625 3.075 MS 4.375 2.925 T-(1) 2.925 MR 4.375 2.625 S-(1) 3.075 2.313 Y-(1) 2.188 TZ(1) TW(1) 3.075 1.665 V-(1) 1.575 TI 3.075 1.388 R- 2.625 3.075 1.110 Z- 2.313 TG(1) TK 3.075 0.925 TE 3.075 0.833 2.925 2.188 SY(1) 2.925 1.575 SV(1) SH(2) 2.925 1.313 2.925 1.050 SF(1) 2.925 0.875 SJ(3) 2.925 0.788 SD(3) YV 2.188 1.575 YH 2.188 1.313 YF 2.188 1.050 YJ 2.188 0.875 YD 2.188 0.788 VH 1.575 1.313 VF 1.575 1.050 VJ 1.575 0.875 VD 1.575 0.788 Reset pulse width blank: trec = 140 ms to 280 ms B: trec = 8.8 ms to 17.6 ms G: trec = 600 ms to 1200 ms Package WY = SOT23-5 WB = SOT23-6 Temperature range 6 = -40 to 85C Shipping method E = ECOPACK(R) package, tubes F = ECOPACK(R) package, tape and reel R(4) = ECOPACK(R) package, tape and reel (pin 1 at top right). 1. These are standard versions and are typically held in stock. A non-standard version may require a higher minimum volumes, and/or longer delivery times. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. 2. Available in STM6719 version only. 3. Available in STM6717 version only. 4. Available for STM6720SY, STM6719SF and STM6719SFB versions only. 26/30 Doc ID 11469 Rev 8 STM6717/6718/6719/6720/STM6777/6778/6779/6780 Table 12. Part numbering Marking description Part number VRST1 threshold (V) VRST2 threshold (V) Topside marking Bottomside marking STM6717SD 2.925 0.788 7SD1 PYWW STM6717SJ 2.925 0.875 7SJ1 PYWW STM6717SF 2.925 1.050 7SF1 PYWW STM6717TG 3.075 1.110 7TG1 PYWW STM6717TGG 3.075 1.110 7TG9 PYWW STM6717TW 3.075 1.665 7TW1 PYWW STM6717SV 2.925 1.575 7SV1 PYWW STM6717SY 2.925 2.188 7SY1 PYWW STM6717TZ 3.075 2.313 7TZ1 PYWW STM6718SF 2.925 1.050 7SF2 PYWW STM6718TG 3.075 1.110 7TG2 PYWW STM6718TW 3.075 1.665 7TW2 PYWW STM6718SV 2.925 1.575 7SV2 PYWW STM6718SY 2.925 2.188 7SY2 PYWW STM6718TZ 3.075 2.313 7TZ2 PYWW STM6719SF 2.925 1.050 7SF3 PYWW STM6719SFB 2.925 1.050 7SFB PYWW STM6719TG 3.075 1.110 7TG3 PYWW STM6719SH 2.925 1.313 7SH3 PYWW STM6719TW 3.075 1.665 7TW3 PYWW STM6719SV 2.925 1.575 7SV3 PYWW STM6719SY 2.925 2.188 7SY3 PYWW STM6719TZ 3.075 2.313 7TZ3 PYWW STM6720SF 2.925 1.050 7SF4 PYWW STM6720TG 3.075 1.110 7TG4 PYWW STM6720TW 3.075 1.665 7TW4 PYWW STM6720SV 2.925 1.575 7SV4 PYWW STM6720SY 2.925 2.188 7SY4 PYWW STM6720TZ 3.075 2.313 7TZ4 PYWW STM6777SF 2.925 1.050 7SF5 PYWW STM6777TG 3.075 1.110 7TG5 PYWW STM6777TW 3.075 1.665 7TW5 PYWW STM6777SV 2.925 1.575 7SV5 PYWW STM6777SY 2.925 2.188 7SY5 PYWW STM6777TZ 3.075 2.313 7TZ5 PYWW Doc ID 11469 Rev 8 27/30 Part numbering Table 12. STM6717/6718/6719/6720/STM6777/6778/6779/6780 Marking description (continued) Part number VRST1 threshold (V) VRST2 threshold (V) Topside marking Bottomside marking STM6778SF 2.925 1.050 7SF6 PYWW STM6778TG 3.075 1.110 7TG6 PYWW STM6778TW 3.075 1.665 7TW6 PYWW STM6778SV 2.925 1.575 7SV6 PYWW STM6778SY 2.925 2.188 7SY6 PYWW STM6778TZ 3.075 2.313 7TZ6 PYWW STM6779L 4.625 -- 7Lx7 PYWW STM6779T 3.075 -- 7Tx7 PYWW STM6779S 2.925 -- 7Sx7 PYWW STM6779Y 2.188 -- 7Yx7 PYWW STM6779V 1.575 -- 7Vx7 PYWW STM6780L 4.625 -- 7Lx8 PYWW STM6780T 3.075 -- 7Tx8 PYWW STM6780S 2.925 -- 7Sx8 PYWW STM6780Y 2.188 -- 7Yx8 PYWW STM6780V 1.575 -- 7Vx8 PYWW Note: For topside marking, "7" is the family number, followed by the VRST1 threshold, VRST2 threshold and device number (1,9 = STM6717, 2 = 6718, 3 = 6719, 4 = 6720, 5 = 6777, 6 = 6778, 7 = 6779, 8 = 6780). For bottomside marking, "P" = assembly site, "Y" = 1-digit year, and "WW" = 2-digit work week. 28/30 Doc ID 11469 Rev 8 STM6717/6718/6719/6720/STM6777/6778/6779/6780 8 Revision history Revision history Table 13. Document revision history Date Revision Changes 18-Oct-2004 1 25-Oct-2004 1.1 Descriptive text, sales types (Table 11) 14-Jan-2005 1.2 Update characteristics, pin functions (Table 2) 09-Feb-2005 1.3 Update characteristics (Figure 9; Table 3) 08-Apr-2005 1.4 Update characteristics and mechanical dimensions; add table (Figure 9, 10, 27, 28, 29; Table 4, 6, 11, 8, 9) 28-Jul-2005 1.5 Update characteristics, reset delay (Figure 10, 27; Table 4, 6, 7, 11) 13-Sep-2005 2 Add operating characteristics; update timings, document status, Leadfree text (Figure Figure 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 26, 27; Table 11) 07-Oct-2005 3 Marked STM6779/6780 as availability request parts (Table 1, 11) 07-Feb-2007 4 Updated STM6779/6780 availability (cover page, Table 1, 11) 12-Jun-2007 5 Updated Table 11, added Table 12: Marking description. 05-Dec-2007 6 Updated cover page, Table 6, 11, and 12. 22-Mar-2010 7 Updated Features; Table 6, 8, 9, 11, 12; footnote 1 of Table 4; Section 6: Package mechanical data; added tape and reel specifications (Figure 30, Table 10, footnote 4 of Table 11); reformatted document. 02-Aug-2011 8 Removed footnote from Table 6: DC and AC characteristics. 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