STM6718VDWY6F - STMicroelectronics, Inc.

August 2011 Doc ID 11469 Rev 8 1/30

STM6717/6718/6719/6720

STM6777/6778/6779/6780

Dual/triple ultra-low voltage supervisors

with push-button reset (with delay option)

Features

■Primary supply (VCC1) monitor.

Fixed (factory-programmed) reset thresholds:

4.63 V to 1.58 V

■Secondary supply (VCC2) monitor

(STM6717/18/19/20/77/78)

■Fixed (factory-programmed) reset thresholds:

3.08 V to 0.79 V

■Tertiary supply monitor (using externally

adjustable RSTIN): 0.626 V internal reference

■RST outputs (push-pull or open drain); state

guaranteed if VCC1 or VCC2 ≥ 0.8 V

■Reset delay time (trec) on power-up: 13.2 ms,

210 ms, 900 ms (typ)

■Manual reset input (MR)

■Optional delayed manual reset input (MRC)

with external capacitor (STM6777/78/79/80)

■Low supply current - 11 µA (typ),

VCC1 = VCC2 = 3.6 V

■Operating temperature: –40 °C to 85 °C

(industrial grade)

SOT23-5 (WY)

SOT23-6 (WB)

Table 1. Device summary

Part

number

Monitored voltages

Manual reset

input (MR)

Delayed MR

pin (MRC)

Reset output (RST)

Package

VCC1 VCC2 RSTIN Active-low

(push-pull)

Active-low

(open drain)

STM6717 ✔✔ ✔ ✔ WY

STM6718 ✔✔ ✔ ✔ WY

STM6719 ✔✔✔ ✔ ✔ WB

STM6720 ✔✔✔ ✔ ✔ WB

STM6777 ✔✔ ✔ ✔ ✔ WB

STM6778 ✔✔ ✔ ✔ ✔ WB

STM6779 ✔✔✔✔ ✔WB

STM6780 ✔✔✔✔✔ WB

www.st.com

Contents STM6717/6718/6719/6720/STM6777/6778/6779/6780
2/30 Doc ID 11469 Rev 8
Contents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1 Pin descriptions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  7
1.1 Active-low, push-pull reset output (RST) - STM6718/20/78/80  . . . . . . . . 7
1.2 Active-low, open drain reset output (RST) - STM6717/19/77/79  . . . . . . . 7
1.3 Push-button reset input (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Manual reset delay input (MRC) - STM6777/78/79/80)  . . . . . . . . . . . . . . 8
1.5 Primary supply voltage monitoring input (VCC1)   . . . . . . . . . . . . . . . . . . . 8
1.6 Secondary supply voltage monitoring input (VCC2)  . . . . . . . . . . . . . . . . . 8
1.7 Adjustable reset comparator input (RSTIN; STM6719/20/79/80)   . . . . . . 8
Operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1 Applications information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  10
Typical operating characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC and AC parameters  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Part numbering  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

STM6717/6718/6719/6720/STM6777/6778/6779/6780 List of tables
Doc ID 11469 Rev 8 3/30
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Signal names  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 5. Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6. DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. tMLMH minimum pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 8. SOT23-5 – 5-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 23
Table 9. SOT23-6 – 6-lead small outline transistor package mechanical data. . . . . . . . . . . . . . . . . 24
Table 10. Carrier tape dimensions for SOT23-5L and SOT23-6L  . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 12. Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 13. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

List of figures STM6717/6718/6719/6720/STM6777/6778/6779/6780
4/30 Doc ID 11469 Rev 8
List of figures
Figure 1. Logic diagram (STM6717/18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Logic diagram (STM6777/78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Logic diagram (STM6719/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Logic diagram (STM6779/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. STM6717/18 SOT23-5 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. STM6777/78 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. STM6719/20 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 8. STM6779/80 SOT23-6 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 9. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 10. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 11. STM67xx interface to processor with bi-directional reset pins . . . . . . . . . . . . . . . . . . . . . . 10
Figure 12. Ensuring RST valid to VCC = 0 (active-low, push-pull outputs). . . . . . . . . . . . . . . . . . . . . . 10
Figure 13. Supply current vs. temperature (VCC1 = 5.5 V; VCC2 = 3.6 V)  . . . . . . . . . . . . . . . . . . . . . . 11
Figure 14. Supply current vs. temperature (VCC1 = 3.6 V; VCC2 = 2.75 V)  . . . . . . . . . . . . . . . . . . . . . 11
Figure 15. Supply current vs. temperature (VCC1 = 3.0 V; VCC2 = 2.0 V)  . . . . . . . . . . . . . . . . . . . . . . 12
Figure 16. Supply current vs. temperature (VCC1 = 2.0 V; VCC2 = 1.0 V)  . . . . . . . . . . . . . . . . . . . . . . 12
Figure 17. Normalized VCC reset time-out period vs. temperature  . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 18. Maximum VCC transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . 13
Figure 19. Normalized VRST1 threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 20. Normalized VRST2 threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 21. Reset input threshold vs. temperature  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 22. VCC1-to-reset delay vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 23. Reset input-to-reset output delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 24. MR-to-reset output delay vs. temperature (VCC1 = 3.6V) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 25. AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 26. MR timing waveform (STM6717/18/19/20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 27. MR timing waveform (STM6777/78/79/80) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 28. SOT23-5 – 5-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 23
Figure 29. SOT23-6 – 6-lead small outline transistor package mechanical drawing . . . . . . . . . . . . . . 24
Figure 30. Carrier tape for SOT23-5L and SOT23-6L . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Description

Doc ID 11469 Rev 8 5/30

1 Description

The STM6717/18/19/20 and STM6777/78/79/80 supervisors are a family of low-voltage/low-

supply current processor (micro or DSP) supervisors, designed to monitor two (or three)

system power supply voltages. They are targeted at applications such as set-top boxes

(STBs), portable, battery-powered systems, networking, and communication systems.

All device options have a push-button-type manual reset input (MR). The

STM6777/78/79/80 also includes an option which enables the user to delay the start of the

manual reset process from 6 µs (MRC pin left open) or more with external capacitor. The

delay is implemented by connecting the appropriately sized capacitor between the MRC pin

and VSS (typical 4 s delay with a 3.3 µF capacitor, see Table 7 on page 21).

Two of the three supplies monitored (VCC1 and VCC2) have fixed (customer-selectable,

factory-trimmed) thresholds (VRST1 and VRST2). The third voltage is monitored using an

externally adjustable RSTIN threshold (0.626 V internal reference).

If any of the three monitored voltages drop below its factory-trimmed or adjustable

thresholds, or if MR is asserted to logic low, a RST is asserted (driven low). Once asserted,

RST is maintained at low for a minimum delay period (trec) after ALL supplies rise above

their respective thresholds and MR returns to high. These devices are guaranteed to be in

the correct reset output logic state when VCC1 and/or VCC2 is greater than 0.8 V.

These devices are available in standard 5-pin or 6-pin SOT23 packages (see Ta bl e 1 o n

page 1).

Description STM6717/6718/6719/6720/STM6777/6778/6779/6780

6/30 Doc ID 11469 Rev 8

Table 2. Signal names

Figure 1. Logic diagram (STM6717/18) Figure 2. Logic diagram (STM6777/78)

Figure 3. Logic diagram (STM6719/20) Figure 4. Logic diagram (STM6779/80)

AI10413

VCC1

STM6717

STM6718

VSS

VCC2

RST

AI10415

VCC1

STM6777

STM6778

VSS

VCC2

RST

MRC

AI10414

VCC1

STM6719

STM6720

VSS

VCC2

RST

RSTIN

AI10416

VCC

STM6779

STM6780

VSS

RST

MRC

RSTIN

MR Push-button reset input

MRC Manual reset delay input

RST Active-low reset output

VCC1 Primary supply voltage input

VCC2 Secondary supply voltage input

RSTIN Adjustable reset comparator input

VSS Ground

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Description

Doc ID 11469 Rev 8 7/30

1.1 Pin descriptions

1.1.1 Active-low, push-pull reset output (RST) - STM6718/20/78/80

The RST pin is driven low and stays low whenever VCC1 or VCC2 or RSTIN falls below its

factory-trimmed or adjustable reset threshold or when MR goes to logic low. It remains low

for trec after ALL supply voltages being monitored rise above their reset thresholds and MR

goes from low to high. (Push-pull outputs are referenced to VCC1.)

1.1.2 Active-low, open drain reset output (RST) - STM6717/19/77/79

The RST pin is driven low and stays low whenever VCC1 or VCC2 or RSTIN falls below its

factory-trimmed or adjustable reset threshold or when MR goes to logic low. It remains low

for trec after ALL supply voltages being monitored rise above their reset thresholds and MR

goes from low to high. Connect an external pull-up resistor to VCC1. A 10 kΩ pull-up resistor

should be sufficient for most applications.

1.1.3 Push-button reset input (MR)

When MR goes low the RST output is driven low. RST remains low as long as MR is low and

for trec after MR returns to high. This active-low input has an internal 50 kΩ pull-up resistor to

Figure 5. STM6717/18 SOT23-5 connections Figure 6. STM6777/78 SOT23-6 connections

Figure 7. STM6719/20 SOT23-6 connections Figure 8. STM6779/80 SOT23-6 connections

RST VCC1

VCC2

VSS

AI10417

RST VCC1

VCC2

VSS

AI10418

MRC

RST VCC1

VCC2

VSS

AI10419

5RSTIN

RST VCC1

MRC

VSS

AI10420

5RSTIN

Description STM6717/6718/6719/6720/STM6777/6778/6779/6780

8/30 Doc ID 11469 Rev 8

VCC1. It can be driven from a TTL or CMOS logic line, or with open drain/collector outputs,

or connected to VSS through a switch. If unused, leave this pin open or connect it to VCC1.

Connect a normally open momentary switch from MR to VSS; external debounce circuitry is

not required. (If MR is driven from long cables or if the device is used in noisy environments,

connecting a 0.1µF capacitor from MR to VSS provides additional noise immunity.

1.1.4 Manual reset delay input (MRC) - STM6777/78/79/80)

This pin is either left open or connected to VSS via a capacitor. By selecting the appropriate

capacitor, the manual reset process, initiated by pressing the push-button manual reset

input, can be delayed by any value from 6 µs or more (see Table 7 on page 21).

1.1.5 Primary supply voltage monitoring input (VCC1)

It also is the input for the primary reset threshold monitor. Available fixed (customer-

selectable, factory-programmed) reset thresholds include 4.63 V to 1.58 V.

1.1.6 Secondary supply voltage monitoring input (VCC2)

This function is available on the STM6717/18/19/20/77/78. Fixed (customer-selectable,

factory-programmed) reset thresholds include 3.08 V to 0.79 V.

1.1.7 Adjustable reset comparator input (RSTIN; STM6719/20/79/80)

This is a high impedance input. RST is driven low when the voltage at the RSTIN pin falls

below 0.626 V (internal reference voltage at this comparator). The monitored voltage reset

threshold is set with an external resistor-divider network.

Table 3. Pin functions

Name Function

STM6717

STM6718

STM6719

STM6720

STM6777

STM6778

STM6779

STM6780

1111RST

Active-low reset output

3333MR

Push-button reset input

— — 5 4 MRC Manual reset delay input

5666V

CC1 Primary supply voltage input

444—V

CC2 Secondary supply voltage input

— 5 — 5 RSTIN Adjustable reset comparator input

2222V

SS Ground

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Description

Doc ID 11469 Rev 8 9/30

Figure 9. Block diagram

1. VCC2 input is available on STM6717/18/19/20/77/78.

2. RSTIN available only on STM6719/20/79/80.

3. MRC available only on STM6777/78/79/80.

Figure 10. Hardware hookup

1. VCC2 is available only on STM6717/18/19/20/77/78.

2. RSTIN available only on STM6719/20/79/80.

3. MRC available only on STM6777/78/79/80.

AI10421

VREF/2 = 0.626 RST

COMPARE

Logic

trec

Generator

RSTIN(2)

VCC2(1)

VCC1

VRST2

VRST1

MRC(3)

VCC1

AI10422

VCC1

VCC2

VSS

VCC1

MRC(3)

0.1µF

STM67xx

RSTIN(2) RST RST (To Processor Reset)

Push-button

Switch

From DC/DC Converter

VCC2(1)

VCC3

0.1µF

VCC3 = (626.5mV)

(

R1 + R2

)

Operation STM6717/6718/6719/6720/STM6777/6778/6779/6780

10/30 Doc ID 11469 Rev 8

2 Operation

2.1 Applications information

1. Interfacing to processors with bi-directional reset pins

Most processors with bi-directional reset pins can interface directly to the open drain

RST outputs (STM6717/19/77/79). Systems simultaneously requiring a push-pull RST

output and a bi-directional reset interface can be in logic contention. To prevent this

contention, connect a 4.7 kΩ resistor between RST and the processor’s reset I/O as

shown in Figure 11.

2. Ensuring a valid RST output down to VCC =0 V

The STM67xx supervisors are guaranteed to be in the correct RST output logic state

when VCC1 and/or VCC2 is greater than 0.8 V. In applications which require valid reset

levels down to VCC = 0, a pull-down resistor to active-low outputs (push-pull only, see

Figure 12) will ensure that the reset line is valid while the reset output can no longer

sink or source current. This scheme does NOT work with the open drain outputs of the

STM6717/19/77/79.

The resistor value used is not critical, but it must be large enough not to load the reset

output when VCC is above the reset threshold. For most applications, 100 kΩ is

adequate.

Figure 11. STM67xx interface to processor with bi-directional reset pins

Figure 12. Ensuring RST valid to VCC = 0 (active-low, push-pull outputs)

AI10425

VCC1

VCC2

VSS

VCC1

STM67xx

RST

To other

system

components

4.7kΩ

VCC2

VSS

Processor

RESET

AI10426

VCC1

VSS

STM67xx

RST

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics

Doc ID 11469 Rev 8 11/30

3 Typical operating characteristics

Note: Typical values are at TA = 25 °C unless otherwise noted.

Figure 13. Supply current vs. temperature (VCC1 = 5.5 V; VCC2 = 3.6 V)

Figure 14. Supply current vs. temperature (VCC1 = 3.6 V; VCC2 = 2.75 V)

ICC1

ICC2

ITOTAL

–40 –20 0 20 40 60 80

Temperature (°C)

Supply current (µA)

AI11843

ICC1

ICC2

ITOTAL

–40 –20 0 20 40 60 80

Temperature (°C)

Supply current (µA)

AI11844

Typical operating characteristics STM6717/6718/6719/6720/STM6777/6778/6779/6780

12/30 Doc ID 11469 Rev 8

Figure 15. Supply current vs. temperature (VCC1 = 3.0 V; VCC2 = 2.0 V)

Figure 16. Supply current vs. temperature (VCC1 = 2.0 V; VCC2 = 1.0 V)

AI11845

–40 –20 0 20 40 60 80

Temperature (°C)

Supply current (µA)

ICC1

ICC2

ITOTAL

AI11846

–40 –20 0 20 40 60 80

Temperature (°C)

Supply current (µA)

ICC1

ICC2

ITOTAL

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics

Doc ID 11469 Rev 8 13/30

Figure 17. Normalized VCC reset time-out period vs. temperature

Figure 18. Maximum VCC transient duration vs. reset threshold overdrive

0.97

AI11847

0.99

1.01

1.03

1.05

1.07

–40 –20 0 20 40 60 80

Temperature (°C)

Reset period

AI11848

100

1000

1 10 100 1000

Reset threshold overdrive (mV)

Maximum VCC transient duration (µs)

Typical operating characteristics STM6717/6718/6719/6720/STM6777/6778/6779/6780

14/30 Doc ID 11469 Rev 8

Figure 19. Normalized VRST1 threshold vs. temperature

Figure 20. Normalized VRST2 threshold vs. temperature

0.996

AI11849

0.998

1.000

1.002

1.004

–40 –20 0 20 40 60 80

Temperature (°C)

VRST1 reset threshold

0.996

AI11850

0.998

1.000

1.002

1.004

–40 –20 0 20 40 60 80

Temperature (°C)

VRST2 reset threshold

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Typical operating characteristics

Doc ID 11469 Rev 8 15/30

Figure 21. Reset input threshold vs. temperature

Figure 22. VCC1-to-reset delay vs. temperature

624

AI11851

625

626

627

628

629

630

–40 –20 0 20 40 60 80

Temperature (°C)

Reset input threshold (mV)

–40 –20 0 20 40 60 80

Temperature (°C)

VCC1-to-reset delay (µs)

AI11852

Typical operating characteristics STM6717/6718/6719/6720/STM6777/6778/6779/6780

16/30 Doc ID 11469 Rev 8

Figure 23. Reset input-to-reset output delay vs. temperature

Figure 24. MR-to-reset output delay vs. temperature (VCC1 = 3.6V)

25.0

AI11853

25.5

26.0

26.5

27.0

27.5

28.0

28.5

29.0

–40 –20 0 20 40 60 80

Temperature (°C)

RSTIN-to-reset output delay (µs)

400

AI11854

420

440

460

480

500

–40 –20 0 20 40 60 80

Temperature (°C)

MR-to-reset output delay (ns)

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Maximum rating

Doc ID 11469 Rev 8 17/30

4 Maximum rating

Stressing the device above the rating listed in the Absolute Maximum Ratings” table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the Operating sections of

this specification is not implied. Exposure to Absolute Maximum Rating conditions for

extended periods may affect device reliability. Refer also to the STMicroelectronics SURE

Program and other relevant quality documents.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit

TSTG Storage temperature (VCC off) –55 to 150 °C

TSLD(1)

1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds.

Lead solder temperature for 10 seconds 260 °C

VIO Input or output voltage –0.3 to VCC1 + 0.3 V

–0.3 to VCC2 + 0.3 V

VCC1, VCC2 Supply voltage –0.3 to 7.0 V

IIO Input or output current (all pins) 20 mA

PDPower dissipation SOT23-5 654 mW

SOT23-6 675 mW

DC and AC parameters STM6717/6718/6719/6720/STM6777/6778/6779/6780

18/30 Doc ID 11469 Rev 8

5 DC and AC parameters

This section summarizes the operating measurement conditions, and the DC and AC

characteristics of the device. The parameters in the DC and AC characteristics tables that

follow, are derived from tests performed under the measurement conditions summarized in

Table 5: Operating and AC measurement conditions. Designers should check that the

operating conditions in their circuit match the operating conditions when relying on the

quoted parameters.

Figure 25. AC testing input/output waveforms

Figure 26. MR timing waveform (STM6717/18/19/20)

Figure 27. MR timing waveform (STM6777/78/79/80)

1. By connecting a certain capacitor between the MRC pin and VSS, the RST can be delayed from 6 µs or

more (tMLMH, see Table 7 on page 21).

Table 5. Operating and AC measurement conditions

Parameter STM67xx Unit

VCC supply voltage 0.8 to 5.5 V

Ambient operating temperature (TA) –40 to 85 °C

Input rise and fall times ≤ 5ns

Input pulse voltages 0.2 to 0.8VCC V

Input and output timing ref. voltages 0.3 to 0.7VCC V

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

AI10423a

RST

MLRL

rec

MLMH

AI10424c

RST

trec

MLMH

(1)

MLRL

STM6717/6718/6719/6720/STM6777/6778/6779/6780 DC and AC parameters

Doc ID 11469 Rev 8 19/30

Table 6. DC and AC characteristics

Sym Alter-

native Description Test condition(1) Min Typ Max Unit

VCC Operating voltage 0.8 5.5 V

ICC1 VCC1 supply current VCC1 < 5.5 V, all I/O pins open 12 35 µA

VCC1 < 3.6 V, all I/O pins open 8 23 µA

ICC2 VCC2 supply current VCC2 < 3.6 V, all I/O pins open 3 9 µA

VCC2 < 2.75 V, all I/O pins open 2.5 7 µA

ILI(2) Input leakage current 0 V = VIN = VCC –1 +1 µA

ILO

Open drain RST output

leakage current

VCC1 > VRST1, VCC2 > VRST2;

RST not asserted 0.5 µA

VOL

Output low voltage (RST;

push-pull or open drain)

VCC1 or VCC2 ≥ 0.8 V,

ISINK = 1 µA, RST asserted 0.3 V

VCC1 or VCC2 ≥ 1.0 V,

ISINK = 50 µA, RST asserted 0.3 V

VCC1 or VCC2 ≥ 1.2 V,

ISINK = 100 µA, RST asserted 0.3 V

VCC1 or VCC2 ≥ 2.7 V,

ISINK = 1.2 mA, RST asserted 0.3 V

VCC1 or VCC2 ≥ 4.5 V,

ISINK = 3.2 mA, RST asserted 0.4 V

VOH

Output high voltage (RST;

push-pull only)

VCC1 ≥ 1.8 V, ISOURCE = 200 µA,

RST not asserted 0.8VCC1 V

VCC1 ≥ 2.7 V, ISOURCE = 500 µA,

RST not asserted 0.8VCC1 V

VCC1 ≥ 4.5 V, ISOURCE = 800 µA,

RST not asserted 0.8VCC1 V

tR(3) Push-pull RST rise time

(STM6718/20/78/80)

Rise time measured from 10% to

90% of VCC;

CL = 5 pF, VCC = 3.3 V

525ns

Reset thresholds

VRST(4) VTH1 VCC1 reset threshold

L (falling) 4.500 4.625 4.750 V

M (falling) 4.250 4.375 4.500 V

T (falling) 3.000 3.075 3.150 V

S (falling) 2.850 2.925 3.000 V

R (falling) 2.550 2.625 2.700 V

Z (falling) 2.250 2.313 2.375 V

Y (falling) 2.125 2.188 2.250 V

W (falling) 1.620 1.665 1.710 V

V (falling) 1.530 1.575 1.620 V

DC and AC parameters STM6717/6718/6719/6720/STM6777/6778/6779/6780

20/30 Doc ID 11469 Rev 8

VRST2(4) VTH2 VCC2 reset threshold

T (falling) 3.000 3.075 3.150 V

S (falling) 2.850 2.925 3.000 V

R (falling) 2.550 2.625 2.700 V

Z (falling) 2.250 2.313 2.375 V

Y (falling) 2.125 2.188 2.250 V

W (falling) 1.620 1.665 1.710 V

V (falling) 1.530 1.575 1.620 V

I (falling) 1.350 1.388 1.425 V

H (falling) 1.275 1.313 1.350 V

G (falling) 1.080 1.110 1.140 V

F (falling) 1.020 1.050 1.080 V

K (falling) 0.895 0.925 0.955 V

J (falling) 0.845 0.875 0.905 V

E (falling) 0.810 0.833 0.855 V

D (falling) 0.765 0.788 0.810 V

VHYST Reset threshold hysteresis Referenced to VRST typical 0.5 %

tRD VCC to RST delay

VCC1 = (VRST1 + 100 mV) to

(VRST – 100 mV) 20 µs

VCC2 = (VRST2 + 75 mV) to

(VRST2 – 75 mV) 20 µs

trec tRP RST pulse width

blank 140 210 280

msB 8.8 13.2 17.6

G 600 900 1200

Adjustable reset comparator input (STM6719/20/79/80)

VRSTIN RSTIN input threshold 611 626.5 642 mV

IRSTIN RSTIN input current –25 +25 nA

RSTIN hysteresis 3 mV

tRSTIND

RSTIN to RST

output delay VRSTIN to (VRSTIN – 30 mV) 22 µs

Table 6. DC and AC characteristics (continued)

Sym Alter-

native Description Test condition(1) Min Typ Max Unit

STM6717/6718/6719/6720/STM6777/6778/6779/6780 DC and AC parameters

Doc ID 11469 Rev 8 21/30

Manual (push-button) reset input

VIL MR input voltage

0.3VC

VIH 0.7VCC1 V

tMLMH tMR

MR minimum pulse width

(STM6717/18/19/20) 1µs

MR minimum pulse width

(STM6777/78/79/80)

MRC connected via

capacitor to VSS

6µs

tMLRL tMRD MR to RST output delay 200 ns

MR glitch immunity

(STM6717/18/19/20) 100 ns

MR pull-up resistance 25 50 80 kΩ

1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC1 = 0.8 to 5.5 V and VCC2 = 0.8 to 3.6 V (except where

noted).

2. Input leakage for the MRC pin is not tested.

3. Guaranteed by design.

4. The leakage current measured on the RST pin is tested with the reset de-asserted (output high impedance).

Table 6. DC and AC characteristics (continued)

Sym Alter-

native Description Test condition(1) Min Typ Max Unit

Table 7. tMLMH minimum pulse width

VCC1

Capacitor value(1)

100 pF 0.1 µF 2.2 µF 3.3 µF 4.7 µF 6.8 µF

1.6 V 120 µs 120 ms 2.6 s 4.0 s 5.6 s 8.2 s

2.0 V 122 µs 122 ms 2.7 s 4.0 s 5.8 s 8.3 s

3.0 V 125 µs 125 ms 2.7 s 4.1 s 5.9 s 8.5 s

4.0 V 128 µs 129 ms 2.8 s 4.2 s 6.0 s 8.7 s

5.0 V 130 µs 130 ms 2.8 s 4.3 s 6.1 s 8.8 s

1. At 25 °C (typical)

Package mechanical data STM6717/6718/6719/6720/STM6777/6778/6779/6780

22/30 Doc ID 11469 Rev 8

6 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Package mechanical data

Doc ID 11469 Rev 8 23/30

Figure 28. SOT23-5 – 5-lead small outline transistor package mechanical drawing

Note: Drawing is not to scale.

Note: Dimensions per JEDEC SOT/SOP product outline MO-178C, variation AA

C 0.10

MCAB

5x b

0.20

Datum A

0.20

0133778

Table 8. SOT23-5 – 5-lead small outline transistor package mechanical data

Symb

mm inches

Min Typ Max Min Typ Max

A——1.45——0.057

A1 — — 0.15 — — 0.006

A2 0.90 1.15 1.30 0.035 0.045 0.051

b 0.30 — 0.50 0.012 — 0.020

C 0.08 — 0.22 0.003 — 0.009

D — 2.90 — — 0.114 —

E — 2.80 — — 0.110 —

E1 — 1.60 — — 0.063 —

e — 0.95 — — 0.037 —

e1 — 1.90 — — 0.075 —

L 0.30 0.45 0.60 0.012 0.018 0.024

Q0°4°8°0°4°8°

N5 5

Package mechanical data STM6717/6718/6719/6720/STM6777/6778/6779/6780

24/30 Doc ID 11469 Rev 8

Figure 29. SOT23-6 – 6-lead small outline transistor package mechanical drawing

Note: Drawing is not to scale.

Note: Dimensions per JEDEC SOT/SOP product outline MO-178C variation AB

e1 D

6x b

0.10 C A B

0.10C

Datum A

0.20

7049714

Table 9. SOT23-6 – 6-lead small outline transistor package mechanical data

Symb

mm inches

Min Typ Max Min Typ Max

A——1.45——0.057

A1 — — 0.15 — — 0.006

A2 0.90 1.15 1.30 0.035 0.045 0.051

b 0.30 — 0.50 0.012 — 0.020

C 0.08 — 0.22 0.003 — 0.009

D — 2.90 — — 0.114 —

E — 2.80 — — 0.110 —

E1 — 1.60 — — 0.063 —

e — 0.95 — — 0.037 —

e1 — 1.90 — — 0.075 —

L 0.30 0.45 0.60 0.012 0.018 0.024

Q0°4°8°0°4°8°

N6 6

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Package mechanical data

Doc ID 11469 Rev 8 25/30

Figure 30. Carrier tape for SOT23-5L and SOT23-6L

Note: Part pin 1 indicator is on bottom left for shipping method “F” and is on top right for shipping

method “R” see Section 7.

CENTER LINES

OF CAVITY

TOP COVER

TAPE

USER DIRECTION OF FEED

AM03073v1

Table 10. Carrier tape dimensions for SOT23-5L and SOT23-6L

Package W D E P0P2FA

0B0K0P1TUnit

Bulk

Qty

SOT23-5

SOT23-6

8.00

+0.30/

–0.10

1.50

+0.10/

–0.00

1.75

±0.10

4.00

±0.10

2.00

±0.10

3.50

±0.05

3.23

±0.10

3.17

±0.10

1.37

±0.10

4.00

±0.10

0.254

±0.013 mm 3000

Part numbering STM6717/6718/6719/6720/STM6777/6778/6779/6780

26/30 Doc ID 11469 Rev 8

7 Part numbering

Table 11. Ordering information scheme

Example: STM67xx LT WY 6 F

Device type

STM67xx

Reset thresholds (VRST1 and VRST2) for VCC1 and VCC2

STM6717/18/19/20/77/78 (VRST1 and VRST2) STM6779/80 (VRST1 only)

Suffix VRST1 VRST2 Suffix VRST1

LT 4.625 3.075 L–(1) 4.625

MS 4.375 2.925 T–(1) 3.075

MR 4.375 2.625 S–(1) 2.925

TZ(1) 3.075 2.313 Y–(1) 2.188

TW(1) 3.075 1.665 V–(1) 1.575

TI 3.075 1.388 R– 2.625

TG(1) 3.075 1.110 Z– 2.313

TK 3.075 0.925

TE 3.075 0.833

SY(1) 2.925 2.188

SV(1) 2.925 1.575

SH(2) 2.925 1.313

SF(1) 2.925 1.050

SJ(3) 2.925 0.875

SD(3) 2.925 0.788

YV 2.188 1.575

YH 2.188 1.313

YF 2.188 1.050

YJ 2.188 0.875

YD 2.188 0.788

VH 1.575 1.313

VF 1.575 1.050

VJ 1.575 0.875

VD 1.575 0.788

Reset pulse width

blank: trec = 140 ms to 280 ms

B: trec = 8.8 ms to 17.6 ms

G: trec = 600 ms to 1200 ms

Package

WY = SOT23-5

WB = SOT23-6

Temperature range

6 = –40 to 85°C

Shipping method

E = ECOPACK® package, tubes

F = ECOPACK® package, tape and reel

R(4) = ECOPACK® package, tape and reel (pin 1 at top right).

1. T

hese are standard versions and are typically held in stock. A non-standard version may require a higher minimum volumes, and/or longer

delivery times. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.

2. Available in STM6719 version only.

3. Available in STM6717 version only.

4. Available for STM6720SY, STM6719SF and STM6719SFB versions only.

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Part numbering

Doc ID 11469 Rev 8 27/30

Table 12. Marking description

Part number VRST1 threshold (V) VRST2 threshold (V) Topside marking Bottomside marking

STM6717SD 2.925 0.788 7SD1 PYWW

STM6717SJ 2.925 0.875 7SJ1 PYWW

STM6717SF 2.925 1.050 7SF1 PYWW

STM6717TG 3.075 1.110 7TG1 PYWW

STM6717TGG 3.075 1.110 7TG9 PYWW

STM6717TW 3.075 1.665 7TW1 PYWW

STM6717SV 2.925 1.575 7SV1 PYWW

STM6717SY 2.925 2.188 7SY1 PYWW

STM6717TZ 3.075 2.313 7TZ1 PYWW

STM6718SF 2.925 1.050 7SF2 PYWW

STM6718TG 3.075 1.110 7TG2 PYWW

STM6718TW 3.075 1.665 7TW2 PYWW

STM6718SV 2.925 1.575 7SV2 PYWW

STM6718SY 2.925 2.188 7SY2 PYWW

STM6718TZ 3.075 2.313 7TZ2 PYWW

STM6719SF 2.925 1.050 7SF3 PYWW

STM6719SFB 2.925 1.050 7SFB PYWW

STM6719TG 3.075 1.110 7TG3 PYWW

STM6719SH 2.925 1.313 7SH3 PYWW

STM6719TW 3.075 1.665 7TW3 PYWW

STM6719SV 2.925 1.575 7SV3 PYWW

STM6719SY 2.925 2.188 7SY3 PYWW

STM6719TZ 3.075 2.313 7TZ3 PYWW

STM6720SF 2.925 1.050 7SF4 PYWW

STM6720TG 3.075 1.110 7TG4 PYWW

STM6720TW 3.075 1.665 7TW4 PYWW

STM6720SV 2.925 1.575 7SV4 PYWW

STM6720SY 2.925 2.188 7SY4 PYWW

STM6720TZ 3.075 2.313 7TZ4 PYWW

STM6777SF 2.925 1.050 7SF5 PYWW

STM6777TG 3.075 1.110 7TG5 PYWW

STM6777TW 3.075 1.665 7TW5 PYWW

STM6777SV 2.925 1.575 7SV5 PYWW

STM6777SY 2.925 2.188 7SY5 PYWW

STM6777TZ 3.075 2.313 7TZ5 PYWW

Part numbering STM6717/6718/6719/6720/STM6777/6778/6779/6780

28/30 Doc ID 11469 Rev 8

Note: For topside marking, “7” is the family number, followed by the VRST1 threshold, VRST2

threshold and device number (1,9 = STM6717, 2 = 6718, 3 = 6719, 4 = 6720, 5 = 6777,

6 = 6778, 7 = 6779, 8 = 6780).

For bottomside marking, “P” = assembly site, “Y” = 1-digit year, and “WW” = 2-digit work

week.

STM6778SF 2.925 1.050 7SF6 PYWW

STM6778TG 3.075 1.110 7TG6 PYWW

STM6778TW 3.075 1.665 7TW6 PYWW

STM6778SV 2.925 1.575 7SV6 PYWW

STM6778SY 2.925 2.188 7SY6 PYWW

STM6778TZ 3.075 2.313 7TZ6 PYWW

STM6779L 4.625 — 7Lx7 PYWW

STM6779T 3.075 — 7Tx7 PYWW

STM6779S 2.925 — 7Sx7 PYWW

STM6779Y 2.188 — 7Yx7 PYWW

STM6779V 1.575 — 7Vx7 PYWW

STM6780L 4.625 — 7Lx8 PYWW

STM6780T 3.075 — 7Tx8 PYWW

STM6780S 2.925 — 7Sx8 PYWW

STM6780Y 2.188 — 7Yx8 PYWW

STM6780V 1.575 — 7Vx8 PYWW

Table 12. Marking description (continued)

Part number VRST1 threshold (V) VRST2 threshold (V) Topside marking Bottomside marking

STM6717/6718/6719/6720/STM6777/6778/6779/6780 Revision history
Doc ID 11469 Rev 8 29/30
8 Revision history
         
Table 13. Document revision history
Date Revision Changes
18-Oct-2004 1 First draft
25-Oct-2004 1.1 Descriptive text, sales types (Ta bl e 1 1 )
14-Jan-2005 1.2 Update characteristics, pin functions (Tab l e 2)
09-Feb-2005 1.3 Update characteristics (Figure 9; Ta b l e 3 )
08-Apr-2005 1.4 Update characteristics and mechanical dimensions; add table 
(Figure 9, 10, 27, 28, 29; Ta b le 4, 6, 11, 8, 9)
28-Jul-2005 1.5 Update characteristics, reset delay (Figure 10, 27; Table 4 , 6, 7, 11)
13-Sep-2005 2
Add operating characteristics; update timings, document status, Lead-
free text (Figure Figure 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 
26, 27; Ta bl e 1 1 )
07-Oct-2005 3 Marked STM6779/6780 as availability request parts (Ta bl e 1 , 11)
07-Feb-2007 4 Updated STM6779/6780 availability (cover page, Ta b le 1 , 11)
12-Jun-2007 5 Updated Ta bl e 1 1 , added Table 12: Marking description.
05-Dec-2007 6 Updated cover page, Ta b l e 6 , 11, and 12.
22-Mar-2010 7
Updated Features; Ta b l e 6, 8, 9, 11, 12; footnote 1 of Ta b l e 4 ; 
Section 6: Package mechanical data; added tape and reel 
specifications (Figure 30, Ta b l e 1 0 , footnote 4 of Tabl e 1 1 ); 
reformatted document.
02-Aug-2011 8 Removed footnote from Table 6: DC and AC characteristics.

STM6717/6718/6719/6720/STM6777/6778/6779/6780

30/30 Doc ID 11469 Rev 8

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